1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP500/DP550/DP650 KMS/DRM driver 11 */ 12 13 #include <linux/module.h> 14 #include <linux/clk.h> 15 #include <linux/component.h> 16 #include <linux/console.h> 17 #include <linux/of_device.h> 18 #include <linux/of_graph.h> 19 #include <linux/of_reserved_mem.h> 20 #include <linux/pm_runtime.h> 21 22 #include <drm/drmP.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_gem_cma_helper.h> 29 #include <drm/drm_of.h> 30 31 #include "malidp_drv.h" 32 #include "malidp_regs.h" 33 #include "malidp_hw.h" 34 35 #define MALIDP_CONF_VALID_TIMEOUT 250 36 37 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev, 38 u32 data[MALIDP_COEFFTAB_NUM_COEFFS]) 39 { 40 int i; 41 /* Update all channels with a single gamma curve. */ 42 const u32 gamma_write_mask = GENMASK(18, 16); 43 /* 44 * Always write an entire table, so the address field in 45 * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask 46 * directly. 47 */ 48 malidp_hw_write(hwdev, gamma_write_mask, 49 hwdev->map.coeffs_base + MALIDP_COEF_TABLE_ADDR); 50 for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) 51 malidp_hw_write(hwdev, data[i], 52 hwdev->map.coeffs_base + 53 MALIDP_COEF_TABLE_DATA); 54 } 55 56 static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc, 57 struct drm_crtc_state *old_state) 58 { 59 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 60 struct malidp_hw_device *hwdev = malidp->dev; 61 62 if (!crtc->state->color_mgmt_changed) 63 return; 64 65 if (!crtc->state->gamma_lut) { 66 malidp_hw_clearbits(hwdev, 67 MALIDP_DISP_FUNC_GAMMA, 68 MALIDP_DE_DISPLAY_FUNC); 69 } else { 70 struct malidp_crtc_state *mc = 71 to_malidp_crtc_state(crtc->state); 72 73 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id != 74 old_state->gamma_lut->base.id)) 75 malidp_write_gamma_table(hwdev, mc->gamma_coeffs); 76 77 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA, 78 MALIDP_DE_DISPLAY_FUNC); 79 } 80 } 81 82 static 83 void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc, 84 struct drm_crtc_state *old_state) 85 { 86 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 87 struct malidp_hw_device *hwdev = malidp->dev; 88 int i; 89 90 if (!crtc->state->color_mgmt_changed) 91 return; 92 93 if (!crtc->state->ctm) { 94 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ, 95 MALIDP_DE_DISPLAY_FUNC); 96 } else { 97 struct malidp_crtc_state *mc = 98 to_malidp_crtc_state(crtc->state); 99 100 if (!old_state->ctm || (crtc->state->ctm->base.id != 101 old_state->ctm->base.id)) 102 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i) 103 malidp_hw_write(hwdev, 104 mc->coloradj_coeffs[i], 105 hwdev->map.coeffs_base + 106 MALIDP_COLOR_ADJ_COEF + 4 * i); 107 108 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ, 109 MALIDP_DE_DISPLAY_FUNC); 110 } 111 } 112 113 static void malidp_atomic_commit_se_config(struct drm_crtc *crtc, 114 struct drm_crtc_state *old_state) 115 { 116 struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state); 117 struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state); 118 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 119 struct malidp_hw_device *hwdev = malidp->dev; 120 struct malidp_se_config *s = &cs->scaler_config; 121 struct malidp_se_config *old_s = &old_cs->scaler_config; 122 u32 se_control = hwdev->map.se_base + 123 ((hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? 124 0x10 : 0xC); 125 u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL; 126 u32 scr = se_control + MALIDP_SE_SCALING_CONTROL; 127 u32 val; 128 129 /* Set SE_CONTROL */ 130 if (!s->scale_enable) { 131 val = malidp_hw_read(hwdev, se_control); 132 val &= ~MALIDP_SE_SCALING_EN; 133 malidp_hw_write(hwdev, val, se_control); 134 return; 135 } 136 137 hwdev->se_set_scaling_coeffs(hwdev, s, old_s); 138 val = malidp_hw_read(hwdev, se_control); 139 val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN; 140 141 val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK); 142 val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0; 143 144 val |= MALIDP_SE_RGBO_IF_EN; 145 malidp_hw_write(hwdev, val, se_control); 146 147 /* Set IN_SIZE & OUT_SIZE. */ 148 val = MALIDP_SE_SET_V_SIZE(s->input_h) | 149 MALIDP_SE_SET_H_SIZE(s->input_w); 150 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE); 151 val = MALIDP_SE_SET_V_SIZE(s->output_h) | 152 MALIDP_SE_SET_H_SIZE(s->output_w); 153 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE); 154 155 /* Set phase regs. */ 156 malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH); 157 malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH); 158 malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH); 159 malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH); 160 } 161 162 /* 163 * set the "config valid" bit and wait until the hardware acts on it 164 */ 165 static int malidp_set_and_wait_config_valid(struct drm_device *drm) 166 { 167 struct malidp_drm *malidp = drm->dev_private; 168 struct malidp_hw_device *hwdev = malidp->dev; 169 int ret; 170 171 atomic_set(&malidp->config_valid, 0); 172 hwdev->set_config_valid(hwdev); 173 /* don't wait for config_valid flag if we are in config mode */ 174 if (hwdev->in_config_mode(hwdev)) 175 return 0; 176 177 ret = wait_event_interruptible_timeout(malidp->wq, 178 atomic_read(&malidp->config_valid) == 1, 179 msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT)); 180 181 return (ret > 0) ? 0 : -ETIMEDOUT; 182 } 183 184 static void malidp_output_poll_changed(struct drm_device *drm) 185 { 186 struct malidp_drm *malidp = drm->dev_private; 187 188 drm_fbdev_cma_hotplug_event(malidp->fbdev); 189 } 190 191 static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state) 192 { 193 struct drm_pending_vblank_event *event; 194 struct drm_device *drm = state->dev; 195 struct malidp_drm *malidp = drm->dev_private; 196 197 if (malidp->crtc.enabled) { 198 /* only set config_valid if the CRTC is enabled */ 199 if (malidp_set_and_wait_config_valid(drm)) 200 DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n"); 201 } 202 203 event = malidp->crtc.state->event; 204 if (event) { 205 malidp->crtc.state->event = NULL; 206 207 spin_lock_irq(&drm->event_lock); 208 if (drm_crtc_vblank_get(&malidp->crtc) == 0) 209 drm_crtc_arm_vblank_event(&malidp->crtc, event); 210 else 211 drm_crtc_send_vblank_event(&malidp->crtc, event); 212 spin_unlock_irq(&drm->event_lock); 213 } 214 drm_atomic_helper_commit_hw_done(state); 215 } 216 217 static void malidp_atomic_commit_tail(struct drm_atomic_state *state) 218 { 219 struct drm_device *drm = state->dev; 220 struct drm_crtc *crtc; 221 struct drm_crtc_state *old_crtc_state; 222 int i; 223 224 pm_runtime_get_sync(drm->dev); 225 226 drm_atomic_helper_commit_modeset_disables(drm, state); 227 228 for_each_crtc_in_state(state, crtc, old_crtc_state, i) { 229 malidp_atomic_commit_update_gamma(crtc, old_crtc_state); 230 malidp_atomic_commit_update_coloradj(crtc, old_crtc_state); 231 malidp_atomic_commit_se_config(crtc, old_crtc_state); 232 } 233 234 drm_atomic_helper_commit_planes(drm, state, 0); 235 236 drm_atomic_helper_commit_modeset_enables(drm, state); 237 238 malidp_atomic_commit_hw_done(state); 239 240 drm_atomic_helper_wait_for_vblanks(drm, state); 241 242 pm_runtime_put(drm->dev); 243 244 drm_atomic_helper_cleanup_planes(drm, state); 245 } 246 247 static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = { 248 .atomic_commit_tail = malidp_atomic_commit_tail, 249 }; 250 251 static const struct drm_mode_config_funcs malidp_mode_config_funcs = { 252 .fb_create = drm_fb_cma_create, 253 .output_poll_changed = malidp_output_poll_changed, 254 .atomic_check = drm_atomic_helper_check, 255 .atomic_commit = drm_atomic_helper_commit, 256 }; 257 258 static int malidp_init(struct drm_device *drm) 259 { 260 int ret; 261 struct malidp_drm *malidp = drm->dev_private; 262 struct malidp_hw_device *hwdev = malidp->dev; 263 264 drm_mode_config_init(drm); 265 266 drm->mode_config.min_width = hwdev->min_line_size; 267 drm->mode_config.min_height = hwdev->min_line_size; 268 drm->mode_config.max_width = hwdev->max_line_size; 269 drm->mode_config.max_height = hwdev->max_line_size; 270 drm->mode_config.funcs = &malidp_mode_config_funcs; 271 drm->mode_config.helper_private = &malidp_mode_config_helpers; 272 273 ret = malidp_crtc_init(drm); 274 if (ret) { 275 drm_mode_config_cleanup(drm); 276 return ret; 277 } 278 279 return 0; 280 } 281 282 static void malidp_fini(struct drm_device *drm) 283 { 284 malidp_de_planes_destroy(drm); 285 drm_mode_config_cleanup(drm); 286 } 287 288 static int malidp_irq_init(struct platform_device *pdev) 289 { 290 int irq_de, irq_se, ret = 0; 291 struct drm_device *drm = dev_get_drvdata(&pdev->dev); 292 293 /* fetch the interrupts from DT */ 294 irq_de = platform_get_irq_byname(pdev, "DE"); 295 if (irq_de < 0) { 296 DRM_ERROR("no 'DE' IRQ specified!\n"); 297 return irq_de; 298 } 299 irq_se = platform_get_irq_byname(pdev, "SE"); 300 if (irq_se < 0) { 301 DRM_ERROR("no 'SE' IRQ specified!\n"); 302 return irq_se; 303 } 304 305 ret = malidp_de_irq_init(drm, irq_de); 306 if (ret) 307 return ret; 308 309 ret = malidp_se_irq_init(drm, irq_se); 310 if (ret) { 311 malidp_de_irq_fini(drm); 312 return ret; 313 } 314 315 return 0; 316 } 317 318 static void malidp_lastclose(struct drm_device *drm) 319 { 320 struct malidp_drm *malidp = drm->dev_private; 321 322 drm_fbdev_cma_restore_mode(malidp->fbdev); 323 } 324 325 DEFINE_DRM_GEM_CMA_FOPS(fops); 326 327 static struct drm_driver malidp_driver = { 328 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC | 329 DRIVER_PRIME, 330 .lastclose = malidp_lastclose, 331 .gem_free_object_unlocked = drm_gem_cma_free_object, 332 .gem_vm_ops = &drm_gem_cma_vm_ops, 333 .dumb_create = drm_gem_cma_dumb_create, 334 .dumb_map_offset = drm_gem_cma_dumb_map_offset, 335 .dumb_destroy = drm_gem_dumb_destroy, 336 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 337 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 338 .gem_prime_export = drm_gem_prime_export, 339 .gem_prime_import = drm_gem_prime_import, 340 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 341 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 342 .gem_prime_vmap = drm_gem_cma_prime_vmap, 343 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 344 .gem_prime_mmap = drm_gem_cma_prime_mmap, 345 .fops = &fops, 346 .name = "mali-dp", 347 .desc = "ARM Mali Display Processor driver", 348 .date = "20160106", 349 .major = 1, 350 .minor = 0, 351 }; 352 353 static const struct of_device_id malidp_drm_of_match[] = { 354 { 355 .compatible = "arm,mali-dp500", 356 .data = &malidp_device[MALIDP_500] 357 }, 358 { 359 .compatible = "arm,mali-dp550", 360 .data = &malidp_device[MALIDP_550] 361 }, 362 { 363 .compatible = "arm,mali-dp650", 364 .data = &malidp_device[MALIDP_650] 365 }, 366 {}, 367 }; 368 MODULE_DEVICE_TABLE(of, malidp_drm_of_match); 369 370 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev, 371 const struct of_device_id *dev_id) 372 { 373 u32 core_id; 374 const char *compatstr_dp500 = "arm,mali-dp500"; 375 bool is_dp500; 376 bool dt_is_dp500; 377 378 /* 379 * The DP500 CORE_ID register is in a different location, so check it 380 * first. If the product id field matches, then this is DP500, otherwise 381 * check the DP550/650 CORE_ID register. 382 */ 383 core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID); 384 /* Offset 0x18 will never read 0x500 on products other than DP500. */ 385 is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500); 386 dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500, 387 sizeof(dev_id->compatible)) != NULL; 388 if (is_dp500 != dt_is_dp500) { 389 DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n", 390 dev_id->compatible, is_dp500 ? "is" : "is not"); 391 return false; 392 } else if (!dt_is_dp500) { 393 u16 product_id; 394 char buf[32]; 395 396 core_id = malidp_hw_read(hwdev, 397 MALIDP550_DC_BASE + MALIDP_DE_CORE_ID); 398 product_id = MALIDP_PRODUCT_ID(core_id); 399 snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id); 400 if (!strnstr(dev_id->compatible, buf, 401 sizeof(dev_id->compatible))) { 402 DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n", 403 dev_id->compatible, product_id); 404 return false; 405 } 406 } 407 return true; 408 } 409 410 static bool malidp_has_sufficient_address_space(const struct resource *res, 411 const struct of_device_id *dev_id) 412 { 413 resource_size_t res_size = resource_size(res); 414 const char *compatstr_dp500 = "arm,mali-dp500"; 415 416 if (!strnstr(dev_id->compatible, compatstr_dp500, 417 sizeof(dev_id->compatible))) 418 return res_size >= MALIDP550_ADDR_SPACE_SIZE; 419 else if (res_size < MALIDP500_ADDR_SPACE_SIZE) 420 return false; 421 return true; 422 } 423 424 static ssize_t core_id_show(struct device *dev, struct device_attribute *attr, 425 char *buf) 426 { 427 struct drm_device *drm = dev_get_drvdata(dev); 428 struct malidp_drm *malidp = drm->dev_private; 429 430 return snprintf(buf, PAGE_SIZE, "%08x\n", malidp->core_id); 431 } 432 433 DEVICE_ATTR_RO(core_id); 434 435 static int malidp_init_sysfs(struct device *dev) 436 { 437 int ret = device_create_file(dev, &dev_attr_core_id); 438 439 if (ret) 440 DRM_ERROR("failed to create device file for core_id\n"); 441 442 return ret; 443 } 444 445 static void malidp_fini_sysfs(struct device *dev) 446 { 447 device_remove_file(dev, &dev_attr_core_id); 448 } 449 450 #define MAX_OUTPUT_CHANNELS 3 451 452 static int malidp_runtime_pm_suspend(struct device *dev) 453 { 454 struct drm_device *drm = dev_get_drvdata(dev); 455 struct malidp_drm *malidp = drm->dev_private; 456 struct malidp_hw_device *hwdev = malidp->dev; 457 458 /* we can only suspend if the hardware is in config mode */ 459 WARN_ON(!hwdev->in_config_mode(hwdev)); 460 461 hwdev->pm_suspended = true; 462 clk_disable_unprepare(hwdev->mclk); 463 clk_disable_unprepare(hwdev->aclk); 464 clk_disable_unprepare(hwdev->pclk); 465 466 return 0; 467 } 468 469 static int malidp_runtime_pm_resume(struct device *dev) 470 { 471 struct drm_device *drm = dev_get_drvdata(dev); 472 struct malidp_drm *malidp = drm->dev_private; 473 struct malidp_hw_device *hwdev = malidp->dev; 474 475 clk_prepare_enable(hwdev->pclk); 476 clk_prepare_enable(hwdev->aclk); 477 clk_prepare_enable(hwdev->mclk); 478 hwdev->pm_suspended = false; 479 480 return 0; 481 } 482 483 static int malidp_bind(struct device *dev) 484 { 485 struct resource *res; 486 struct drm_device *drm; 487 struct malidp_drm *malidp; 488 struct malidp_hw_device *hwdev; 489 struct platform_device *pdev = to_platform_device(dev); 490 struct of_device_id const *dev_id; 491 /* number of lines for the R, G and B output */ 492 u8 output_width[MAX_OUTPUT_CHANNELS]; 493 int ret = 0, i; 494 u32 version, out_depth = 0; 495 496 malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL); 497 if (!malidp) 498 return -ENOMEM; 499 500 hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL); 501 if (!hwdev) 502 return -ENOMEM; 503 504 /* 505 * copy the associated data from malidp_drm_of_match to avoid 506 * having to keep a reference to the OF node after binding 507 */ 508 memcpy(hwdev, of_device_get_match_data(dev), sizeof(*hwdev)); 509 malidp->dev = hwdev; 510 511 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 512 hwdev->regs = devm_ioremap_resource(dev, res); 513 if (IS_ERR(hwdev->regs)) 514 return PTR_ERR(hwdev->regs); 515 516 hwdev->pclk = devm_clk_get(dev, "pclk"); 517 if (IS_ERR(hwdev->pclk)) 518 return PTR_ERR(hwdev->pclk); 519 520 hwdev->aclk = devm_clk_get(dev, "aclk"); 521 if (IS_ERR(hwdev->aclk)) 522 return PTR_ERR(hwdev->aclk); 523 524 hwdev->mclk = devm_clk_get(dev, "mclk"); 525 if (IS_ERR(hwdev->mclk)) 526 return PTR_ERR(hwdev->mclk); 527 528 hwdev->pxlclk = devm_clk_get(dev, "pxlclk"); 529 if (IS_ERR(hwdev->pxlclk)) 530 return PTR_ERR(hwdev->pxlclk); 531 532 /* Get the optional framebuffer memory resource */ 533 ret = of_reserved_mem_device_init(dev); 534 if (ret && ret != -ENODEV) 535 return ret; 536 537 drm = drm_dev_alloc(&malidp_driver, dev); 538 if (IS_ERR(drm)) { 539 ret = PTR_ERR(drm); 540 goto alloc_fail; 541 } 542 543 drm->dev_private = malidp; 544 dev_set_drvdata(dev, drm); 545 546 /* Enable power management */ 547 pm_runtime_enable(dev); 548 549 /* Resume device to enable the clocks */ 550 if (pm_runtime_enabled(dev)) 551 pm_runtime_get_sync(dev); 552 else 553 malidp_runtime_pm_resume(dev); 554 555 dev_id = of_match_device(malidp_drm_of_match, dev); 556 if (!dev_id) { 557 ret = -EINVAL; 558 goto query_hw_fail; 559 } 560 561 if (!malidp_has_sufficient_address_space(res, dev_id)) { 562 DRM_ERROR("Insufficient address space in device-tree.\n"); 563 ret = -EINVAL; 564 goto query_hw_fail; 565 } 566 567 if (!malidp_is_compatible_hw_id(hwdev, dev_id)) { 568 ret = -EINVAL; 569 goto query_hw_fail; 570 } 571 572 ret = hwdev->query_hw(hwdev); 573 if (ret) { 574 DRM_ERROR("Invalid HW configuration\n"); 575 goto query_hw_fail; 576 } 577 578 version = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_DE_CORE_ID); 579 DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16, 580 (version >> 12) & 0xf, (version >> 8) & 0xf); 581 582 malidp->core_id = version; 583 584 /* set the number of lines used for output of RGB data */ 585 ret = of_property_read_u8_array(dev->of_node, 586 "arm,malidp-output-port-lines", 587 output_width, MAX_OUTPUT_CHANNELS); 588 if (ret) 589 goto query_hw_fail; 590 591 for (i = 0; i < MAX_OUTPUT_CHANNELS; i++) 592 out_depth = (out_depth << 8) | (output_width[i] & 0xf); 593 malidp_hw_write(hwdev, out_depth, hwdev->map.out_depth_base); 594 595 atomic_set(&malidp->config_valid, 0); 596 init_waitqueue_head(&malidp->wq); 597 598 ret = malidp_init(drm); 599 if (ret < 0) 600 goto query_hw_fail; 601 602 ret = malidp_init_sysfs(dev); 603 if (ret) 604 goto init_fail; 605 606 /* Set the CRTC's port so that the encoder component can find it */ 607 malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); 608 609 ret = component_bind_all(dev, drm); 610 if (ret) { 611 DRM_ERROR("Failed to bind all components\n"); 612 goto bind_fail; 613 } 614 615 ret = malidp_irq_init(pdev); 616 if (ret < 0) 617 goto irq_init_fail; 618 619 drm->irq_enabled = true; 620 621 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 622 if (ret < 0) { 623 DRM_ERROR("failed to initialise vblank\n"); 624 goto vblank_fail; 625 } 626 pm_runtime_put(dev); 627 628 drm_mode_config_reset(drm); 629 630 malidp->fbdev = drm_fbdev_cma_init(drm, 32, 631 drm->mode_config.num_connector); 632 633 if (IS_ERR(malidp->fbdev)) { 634 ret = PTR_ERR(malidp->fbdev); 635 malidp->fbdev = NULL; 636 goto fbdev_fail; 637 } 638 639 drm_kms_helper_poll_init(drm); 640 641 ret = drm_dev_register(drm, 0); 642 if (ret) 643 goto register_fail; 644 645 return 0; 646 647 register_fail: 648 if (malidp->fbdev) { 649 drm_fbdev_cma_fini(malidp->fbdev); 650 malidp->fbdev = NULL; 651 } 652 drm_kms_helper_poll_fini(drm); 653 fbdev_fail: 654 pm_runtime_get_sync(dev); 655 vblank_fail: 656 malidp_se_irq_fini(drm); 657 malidp_de_irq_fini(drm); 658 drm->irq_enabled = false; 659 irq_init_fail: 660 component_unbind_all(dev, drm); 661 bind_fail: 662 of_node_put(malidp->crtc.port); 663 malidp->crtc.port = NULL; 664 init_fail: 665 malidp_fini_sysfs(dev); 666 malidp_fini(drm); 667 query_hw_fail: 668 pm_runtime_put(dev); 669 if (pm_runtime_enabled(dev)) 670 pm_runtime_disable(dev); 671 else 672 malidp_runtime_pm_suspend(dev); 673 drm->dev_private = NULL; 674 dev_set_drvdata(dev, NULL); 675 drm_dev_unref(drm); 676 alloc_fail: 677 of_reserved_mem_device_release(dev); 678 679 return ret; 680 } 681 682 static void malidp_unbind(struct device *dev) 683 { 684 struct drm_device *drm = dev_get_drvdata(dev); 685 struct malidp_drm *malidp = drm->dev_private; 686 687 drm_dev_unregister(drm); 688 if (malidp->fbdev) { 689 drm_fbdev_cma_fini(malidp->fbdev); 690 malidp->fbdev = NULL; 691 } 692 drm_kms_helper_poll_fini(drm); 693 pm_runtime_get_sync(dev); 694 malidp_se_irq_fini(drm); 695 malidp_de_irq_fini(drm); 696 component_unbind_all(dev, drm); 697 of_node_put(malidp->crtc.port); 698 malidp->crtc.port = NULL; 699 malidp_fini_sysfs(dev); 700 malidp_fini(drm); 701 pm_runtime_put(dev); 702 if (pm_runtime_enabled(dev)) 703 pm_runtime_disable(dev); 704 else 705 malidp_runtime_pm_suspend(dev); 706 drm->dev_private = NULL; 707 dev_set_drvdata(dev, NULL); 708 drm_dev_unref(drm); 709 of_reserved_mem_device_release(dev); 710 } 711 712 static const struct component_master_ops malidp_master_ops = { 713 .bind = malidp_bind, 714 .unbind = malidp_unbind, 715 }; 716 717 static int malidp_compare_dev(struct device *dev, void *data) 718 { 719 struct device_node *np = data; 720 721 return dev->of_node == np; 722 } 723 724 static int malidp_platform_probe(struct platform_device *pdev) 725 { 726 struct device_node *port; 727 struct component_match *match = NULL; 728 729 if (!pdev->dev.of_node) 730 return -ENODEV; 731 732 /* there is only one output port inside each device, find it */ 733 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); 734 if (!port) 735 return -ENODEV; 736 737 drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev, 738 port); 739 of_node_put(port); 740 return component_master_add_with_match(&pdev->dev, &malidp_master_ops, 741 match); 742 } 743 744 static int malidp_platform_remove(struct platform_device *pdev) 745 { 746 component_master_del(&pdev->dev, &malidp_master_ops); 747 return 0; 748 } 749 750 static int __maybe_unused malidp_pm_suspend(struct device *dev) 751 { 752 struct drm_device *drm = dev_get_drvdata(dev); 753 struct malidp_drm *malidp = drm->dev_private; 754 755 drm_kms_helper_poll_disable(drm); 756 console_lock(); 757 drm_fbdev_cma_set_suspend(malidp->fbdev, 1); 758 console_unlock(); 759 malidp->pm_state = drm_atomic_helper_suspend(drm); 760 if (IS_ERR(malidp->pm_state)) { 761 console_lock(); 762 drm_fbdev_cma_set_suspend(malidp->fbdev, 0); 763 console_unlock(); 764 drm_kms_helper_poll_enable(drm); 765 return PTR_ERR(malidp->pm_state); 766 } 767 768 return 0; 769 } 770 771 static int __maybe_unused malidp_pm_resume(struct device *dev) 772 { 773 struct drm_device *drm = dev_get_drvdata(dev); 774 struct malidp_drm *malidp = drm->dev_private; 775 776 drm_atomic_helper_resume(drm, malidp->pm_state); 777 console_lock(); 778 drm_fbdev_cma_set_suspend(malidp->fbdev, 0); 779 console_unlock(); 780 drm_kms_helper_poll_enable(drm); 781 782 return 0; 783 } 784 785 static const struct dev_pm_ops malidp_pm_ops = { 786 SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \ 787 SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL) 788 }; 789 790 static struct platform_driver malidp_platform_driver = { 791 .probe = malidp_platform_probe, 792 .remove = malidp_platform_remove, 793 .driver = { 794 .name = "mali-dp", 795 .pm = &malidp_pm_ops, 796 .of_match_table = malidp_drm_of_match, 797 }, 798 }; 799 800 module_platform_driver(malidp_platform_driver); 801 802 MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>"); 803 MODULE_DESCRIPTION("ARM Mali DP DRM driver"); 804 MODULE_LICENSE("GPL v2"); 805