1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP500/DP550/DP650 driver (crtc operations) 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_crtc_helper.h> 18 #include <linux/clk.h> 19 #include <linux/pm_runtime.h> 20 #include <video/videomode.h> 21 22 #include "malidp_drv.h" 23 #include "malidp_hw.h" 24 25 static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc, 26 const struct drm_display_mode *mode) 27 { 28 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 29 struct malidp_hw_device *hwdev = malidp->dev; 30 31 /* 32 * check that the hardware can drive the required clock rate, 33 * but skip the check if the clock is meant to be disabled (req_rate = 0) 34 */ 35 long rate, req_rate = mode->crtc_clock * 1000; 36 37 if (req_rate) { 38 rate = clk_round_rate(hwdev->pxlclk, req_rate); 39 if (rate != req_rate) { 40 DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n", 41 req_rate); 42 return MODE_NOCLOCK; 43 } 44 } 45 46 return MODE_OK; 47 } 48 49 static void malidp_crtc_atomic_enable(struct drm_crtc *crtc, 50 struct drm_crtc_state *old_state) 51 { 52 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 53 struct malidp_hw_device *hwdev = malidp->dev; 54 struct videomode vm; 55 int err = pm_runtime_get_sync(crtc->dev->dev); 56 57 if (err < 0) { 58 DRM_DEBUG_DRIVER("Failed to enable runtime power management: %d\n", err); 59 return; 60 } 61 62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); 63 clk_prepare_enable(hwdev->pxlclk); 64 65 /* We rely on firmware to set mclk to a sensible level. */ 66 clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000); 67 68 hwdev->modeset(hwdev, &vm); 69 hwdev->leave_config_mode(hwdev); 70 drm_crtc_vblank_on(crtc); 71 } 72 73 static void malidp_crtc_atomic_disable(struct drm_crtc *crtc, 74 struct drm_crtc_state *old_state) 75 { 76 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 77 struct malidp_hw_device *hwdev = malidp->dev; 78 int err; 79 80 drm_crtc_vblank_off(crtc); 81 hwdev->enter_config_mode(hwdev); 82 clk_disable_unprepare(hwdev->pxlclk); 83 84 err = pm_runtime_put(crtc->dev->dev); 85 if (err < 0) { 86 DRM_DEBUG_DRIVER("Failed to disable runtime power management: %d\n", err); 87 } 88 } 89 90 static const struct gamma_curve_segment { 91 u16 start; 92 u16 end; 93 } segments[MALIDP_COEFFTAB_NUM_COEFFS] = { 94 /* sector 0 */ 95 { 0, 0 }, { 1, 1 }, { 2, 2 }, { 3, 3 }, 96 { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, 97 { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, 98 { 12, 12 }, { 13, 13 }, { 14, 14 }, { 15, 15 }, 99 /* sector 1 */ 100 { 16, 19 }, { 20, 23 }, { 24, 27 }, { 28, 31 }, 101 /* sector 2 */ 102 { 32, 39 }, { 40, 47 }, { 48, 55 }, { 56, 63 }, 103 /* sector 3 */ 104 { 64, 79 }, { 80, 95 }, { 96, 111 }, { 112, 127 }, 105 /* sector 4 */ 106 { 128, 159 }, { 160, 191 }, { 192, 223 }, { 224, 255 }, 107 /* sector 5 */ 108 { 256, 319 }, { 320, 383 }, { 384, 447 }, { 448, 511 }, 109 /* sector 6 */ 110 { 512, 639 }, { 640, 767 }, { 768, 895 }, { 896, 1023 }, 111 { 1024, 1151 }, { 1152, 1279 }, { 1280, 1407 }, { 1408, 1535 }, 112 { 1536, 1663 }, { 1664, 1791 }, { 1792, 1919 }, { 1920, 2047 }, 113 { 2048, 2175 }, { 2176, 2303 }, { 2304, 2431 }, { 2432, 2559 }, 114 { 2560, 2687 }, { 2688, 2815 }, { 2816, 2943 }, { 2944, 3071 }, 115 { 3072, 3199 }, { 3200, 3327 }, { 3328, 3455 }, { 3456, 3583 }, 116 { 3584, 3711 }, { 3712, 3839 }, { 3840, 3967 }, { 3968, 4095 }, 117 }; 118 119 #define DE_COEFTAB_DATA(a, b) ((((a) & 0xfff) << 16) | (((b) & 0xfff))) 120 121 static void malidp_generate_gamma_table(struct drm_property_blob *lut_blob, 122 u32 coeffs[MALIDP_COEFFTAB_NUM_COEFFS]) 123 { 124 struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data; 125 int i; 126 127 for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) { 128 u32 a, b, delta_in, out_start, out_end; 129 130 delta_in = segments[i].end - segments[i].start; 131 /* DP has 12-bit internal precision for its LUTs. */ 132 out_start = drm_color_lut_extract(lut[segments[i].start].green, 133 12); 134 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12); 135 a = (delta_in == 0) ? 0 : ((out_end - out_start) * 256) / delta_in; 136 b = out_start; 137 coeffs[i] = DE_COEFTAB_DATA(a, b); 138 } 139 } 140 141 /* 142 * Check if there is a new gamma LUT and if it is of an acceptable size. Also, 143 * reject any LUTs that use distinct red, green, and blue curves. 144 */ 145 static int malidp_crtc_atomic_check_gamma(struct drm_crtc *crtc, 146 struct drm_crtc_state *state) 147 { 148 struct malidp_crtc_state *mc = to_malidp_crtc_state(state); 149 struct drm_color_lut *lut; 150 size_t lut_size; 151 int i; 152 153 if (!state->color_mgmt_changed || !state->gamma_lut) 154 return 0; 155 156 if (crtc->state->gamma_lut && 157 (crtc->state->gamma_lut->base.id == state->gamma_lut->base.id)) 158 return 0; 159 160 if (state->gamma_lut->length % sizeof(struct drm_color_lut)) 161 return -EINVAL; 162 163 lut_size = state->gamma_lut->length / sizeof(struct drm_color_lut); 164 if (lut_size != MALIDP_GAMMA_LUT_SIZE) 165 return -EINVAL; 166 167 lut = (struct drm_color_lut *)state->gamma_lut->data; 168 for (i = 0; i < lut_size; ++i) 169 if (!((lut[i].red == lut[i].green) && 170 (lut[i].red == lut[i].blue))) 171 return -EINVAL; 172 173 if (!state->mode_changed) { 174 int ret; 175 176 state->mode_changed = true; 177 /* 178 * Kerneldoc for drm_atomic_helper_check_modeset mandates that 179 * it be invoked when the driver sets ->mode_changed. Since 180 * changing the gamma LUT doesn't depend on any external 181 * resources, it is safe to call it only once. 182 */ 183 ret = drm_atomic_helper_check_modeset(crtc->dev, state->state); 184 if (ret) 185 return ret; 186 } 187 188 malidp_generate_gamma_table(state->gamma_lut, mc->gamma_coeffs); 189 return 0; 190 } 191 192 /* 193 * Check if there is a new CTM and if it contains valid input. Valid here means 194 * that the number is inside the representable range for a Q3.12 number, 195 * excluding truncating the fractional part of the input data. 196 * 197 * The COLORADJ registers can be changed atomically. 198 */ 199 static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc, 200 struct drm_crtc_state *state) 201 { 202 struct malidp_crtc_state *mc = to_malidp_crtc_state(state); 203 struct drm_color_ctm *ctm; 204 int i; 205 206 if (!state->color_mgmt_changed) 207 return 0; 208 209 if (!state->ctm) 210 return 0; 211 212 if (crtc->state->ctm && (crtc->state->ctm->base.id == 213 state->ctm->base.id)) 214 return 0; 215 216 /* 217 * The size of the ctm is checked in 218 * drm_atomic_replace_property_blob_from_id. 219 */ 220 ctm = (struct drm_color_ctm *)state->ctm->data; 221 for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) { 222 /* Convert from S31.32 to Q3.12. */ 223 s64 val = ctm->matrix[i]; 224 u32 mag = ((((u64)val) & ~BIT_ULL(63)) >> 20) & 225 GENMASK_ULL(14, 0); 226 227 /* 228 * Convert to 2s complement and check the destination's top bit 229 * for overflow. NB: Can't check before converting or it'd 230 * incorrectly reject the case: 231 * sign == 1 232 * mag == 0x2000 233 */ 234 if (val & BIT_ULL(63)) 235 mag = ~mag + 1; 236 if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14))) 237 return -EINVAL; 238 mc->coloradj_coeffs[i] = mag; 239 } 240 241 return 0; 242 } 243 244 static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, 245 struct drm_crtc_state *state) 246 { 247 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 248 struct malidp_hw_device *hwdev = malidp->dev; 249 struct malidp_crtc_state *cs = to_malidp_crtc_state(state); 250 struct malidp_se_config *s = &cs->scaler_config; 251 struct drm_plane *plane; 252 struct videomode vm; 253 const struct drm_plane_state *pstate; 254 u32 h_upscale_factor = 0; /* U16.16 */ 255 u32 v_upscale_factor = 0; /* U16.16 */ 256 u8 scaling = cs->scaled_planes_mask; 257 int ret; 258 259 if (!scaling) { 260 s->scale_enable = false; 261 goto mclk_calc; 262 } 263 264 /* The scaling engine can only handle one plane at a time. */ 265 if (scaling & (scaling - 1)) 266 return -EINVAL; 267 268 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 269 struct malidp_plane *mp = to_malidp_plane(plane); 270 u32 phase; 271 272 if (!(mp->layer->id & scaling)) 273 continue; 274 275 /* 276 * Convert crtc_[w|h] to U32.32, then divide by U16.16 src_[w|h] 277 * to get the U16.16 result. 278 */ 279 h_upscale_factor = div_u64((u64)pstate->crtc_w << 32, 280 pstate->src_w); 281 v_upscale_factor = div_u64((u64)pstate->crtc_h << 32, 282 pstate->src_h); 283 284 s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 || 285 (v_upscale_factor >> 16) >= 2); 286 287 s->input_w = pstate->src_w >> 16; 288 s->input_h = pstate->src_h >> 16; 289 s->output_w = pstate->crtc_w; 290 s->output_h = pstate->crtc_h; 291 292 #define SE_N_PHASE 4 293 #define SE_SHIFT_N_PHASE 12 294 /* Calculate initial_phase and delta_phase for horizontal. */ 295 phase = s->input_w; 296 s->h_init_phase = 297 ((phase << SE_N_PHASE) / s->output_w + 1) / 2; 298 299 phase = s->input_w; 300 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE); 301 s->h_delta_phase = phase / s->output_w; 302 303 /* Same for vertical. */ 304 phase = s->input_h; 305 s->v_init_phase = 306 ((phase << SE_N_PHASE) / s->output_h + 1) / 2; 307 308 phase = s->input_h; 309 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE); 310 s->v_delta_phase = phase / s->output_h; 311 #undef SE_N_PHASE 312 #undef SE_SHIFT_N_PHASE 313 s->plane_src_id = mp->layer->id; 314 } 315 316 s->scale_enable = true; 317 s->hcoeff = malidp_se_select_coeffs(h_upscale_factor); 318 s->vcoeff = malidp_se_select_coeffs(v_upscale_factor); 319 320 mclk_calc: 321 drm_display_mode_to_videomode(&state->adjusted_mode, &vm); 322 ret = hwdev->se_calc_mclk(hwdev, s, &vm); 323 if (ret < 0) 324 return -EINVAL; 325 return 0; 326 } 327 328 static int malidp_crtc_atomic_check(struct drm_crtc *crtc, 329 struct drm_crtc_state *state) 330 { 331 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 332 struct malidp_hw_device *hwdev = malidp->dev; 333 struct drm_plane *plane; 334 const struct drm_plane_state *pstate; 335 u32 rot_mem_free, rot_mem_usable; 336 int rotated_planes = 0; 337 int ret; 338 339 /* 340 * check if there is enough rotation memory available for planes 341 * that need 90° and 270° rotation. Each plane has set its required 342 * memory size in the ->plane_check() callback, here we only make 343 * sure that the sums are less that the total usable memory. 344 * 345 * The rotation memory allocation algorithm (for each plane): 346 * a. If no more rotated planes exist, all remaining rotate 347 * memory in the bank is available for use by the plane. 348 * b. If other rotated planes exist, and plane's layer ID is 349 * DE_VIDEO1, it can use all the memory from first bank if 350 * secondary rotation memory bank is available, otherwise it can 351 * use up to half the bank's memory. 352 * c. If other rotated planes exist, and plane's layer ID is not 353 * DE_VIDEO1, it can use half of the available memory 354 * 355 * Note: this algorithm assumes that the order in which the planes are 356 * checked always has DE_VIDEO1 plane first in the list if it is 357 * rotated. Because that is how we create the planes in the first 358 * place, under current DRM version things work, but if ever the order 359 * in which drm_atomic_crtc_state_for_each_plane() iterates over planes 360 * changes, we need to pre-sort the planes before validation. 361 */ 362 363 /* first count the number of rotated planes */ 364 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 365 if (pstate->rotation & MALIDP_ROTATED_MASK) 366 rotated_planes++; 367 } 368 369 rot_mem_free = hwdev->rotation_memory[0]; 370 /* 371 * if we have more than 1 plane using rotation memory, use the second 372 * block of rotation memory as well 373 */ 374 if (rotated_planes > 1) 375 rot_mem_free += hwdev->rotation_memory[1]; 376 377 /* now validate the rotation memory requirements */ 378 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 379 struct malidp_plane *mp = to_malidp_plane(plane); 380 struct malidp_plane_state *ms = to_malidp_plane_state(pstate); 381 382 if (pstate->rotation & MALIDP_ROTATED_MASK) { 383 /* process current plane */ 384 rotated_planes--; 385 386 if (!rotated_planes) { 387 /* no more rotated planes, we can use what's left */ 388 rot_mem_usable = rot_mem_free; 389 } else { 390 if ((mp->layer->id != DE_VIDEO1) || 391 (hwdev->rotation_memory[1] == 0)) 392 rot_mem_usable = rot_mem_free / 2; 393 else 394 rot_mem_usable = hwdev->rotation_memory[0]; 395 } 396 397 rot_mem_free -= rot_mem_usable; 398 399 if (ms->rotmem_size > rot_mem_usable) 400 return -EINVAL; 401 } 402 } 403 404 ret = malidp_crtc_atomic_check_gamma(crtc, state); 405 ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, state); 406 ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, state); 407 408 return ret; 409 } 410 411 static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = { 412 .mode_valid = malidp_crtc_mode_valid, 413 .atomic_check = malidp_crtc_atomic_check, 414 .atomic_enable = malidp_crtc_atomic_enable, 415 .atomic_disable = malidp_crtc_atomic_disable, 416 }; 417 418 static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc *crtc) 419 { 420 struct malidp_crtc_state *state, *old_state; 421 422 if (WARN_ON(!crtc->state)) 423 return NULL; 424 425 old_state = to_malidp_crtc_state(crtc->state); 426 state = kmalloc(sizeof(*state), GFP_KERNEL); 427 if (!state) 428 return NULL; 429 430 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 431 memcpy(state->gamma_coeffs, old_state->gamma_coeffs, 432 sizeof(state->gamma_coeffs)); 433 memcpy(state->coloradj_coeffs, old_state->coloradj_coeffs, 434 sizeof(state->coloradj_coeffs)); 435 memcpy(&state->scaler_config, &old_state->scaler_config, 436 sizeof(state->scaler_config)); 437 state->scaled_planes_mask = 0; 438 439 return &state->base; 440 } 441 442 static void malidp_crtc_reset(struct drm_crtc *crtc) 443 { 444 struct malidp_crtc_state *state = NULL; 445 446 if (crtc->state) { 447 state = to_malidp_crtc_state(crtc->state); 448 __drm_atomic_helper_crtc_destroy_state(crtc->state); 449 } 450 451 kfree(state); 452 state = kzalloc(sizeof(*state), GFP_KERNEL); 453 if (state) { 454 crtc->state = &state->base; 455 crtc->state->crtc = crtc; 456 } 457 } 458 459 static void malidp_crtc_destroy_state(struct drm_crtc *crtc, 460 struct drm_crtc_state *state) 461 { 462 struct malidp_crtc_state *mali_state = NULL; 463 464 if (state) { 465 mali_state = to_malidp_crtc_state(state); 466 __drm_atomic_helper_crtc_destroy_state(state); 467 } 468 469 kfree(mali_state); 470 } 471 472 static int malidp_crtc_enable_vblank(struct drm_crtc *crtc) 473 { 474 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 475 struct malidp_hw_device *hwdev = malidp->dev; 476 477 malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK, 478 hwdev->map.de_irq_map.vsync_irq); 479 return 0; 480 } 481 482 static void malidp_crtc_disable_vblank(struct drm_crtc *crtc) 483 { 484 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 485 struct malidp_hw_device *hwdev = malidp->dev; 486 487 malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 488 hwdev->map.de_irq_map.vsync_irq); 489 } 490 491 static const struct drm_crtc_funcs malidp_crtc_funcs = { 492 .gamma_set = drm_atomic_helper_legacy_gamma_set, 493 .destroy = drm_crtc_cleanup, 494 .set_config = drm_atomic_helper_set_config, 495 .page_flip = drm_atomic_helper_page_flip, 496 .reset = malidp_crtc_reset, 497 .atomic_duplicate_state = malidp_crtc_duplicate_state, 498 .atomic_destroy_state = malidp_crtc_destroy_state, 499 .enable_vblank = malidp_crtc_enable_vblank, 500 .disable_vblank = malidp_crtc_disable_vblank, 501 }; 502 503 int malidp_crtc_init(struct drm_device *drm) 504 { 505 struct malidp_drm *malidp = drm->dev_private; 506 struct drm_plane *primary = NULL, *plane; 507 int ret; 508 509 ret = malidp_de_planes_init(drm); 510 if (ret < 0) { 511 DRM_ERROR("Failed to initialise planes\n"); 512 return ret; 513 } 514 515 drm_for_each_plane(plane, drm) { 516 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 517 primary = plane; 518 break; 519 } 520 } 521 522 if (!primary) { 523 DRM_ERROR("no primary plane found\n"); 524 ret = -EINVAL; 525 goto crtc_cleanup_planes; 526 } 527 528 ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL, 529 &malidp_crtc_funcs, NULL); 530 if (ret) 531 goto crtc_cleanup_planes; 532 533 drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs); 534 drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE); 535 /* No inverse-gamma: it is per-plane. */ 536 drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE); 537 538 malidp_se_set_enh_coeffs(malidp->dev); 539 540 return 0; 541 542 crtc_cleanup_planes: 543 malidp_de_planes_destroy(drm); 544 545 return ret; 546 } 547