1 /* 2 * Copyright (C) 2013-2015 ARM Limited 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file COPYING in the main directory of this archive 7 * for more details. 8 * 9 * ARM HDLCD Driver 10 */ 11 12 #include <linux/module.h> 13 #include <linux/spinlock.h> 14 #include <linux/clk.h> 15 #include <linux/component.h> 16 #include <linux/list.h> 17 #include <linux/of_graph.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/pm_runtime.h> 20 21 #include <drm/drmP.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_crtc.h> 24 #include <drm/drm_crtc_helper.h> 25 #include <drm/drm_fb_helper.h> 26 #include <drm/drm_fb_cma_helper.h> 27 #include <drm/drm_gem_cma_helper.h> 28 #include <drm/drm_of.h> 29 30 #include "hdlcd_drv.h" 31 #include "hdlcd_regs.h" 32 33 static int hdlcd_load(struct drm_device *drm, unsigned long flags) 34 { 35 struct hdlcd_drm_private *hdlcd = drm->dev_private; 36 struct platform_device *pdev = to_platform_device(drm->dev); 37 struct resource *res; 38 u32 version; 39 int ret; 40 41 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk"); 42 if (IS_ERR(hdlcd->clk)) 43 return PTR_ERR(hdlcd->clk); 44 45 #ifdef CONFIG_DEBUG_FS 46 atomic_set(&hdlcd->buffer_underrun_count, 0); 47 atomic_set(&hdlcd->bus_error_count, 0); 48 atomic_set(&hdlcd->vsync_count, 0); 49 atomic_set(&hdlcd->dma_end_count, 0); 50 #endif 51 52 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 53 hdlcd->mmio = devm_ioremap_resource(drm->dev, res); 54 if (IS_ERR(hdlcd->mmio)) { 55 DRM_ERROR("failed to map control registers area\n"); 56 ret = PTR_ERR(hdlcd->mmio); 57 hdlcd->mmio = NULL; 58 return ret; 59 } 60 61 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION); 62 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) { 63 DRM_ERROR("unknown product id: 0x%x\n", version); 64 return -EINVAL; 65 } 66 DRM_INFO("found ARM HDLCD version r%dp%d\n", 67 (version & HDLCD_VERSION_MAJOR_MASK) >> 8, 68 version & HDLCD_VERSION_MINOR_MASK); 69 70 /* Get the optional framebuffer memory resource */ 71 ret = of_reserved_mem_device_init(drm->dev); 72 if (ret && ret != -ENODEV) 73 return ret; 74 75 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); 76 if (ret) 77 goto setup_fail; 78 79 ret = hdlcd_setup_crtc(drm); 80 if (ret < 0) { 81 DRM_ERROR("failed to create crtc\n"); 82 goto setup_fail; 83 } 84 85 ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); 86 if (ret < 0) { 87 DRM_ERROR("failed to install IRQ handler\n"); 88 goto irq_fail; 89 } 90 91 return 0; 92 93 irq_fail: 94 drm_crtc_cleanup(&hdlcd->crtc); 95 setup_fail: 96 of_reserved_mem_device_release(drm->dev); 97 98 return ret; 99 } 100 101 static void hdlcd_fb_output_poll_changed(struct drm_device *drm) 102 { 103 struct hdlcd_drm_private *hdlcd = drm->dev_private; 104 105 drm_fbdev_cma_hotplug_event(hdlcd->fbdev); 106 } 107 108 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = { 109 .fb_create = drm_fb_cma_create, 110 .output_poll_changed = hdlcd_fb_output_poll_changed, 111 .atomic_check = drm_atomic_helper_check, 112 .atomic_commit = drm_atomic_helper_commit, 113 }; 114 115 static void hdlcd_setup_mode_config(struct drm_device *drm) 116 { 117 drm_mode_config_init(drm); 118 drm->mode_config.min_width = 0; 119 drm->mode_config.min_height = 0; 120 drm->mode_config.max_width = HDLCD_MAX_XRES; 121 drm->mode_config.max_height = HDLCD_MAX_YRES; 122 drm->mode_config.funcs = &hdlcd_mode_config_funcs; 123 } 124 125 static void hdlcd_lastclose(struct drm_device *drm) 126 { 127 struct hdlcd_drm_private *hdlcd = drm->dev_private; 128 129 drm_fbdev_cma_restore_mode(hdlcd->fbdev); 130 } 131 132 static irqreturn_t hdlcd_irq(int irq, void *arg) 133 { 134 struct drm_device *drm = arg; 135 struct hdlcd_drm_private *hdlcd = drm->dev_private; 136 unsigned long irq_status; 137 138 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS); 139 140 #ifdef CONFIG_DEBUG_FS 141 if (irq_status & HDLCD_INTERRUPT_UNDERRUN) 142 atomic_inc(&hdlcd->buffer_underrun_count); 143 144 if (irq_status & HDLCD_INTERRUPT_DMA_END) 145 atomic_inc(&hdlcd->dma_end_count); 146 147 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR) 148 atomic_inc(&hdlcd->bus_error_count); 149 150 if (irq_status & HDLCD_INTERRUPT_VSYNC) 151 atomic_inc(&hdlcd->vsync_count); 152 153 #endif 154 if (irq_status & HDLCD_INTERRUPT_VSYNC) 155 drm_crtc_handle_vblank(&hdlcd->crtc); 156 157 /* acknowledge interrupt(s) */ 158 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status); 159 160 return IRQ_HANDLED; 161 } 162 163 static void hdlcd_irq_preinstall(struct drm_device *drm) 164 { 165 struct hdlcd_drm_private *hdlcd = drm->dev_private; 166 /* Ensure interrupts are disabled */ 167 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0); 168 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0); 169 } 170 171 static int hdlcd_irq_postinstall(struct drm_device *drm) 172 { 173 #ifdef CONFIG_DEBUG_FS 174 struct hdlcd_drm_private *hdlcd = drm->dev_private; 175 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 176 177 /* enable debug interrupts */ 178 irq_mask |= HDLCD_DEBUG_INT_MASK; 179 180 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); 181 #endif 182 return 0; 183 } 184 185 static void hdlcd_irq_uninstall(struct drm_device *drm) 186 { 187 struct hdlcd_drm_private *hdlcd = drm->dev_private; 188 /* disable all the interrupts that we might have enabled */ 189 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 190 191 #ifdef CONFIG_DEBUG_FS 192 /* disable debug interrupts */ 193 irq_mask &= ~HDLCD_DEBUG_INT_MASK; 194 #endif 195 196 /* disable vsync interrupts */ 197 irq_mask &= ~HDLCD_INTERRUPT_VSYNC; 198 199 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); 200 } 201 202 #ifdef CONFIG_DEBUG_FS 203 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg) 204 { 205 struct drm_info_node *node = (struct drm_info_node *)m->private; 206 struct drm_device *drm = node->minor->dev; 207 struct hdlcd_drm_private *hdlcd = drm->dev_private; 208 209 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count)); 210 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count)); 211 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count)); 212 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count)); 213 return 0; 214 } 215 216 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg) 217 { 218 struct drm_info_node *node = (struct drm_info_node *)m->private; 219 struct drm_device *drm = node->minor->dev; 220 struct hdlcd_drm_private *hdlcd = drm->dev_private; 221 unsigned long clkrate = clk_get_rate(hdlcd->clk); 222 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000; 223 224 seq_printf(m, "hw : %lu\n", clkrate); 225 seq_printf(m, "mode: %lu\n", mode_clock); 226 return 0; 227 } 228 229 static struct drm_info_list hdlcd_debugfs_list[] = { 230 { "interrupt_count", hdlcd_show_underrun_count, 0 }, 231 { "clocks", hdlcd_show_pxlclock, 0 }, 232 { "fb", drm_fb_cma_debugfs_show, 0 }, 233 }; 234 235 static int hdlcd_debugfs_init(struct drm_minor *minor) 236 { 237 return drm_debugfs_create_files(hdlcd_debugfs_list, 238 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor); 239 } 240 #endif 241 242 DEFINE_DRM_GEM_CMA_FOPS(fops); 243 244 static struct drm_driver hdlcd_driver = { 245 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | 246 DRIVER_MODESET | DRIVER_PRIME | 247 DRIVER_ATOMIC, 248 .lastclose = hdlcd_lastclose, 249 .irq_handler = hdlcd_irq, 250 .irq_preinstall = hdlcd_irq_preinstall, 251 .irq_postinstall = hdlcd_irq_postinstall, 252 .irq_uninstall = hdlcd_irq_uninstall, 253 .gem_free_object_unlocked = drm_gem_cma_free_object, 254 .gem_vm_ops = &drm_gem_cma_vm_ops, 255 .dumb_create = drm_gem_cma_dumb_create, 256 .dumb_map_offset = drm_gem_cma_dumb_map_offset, 257 .dumb_destroy = drm_gem_dumb_destroy, 258 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 259 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 260 .gem_prime_export = drm_gem_prime_export, 261 .gem_prime_import = drm_gem_prime_import, 262 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 263 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 264 .gem_prime_vmap = drm_gem_cma_prime_vmap, 265 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 266 .gem_prime_mmap = drm_gem_cma_prime_mmap, 267 #ifdef CONFIG_DEBUG_FS 268 .debugfs_init = hdlcd_debugfs_init, 269 #endif 270 .fops = &fops, 271 .name = "hdlcd", 272 .desc = "ARM HDLCD Controller DRM", 273 .date = "20151021", 274 .major = 1, 275 .minor = 0, 276 }; 277 278 static int hdlcd_drm_bind(struct device *dev) 279 { 280 struct drm_device *drm; 281 struct hdlcd_drm_private *hdlcd; 282 int ret; 283 284 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL); 285 if (!hdlcd) 286 return -ENOMEM; 287 288 drm = drm_dev_alloc(&hdlcd_driver, dev); 289 if (IS_ERR(drm)) 290 return PTR_ERR(drm); 291 292 drm->dev_private = hdlcd; 293 dev_set_drvdata(dev, drm); 294 295 hdlcd_setup_mode_config(drm); 296 ret = hdlcd_load(drm, 0); 297 if (ret) 298 goto err_free; 299 300 ret = component_bind_all(dev, drm); 301 if (ret) { 302 DRM_ERROR("Failed to bind all components\n"); 303 goto err_unload; 304 } 305 306 ret = pm_runtime_set_active(dev); 307 if (ret) 308 goto err_pm_active; 309 310 pm_runtime_enable(dev); 311 312 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 313 if (ret < 0) { 314 DRM_ERROR("failed to initialise vblank\n"); 315 goto err_vblank; 316 } 317 318 drm_mode_config_reset(drm); 319 drm_kms_helper_poll_init(drm); 320 321 hdlcd->fbdev = drm_fbdev_cma_init(drm, 32, 322 drm->mode_config.num_connector); 323 324 if (IS_ERR(hdlcd->fbdev)) { 325 ret = PTR_ERR(hdlcd->fbdev); 326 hdlcd->fbdev = NULL; 327 goto err_fbdev; 328 } 329 330 ret = drm_dev_register(drm, 0); 331 if (ret) 332 goto err_register; 333 334 return 0; 335 336 err_register: 337 if (hdlcd->fbdev) { 338 drm_fbdev_cma_fini(hdlcd->fbdev); 339 hdlcd->fbdev = NULL; 340 } 341 err_fbdev: 342 drm_kms_helper_poll_fini(drm); 343 drm_vblank_cleanup(drm); 344 err_vblank: 345 pm_runtime_disable(drm->dev); 346 err_pm_active: 347 component_unbind_all(dev, drm); 348 err_unload: 349 drm_irq_uninstall(drm); 350 of_reserved_mem_device_release(drm->dev); 351 err_free: 352 drm_mode_config_cleanup(drm); 353 dev_set_drvdata(dev, NULL); 354 drm_dev_unref(drm); 355 356 return ret; 357 } 358 359 static void hdlcd_drm_unbind(struct device *dev) 360 { 361 struct drm_device *drm = dev_get_drvdata(dev); 362 struct hdlcd_drm_private *hdlcd = drm->dev_private; 363 364 drm_dev_unregister(drm); 365 if (hdlcd->fbdev) { 366 drm_fbdev_cma_fini(hdlcd->fbdev); 367 hdlcd->fbdev = NULL; 368 } 369 drm_kms_helper_poll_fini(drm); 370 component_unbind_all(dev, drm); 371 drm_vblank_cleanup(drm); 372 pm_runtime_get_sync(drm->dev); 373 drm_irq_uninstall(drm); 374 pm_runtime_put_sync(drm->dev); 375 pm_runtime_disable(drm->dev); 376 of_reserved_mem_device_release(drm->dev); 377 drm_mode_config_cleanup(drm); 378 drm_dev_unref(drm); 379 drm->dev_private = NULL; 380 dev_set_drvdata(dev, NULL); 381 } 382 383 static const struct component_master_ops hdlcd_master_ops = { 384 .bind = hdlcd_drm_bind, 385 .unbind = hdlcd_drm_unbind, 386 }; 387 388 static int compare_dev(struct device *dev, void *data) 389 { 390 return dev->of_node == data; 391 } 392 393 static int hdlcd_probe(struct platform_device *pdev) 394 { 395 struct device_node *port; 396 struct component_match *match = NULL; 397 398 /* there is only one output port inside each device, find it */ 399 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); 400 if (!port) 401 return -ENODEV; 402 403 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port); 404 of_node_put(port); 405 406 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops, 407 match); 408 } 409 410 static int hdlcd_remove(struct platform_device *pdev) 411 { 412 component_master_del(&pdev->dev, &hdlcd_master_ops); 413 return 0; 414 } 415 416 static const struct of_device_id hdlcd_of_match[] = { 417 { .compatible = "arm,hdlcd" }, 418 {}, 419 }; 420 MODULE_DEVICE_TABLE(of, hdlcd_of_match); 421 422 static int __maybe_unused hdlcd_pm_suspend(struct device *dev) 423 { 424 struct drm_device *drm = dev_get_drvdata(dev); 425 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL; 426 427 if (!hdlcd) 428 return 0; 429 430 drm_kms_helper_poll_disable(drm); 431 432 hdlcd->state = drm_atomic_helper_suspend(drm); 433 if (IS_ERR(hdlcd->state)) { 434 drm_kms_helper_poll_enable(drm); 435 return PTR_ERR(hdlcd->state); 436 } 437 438 return 0; 439 } 440 441 static int __maybe_unused hdlcd_pm_resume(struct device *dev) 442 { 443 struct drm_device *drm = dev_get_drvdata(dev); 444 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL; 445 446 if (!hdlcd) 447 return 0; 448 449 drm_atomic_helper_resume(drm, hdlcd->state); 450 drm_kms_helper_poll_enable(drm); 451 pm_runtime_set_active(dev); 452 453 return 0; 454 } 455 456 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume); 457 458 static struct platform_driver hdlcd_platform_driver = { 459 .probe = hdlcd_probe, 460 .remove = hdlcd_remove, 461 .driver = { 462 .name = "hdlcd", 463 .pm = &hdlcd_pm_ops, 464 .of_match_table = hdlcd_of_match, 465 }, 466 }; 467 468 module_platform_driver(hdlcd_platform_driver); 469 470 MODULE_AUTHOR("Liviu Dudau"); 471 MODULE_DESCRIPTION("ARM HDLCD DRM driver"); 472 MODULE_LICENSE("GPL v2"); 473