1 /* 2 * Copyright (C) 2013-2015 ARM Limited 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file COPYING in the main directory of this archive 7 * for more details. 8 * 9 * ARM HDLCD Driver 10 */ 11 12 #include <linux/module.h> 13 #include <linux/spinlock.h> 14 #include <linux/clk.h> 15 #include <linux/component.h> 16 #include <linux/console.h> 17 #include <linux/list.h> 18 #include <linux/of_graph.h> 19 #include <linux/of_reserved_mem.h> 20 #include <linux/pm_runtime.h> 21 22 #include <drm/drmP.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_fb_helper.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_gem_cma_helper.h> 29 #include <drm/drm_gem_framebuffer_helper.h> 30 #include <drm/drm_modeset_helper.h> 31 #include <drm/drm_of.h> 32 33 #include "hdlcd_drv.h" 34 #include "hdlcd_regs.h" 35 36 static int hdlcd_load(struct drm_device *drm, unsigned long flags) 37 { 38 struct hdlcd_drm_private *hdlcd = drm->dev_private; 39 struct platform_device *pdev = to_platform_device(drm->dev); 40 struct resource *res; 41 u32 version; 42 int ret; 43 44 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk"); 45 if (IS_ERR(hdlcd->clk)) 46 return PTR_ERR(hdlcd->clk); 47 48 #ifdef CONFIG_DEBUG_FS 49 atomic_set(&hdlcd->buffer_underrun_count, 0); 50 atomic_set(&hdlcd->bus_error_count, 0); 51 atomic_set(&hdlcd->vsync_count, 0); 52 atomic_set(&hdlcd->dma_end_count, 0); 53 #endif 54 55 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 56 hdlcd->mmio = devm_ioremap_resource(drm->dev, res); 57 if (IS_ERR(hdlcd->mmio)) { 58 DRM_ERROR("failed to map control registers area\n"); 59 ret = PTR_ERR(hdlcd->mmio); 60 hdlcd->mmio = NULL; 61 return ret; 62 } 63 64 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION); 65 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) { 66 DRM_ERROR("unknown product id: 0x%x\n", version); 67 return -EINVAL; 68 } 69 DRM_INFO("found ARM HDLCD version r%dp%d\n", 70 (version & HDLCD_VERSION_MAJOR_MASK) >> 8, 71 version & HDLCD_VERSION_MINOR_MASK); 72 73 /* Get the optional framebuffer memory resource */ 74 ret = of_reserved_mem_device_init(drm->dev); 75 if (ret && ret != -ENODEV) 76 return ret; 77 78 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); 79 if (ret) 80 goto setup_fail; 81 82 ret = hdlcd_setup_crtc(drm); 83 if (ret < 0) { 84 DRM_ERROR("failed to create crtc\n"); 85 goto setup_fail; 86 } 87 88 ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); 89 if (ret < 0) { 90 DRM_ERROR("failed to install IRQ handler\n"); 91 goto irq_fail; 92 } 93 94 return 0; 95 96 irq_fail: 97 drm_crtc_cleanup(&hdlcd->crtc); 98 setup_fail: 99 of_reserved_mem_device_release(drm->dev); 100 101 return ret; 102 } 103 104 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = { 105 .fb_create = drm_gem_fb_create, 106 .output_poll_changed = drm_fb_helper_output_poll_changed, 107 .atomic_check = drm_atomic_helper_check, 108 .atomic_commit = drm_atomic_helper_commit, 109 }; 110 111 static void hdlcd_setup_mode_config(struct drm_device *drm) 112 { 113 drm_mode_config_init(drm); 114 drm->mode_config.min_width = 0; 115 drm->mode_config.min_height = 0; 116 drm->mode_config.max_width = HDLCD_MAX_XRES; 117 drm->mode_config.max_height = HDLCD_MAX_YRES; 118 drm->mode_config.funcs = &hdlcd_mode_config_funcs; 119 } 120 121 static irqreturn_t hdlcd_irq(int irq, void *arg) 122 { 123 struct drm_device *drm = arg; 124 struct hdlcd_drm_private *hdlcd = drm->dev_private; 125 unsigned long irq_status; 126 127 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS); 128 129 #ifdef CONFIG_DEBUG_FS 130 if (irq_status & HDLCD_INTERRUPT_UNDERRUN) 131 atomic_inc(&hdlcd->buffer_underrun_count); 132 133 if (irq_status & HDLCD_INTERRUPT_DMA_END) 134 atomic_inc(&hdlcd->dma_end_count); 135 136 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR) 137 atomic_inc(&hdlcd->bus_error_count); 138 139 if (irq_status & HDLCD_INTERRUPT_VSYNC) 140 atomic_inc(&hdlcd->vsync_count); 141 142 #endif 143 if (irq_status & HDLCD_INTERRUPT_VSYNC) 144 drm_crtc_handle_vblank(&hdlcd->crtc); 145 146 /* acknowledge interrupt(s) */ 147 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status); 148 149 return IRQ_HANDLED; 150 } 151 152 static void hdlcd_irq_preinstall(struct drm_device *drm) 153 { 154 struct hdlcd_drm_private *hdlcd = drm->dev_private; 155 /* Ensure interrupts are disabled */ 156 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0); 157 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0); 158 } 159 160 static int hdlcd_irq_postinstall(struct drm_device *drm) 161 { 162 #ifdef CONFIG_DEBUG_FS 163 struct hdlcd_drm_private *hdlcd = drm->dev_private; 164 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 165 166 /* enable debug interrupts */ 167 irq_mask |= HDLCD_DEBUG_INT_MASK; 168 169 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); 170 #endif 171 return 0; 172 } 173 174 static void hdlcd_irq_uninstall(struct drm_device *drm) 175 { 176 struct hdlcd_drm_private *hdlcd = drm->dev_private; 177 /* disable all the interrupts that we might have enabled */ 178 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 179 180 #ifdef CONFIG_DEBUG_FS 181 /* disable debug interrupts */ 182 irq_mask &= ~HDLCD_DEBUG_INT_MASK; 183 #endif 184 185 /* disable vsync interrupts */ 186 irq_mask &= ~HDLCD_INTERRUPT_VSYNC; 187 188 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); 189 } 190 191 #ifdef CONFIG_DEBUG_FS 192 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg) 193 { 194 struct drm_info_node *node = (struct drm_info_node *)m->private; 195 struct drm_device *drm = node->minor->dev; 196 struct hdlcd_drm_private *hdlcd = drm->dev_private; 197 198 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count)); 199 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count)); 200 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count)); 201 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count)); 202 return 0; 203 } 204 205 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg) 206 { 207 struct drm_info_node *node = (struct drm_info_node *)m->private; 208 struct drm_device *drm = node->minor->dev; 209 struct hdlcd_drm_private *hdlcd = drm->dev_private; 210 unsigned long clkrate = clk_get_rate(hdlcd->clk); 211 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000; 212 213 seq_printf(m, "hw : %lu\n", clkrate); 214 seq_printf(m, "mode: %lu\n", mode_clock); 215 return 0; 216 } 217 218 static struct drm_info_list hdlcd_debugfs_list[] = { 219 { "interrupt_count", hdlcd_show_underrun_count, 0 }, 220 { "clocks", hdlcd_show_pxlclock, 0 }, 221 }; 222 223 static int hdlcd_debugfs_init(struct drm_minor *minor) 224 { 225 return drm_debugfs_create_files(hdlcd_debugfs_list, 226 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor); 227 } 228 #endif 229 230 DEFINE_DRM_GEM_CMA_FOPS(fops); 231 232 static struct drm_driver hdlcd_driver = { 233 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | 234 DRIVER_MODESET | DRIVER_PRIME | 235 DRIVER_ATOMIC, 236 .lastclose = drm_fb_helper_lastclose, 237 .irq_handler = hdlcd_irq, 238 .irq_preinstall = hdlcd_irq_preinstall, 239 .irq_postinstall = hdlcd_irq_postinstall, 240 .irq_uninstall = hdlcd_irq_uninstall, 241 .gem_free_object_unlocked = drm_gem_cma_free_object, 242 .gem_print_info = drm_gem_cma_print_info, 243 .gem_vm_ops = &drm_gem_cma_vm_ops, 244 .dumb_create = drm_gem_cma_dumb_create, 245 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 246 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 247 .gem_prime_export = drm_gem_prime_export, 248 .gem_prime_import = drm_gem_prime_import, 249 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 250 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 251 .gem_prime_vmap = drm_gem_cma_prime_vmap, 252 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 253 .gem_prime_mmap = drm_gem_cma_prime_mmap, 254 #ifdef CONFIG_DEBUG_FS 255 .debugfs_init = hdlcd_debugfs_init, 256 #endif 257 .fops = &fops, 258 .name = "hdlcd", 259 .desc = "ARM HDLCD Controller DRM", 260 .date = "20151021", 261 .major = 1, 262 .minor = 0, 263 }; 264 265 static int hdlcd_drm_bind(struct device *dev) 266 { 267 struct drm_device *drm; 268 struct hdlcd_drm_private *hdlcd; 269 int ret; 270 271 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL); 272 if (!hdlcd) 273 return -ENOMEM; 274 275 drm = drm_dev_alloc(&hdlcd_driver, dev); 276 if (IS_ERR(drm)) 277 return PTR_ERR(drm); 278 279 drm->dev_private = hdlcd; 280 dev_set_drvdata(dev, drm); 281 282 hdlcd_setup_mode_config(drm); 283 ret = hdlcd_load(drm, 0); 284 if (ret) 285 goto err_free; 286 287 /* Set the CRTC's port so that the encoder component can find it */ 288 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); 289 290 ret = component_bind_all(dev, drm); 291 if (ret) { 292 DRM_ERROR("Failed to bind all components\n"); 293 goto err_unload; 294 } 295 296 ret = pm_runtime_set_active(dev); 297 if (ret) 298 goto err_pm_active; 299 300 pm_runtime_enable(dev); 301 302 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 303 if (ret < 0) { 304 DRM_ERROR("failed to initialise vblank\n"); 305 goto err_vblank; 306 } 307 308 drm_mode_config_reset(drm); 309 drm_kms_helper_poll_init(drm); 310 311 ret = drm_fb_cma_fbdev_init(drm, 32, 0); 312 if (ret) 313 goto err_fbdev; 314 315 ret = drm_dev_register(drm, 0); 316 if (ret) 317 goto err_register; 318 319 return 0; 320 321 err_register: 322 drm_fb_cma_fbdev_fini(drm); 323 err_fbdev: 324 drm_kms_helper_poll_fini(drm); 325 err_vblank: 326 pm_runtime_disable(drm->dev); 327 err_pm_active: 328 drm_atomic_helper_shutdown(drm); 329 component_unbind_all(dev, drm); 330 err_unload: 331 of_node_put(hdlcd->crtc.port); 332 hdlcd->crtc.port = NULL; 333 drm_irq_uninstall(drm); 334 of_reserved_mem_device_release(drm->dev); 335 err_free: 336 drm_mode_config_cleanup(drm); 337 dev_set_drvdata(dev, NULL); 338 drm_dev_put(drm); 339 340 return ret; 341 } 342 343 static void hdlcd_drm_unbind(struct device *dev) 344 { 345 struct drm_device *drm = dev_get_drvdata(dev); 346 struct hdlcd_drm_private *hdlcd = drm->dev_private; 347 348 drm_dev_unregister(drm); 349 drm_fb_cma_fbdev_fini(drm); 350 drm_kms_helper_poll_fini(drm); 351 component_unbind_all(dev, drm); 352 of_node_put(hdlcd->crtc.port); 353 hdlcd->crtc.port = NULL; 354 pm_runtime_get_sync(dev); 355 drm_crtc_vblank_off(&hdlcd->crtc); 356 drm_irq_uninstall(drm); 357 drm_atomic_helper_shutdown(drm); 358 pm_runtime_put(dev); 359 if (pm_runtime_enabled(dev)) 360 pm_runtime_disable(dev); 361 of_reserved_mem_device_release(dev); 362 drm_mode_config_cleanup(drm); 363 drm->dev_private = NULL; 364 dev_set_drvdata(dev, NULL); 365 drm_dev_put(drm); 366 } 367 368 static const struct component_master_ops hdlcd_master_ops = { 369 .bind = hdlcd_drm_bind, 370 .unbind = hdlcd_drm_unbind, 371 }; 372 373 static int compare_dev(struct device *dev, void *data) 374 { 375 return dev->of_node == data; 376 } 377 378 static int hdlcd_probe(struct platform_device *pdev) 379 { 380 struct device_node *port; 381 struct component_match *match = NULL; 382 383 /* there is only one output port inside each device, find it */ 384 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); 385 if (!port) 386 return -ENODEV; 387 388 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port); 389 of_node_put(port); 390 391 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops, 392 match); 393 } 394 395 static int hdlcd_remove(struct platform_device *pdev) 396 { 397 component_master_del(&pdev->dev, &hdlcd_master_ops); 398 return 0; 399 } 400 401 static const struct of_device_id hdlcd_of_match[] = { 402 { .compatible = "arm,hdlcd" }, 403 {}, 404 }; 405 MODULE_DEVICE_TABLE(of, hdlcd_of_match); 406 407 static int __maybe_unused hdlcd_pm_suspend(struct device *dev) 408 { 409 struct drm_device *drm = dev_get_drvdata(dev); 410 411 return drm_mode_config_helper_suspend(drm); 412 } 413 414 static int __maybe_unused hdlcd_pm_resume(struct device *dev) 415 { 416 struct drm_device *drm = dev_get_drvdata(dev); 417 418 drm_mode_config_helper_resume(drm); 419 420 return 0; 421 } 422 423 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume); 424 425 static struct platform_driver hdlcd_platform_driver = { 426 .probe = hdlcd_probe, 427 .remove = hdlcd_remove, 428 .driver = { 429 .name = "hdlcd", 430 .pm = &hdlcd_pm_ops, 431 .of_match_table = hdlcd_of_match, 432 }, 433 }; 434 435 module_platform_driver(hdlcd_platform_driver); 436 437 MODULE_AUTHOR("Liviu Dudau"); 438 MODULE_DESCRIPTION("ARM HDLCD DRM driver"); 439 MODULE_LICENSE("GPL v2"); 440