1 /* 2 * Copyright (C) 2013-2015 ARM Limited 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file COPYING in the main directory of this archive 7 * for more details. 8 * 9 * ARM HDLCD Driver 10 */ 11 12 #include <linux/module.h> 13 #include <linux/spinlock.h> 14 #include <linux/clk.h> 15 #include <linux/component.h> 16 #include <linux/console.h> 17 #include <linux/list.h> 18 #include <linux/of_graph.h> 19 #include <linux/of_reserved_mem.h> 20 #include <linux/pm_runtime.h> 21 22 #include <drm/drmP.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_fb_cma_helper.h> 26 #include <drm/drm_fb_helper.h> 27 #include <drm/drm_gem_cma_helper.h> 28 #include <drm/drm_gem_framebuffer_helper.h> 29 #include <drm/drm_modeset_helper.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_probe_helper.h> 32 33 #include "hdlcd_drv.h" 34 #include "hdlcd_regs.h" 35 36 static int hdlcd_load(struct drm_device *drm, unsigned long flags) 37 { 38 struct hdlcd_drm_private *hdlcd = drm->dev_private; 39 struct platform_device *pdev = to_platform_device(drm->dev); 40 struct resource *res; 41 u32 version; 42 int ret; 43 44 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk"); 45 if (IS_ERR(hdlcd->clk)) 46 return PTR_ERR(hdlcd->clk); 47 48 #ifdef CONFIG_DEBUG_FS 49 atomic_set(&hdlcd->buffer_underrun_count, 0); 50 atomic_set(&hdlcd->bus_error_count, 0); 51 atomic_set(&hdlcd->vsync_count, 0); 52 atomic_set(&hdlcd->dma_end_count, 0); 53 #endif 54 55 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 56 hdlcd->mmio = devm_ioremap_resource(drm->dev, res); 57 if (IS_ERR(hdlcd->mmio)) { 58 DRM_ERROR("failed to map control registers area\n"); 59 ret = PTR_ERR(hdlcd->mmio); 60 hdlcd->mmio = NULL; 61 return ret; 62 } 63 64 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION); 65 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) { 66 DRM_ERROR("unknown product id: 0x%x\n", version); 67 return -EINVAL; 68 } 69 DRM_INFO("found ARM HDLCD version r%dp%d\n", 70 (version & HDLCD_VERSION_MAJOR_MASK) >> 8, 71 version & HDLCD_VERSION_MINOR_MASK); 72 73 /* Get the optional framebuffer memory resource */ 74 ret = of_reserved_mem_device_init(drm->dev); 75 if (ret && ret != -ENODEV) 76 return ret; 77 78 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); 79 if (ret) 80 goto setup_fail; 81 82 ret = hdlcd_setup_crtc(drm); 83 if (ret < 0) { 84 DRM_ERROR("failed to create crtc\n"); 85 goto setup_fail; 86 } 87 88 ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); 89 if (ret < 0) { 90 DRM_ERROR("failed to install IRQ handler\n"); 91 goto irq_fail; 92 } 93 94 return 0; 95 96 irq_fail: 97 drm_crtc_cleanup(&hdlcd->crtc); 98 setup_fail: 99 of_reserved_mem_device_release(drm->dev); 100 101 return ret; 102 } 103 104 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = { 105 .fb_create = drm_gem_fb_create, 106 .atomic_check = drm_atomic_helper_check, 107 .atomic_commit = drm_atomic_helper_commit, 108 }; 109 110 static void hdlcd_setup_mode_config(struct drm_device *drm) 111 { 112 drm_mode_config_init(drm); 113 drm->mode_config.min_width = 0; 114 drm->mode_config.min_height = 0; 115 drm->mode_config.max_width = HDLCD_MAX_XRES; 116 drm->mode_config.max_height = HDLCD_MAX_YRES; 117 drm->mode_config.funcs = &hdlcd_mode_config_funcs; 118 } 119 120 static irqreturn_t hdlcd_irq(int irq, void *arg) 121 { 122 struct drm_device *drm = arg; 123 struct hdlcd_drm_private *hdlcd = drm->dev_private; 124 unsigned long irq_status; 125 126 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS); 127 128 #ifdef CONFIG_DEBUG_FS 129 if (irq_status & HDLCD_INTERRUPT_UNDERRUN) 130 atomic_inc(&hdlcd->buffer_underrun_count); 131 132 if (irq_status & HDLCD_INTERRUPT_DMA_END) 133 atomic_inc(&hdlcd->dma_end_count); 134 135 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR) 136 atomic_inc(&hdlcd->bus_error_count); 137 138 if (irq_status & HDLCD_INTERRUPT_VSYNC) 139 atomic_inc(&hdlcd->vsync_count); 140 141 #endif 142 if (irq_status & HDLCD_INTERRUPT_VSYNC) 143 drm_crtc_handle_vblank(&hdlcd->crtc); 144 145 /* acknowledge interrupt(s) */ 146 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status); 147 148 return IRQ_HANDLED; 149 } 150 151 static void hdlcd_irq_preinstall(struct drm_device *drm) 152 { 153 struct hdlcd_drm_private *hdlcd = drm->dev_private; 154 /* Ensure interrupts are disabled */ 155 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0); 156 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0); 157 } 158 159 static int hdlcd_irq_postinstall(struct drm_device *drm) 160 { 161 #ifdef CONFIG_DEBUG_FS 162 struct hdlcd_drm_private *hdlcd = drm->dev_private; 163 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 164 165 /* enable debug interrupts */ 166 irq_mask |= HDLCD_DEBUG_INT_MASK; 167 168 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); 169 #endif 170 return 0; 171 } 172 173 static void hdlcd_irq_uninstall(struct drm_device *drm) 174 { 175 struct hdlcd_drm_private *hdlcd = drm->dev_private; 176 /* disable all the interrupts that we might have enabled */ 177 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 178 179 #ifdef CONFIG_DEBUG_FS 180 /* disable debug interrupts */ 181 irq_mask &= ~HDLCD_DEBUG_INT_MASK; 182 #endif 183 184 /* disable vsync interrupts */ 185 irq_mask &= ~HDLCD_INTERRUPT_VSYNC; 186 187 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); 188 } 189 190 #ifdef CONFIG_DEBUG_FS 191 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg) 192 { 193 struct drm_info_node *node = (struct drm_info_node *)m->private; 194 struct drm_device *drm = node->minor->dev; 195 struct hdlcd_drm_private *hdlcd = drm->dev_private; 196 197 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count)); 198 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count)); 199 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count)); 200 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count)); 201 return 0; 202 } 203 204 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg) 205 { 206 struct drm_info_node *node = (struct drm_info_node *)m->private; 207 struct drm_device *drm = node->minor->dev; 208 struct hdlcd_drm_private *hdlcd = drm->dev_private; 209 unsigned long clkrate = clk_get_rate(hdlcd->clk); 210 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000; 211 212 seq_printf(m, "hw : %lu\n", clkrate); 213 seq_printf(m, "mode: %lu\n", mode_clock); 214 return 0; 215 } 216 217 static struct drm_info_list hdlcd_debugfs_list[] = { 218 { "interrupt_count", hdlcd_show_underrun_count, 0 }, 219 { "clocks", hdlcd_show_pxlclock, 0 }, 220 }; 221 222 static int hdlcd_debugfs_init(struct drm_minor *minor) 223 { 224 return drm_debugfs_create_files(hdlcd_debugfs_list, 225 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor); 226 } 227 #endif 228 229 DEFINE_DRM_GEM_CMA_FOPS(fops); 230 231 static struct drm_driver hdlcd_driver = { 232 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 233 .irq_handler = hdlcd_irq, 234 .irq_preinstall = hdlcd_irq_preinstall, 235 .irq_postinstall = hdlcd_irq_postinstall, 236 .irq_uninstall = hdlcd_irq_uninstall, 237 .gem_free_object_unlocked = drm_gem_cma_free_object, 238 .gem_print_info = drm_gem_cma_print_info, 239 .gem_vm_ops = &drm_gem_cma_vm_ops, 240 .dumb_create = drm_gem_cma_dumb_create, 241 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 242 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 243 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 244 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 245 .gem_prime_vmap = drm_gem_cma_prime_vmap, 246 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 247 .gem_prime_mmap = drm_gem_cma_prime_mmap, 248 #ifdef CONFIG_DEBUG_FS 249 .debugfs_init = hdlcd_debugfs_init, 250 #endif 251 .fops = &fops, 252 .name = "hdlcd", 253 .desc = "ARM HDLCD Controller DRM", 254 .date = "20151021", 255 .major = 1, 256 .minor = 0, 257 }; 258 259 static int hdlcd_drm_bind(struct device *dev) 260 { 261 struct drm_device *drm; 262 struct hdlcd_drm_private *hdlcd; 263 int ret; 264 265 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL); 266 if (!hdlcd) 267 return -ENOMEM; 268 269 drm = drm_dev_alloc(&hdlcd_driver, dev); 270 if (IS_ERR(drm)) 271 return PTR_ERR(drm); 272 273 drm->dev_private = hdlcd; 274 dev_set_drvdata(dev, drm); 275 276 hdlcd_setup_mode_config(drm); 277 ret = hdlcd_load(drm, 0); 278 if (ret) 279 goto err_free; 280 281 /* Set the CRTC's port so that the encoder component can find it */ 282 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); 283 284 ret = component_bind_all(dev, drm); 285 if (ret) { 286 DRM_ERROR("Failed to bind all components\n"); 287 goto err_unload; 288 } 289 290 ret = pm_runtime_set_active(dev); 291 if (ret) 292 goto err_pm_active; 293 294 pm_runtime_enable(dev); 295 296 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 297 if (ret < 0) { 298 DRM_ERROR("failed to initialise vblank\n"); 299 goto err_vblank; 300 } 301 302 drm_mode_config_reset(drm); 303 drm_kms_helper_poll_init(drm); 304 305 ret = drm_dev_register(drm, 0); 306 if (ret) 307 goto err_register; 308 309 drm_fbdev_generic_setup(drm, 32); 310 311 return 0; 312 313 err_register: 314 drm_kms_helper_poll_fini(drm); 315 err_vblank: 316 pm_runtime_disable(drm->dev); 317 err_pm_active: 318 drm_atomic_helper_shutdown(drm); 319 component_unbind_all(dev, drm); 320 err_unload: 321 of_node_put(hdlcd->crtc.port); 322 hdlcd->crtc.port = NULL; 323 drm_irq_uninstall(drm); 324 of_reserved_mem_device_release(drm->dev); 325 err_free: 326 drm_mode_config_cleanup(drm); 327 dev_set_drvdata(dev, NULL); 328 drm_dev_put(drm); 329 330 return ret; 331 } 332 333 static void hdlcd_drm_unbind(struct device *dev) 334 { 335 struct drm_device *drm = dev_get_drvdata(dev); 336 struct hdlcd_drm_private *hdlcd = drm->dev_private; 337 338 drm_dev_unregister(drm); 339 drm_kms_helper_poll_fini(drm); 340 component_unbind_all(dev, drm); 341 of_node_put(hdlcd->crtc.port); 342 hdlcd->crtc.port = NULL; 343 pm_runtime_get_sync(dev); 344 drm_crtc_vblank_off(&hdlcd->crtc); 345 drm_irq_uninstall(drm); 346 drm_atomic_helper_shutdown(drm); 347 pm_runtime_put(dev); 348 if (pm_runtime_enabled(dev)) 349 pm_runtime_disable(dev); 350 of_reserved_mem_device_release(dev); 351 drm_mode_config_cleanup(drm); 352 drm->dev_private = NULL; 353 dev_set_drvdata(dev, NULL); 354 drm_dev_put(drm); 355 } 356 357 static const struct component_master_ops hdlcd_master_ops = { 358 .bind = hdlcd_drm_bind, 359 .unbind = hdlcd_drm_unbind, 360 }; 361 362 static int compare_dev(struct device *dev, void *data) 363 { 364 return dev->of_node == data; 365 } 366 367 static int hdlcd_probe(struct platform_device *pdev) 368 { 369 struct device_node *port; 370 struct component_match *match = NULL; 371 372 /* there is only one output port inside each device, find it */ 373 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); 374 if (!port) 375 return -ENODEV; 376 377 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port); 378 of_node_put(port); 379 380 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops, 381 match); 382 } 383 384 static int hdlcd_remove(struct platform_device *pdev) 385 { 386 component_master_del(&pdev->dev, &hdlcd_master_ops); 387 return 0; 388 } 389 390 static const struct of_device_id hdlcd_of_match[] = { 391 { .compatible = "arm,hdlcd" }, 392 {}, 393 }; 394 MODULE_DEVICE_TABLE(of, hdlcd_of_match); 395 396 static int __maybe_unused hdlcd_pm_suspend(struct device *dev) 397 { 398 struct drm_device *drm = dev_get_drvdata(dev); 399 400 return drm_mode_config_helper_suspend(drm); 401 } 402 403 static int __maybe_unused hdlcd_pm_resume(struct device *dev) 404 { 405 struct drm_device *drm = dev_get_drvdata(dev); 406 407 drm_mode_config_helper_resume(drm); 408 409 return 0; 410 } 411 412 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume); 413 414 static struct platform_driver hdlcd_platform_driver = { 415 .probe = hdlcd_probe, 416 .remove = hdlcd_remove, 417 .driver = { 418 .name = "hdlcd", 419 .pm = &hdlcd_pm_ops, 420 .of_match_table = hdlcd_of_match, 421 }, 422 }; 423 424 module_platform_driver(hdlcd_platform_driver); 425 426 MODULE_AUTHOR("Liviu Dudau"); 427 MODULE_DESCRIPTION("ARM HDLCD DRM driver"); 428 MODULE_LICENSE("GPL v2"); 429