18e22d792SLiviu Dudau /* 28e22d792SLiviu Dudau * Copyright (C) 2013-2015 ARM Limited 38e22d792SLiviu Dudau * Author: Liviu Dudau <Liviu.Dudau@arm.com> 48e22d792SLiviu Dudau * 58e22d792SLiviu Dudau * This file is subject to the terms and conditions of the GNU General Public 68e22d792SLiviu Dudau * License. See the file COPYING in the main directory of this archive 78e22d792SLiviu Dudau * for more details. 88e22d792SLiviu Dudau * 98e22d792SLiviu Dudau * ARM HDLCD Driver 108e22d792SLiviu Dudau */ 118e22d792SLiviu Dudau 128e22d792SLiviu Dudau #include <linux/module.h> 138e22d792SLiviu Dudau #include <linux/spinlock.h> 148e22d792SLiviu Dudau #include <linux/clk.h> 158e22d792SLiviu Dudau #include <linux/component.h> 16febae9bcSLiviu Dudau #include <linux/console.h> 17535d1b94SSam Ravnborg #include <linux/dma-mapping.h> 188e22d792SLiviu Dudau #include <linux/list.h> 198e22d792SLiviu Dudau #include <linux/of_graph.h> 208e22d792SLiviu Dudau #include <linux/of_reserved_mem.h> 21535d1b94SSam Ravnborg #include <linux/platform_device.h> 228e22d792SLiviu Dudau #include <linux/pm_runtime.h> 238e22d792SLiviu Dudau 244b760f76SRobin Murphy #include <drm/drm_aperture.h> 258e22d792SLiviu Dudau #include <drm/drm_atomic_helper.h> 268e22d792SLiviu Dudau #include <drm/drm_crtc.h> 27535d1b94SSam Ravnborg #include <drm/drm_debugfs.h> 28535d1b94SSam Ravnborg #include <drm/drm_drv.h> 298ab59da2SThomas Zimmermann #include <drm/drm_fbdev_generic.h> 304a83c26aSDanilo Krummrich #include <drm/drm_gem_dma_helper.h> 3139ffd906SNoralf Trønnes #include <drm/drm_gem_framebuffer_helper.h> 325c7e5a22SNoralf Trønnes #include <drm/drm_modeset_helper.h> 336aef2293SJavier Martinez Canillas #include <drm/drm_module.h> 348e22d792SLiviu Dudau #include <drm/drm_of.h> 35fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 36535d1b94SSam Ravnborg #include <drm/drm_vblank.h> 378e22d792SLiviu Dudau 388e22d792SLiviu Dudau #include "hdlcd_drv.h" 398e22d792SLiviu Dudau #include "hdlcd_regs.h" 408e22d792SLiviu Dudau 4171eba7bdSThomas Zimmermann static irqreturn_t hdlcd_irq(int irq, void *arg) 4271eba7bdSThomas Zimmermann { 43f818eac1SRobin Murphy struct hdlcd_drm_private *hdlcd = arg; 4471eba7bdSThomas Zimmermann unsigned long irq_status; 4571eba7bdSThomas Zimmermann 4671eba7bdSThomas Zimmermann irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS); 4771eba7bdSThomas Zimmermann 4871eba7bdSThomas Zimmermann #ifdef CONFIG_DEBUG_FS 4971eba7bdSThomas Zimmermann if (irq_status & HDLCD_INTERRUPT_UNDERRUN) 5071eba7bdSThomas Zimmermann atomic_inc(&hdlcd->buffer_underrun_count); 5171eba7bdSThomas Zimmermann 5271eba7bdSThomas Zimmermann if (irq_status & HDLCD_INTERRUPT_DMA_END) 5371eba7bdSThomas Zimmermann atomic_inc(&hdlcd->dma_end_count); 5471eba7bdSThomas Zimmermann 5571eba7bdSThomas Zimmermann if (irq_status & HDLCD_INTERRUPT_BUS_ERROR) 5671eba7bdSThomas Zimmermann atomic_inc(&hdlcd->bus_error_count); 5771eba7bdSThomas Zimmermann 5871eba7bdSThomas Zimmermann if (irq_status & HDLCD_INTERRUPT_VSYNC) 5971eba7bdSThomas Zimmermann atomic_inc(&hdlcd->vsync_count); 6071eba7bdSThomas Zimmermann 6171eba7bdSThomas Zimmermann #endif 6271eba7bdSThomas Zimmermann if (irq_status & HDLCD_INTERRUPT_VSYNC) 6371eba7bdSThomas Zimmermann drm_crtc_handle_vblank(&hdlcd->crtc); 6471eba7bdSThomas Zimmermann 6571eba7bdSThomas Zimmermann /* acknowledge interrupt(s) */ 6671eba7bdSThomas Zimmermann hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status); 6771eba7bdSThomas Zimmermann 6871eba7bdSThomas Zimmermann return IRQ_HANDLED; 6971eba7bdSThomas Zimmermann } 7071eba7bdSThomas Zimmermann 71f818eac1SRobin Murphy static int hdlcd_irq_install(struct hdlcd_drm_private *hdlcd) 7271eba7bdSThomas Zimmermann { 7371eba7bdSThomas Zimmermann int ret; 7471eba7bdSThomas Zimmermann 75f818eac1SRobin Murphy /* Ensure interrupts are disabled */ 76f818eac1SRobin Murphy hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0); 77f818eac1SRobin Murphy hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0); 7871eba7bdSThomas Zimmermann 79f818eac1SRobin Murphy ret = request_irq(hdlcd->irq, hdlcd_irq, 0, "hdlcd", hdlcd); 8071eba7bdSThomas Zimmermann if (ret) 8171eba7bdSThomas Zimmermann return ret; 8271eba7bdSThomas Zimmermann 83f818eac1SRobin Murphy #ifdef CONFIG_DEBUG_FS 84f818eac1SRobin Murphy /* enable debug interrupts */ 85f818eac1SRobin Murphy hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, HDLCD_DEBUG_INT_MASK); 86f818eac1SRobin Murphy #endif 8771eba7bdSThomas Zimmermann 8871eba7bdSThomas Zimmermann return 0; 8971eba7bdSThomas Zimmermann } 9071eba7bdSThomas Zimmermann 91f818eac1SRobin Murphy static void hdlcd_irq_uninstall(struct hdlcd_drm_private *hdlcd) 9271eba7bdSThomas Zimmermann { 9371eba7bdSThomas Zimmermann /* disable all the interrupts that we might have enabled */ 94f818eac1SRobin Murphy hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0); 9571eba7bdSThomas Zimmermann 96f818eac1SRobin Murphy free_irq(hdlcd->irq, hdlcd); 9771eba7bdSThomas Zimmermann } 9871eba7bdSThomas Zimmermann 998e22d792SLiviu Dudau static int hdlcd_load(struct drm_device *drm, unsigned long flags) 1008e22d792SLiviu Dudau { 1015f56e596SDanilo Krummrich struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm); 1028e22d792SLiviu Dudau struct platform_device *pdev = to_platform_device(drm->dev); 1038e22d792SLiviu Dudau struct resource *res; 1048e22d792SLiviu Dudau u32 version; 1058e22d792SLiviu Dudau int ret; 1068e22d792SLiviu Dudau 1078e22d792SLiviu Dudau hdlcd->clk = devm_clk_get(drm->dev, "pxlclk"); 1088e22d792SLiviu Dudau if (IS_ERR(hdlcd->clk)) 1098e22d792SLiviu Dudau return PTR_ERR(hdlcd->clk); 1108e22d792SLiviu Dudau 1118e22d792SLiviu Dudau #ifdef CONFIG_DEBUG_FS 1128e22d792SLiviu Dudau atomic_set(&hdlcd->buffer_underrun_count, 0); 1138e22d792SLiviu Dudau atomic_set(&hdlcd->bus_error_count, 0); 1148e22d792SLiviu Dudau atomic_set(&hdlcd->vsync_count, 0); 1158e22d792SLiviu Dudau atomic_set(&hdlcd->dma_end_count, 0); 1168e22d792SLiviu Dudau #endif 1178e22d792SLiviu Dudau 1188e22d792SLiviu Dudau res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1198e22d792SLiviu Dudau hdlcd->mmio = devm_ioremap_resource(drm->dev, res); 1208e22d792SLiviu Dudau if (IS_ERR(hdlcd->mmio)) { 1218e22d792SLiviu Dudau DRM_ERROR("failed to map control registers area\n"); 12269c2565aSDan Carpenter ret = PTR_ERR(hdlcd->mmio); 1238e22d792SLiviu Dudau hdlcd->mmio = NULL; 12469c2565aSDan Carpenter return ret; 1258e22d792SLiviu Dudau } 1268e22d792SLiviu Dudau 1278e22d792SLiviu Dudau version = hdlcd_read(hdlcd, HDLCD_REG_VERSION); 1288e22d792SLiviu Dudau if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) { 1298e22d792SLiviu Dudau DRM_ERROR("unknown product id: 0x%x\n", version); 13061a6dcd7SAlexey Brodkin return -EINVAL; 1318e22d792SLiviu Dudau } 1328e22d792SLiviu Dudau DRM_INFO("found ARM HDLCD version r%dp%d\n", 1338e22d792SLiviu Dudau (version & HDLCD_VERSION_MAJOR_MASK) >> 8, 1348e22d792SLiviu Dudau version & HDLCD_VERSION_MINOR_MASK); 1358e22d792SLiviu Dudau 1368e22d792SLiviu Dudau /* Get the optional framebuffer memory resource */ 1378e22d792SLiviu Dudau ret = of_reserved_mem_device_init(drm->dev); 1388e22d792SLiviu Dudau if (ret && ret != -ENODEV) 13961a6dcd7SAlexey Brodkin return ret; 1408e22d792SLiviu Dudau 1418e22d792SLiviu Dudau ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); 1428e22d792SLiviu Dudau if (ret) 1438e22d792SLiviu Dudau goto setup_fail; 1448e22d792SLiviu Dudau 1458e22d792SLiviu Dudau ret = hdlcd_setup_crtc(drm); 1468e22d792SLiviu Dudau if (ret < 0) { 1478e22d792SLiviu Dudau DRM_ERROR("failed to create crtc\n"); 1488e22d792SLiviu Dudau goto setup_fail; 1498e22d792SLiviu Dudau } 1508e22d792SLiviu Dudau 15171eba7bdSThomas Zimmermann ret = platform_get_irq(pdev, 0); 15271eba7bdSThomas Zimmermann if (ret < 0) 15371eba7bdSThomas Zimmermann goto irq_fail; 15471eba7bdSThomas Zimmermann hdlcd->irq = ret; 15571eba7bdSThomas Zimmermann 156f818eac1SRobin Murphy ret = hdlcd_irq_install(hdlcd); 1578e22d792SLiviu Dudau if (ret < 0) { 1588e22d792SLiviu Dudau DRM_ERROR("failed to install IRQ handler\n"); 1598e22d792SLiviu Dudau goto irq_fail; 1608e22d792SLiviu Dudau } 1618e22d792SLiviu Dudau 1628e22d792SLiviu Dudau return 0; 1638e22d792SLiviu Dudau 1648e22d792SLiviu Dudau irq_fail: 1658e22d792SLiviu Dudau drm_crtc_cleanup(&hdlcd->crtc); 1668e22d792SLiviu Dudau setup_fail: 1678e22d792SLiviu Dudau of_reserved_mem_device_release(drm->dev); 1688e22d792SLiviu Dudau 1698e22d792SLiviu Dudau return ret; 1708e22d792SLiviu Dudau } 1718e22d792SLiviu Dudau 1728e22d792SLiviu Dudau static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = { 17339ffd906SNoralf Trønnes .fb_create = drm_gem_fb_create, 1748e22d792SLiviu Dudau .atomic_check = drm_atomic_helper_check, 1752bd6cc8cSDaniel Vetter .atomic_commit = drm_atomic_helper_commit, 1768e22d792SLiviu Dudau }; 1778e22d792SLiviu Dudau 178611fc22cSDanilo Krummrich static int hdlcd_setup_mode_config(struct drm_device *drm) 1798e22d792SLiviu Dudau { 180611fc22cSDanilo Krummrich int ret; 181611fc22cSDanilo Krummrich 182611fc22cSDanilo Krummrich ret = drmm_mode_config_init(drm); 183611fc22cSDanilo Krummrich if (ret) 184611fc22cSDanilo Krummrich return ret; 185611fc22cSDanilo Krummrich 1868e22d792SLiviu Dudau drm->mode_config.min_width = 0; 1878e22d792SLiviu Dudau drm->mode_config.min_height = 0; 1888e22d792SLiviu Dudau drm->mode_config.max_width = HDLCD_MAX_XRES; 1898e22d792SLiviu Dudau drm->mode_config.max_height = HDLCD_MAX_YRES; 1908e22d792SLiviu Dudau drm->mode_config.funcs = &hdlcd_mode_config_funcs; 191611fc22cSDanilo Krummrich 192611fc22cSDanilo Krummrich return 0; 1938e22d792SLiviu Dudau } 1948e22d792SLiviu Dudau 1958e22d792SLiviu Dudau #ifdef CONFIG_DEBUG_FS 1968e22d792SLiviu Dudau static int hdlcd_show_underrun_count(struct seq_file *m, void *arg) 1978e22d792SLiviu Dudau { 198*2e3ab8a6SMaíra Canal struct drm_debugfs_entry *entry = m->private; 199*2e3ab8a6SMaíra Canal struct drm_device *drm = entry->dev; 2005f56e596SDanilo Krummrich struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm); 2018e22d792SLiviu Dudau 2028e22d792SLiviu Dudau seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count)); 2038e22d792SLiviu Dudau seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count)); 2048e22d792SLiviu Dudau seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count)); 2058e22d792SLiviu Dudau seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count)); 2068e22d792SLiviu Dudau return 0; 2078e22d792SLiviu Dudau } 2088e22d792SLiviu Dudau 2098e22d792SLiviu Dudau static int hdlcd_show_pxlclock(struct seq_file *m, void *arg) 2108e22d792SLiviu Dudau { 211*2e3ab8a6SMaíra Canal struct drm_debugfs_entry *entry = m->private; 212*2e3ab8a6SMaíra Canal struct drm_device *drm = entry->dev; 2135f56e596SDanilo Krummrich struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm); 2148e22d792SLiviu Dudau unsigned long clkrate = clk_get_rate(hdlcd->clk); 2158e22d792SLiviu Dudau unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000; 2168e22d792SLiviu Dudau 2178e22d792SLiviu Dudau seq_printf(m, "hw : %lu\n", clkrate); 2188e22d792SLiviu Dudau seq_printf(m, "mode: %lu\n", mode_clock); 2198e22d792SLiviu Dudau return 0; 2208e22d792SLiviu Dudau } 2218e22d792SLiviu Dudau 222*2e3ab8a6SMaíra Canal static struct drm_debugfs_info hdlcd_debugfs_list[] = { 2238e22d792SLiviu Dudau { "interrupt_count", hdlcd_show_underrun_count, 0 }, 2248e22d792SLiviu Dudau { "clocks", hdlcd_show_pxlclock, 0 }, 2258e22d792SLiviu Dudau }; 2268e22d792SLiviu Dudau #endif 2278e22d792SLiviu Dudau 2284a83c26aSDanilo Krummrich DEFINE_DRM_GEM_DMA_FOPS(fops); 2298e22d792SLiviu Dudau 23070a59dd8SDaniel Vetter static const struct drm_driver hdlcd_driver = { 2310424fdafSDaniel Vetter .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 2324a83c26aSDanilo Krummrich DRM_GEM_DMA_DRIVER_OPS, 2338e22d792SLiviu Dudau .fops = &fops, 2348e22d792SLiviu Dudau .name = "hdlcd", 2358e22d792SLiviu Dudau .desc = "ARM HDLCD Controller DRM", 2368e22d792SLiviu Dudau .date = "20151021", 2378e22d792SLiviu Dudau .major = 1, 2388e22d792SLiviu Dudau .minor = 0, 2398e22d792SLiviu Dudau }; 2408e22d792SLiviu Dudau 2418e22d792SLiviu Dudau static int hdlcd_drm_bind(struct device *dev) 2428e22d792SLiviu Dudau { 2438e22d792SLiviu Dudau struct drm_device *drm; 2448e22d792SLiviu Dudau struct hdlcd_drm_private *hdlcd; 2458e22d792SLiviu Dudau int ret; 2468e22d792SLiviu Dudau 2479914013fSDanilo Krummrich hdlcd = devm_drm_dev_alloc(dev, &hdlcd_driver, typeof(*hdlcd), base); 2489914013fSDanilo Krummrich if (IS_ERR(hdlcd)) 2499914013fSDanilo Krummrich return PTR_ERR(hdlcd); 2508e22d792SLiviu Dudau 2519914013fSDanilo Krummrich drm = &hdlcd->base; 2528e22d792SLiviu Dudau 253a95acec1SLiviu Dudau dev_set_drvdata(dev, drm); 254a95acec1SLiviu Dudau 255611fc22cSDanilo Krummrich ret = hdlcd_setup_mode_config(drm); 256611fc22cSDanilo Krummrich if (ret) 257611fc22cSDanilo Krummrich goto err_free; 258611fc22cSDanilo Krummrich 2598e22d792SLiviu Dudau ret = hdlcd_load(drm, 0); 2608e22d792SLiviu Dudau if (ret) 2618e22d792SLiviu Dudau goto err_free; 2628e22d792SLiviu Dudau 263de5cc815SLiviu Dudau /* Set the CRTC's port so that the encoder component can find it */ 264de5cc815SLiviu Dudau hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); 265de5cc815SLiviu Dudau 2668e22d792SLiviu Dudau ret = component_bind_all(dev, drm); 2678e22d792SLiviu Dudau if (ret) { 2688e22d792SLiviu Dudau DRM_ERROR("Failed to bind all components\n"); 26990731c24SBrian Starkey goto err_unload; 2708e22d792SLiviu Dudau } 2718e22d792SLiviu Dudau 272a95acec1SLiviu Dudau ret = pm_runtime_set_active(dev); 273a95acec1SLiviu Dudau if (ret) 274a95acec1SLiviu Dudau goto err_pm_active; 275a95acec1SLiviu Dudau 276a95acec1SLiviu Dudau pm_runtime_enable(dev); 277a95acec1SLiviu Dudau 2788e22d792SLiviu Dudau ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 2798e22d792SLiviu Dudau if (ret < 0) { 2808e22d792SLiviu Dudau DRM_ERROR("failed to initialise vblank\n"); 2818e22d792SLiviu Dudau goto err_vblank; 2828e22d792SLiviu Dudau } 2838e22d792SLiviu Dudau 2844b760f76SRobin Murphy /* 2854b760f76SRobin Murphy * If EFI left us running, take over from simple framebuffer 2864b760f76SRobin Murphy * drivers. Read HDLCD_REG_COMMAND to see if we are enabled. 2874b760f76SRobin Murphy */ 2884b760f76SRobin Murphy if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) { 2894b760f76SRobin Murphy hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); 2904b760f76SRobin Murphy drm_aperture_remove_framebuffers(false, &hdlcd_driver); 2914b760f76SRobin Murphy } 2924b760f76SRobin Murphy 2938e22d792SLiviu Dudau drm_mode_config_reset(drm); 2948e22d792SLiviu Dudau drm_kms_helper_poll_init(drm); 2958e22d792SLiviu Dudau 296*2e3ab8a6SMaíra Canal #ifdef CONFIG_DEBUG_FS 297*2e3ab8a6SMaíra Canal drm_debugfs_add_files(drm, hdlcd_debugfs_list, ARRAY_SIZE(hdlcd_debugfs_list)); 298*2e3ab8a6SMaíra Canal #endif 299*2e3ab8a6SMaíra Canal 30090731c24SBrian Starkey ret = drm_dev_register(drm, 0); 30190731c24SBrian Starkey if (ret) 30290731c24SBrian Starkey goto err_register; 30390731c24SBrian Starkey 304941e97c1SNoralf Trønnes drm_fbdev_generic_setup(drm, 32); 305941e97c1SNoralf Trønnes 3068e22d792SLiviu Dudau return 0; 3078e22d792SLiviu Dudau 30890731c24SBrian Starkey err_register: 3098e22d792SLiviu Dudau drm_kms_helper_poll_fini(drm); 3108e22d792SLiviu Dudau err_vblank: 311a95acec1SLiviu Dudau pm_runtime_disable(drm->dev); 312a95acec1SLiviu Dudau err_pm_active: 313d664b851SLiviu Dudau drm_atomic_helper_shutdown(drm); 3148e22d792SLiviu Dudau component_unbind_all(dev, drm); 3158e22d792SLiviu Dudau err_unload: 316de5cc815SLiviu Dudau of_node_put(hdlcd->crtc.port); 317de5cc815SLiviu Dudau hdlcd->crtc.port = NULL; 318f818eac1SRobin Murphy hdlcd_irq_uninstall(hdlcd); 3198e22d792SLiviu Dudau of_reserved_mem_device_release(drm->dev); 3208e22d792SLiviu Dudau err_free: 321a95acec1SLiviu Dudau dev_set_drvdata(dev, NULL); 3228e22d792SLiviu Dudau return ret; 3238e22d792SLiviu Dudau } 3248e22d792SLiviu Dudau 3258e22d792SLiviu Dudau static void hdlcd_drm_unbind(struct device *dev) 3268e22d792SLiviu Dudau { 3278e22d792SLiviu Dudau struct drm_device *drm = dev_get_drvdata(dev); 3285f56e596SDanilo Krummrich struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm); 3298e22d792SLiviu Dudau 33090731c24SBrian Starkey drm_dev_unregister(drm); 3318e22d792SLiviu Dudau drm_kms_helper_poll_fini(drm); 3328e22d792SLiviu Dudau component_unbind_all(dev, drm); 333de5cc815SLiviu Dudau of_node_put(hdlcd->crtc.port); 334de5cc815SLiviu Dudau hdlcd->crtc.port = NULL; 335d664b851SLiviu Dudau pm_runtime_get_sync(dev); 3369fd466f5SLaurent Pinchart drm_atomic_helper_shutdown(drm); 337f818eac1SRobin Murphy hdlcd_irq_uninstall(hdlcd); 338d664b851SLiviu Dudau pm_runtime_put(dev); 339d664b851SLiviu Dudau if (pm_runtime_enabled(dev)) 340d664b851SLiviu Dudau pm_runtime_disable(dev); 341d664b851SLiviu Dudau of_reserved_mem_device_release(dev); 3428e22d792SLiviu Dudau dev_set_drvdata(dev, NULL); 3438e22d792SLiviu Dudau } 3448e22d792SLiviu Dudau 3458e22d792SLiviu Dudau static const struct component_master_ops hdlcd_master_ops = { 3468e22d792SLiviu Dudau .bind = hdlcd_drm_bind, 3478e22d792SLiviu Dudau .unbind = hdlcd_drm_unbind, 3488e22d792SLiviu Dudau }; 3498e22d792SLiviu Dudau 3508e22d792SLiviu Dudau static int compare_dev(struct device *dev, void *data) 3518e22d792SLiviu Dudau { 3528e22d792SLiviu Dudau return dev->of_node == data; 3538e22d792SLiviu Dudau } 3548e22d792SLiviu Dudau 3558e22d792SLiviu Dudau static int hdlcd_probe(struct platform_device *pdev) 3568e22d792SLiviu Dudau { 35786418f90SRob Herring struct device_node *port; 3588e22d792SLiviu Dudau struct component_match *match = NULL; 3598e22d792SLiviu Dudau 3608e22d792SLiviu Dudau /* there is only one output port inside each device, find it */ 36186418f90SRob Herring port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); 36286418f90SRob Herring if (!port) 3638e22d792SLiviu Dudau return -ENODEV; 3648e22d792SLiviu Dudau 36597ac0e47SRussell King drm_of_component_match_add(&pdev->dev, &match, compare_dev, port); 36697ac0e47SRussell King of_node_put(port); 3678e22d792SLiviu Dudau 3688e22d792SLiviu Dudau return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops, 3698e22d792SLiviu Dudau match); 3708e22d792SLiviu Dudau } 3718e22d792SLiviu Dudau 3728e22d792SLiviu Dudau static int hdlcd_remove(struct platform_device *pdev) 3738e22d792SLiviu Dudau { 3748e22d792SLiviu Dudau component_master_del(&pdev->dev, &hdlcd_master_ops); 3758e22d792SLiviu Dudau return 0; 3768e22d792SLiviu Dudau } 3778e22d792SLiviu Dudau 3788e22d792SLiviu Dudau static const struct of_device_id hdlcd_of_match[] = { 3798e22d792SLiviu Dudau { .compatible = "arm,hdlcd" }, 3808e22d792SLiviu Dudau {}, 3818e22d792SLiviu Dudau }; 3828e22d792SLiviu Dudau MODULE_DEVICE_TABLE(of, hdlcd_of_match); 3838e22d792SLiviu Dudau 3848e22d792SLiviu Dudau static int __maybe_unused hdlcd_pm_suspend(struct device *dev) 3858e22d792SLiviu Dudau { 3868e22d792SLiviu Dudau struct drm_device *drm = dev_get_drvdata(dev); 3878e22d792SLiviu Dudau 3885c7e5a22SNoralf Trønnes return drm_mode_config_helper_suspend(drm); 3898e22d792SLiviu Dudau } 3908e22d792SLiviu Dudau 3918e22d792SLiviu Dudau static int __maybe_unused hdlcd_pm_resume(struct device *dev) 3928e22d792SLiviu Dudau { 3938e22d792SLiviu Dudau struct drm_device *drm = dev_get_drvdata(dev); 3948e22d792SLiviu Dudau 3955c7e5a22SNoralf Trønnes drm_mode_config_helper_resume(drm); 396a95acec1SLiviu Dudau 3978e22d792SLiviu Dudau return 0; 3988e22d792SLiviu Dudau } 3998e22d792SLiviu Dudau 4008e22d792SLiviu Dudau static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume); 4018e22d792SLiviu Dudau 4028e22d792SLiviu Dudau static struct platform_driver hdlcd_platform_driver = { 4038e22d792SLiviu Dudau .probe = hdlcd_probe, 4048e22d792SLiviu Dudau .remove = hdlcd_remove, 4058e22d792SLiviu Dudau .driver = { 4068e22d792SLiviu Dudau .name = "hdlcd", 4078e22d792SLiviu Dudau .pm = &hdlcd_pm_ops, 4088e22d792SLiviu Dudau .of_match_table = hdlcd_of_match, 4098e22d792SLiviu Dudau }, 4108e22d792SLiviu Dudau }; 4118e22d792SLiviu Dudau 4126aef2293SJavier Martinez Canillas drm_module_platform_driver(hdlcd_platform_driver); 4138e22d792SLiviu Dudau 4148e22d792SLiviu Dudau MODULE_AUTHOR("Liviu Dudau"); 4158e22d792SLiviu Dudau MODULE_DESCRIPTION("ARM HDLCD DRM driver"); 4168e22d792SLiviu Dudau MODULE_LICENSE("GPL v2"); 417