1 /* 2 * Copyright (C) 2013-2015 ARM Limited 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file COPYING in the main directory of this archive 7 * for more details. 8 * 9 * Implementation of a CRTC class for the HDLCD driver. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/of_graph.h> 14 #include <linux/platform_data/simplefb.h> 15 16 #include <video/videomode.h> 17 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_crtc.h> 21 #include <drm/drm_fb_dma_helper.h> 22 #include <drm/drm_fb_helper.h> 23 #include <drm/drm_framebuffer.h> 24 #include <drm/drm_gem_dma_helper.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_probe_helper.h> 27 #include <drm/drm_vblank.h> 28 29 #include "hdlcd_drv.h" 30 #include "hdlcd_regs.h" 31 32 /* 33 * The HDLCD controller is a dumb RGB streamer that gets connected to 34 * a single HDMI transmitter or in the case of the ARM Models it gets 35 * emulated by the software that does the actual rendering. 36 * 37 */ 38 39 static void hdlcd_crtc_cleanup(struct drm_crtc *crtc) 40 { 41 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 42 43 /* stop the controller on cleanup */ 44 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); 45 drm_crtc_cleanup(crtc); 46 } 47 48 static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc) 49 { 50 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 51 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 52 53 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); 54 55 return 0; 56 } 57 58 static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc) 59 { 60 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 61 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 62 63 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); 64 } 65 66 static const struct drm_crtc_funcs hdlcd_crtc_funcs = { 67 .destroy = hdlcd_crtc_cleanup, 68 .set_config = drm_atomic_helper_set_config, 69 .page_flip = drm_atomic_helper_page_flip, 70 .reset = drm_atomic_helper_crtc_reset, 71 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 72 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 73 .enable_vblank = hdlcd_crtc_enable_vblank, 74 .disable_vblank = hdlcd_crtc_disable_vblank, 75 }; 76 77 static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS; 78 79 /* 80 * Setup the HDLCD registers for decoding the pixels out of the framebuffer 81 */ 82 static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc) 83 { 84 unsigned int btpp; 85 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 86 const struct drm_framebuffer *fb = crtc->primary->state->fb; 87 uint32_t pixel_format; 88 struct simplefb_format *format = NULL; 89 int i; 90 91 pixel_format = fb->format->format; 92 93 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { 94 if (supported_formats[i].fourcc == pixel_format) 95 format = &supported_formats[i]; 96 } 97 98 if (WARN_ON(!format)) 99 return 0; 100 101 /* HDLCD uses 'bytes per pixel', zero means 1 byte */ 102 btpp = (format->bits_per_pixel + 7) / 8; 103 hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3); 104 105 /* 106 * The format of the HDLCD_REG_<color>_SELECT register is: 107 * - bits[23:16] - default value for that color component 108 * - bits[11:8] - number of bits to extract for each color component 109 * - bits[4:0] - index of the lowest bit to extract 110 * 111 * The default color value is used when bits[11:8] are zero, when the 112 * pixel is outside the visible frame area or when there is a 113 * buffer underrun. 114 */ 115 hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset | 116 #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN 117 0x00ff0000 | /* show underruns in red */ 118 #endif 119 ((format->red.length & 0xf) << 8)); 120 hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset | 121 ((format->green.length & 0xf) << 8)); 122 hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset | 123 ((format->blue.length & 0xf) << 8)); 124 125 return 0; 126 } 127 128 static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) 129 { 130 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 131 struct drm_display_mode *m = &crtc->state->adjusted_mode; 132 struct videomode vm; 133 unsigned int polarities, err; 134 135 vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; 136 vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; 137 vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; 138 vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; 139 vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; 140 vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; 141 142 polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA; 143 144 if (m->flags & DRM_MODE_FLAG_PHSYNC) 145 polarities |= HDLCD_POLARITY_HSYNC; 146 if (m->flags & DRM_MODE_FLAG_PVSYNC) 147 polarities |= HDLCD_POLARITY_VSYNC; 148 149 /* Allow max number of outstanding requests and largest burst size */ 150 hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS, 151 HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16); 152 153 hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1); 154 hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1); 155 hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1); 156 hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1); 157 hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1); 158 hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1); 159 hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1); 160 hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1); 161 hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities); 162 163 err = hdlcd_set_pxl_fmt(crtc); 164 if (err) 165 return; 166 167 clk_set_rate(hdlcd->clk, m->crtc_clock * 1000); 168 } 169 170 static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, 171 struct drm_atomic_state *state) 172 { 173 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 174 175 clk_prepare_enable(hdlcd->clk); 176 hdlcd_crtc_mode_set_nofb(crtc); 177 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); 178 drm_crtc_vblank_on(crtc); 179 } 180 181 static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc, 182 struct drm_atomic_state *state) 183 { 184 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 185 186 drm_crtc_vblank_off(crtc); 187 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); 188 clk_disable_unprepare(hdlcd->clk); 189 } 190 191 static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, 192 const struct drm_display_mode *mode) 193 { 194 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 195 long rate, clk_rate = mode->clock * 1000; 196 197 rate = clk_round_rate(hdlcd->clk, clk_rate); 198 /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */ 199 if (abs(rate - clk_rate) * 1000 > clk_rate) { 200 /* clock required by mode not supported by hardware */ 201 return MODE_NOCLOCK; 202 } 203 204 return MODE_OK; 205 } 206 207 static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, 208 struct drm_atomic_state *state) 209 { 210 struct drm_pending_vblank_event *event = crtc->state->event; 211 212 if (event) { 213 crtc->state->event = NULL; 214 215 spin_lock_irq(&crtc->dev->event_lock); 216 if (drm_crtc_vblank_get(crtc) == 0) 217 drm_crtc_arm_vblank_event(crtc, event); 218 else 219 drm_crtc_send_vblank_event(crtc, event); 220 spin_unlock_irq(&crtc->dev->event_lock); 221 } 222 } 223 224 static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { 225 .mode_valid = hdlcd_crtc_mode_valid, 226 .atomic_begin = hdlcd_crtc_atomic_begin, 227 .atomic_enable = hdlcd_crtc_atomic_enable, 228 .atomic_disable = hdlcd_crtc_atomic_disable, 229 }; 230 231 static int hdlcd_plane_atomic_check(struct drm_plane *plane, 232 struct drm_atomic_state *state) 233 { 234 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 235 plane); 236 int i; 237 struct drm_crtc *crtc; 238 struct drm_crtc_state *crtc_state; 239 u32 src_h = new_plane_state->src_h >> 16; 240 241 /* only the HDLCD_REG_FB_LINE_COUNT register has a limit */ 242 if (src_h >= HDLCD_MAX_YRES) { 243 DRM_DEBUG_KMS("Invalid source width: %d\n", src_h); 244 return -EINVAL; 245 } 246 247 for_each_new_crtc_in_state(state, crtc, crtc_state, 248 i) { 249 /* we cannot disable the plane while the CRTC is active */ 250 if (!new_plane_state->fb && crtc_state->active) 251 return -EINVAL; 252 return drm_atomic_helper_check_plane_state(new_plane_state, 253 crtc_state, 254 DRM_PLANE_NO_SCALING, 255 DRM_PLANE_NO_SCALING, 256 false, true); 257 } 258 259 return 0; 260 } 261 262 static void hdlcd_plane_atomic_update(struct drm_plane *plane, 263 struct drm_atomic_state *state) 264 { 265 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 266 plane); 267 struct drm_framebuffer *fb = new_plane_state->fb; 268 struct hdlcd_drm_private *hdlcd; 269 u32 dest_h; 270 dma_addr_t scanout_start; 271 272 if (!fb) 273 return; 274 275 dest_h = drm_rect_height(&new_plane_state->dst); 276 scanout_start = drm_fb_dma_get_gem_addr(fb, new_plane_state, 0); 277 278 hdlcd = plane->dev->dev_private; 279 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]); 280 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]); 281 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1); 282 hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start); 283 } 284 285 static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = { 286 .atomic_check = hdlcd_plane_atomic_check, 287 .atomic_update = hdlcd_plane_atomic_update, 288 }; 289 290 static const struct drm_plane_funcs hdlcd_plane_funcs = { 291 .update_plane = drm_atomic_helper_update_plane, 292 .disable_plane = drm_atomic_helper_disable_plane, 293 .destroy = drm_plane_cleanup, 294 .reset = drm_atomic_helper_plane_reset, 295 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 296 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 297 }; 298 299 static struct drm_plane *hdlcd_plane_init(struct drm_device *drm) 300 { 301 struct hdlcd_drm_private *hdlcd = drm->dev_private; 302 struct drm_plane *plane = NULL; 303 u32 formats[ARRAY_SIZE(supported_formats)], i; 304 int ret; 305 306 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); 307 if (!plane) 308 return ERR_PTR(-ENOMEM); 309 310 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) 311 formats[i] = supported_formats[i].fourcc; 312 313 ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs, 314 formats, ARRAY_SIZE(formats), 315 NULL, 316 DRM_PLANE_TYPE_PRIMARY, NULL); 317 if (ret) 318 return ERR_PTR(ret); 319 320 drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs); 321 hdlcd->plane = plane; 322 323 return plane; 324 } 325 326 int hdlcd_setup_crtc(struct drm_device *drm) 327 { 328 struct hdlcd_drm_private *hdlcd = drm->dev_private; 329 struct drm_plane *primary; 330 int ret; 331 332 primary = hdlcd_plane_init(drm); 333 if (IS_ERR(primary)) 334 return PTR_ERR(primary); 335 336 ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL, 337 &hdlcd_crtc_funcs, NULL); 338 if (ret) 339 return ret; 340 341 drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs); 342 return 0; 343 } 344