1 /* 2 * Copyright (C) 2013-2015 ARM Limited 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file COPYING in the main directory of this archive 7 * for more details. 8 * 9 * Implementation of a CRTC class for the HDLCD driver. 10 */ 11 12 #include <drm/drmP.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_crtc.h> 15 #include <drm/drm_crtc_helper.h> 16 #include <drm/drm_fb_helper.h> 17 #include <drm/drm_fb_cma_helper.h> 18 #include <drm/drm_gem_cma_helper.h> 19 #include <drm/drm_of.h> 20 #include <drm/drm_plane_helper.h> 21 #include <linux/clk.h> 22 #include <linux/of_graph.h> 23 #include <linux/platform_data/simplefb.h> 24 #include <video/videomode.h> 25 26 #include "hdlcd_drv.h" 27 #include "hdlcd_regs.h" 28 29 /* 30 * The HDLCD controller is a dumb RGB streamer that gets connected to 31 * a single HDMI transmitter or in the case of the ARM Models it gets 32 * emulated by the software that does the actual rendering. 33 * 34 */ 35 36 static void hdlcd_crtc_cleanup(struct drm_crtc *crtc) 37 { 38 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 39 40 /* stop the controller on cleanup */ 41 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); 42 drm_crtc_cleanup(crtc); 43 } 44 45 static const struct drm_crtc_funcs hdlcd_crtc_funcs = { 46 .destroy = hdlcd_crtc_cleanup, 47 .set_config = drm_atomic_helper_set_config, 48 .page_flip = drm_atomic_helper_page_flip, 49 .reset = drm_atomic_helper_crtc_reset, 50 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 51 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 52 }; 53 54 static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS; 55 56 /* 57 * Setup the HDLCD registers for decoding the pixels out of the framebuffer 58 */ 59 static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc) 60 { 61 unsigned int btpp; 62 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 63 uint32_t pixel_format; 64 struct simplefb_format *format = NULL; 65 int i; 66 67 pixel_format = crtc->primary->state->fb->pixel_format; 68 69 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { 70 if (supported_formats[i].fourcc == pixel_format) 71 format = &supported_formats[i]; 72 } 73 74 if (WARN_ON(!format)) 75 return 0; 76 77 /* HDLCD uses 'bytes per pixel', zero means 1 byte */ 78 btpp = (format->bits_per_pixel + 7) / 8; 79 hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3); 80 81 /* 82 * The format of the HDLCD_REG_<color>_SELECT register is: 83 * - bits[23:16] - default value for that color component 84 * - bits[11:8] - number of bits to extract for each color component 85 * - bits[4:0] - index of the lowest bit to extract 86 * 87 * The default color value is used when bits[11:8] are zero, when the 88 * pixel is outside the visible frame area or when there is a 89 * buffer underrun. 90 */ 91 hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset | 92 #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN 93 0x00ff0000 | /* show underruns in red */ 94 #endif 95 ((format->red.length & 0xf) << 8)); 96 hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset | 97 ((format->green.length & 0xf) << 8)); 98 hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset | 99 ((format->blue.length & 0xf) << 8)); 100 101 return 0; 102 } 103 104 static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) 105 { 106 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 107 struct drm_display_mode *m = &crtc->state->adjusted_mode; 108 struct videomode vm; 109 unsigned int polarities, err; 110 111 vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; 112 vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; 113 vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; 114 vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; 115 vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; 116 vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; 117 118 polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA; 119 120 if (m->flags & DRM_MODE_FLAG_PHSYNC) 121 polarities |= HDLCD_POLARITY_HSYNC; 122 if (m->flags & DRM_MODE_FLAG_PVSYNC) 123 polarities |= HDLCD_POLARITY_VSYNC; 124 125 /* Allow max number of outstanding requests and largest burst size */ 126 hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS, 127 HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16); 128 129 hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1); 130 hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1); 131 hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1); 132 hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1); 133 hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1); 134 hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1); 135 hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1); 136 hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1); 137 hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities); 138 139 err = hdlcd_set_pxl_fmt(crtc); 140 if (err) 141 return; 142 143 clk_set_rate(hdlcd->clk, m->crtc_clock * 1000); 144 } 145 146 static void hdlcd_crtc_enable(struct drm_crtc *crtc) 147 { 148 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 149 150 clk_prepare_enable(hdlcd->clk); 151 hdlcd_crtc_mode_set_nofb(crtc); 152 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); 153 drm_crtc_vblank_on(crtc); 154 } 155 156 static void hdlcd_crtc_disable(struct drm_crtc *crtc) 157 { 158 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 159 160 drm_crtc_vblank_off(crtc); 161 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); 162 clk_disable_unprepare(hdlcd->clk); 163 } 164 165 static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc, 166 struct drm_crtc_state *state) 167 { 168 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 169 struct drm_display_mode *mode = &state->adjusted_mode; 170 long rate, clk_rate = mode->clock * 1000; 171 172 rate = clk_round_rate(hdlcd->clk, clk_rate); 173 if (rate != clk_rate) { 174 /* clock required by mode not supported by hardware */ 175 return -EINVAL; 176 } 177 178 return 0; 179 } 180 181 static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, 182 struct drm_crtc_state *state) 183 { 184 struct drm_pending_vblank_event *event = crtc->state->event; 185 186 if (event) { 187 crtc->state->event = NULL; 188 189 spin_lock_irq(&crtc->dev->event_lock); 190 if (drm_crtc_vblank_get(crtc) == 0) 191 drm_crtc_arm_vblank_event(crtc, event); 192 else 193 drm_crtc_send_vblank_event(crtc, event); 194 spin_unlock_irq(&crtc->dev->event_lock); 195 } 196 } 197 198 static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { 199 .enable = hdlcd_crtc_enable, 200 .disable = hdlcd_crtc_disable, 201 .atomic_check = hdlcd_crtc_atomic_check, 202 .atomic_begin = hdlcd_crtc_atomic_begin, 203 }; 204 205 static int hdlcd_plane_atomic_check(struct drm_plane *plane, 206 struct drm_plane_state *state) 207 { 208 u32 src_w, src_h; 209 210 src_w = state->src_w >> 16; 211 src_h = state->src_h >> 16; 212 213 /* we can't do any scaling of the plane source */ 214 if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) 215 return -EINVAL; 216 217 return 0; 218 } 219 220 static void hdlcd_plane_atomic_update(struct drm_plane *plane, 221 struct drm_plane_state *state) 222 { 223 struct hdlcd_drm_private *hdlcd; 224 struct drm_gem_cma_object *gem; 225 u32 src_w, src_h, dest_w, dest_h; 226 dma_addr_t scanout_start; 227 228 if (!plane->state->fb) 229 return; 230 231 src_w = plane->state->src_w >> 16; 232 src_h = plane->state->src_h >> 16; 233 dest_w = plane->state->crtc_w; 234 dest_h = plane->state->crtc_h; 235 gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0); 236 scanout_start = gem->paddr + plane->state->fb->offsets[0] + 237 plane->state->crtc_y * plane->state->fb->pitches[0] + 238 plane->state->crtc_x * 239 drm_format_plane_cpp(plane->state->fb->pixel_format, 0); 240 241 hdlcd = plane->dev->dev_private; 242 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, plane->state->fb->pitches[0]); 243 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, plane->state->fb->pitches[0]); 244 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1); 245 hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start); 246 } 247 248 static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = { 249 .atomic_check = hdlcd_plane_atomic_check, 250 .atomic_update = hdlcd_plane_atomic_update, 251 }; 252 253 static void hdlcd_plane_destroy(struct drm_plane *plane) 254 { 255 drm_plane_helper_disable(plane); 256 drm_plane_cleanup(plane); 257 } 258 259 static const struct drm_plane_funcs hdlcd_plane_funcs = { 260 .update_plane = drm_atomic_helper_update_plane, 261 .disable_plane = drm_atomic_helper_disable_plane, 262 .destroy = hdlcd_plane_destroy, 263 .reset = drm_atomic_helper_plane_reset, 264 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 265 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 266 }; 267 268 static struct drm_plane *hdlcd_plane_init(struct drm_device *drm) 269 { 270 struct hdlcd_drm_private *hdlcd = drm->dev_private; 271 struct drm_plane *plane = NULL; 272 u32 formats[ARRAY_SIZE(supported_formats)], i; 273 int ret; 274 275 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); 276 if (!plane) 277 return ERR_PTR(-ENOMEM); 278 279 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) 280 formats[i] = supported_formats[i].fourcc; 281 282 ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs, 283 formats, ARRAY_SIZE(formats), 284 DRM_PLANE_TYPE_PRIMARY, NULL); 285 if (ret) { 286 devm_kfree(drm->dev, plane); 287 return ERR_PTR(ret); 288 } 289 290 drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs); 291 hdlcd->plane = plane; 292 293 return plane; 294 } 295 296 int hdlcd_setup_crtc(struct drm_device *drm) 297 { 298 struct hdlcd_drm_private *hdlcd = drm->dev_private; 299 struct drm_plane *primary; 300 int ret; 301 302 primary = hdlcd_plane_init(drm); 303 if (IS_ERR(primary)) 304 return PTR_ERR(primary); 305 306 ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL, 307 &hdlcd_crtc_funcs, NULL); 308 if (ret) { 309 hdlcd_plane_destroy(primary); 310 devm_kfree(drm->dev, primary); 311 return ret; 312 } 313 314 drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs); 315 return 0; 316 } 317