1 /* 2 * Copyright (C) 2013-2015 ARM Limited 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file COPYING in the main directory of this archive 7 * for more details. 8 * 9 * Implementation of a CRTC class for the HDLCD driver. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/of_graph.h> 14 #include <linux/platform_data/simplefb.h> 15 16 #include <video/videomode.h> 17 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_crtc.h> 21 #include <drm/drm_fb_cma_helper.h> 22 #include <drm/drm_fb_helper.h> 23 #include <drm/drm_framebuffer.h> 24 #include <drm/drm_gem_cma_helper.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_plane_helper.h> 27 #include <drm/drm_probe_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include "hdlcd_drv.h" 31 #include "hdlcd_regs.h" 32 33 /* 34 * The HDLCD controller is a dumb RGB streamer that gets connected to 35 * a single HDMI transmitter or in the case of the ARM Models it gets 36 * emulated by the software that does the actual rendering. 37 * 38 */ 39 40 static void hdlcd_crtc_cleanup(struct drm_crtc *crtc) 41 { 42 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 43 44 /* stop the controller on cleanup */ 45 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); 46 drm_crtc_cleanup(crtc); 47 } 48 49 static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc) 50 { 51 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 52 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 53 54 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); 55 56 return 0; 57 } 58 59 static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc) 60 { 61 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 62 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 63 64 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); 65 } 66 67 static const struct drm_crtc_funcs hdlcd_crtc_funcs = { 68 .destroy = hdlcd_crtc_cleanup, 69 .set_config = drm_atomic_helper_set_config, 70 .page_flip = drm_atomic_helper_page_flip, 71 .reset = drm_atomic_helper_crtc_reset, 72 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 73 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 74 .enable_vblank = hdlcd_crtc_enable_vblank, 75 .disable_vblank = hdlcd_crtc_disable_vblank, 76 }; 77 78 static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS; 79 80 /* 81 * Setup the HDLCD registers for decoding the pixels out of the framebuffer 82 */ 83 static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc) 84 { 85 unsigned int btpp; 86 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 87 const struct drm_framebuffer *fb = crtc->primary->state->fb; 88 uint32_t pixel_format; 89 struct simplefb_format *format = NULL; 90 int i; 91 92 pixel_format = fb->format->format; 93 94 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { 95 if (supported_formats[i].fourcc == pixel_format) 96 format = &supported_formats[i]; 97 } 98 99 if (WARN_ON(!format)) 100 return 0; 101 102 /* HDLCD uses 'bytes per pixel', zero means 1 byte */ 103 btpp = (format->bits_per_pixel + 7) / 8; 104 hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3); 105 106 /* 107 * The format of the HDLCD_REG_<color>_SELECT register is: 108 * - bits[23:16] - default value for that color component 109 * - bits[11:8] - number of bits to extract for each color component 110 * - bits[4:0] - index of the lowest bit to extract 111 * 112 * The default color value is used when bits[11:8] are zero, when the 113 * pixel is outside the visible frame area or when there is a 114 * buffer underrun. 115 */ 116 hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset | 117 #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN 118 0x00ff0000 | /* show underruns in red */ 119 #endif 120 ((format->red.length & 0xf) << 8)); 121 hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset | 122 ((format->green.length & 0xf) << 8)); 123 hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset | 124 ((format->blue.length & 0xf) << 8)); 125 126 return 0; 127 } 128 129 static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) 130 { 131 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 132 struct drm_display_mode *m = &crtc->state->adjusted_mode; 133 struct videomode vm; 134 unsigned int polarities, err; 135 136 vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; 137 vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; 138 vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; 139 vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; 140 vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; 141 vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; 142 143 polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA; 144 145 if (m->flags & DRM_MODE_FLAG_PHSYNC) 146 polarities |= HDLCD_POLARITY_HSYNC; 147 if (m->flags & DRM_MODE_FLAG_PVSYNC) 148 polarities |= HDLCD_POLARITY_VSYNC; 149 150 /* Allow max number of outstanding requests and largest burst size */ 151 hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS, 152 HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16); 153 154 hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1); 155 hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1); 156 hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1); 157 hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1); 158 hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1); 159 hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1); 160 hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1); 161 hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1); 162 hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities); 163 164 err = hdlcd_set_pxl_fmt(crtc); 165 if (err) 166 return; 167 168 clk_set_rate(hdlcd->clk, m->crtc_clock * 1000); 169 } 170 171 static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, 172 struct drm_atomic_state *state) 173 { 174 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 175 176 clk_prepare_enable(hdlcd->clk); 177 hdlcd_crtc_mode_set_nofb(crtc); 178 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); 179 drm_crtc_vblank_on(crtc); 180 } 181 182 static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc, 183 struct drm_atomic_state *state) 184 { 185 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 186 187 drm_crtc_vblank_off(crtc); 188 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); 189 clk_disable_unprepare(hdlcd->clk); 190 } 191 192 static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, 193 const struct drm_display_mode *mode) 194 { 195 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 196 long rate, clk_rate = mode->clock * 1000; 197 198 rate = clk_round_rate(hdlcd->clk, clk_rate); 199 /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */ 200 if (abs(rate - clk_rate) * 1000 > clk_rate) { 201 /* clock required by mode not supported by hardware */ 202 return MODE_NOCLOCK; 203 } 204 205 return MODE_OK; 206 } 207 208 static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, 209 struct drm_atomic_state *state) 210 { 211 struct drm_pending_vblank_event *event = crtc->state->event; 212 213 if (event) { 214 crtc->state->event = NULL; 215 216 spin_lock_irq(&crtc->dev->event_lock); 217 if (drm_crtc_vblank_get(crtc) == 0) 218 drm_crtc_arm_vblank_event(crtc, event); 219 else 220 drm_crtc_send_vblank_event(crtc, event); 221 spin_unlock_irq(&crtc->dev->event_lock); 222 } 223 } 224 225 static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { 226 .mode_valid = hdlcd_crtc_mode_valid, 227 .atomic_begin = hdlcd_crtc_atomic_begin, 228 .atomic_enable = hdlcd_crtc_atomic_enable, 229 .atomic_disable = hdlcd_crtc_atomic_disable, 230 }; 231 232 static int hdlcd_plane_atomic_check(struct drm_plane *plane, 233 struct drm_atomic_state *state) 234 { 235 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 236 plane); 237 int i; 238 struct drm_crtc *crtc; 239 struct drm_crtc_state *crtc_state; 240 u32 src_h = new_plane_state->src_h >> 16; 241 242 /* only the HDLCD_REG_FB_LINE_COUNT register has a limit */ 243 if (src_h >= HDLCD_MAX_YRES) { 244 DRM_DEBUG_KMS("Invalid source width: %d\n", src_h); 245 return -EINVAL; 246 } 247 248 for_each_new_crtc_in_state(state, crtc, crtc_state, 249 i) { 250 /* we cannot disable the plane while the CRTC is active */ 251 if (!new_plane_state->fb && crtc_state->active) 252 return -EINVAL; 253 return drm_atomic_helper_check_plane_state(new_plane_state, 254 crtc_state, 255 DRM_PLANE_HELPER_NO_SCALING, 256 DRM_PLANE_HELPER_NO_SCALING, 257 false, true); 258 } 259 260 return 0; 261 } 262 263 static void hdlcd_plane_atomic_update(struct drm_plane *plane, 264 struct drm_atomic_state *state) 265 { 266 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 267 plane); 268 struct drm_framebuffer *fb = new_plane_state->fb; 269 struct hdlcd_drm_private *hdlcd; 270 u32 dest_h; 271 dma_addr_t scanout_start; 272 273 if (!fb) 274 return; 275 276 dest_h = drm_rect_height(&new_plane_state->dst); 277 scanout_start = drm_fb_cma_get_gem_addr(fb, new_plane_state, 0); 278 279 hdlcd = plane->dev->dev_private; 280 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]); 281 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]); 282 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1); 283 hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start); 284 } 285 286 static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = { 287 .atomic_check = hdlcd_plane_atomic_check, 288 .atomic_update = hdlcd_plane_atomic_update, 289 }; 290 291 static const struct drm_plane_funcs hdlcd_plane_funcs = { 292 .update_plane = drm_atomic_helper_update_plane, 293 .disable_plane = drm_atomic_helper_disable_plane, 294 .destroy = drm_plane_cleanup, 295 .reset = drm_atomic_helper_plane_reset, 296 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 297 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 298 }; 299 300 static struct drm_plane *hdlcd_plane_init(struct drm_device *drm) 301 { 302 struct hdlcd_drm_private *hdlcd = drm->dev_private; 303 struct drm_plane *plane = NULL; 304 u32 formats[ARRAY_SIZE(supported_formats)], i; 305 int ret; 306 307 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); 308 if (!plane) 309 return ERR_PTR(-ENOMEM); 310 311 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) 312 formats[i] = supported_formats[i].fourcc; 313 314 ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs, 315 formats, ARRAY_SIZE(formats), 316 NULL, 317 DRM_PLANE_TYPE_PRIMARY, NULL); 318 if (ret) 319 return ERR_PTR(ret); 320 321 drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs); 322 hdlcd->plane = plane; 323 324 return plane; 325 } 326 327 int hdlcd_setup_crtc(struct drm_device *drm) 328 { 329 struct hdlcd_drm_private *hdlcd = drm->dev_private; 330 struct drm_plane *primary; 331 int ret; 332 333 primary = hdlcd_plane_init(drm); 334 if (IS_ERR(primary)) 335 return PTR_ERR(primary); 336 337 ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL, 338 &hdlcd_crtc_funcs, NULL); 339 if (ret) 340 return ret; 341 342 drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs); 343 return 0; 344 } 345