1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
4  * Author: James.Qian.Wang <james.qian.wang@arm.com>
5  *
6  */
7 #ifndef _KOMEDA_DEV_H_
8 #define _KOMEDA_DEV_H_
9 
10 #include <linux/device.h>
11 #include <linux/clk.h>
12 #include "komeda_pipeline.h"
13 #include "malidp_product.h"
14 #include "komeda_format_caps.h"
15 
16 #define KOMEDA_EVENT_VSYNC		BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP		BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN		BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY		BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR		BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW		BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE		BIT_ULL(6)
23 
24 #define KOMEDA_ERR_TETO			BIT_ULL(14)
25 #define KOMEDA_ERR_TEMR			BIT_ULL(15)
26 #define KOMEDA_ERR_TITR			BIT_ULL(16)
27 #define KOMEDA_ERR_CPE			BIT_ULL(17)
28 #define KOMEDA_ERR_CFGE			BIT_ULL(18)
29 #define KOMEDA_ERR_AXIE			BIT_ULL(19)
30 #define KOMEDA_ERR_ACE0			BIT_ULL(20)
31 #define KOMEDA_ERR_ACE1			BIT_ULL(21)
32 #define KOMEDA_ERR_ACE2			BIT_ULL(22)
33 #define KOMEDA_ERR_ACE3			BIT_ULL(23)
34 #define KOMEDA_ERR_DRIFTTO		BIT_ULL(24)
35 #define KOMEDA_ERR_FRAMETO		BIT_ULL(25)
36 #define KOMEDA_ERR_CSCE			BIT_ULL(26)
37 #define KOMEDA_ERR_ZME			BIT_ULL(27)
38 #define KOMEDA_ERR_MERR			BIT_ULL(28)
39 #define KOMEDA_ERR_TCF			BIT_ULL(29)
40 #define KOMEDA_ERR_TTNG			BIT_ULL(30)
41 #define KOMEDA_ERR_TTF			BIT_ULL(31)
42 
43 /* malidp device id */
44 enum {
45 	MALI_D71 = 0,
46 };
47 
48 /* pipeline DT ports */
49 enum {
50 	KOMEDA_OF_PORT_OUTPUT		= 0,
51 	KOMEDA_OF_PORT_COPROC		= 1,
52 };
53 
54 struct komeda_chip_info {
55 	u32 arch_id;
56 	u32 core_id;
57 	u32 core_info;
58 	u32 bus_width;
59 };
60 
61 struct komeda_product_data {
62 	u32 product_id;
63 	struct komeda_dev_funcs *(*identify)(u32 __iomem *reg,
64 					     struct komeda_chip_info *info);
65 };
66 
67 struct komeda_dev;
68 
69 struct komeda_events {
70 	u64 global;
71 	u64 pipes[KOMEDA_MAX_PIPELINES];
72 };
73 
74 /**
75  * struct komeda_dev_funcs
76  *
77  * Supplied by chip level and returned by the chip entry function xxx_identify,
78  */
79 struct komeda_dev_funcs {
80 	/**
81 	 * @init_format_table:
82 	 *
83 	 * initialize &komeda_dev->format_table, this function should be called
84 	 * before the &enum_resource
85 	 */
86 	void (*init_format_table)(struct komeda_dev *mdev);
87 	/**
88 	 * @enum_resources:
89 	 *
90 	 * for CHIP to report or add pipeline and component resources to CORE
91 	 */
92 	int (*enum_resources)(struct komeda_dev *mdev);
93 	/** @cleanup: call to chip to cleanup komeda_dev->chip data */
94 	void (*cleanup)(struct komeda_dev *mdev);
95 	/**
96 	 * @irq_handler:
97 	 *
98 	 * for CORE to get the HW event from the CHIP when interrupt happened.
99 	 */
100 	irqreturn_t (*irq_handler)(struct komeda_dev *mdev,
101 				   struct komeda_events *events);
102 	/** @enable_irq: enable irq */
103 	int (*enable_irq)(struct komeda_dev *mdev);
104 	/** @disable_irq: disable irq */
105 	int (*disable_irq)(struct komeda_dev *mdev);
106 	/** @on_off_vblank: notify HW to on/off vblank */
107 	void (*on_off_vblank)(struct komeda_dev *mdev,
108 			      int master_pipe, bool on);
109 
110 	/** @dump_register: Optional, dump registers to seq_file */
111 	void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);
112 	/**
113 	 * @change_opmode:
114 	 *
115 	 * Notify HW to switch to a new display operation mode.
116 	 */
117 	int (*change_opmode)(struct komeda_dev *mdev, int new_mode);
118 	/** @flush: Notify the HW to flush or kickoff the update */
119 	void (*flush)(struct komeda_dev *mdev,
120 		      int master_pipe, u32 active_pipes);
121 };
122 
123 /*
124  * DISPLAY_MODE describes how many display been enabled, and which will be
125  * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the
126  * pipeline resources assignment according to this usage hint.
127  * -   KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.
128  * -   KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.
129  * -   KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.
130  * And D71 supports assign two pipelines to one single display on mode
131  * KOMEDA_MODE_DISP0/DISP1
132  */
133 enum {
134 	KOMEDA_MODE_INACTIVE	= 0,
135 	KOMEDA_MODE_DISP0	= BIT(0),
136 	KOMEDA_MODE_DISP1	= BIT(1),
137 	KOMEDA_MODE_DUAL_DISP	= KOMEDA_MODE_DISP0 | KOMEDA_MODE_DISP1,
138 };
139 
140 /**
141  * struct komeda_dev
142  *
143  * Pipeline and component are used to describe how to handle the pixel data.
144  * komeda_device is for describing the whole view of the device, and the
145  * control-abilites of device.
146  */
147 struct komeda_dev {
148 	/** @dev: the base device structure */
149 	struct device *dev;
150 	/** @reg_base: the base address of komeda io space */
151 	u32 __iomem   *reg_base;
152 
153 	/** @chip: the basic chip information */
154 	struct komeda_chip_info chip;
155 	/** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */
156 	struct komeda_format_caps_table fmt_tbl;
157 	/** @pclk: APB clock for register access */
158 	struct clk *pclk;
159 	/** @mclk: HW main engine clk */
160 	struct clk *mclk;
161 
162 	/** @irq: irq number */
163 	int irq;
164 
165 	/** @lock: used to protect dpmode */
166 	struct mutex lock;
167 	/** @dpmode: current display mode */
168 	u32 dpmode;
169 
170 	/** @n_pipelines: the number of pipe in @pipelines */
171 	int n_pipelines;
172 	/** @pipelines: the komeda pipelines */
173 	struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
174 
175 	/** @funcs: chip funcs to access to HW */
176 	struct komeda_dev_funcs *funcs;
177 	/**
178 	 * @chip_data:
179 	 *
180 	 * chip data will be added by &komeda_dev_funcs.enum_resources() and
181 	 * destroyed by &komeda_dev_funcs.cleanup()
182 	 */
183 	void *chip_data;
184 
185 	/** @debugfs_root: root directory of komeda debugfs */
186 	struct dentry *debugfs_root;
187 };
188 
189 static inline bool
190 komeda_product_match(struct komeda_dev *mdev, u32 target)
191 {
192 	return MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id) == target;
193 }
194 
195 struct komeda_dev_funcs *
196 d71_identify(u32 __iomem *reg, struct komeda_chip_info *chip);
197 
198 struct komeda_dev *komeda_dev_create(struct device *dev);
199 void komeda_dev_destroy(struct komeda_dev *mdev);
200 
201 struct komeda_dev *dev_to_mdev(struct device *dev);
202 
203 #endif /*_KOMEDA_DEV_H_*/
204