1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) COPYRIGHT 2018 ARM Limited. All rights reserved. 4 * Author: James.Qian.Wang <james.qian.wang@arm.com> 5 * 6 */ 7 #include <linux/clk.h> 8 #include <linux/pm_runtime.h> 9 #include <linux/spinlock.h> 10 11 #include <drm/drm_atomic.h> 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_crtc_helper.h> 14 #include <drm/drm_print.h> 15 #include <drm/drm_vblank.h> 16 17 #include "komeda_dev.h" 18 #include "komeda_kms.h" 19 20 void komeda_crtc_get_color_config(struct drm_crtc_state *crtc_st, 21 u32 *color_depths, u32 *color_formats) 22 { 23 struct drm_connector *conn; 24 struct drm_connector_state *conn_st; 25 u32 conn_color_formats = ~0u; 26 int i, min_bpc = 31, conn_bpc = 0; 27 28 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { 29 if (conn_st->crtc != crtc_st->crtc) 30 continue; 31 32 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; 33 conn_color_formats &= conn->display_info.color_formats; 34 35 if (conn_bpc < min_bpc) 36 min_bpc = conn_bpc; 37 } 38 39 /* connector doesn't config any color_format, use RGB444 as default */ 40 if (!conn_color_formats) 41 conn_color_formats = DRM_COLOR_FORMAT_RGB444; 42 43 *color_depths = GENMASK(min_bpc, 0); 44 *color_formats = conn_color_formats; 45 } 46 47 static void komeda_crtc_update_clock_ratio(struct komeda_crtc_state *kcrtc_st) 48 { 49 u64 pxlclk, aclk; 50 51 if (!kcrtc_st->base.active) { 52 kcrtc_st->clock_ratio = 0; 53 return; 54 } 55 56 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; 57 aclk = komeda_crtc_get_aclk(kcrtc_st); 58 59 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); 60 } 61 62 /** 63 * komeda_crtc_atomic_check - build display output data flow 64 * @crtc: DRM crtc 65 * @state: the crtc state object 66 * 67 * crtc_atomic_check is the final check stage, so beside build a display data 68 * pipeline according to the crtc_state, but still needs to release or disable 69 * the unclaimed pipeline resources. 70 * 71 * RETURNS: 72 * Zero for success or -errno 73 */ 74 static int 75 komeda_crtc_atomic_check(struct drm_crtc *crtc, 76 struct drm_atomic_state *state) 77 { 78 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 79 crtc); 80 struct komeda_crtc *kcrtc = to_kcrtc(crtc); 81 struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc_state); 82 int err; 83 84 if (drm_atomic_crtc_needs_modeset(crtc_state)) 85 komeda_crtc_update_clock_ratio(kcrtc_st); 86 87 if (crtc_state->active) { 88 err = komeda_build_display_data_flow(kcrtc, kcrtc_st); 89 if (err) 90 return err; 91 } 92 93 /* release unclaimed pipeline resources */ 94 err = komeda_release_unclaimed_resources(kcrtc->slave, kcrtc_st); 95 if (err) 96 return err; 97 98 err = komeda_release_unclaimed_resources(kcrtc->master, kcrtc_st); 99 if (err) 100 return err; 101 102 return 0; 103 } 104 105 /* For active a crtc, mainly need two parts of preparation 106 * 1. adjust display operation mode. 107 * 2. enable needed clk 108 */ 109 static int 110 komeda_crtc_prepare(struct komeda_crtc *kcrtc) 111 { 112 struct komeda_dev *mdev = kcrtc->base.dev->dev_private; 113 struct komeda_pipeline *master = kcrtc->master; 114 struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(kcrtc->base.state); 115 struct drm_display_mode *mode = &kcrtc_st->base.adjusted_mode; 116 u32 new_mode; 117 int err; 118 119 mutex_lock(&mdev->lock); 120 121 new_mode = mdev->dpmode | BIT(master->id); 122 if (WARN_ON(new_mode == mdev->dpmode)) { 123 err = 0; 124 goto unlock; 125 } 126 127 err = mdev->funcs->change_opmode(mdev, new_mode); 128 if (err) { 129 DRM_ERROR("failed to change opmode: 0x%x -> 0x%x.\n,", 130 mdev->dpmode, new_mode); 131 goto unlock; 132 } 133 134 mdev->dpmode = new_mode; 135 /* Only need to enable aclk on single display mode, but no need to 136 * enable aclk it on dual display mode, since the dual mode always 137 * switch from single display mode, the aclk already enabled, no need 138 * to enable it again. 139 */ 140 if (new_mode != KOMEDA_MODE_DUAL_DISP) { 141 err = clk_set_rate(mdev->aclk, komeda_crtc_get_aclk(kcrtc_st)); 142 if (err) 143 DRM_ERROR("failed to set aclk.\n"); 144 err = clk_prepare_enable(mdev->aclk); 145 if (err) 146 DRM_ERROR("failed to enable aclk.\n"); 147 } 148 149 err = clk_set_rate(master->pxlclk, mode->crtc_clock * 1000); 150 if (err) 151 DRM_ERROR("failed to set pxlclk for pipe%d\n", master->id); 152 err = clk_prepare_enable(master->pxlclk); 153 if (err) 154 DRM_ERROR("failed to enable pxl clk for pipe%d.\n", master->id); 155 156 unlock: 157 mutex_unlock(&mdev->lock); 158 159 return err; 160 } 161 162 static int 163 komeda_crtc_unprepare(struct komeda_crtc *kcrtc) 164 { 165 struct komeda_dev *mdev = kcrtc->base.dev->dev_private; 166 struct komeda_pipeline *master = kcrtc->master; 167 u32 new_mode; 168 int err; 169 170 mutex_lock(&mdev->lock); 171 172 new_mode = mdev->dpmode & (~BIT(master->id)); 173 174 if (WARN_ON(new_mode == mdev->dpmode)) { 175 err = 0; 176 goto unlock; 177 } 178 179 err = mdev->funcs->change_opmode(mdev, new_mode); 180 if (err) { 181 DRM_ERROR("failed to change opmode: 0x%x -> 0x%x.\n,", 182 mdev->dpmode, new_mode); 183 goto unlock; 184 } 185 186 mdev->dpmode = new_mode; 187 188 clk_disable_unprepare(master->pxlclk); 189 if (new_mode == KOMEDA_MODE_INACTIVE) 190 clk_disable_unprepare(mdev->aclk); 191 192 unlock: 193 mutex_unlock(&mdev->lock); 194 195 return err; 196 } 197 198 void komeda_crtc_handle_event(struct komeda_crtc *kcrtc, 199 struct komeda_events *evts) 200 { 201 struct drm_crtc *crtc = &kcrtc->base; 202 u32 events = evts->pipes[kcrtc->master->id]; 203 204 if (events & KOMEDA_EVENT_VSYNC) 205 drm_crtc_handle_vblank(crtc); 206 207 if (events & KOMEDA_EVENT_EOW) { 208 struct komeda_wb_connector *wb_conn = kcrtc->wb_conn; 209 210 if (wb_conn) 211 drm_writeback_signal_completion(&wb_conn->base, 0); 212 else 213 DRM_WARN("CRTC[%d]: EOW happen but no wb_connector.\n", 214 drm_crtc_index(&kcrtc->base)); 215 } 216 /* will handle it together with the write back support */ 217 if (events & KOMEDA_EVENT_EOW) 218 DRM_DEBUG("EOW.\n"); 219 220 if (events & KOMEDA_EVENT_FLIP) { 221 unsigned long flags; 222 struct drm_pending_vblank_event *event; 223 224 spin_lock_irqsave(&crtc->dev->event_lock, flags); 225 if (kcrtc->disable_done) { 226 complete_all(kcrtc->disable_done); 227 kcrtc->disable_done = NULL; 228 } else if (crtc->state->event) { 229 event = crtc->state->event; 230 /* 231 * Consume event before notifying drm core that flip 232 * happened. 233 */ 234 crtc->state->event = NULL; 235 drm_crtc_send_vblank_event(crtc, event); 236 } else { 237 DRM_WARN("CRTC[%d]: FLIP happened but no pending commit.\n", 238 drm_crtc_index(&kcrtc->base)); 239 } 240 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 241 } 242 } 243 244 static void 245 komeda_crtc_do_flush(struct drm_crtc *crtc, 246 struct drm_crtc_state *old) 247 { 248 struct komeda_crtc *kcrtc = to_kcrtc(crtc); 249 struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc->state); 250 struct komeda_dev *mdev = kcrtc->base.dev->dev_private; 251 struct komeda_pipeline *master = kcrtc->master; 252 struct komeda_pipeline *slave = kcrtc->slave; 253 struct komeda_wb_connector *wb_conn = kcrtc->wb_conn; 254 struct drm_connector_state *conn_st; 255 256 DRM_DEBUG_ATOMIC("CRTC%d_FLUSH: active_pipes: 0x%x, affected: 0x%x.\n", 257 drm_crtc_index(crtc), 258 kcrtc_st->active_pipes, kcrtc_st->affected_pipes); 259 260 /* step 1: update the pipeline/component state to HW */ 261 if (has_bit(master->id, kcrtc_st->affected_pipes)) 262 komeda_pipeline_update(master, old->state); 263 264 if (slave && has_bit(slave->id, kcrtc_st->affected_pipes)) 265 komeda_pipeline_update(slave, old->state); 266 267 conn_st = wb_conn ? wb_conn->base.base.state : NULL; 268 if (conn_st && conn_st->writeback_job) 269 drm_writeback_queue_job(&wb_conn->base, conn_st); 270 271 /* step 2: notify the HW to kickoff the update */ 272 mdev->funcs->flush(mdev, master->id, kcrtc_st->active_pipes); 273 } 274 275 static void 276 komeda_crtc_atomic_enable(struct drm_crtc *crtc, 277 struct drm_atomic_state *state) 278 { 279 struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, 280 crtc); 281 pm_runtime_get_sync(crtc->dev->dev); 282 komeda_crtc_prepare(to_kcrtc(crtc)); 283 drm_crtc_vblank_on(crtc); 284 WARN_ON(drm_crtc_vblank_get(crtc)); 285 komeda_crtc_do_flush(crtc, old); 286 } 287 288 void 289 komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, 290 struct completion *input_flip_done) 291 { 292 struct drm_device *drm = kcrtc->base.dev; 293 struct komeda_dev *mdev = kcrtc->master->mdev; 294 struct completion *flip_done; 295 struct completion temp; 296 int timeout; 297 298 /* if caller doesn't send a flip_done, use a private flip_done */ 299 if (input_flip_done) { 300 flip_done = input_flip_done; 301 } else { 302 init_completion(&temp); 303 kcrtc->disable_done = &temp; 304 flip_done = &temp; 305 } 306 307 mdev->funcs->flush(mdev, kcrtc->master->id, 0); 308 309 /* wait the flip take affect.*/ 310 timeout = wait_for_completion_timeout(flip_done, HZ); 311 if (timeout == 0) { 312 DRM_ERROR("wait pipe%d flip done timeout\n", kcrtc->master->id); 313 if (!input_flip_done) { 314 unsigned long flags; 315 316 spin_lock_irqsave(&drm->event_lock, flags); 317 kcrtc->disable_done = NULL; 318 spin_unlock_irqrestore(&drm->event_lock, flags); 319 } 320 } 321 } 322 323 static void 324 komeda_crtc_atomic_disable(struct drm_crtc *crtc, 325 struct drm_atomic_state *state) 326 { 327 struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, 328 crtc); 329 struct komeda_crtc *kcrtc = to_kcrtc(crtc); 330 struct komeda_crtc_state *old_st = to_kcrtc_st(old); 331 struct komeda_pipeline *master = kcrtc->master; 332 struct komeda_pipeline *slave = kcrtc->slave; 333 struct completion *disable_done; 334 bool needs_phase2 = false; 335 336 DRM_DEBUG_ATOMIC("CRTC%d_DISABLE: active_pipes: 0x%x, affected: 0x%x\n", 337 drm_crtc_index(crtc), 338 old_st->active_pipes, old_st->affected_pipes); 339 340 if (slave && has_bit(slave->id, old_st->active_pipes)) 341 komeda_pipeline_disable(slave, old->state); 342 343 if (has_bit(master->id, old_st->active_pipes)) 344 needs_phase2 = komeda_pipeline_disable(master, old->state); 345 346 /* crtc_disable has two scenarios according to the state->active switch. 347 * 1. active -> inactive 348 * this commit is a disable commit. and the commit will be finished 349 * or done after the disable operation. on this case we can directly 350 * use the crtc->state->event to tracking the HW disable operation. 351 * 2. active -> active 352 * the crtc->commit is not for disable, but a modeset operation when 353 * crtc is active, such commit actually has been completed by 3 354 * DRM operations: 355 * crtc_disable, update_planes(crtc_flush), crtc_enable 356 * so on this case the crtc->commit is for the whole process. 357 * we can not use it for tracing the disable, we need a temporary 358 * flip_done for tracing the disable. and crtc->state->event for 359 * the crtc_enable operation. 360 * That's also the reason why skip modeset commit in 361 * komeda_crtc_atomic_flush() 362 */ 363 disable_done = (needs_phase2 || crtc->state->active) ? 364 NULL : &crtc->state->commit->flip_done; 365 366 /* wait phase 1 disable done */ 367 komeda_crtc_flush_and_wait_for_flip_done(kcrtc, disable_done); 368 369 /* phase 2 */ 370 if (needs_phase2) { 371 komeda_pipeline_disable(kcrtc->master, old->state); 372 373 disable_done = crtc->state->active ? 374 NULL : &crtc->state->commit->flip_done; 375 376 komeda_crtc_flush_and_wait_for_flip_done(kcrtc, disable_done); 377 } 378 379 drm_crtc_vblank_put(crtc); 380 drm_crtc_vblank_off(crtc); 381 komeda_crtc_unprepare(kcrtc); 382 pm_runtime_put(crtc->dev->dev); 383 } 384 385 static void 386 komeda_crtc_atomic_flush(struct drm_crtc *crtc, 387 struct drm_atomic_state *state) 388 { 389 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 390 crtc); 391 struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, 392 crtc); 393 /* commit with modeset will be handled in enable/disable */ 394 if (drm_atomic_crtc_needs_modeset(crtc_state)) 395 return; 396 397 komeda_crtc_do_flush(crtc, old); 398 } 399 400 /* Returns the minimum frequency of the aclk rate (main engine clock) in Hz */ 401 static unsigned long 402 komeda_calc_min_aclk_rate(struct komeda_crtc *kcrtc, 403 unsigned long pxlclk) 404 { 405 /* Once dual-link one display pipeline drives two display outputs, 406 * the aclk needs run on the double rate of pxlclk 407 */ 408 if (kcrtc->master->dual_link) 409 return pxlclk * 2; 410 else 411 return pxlclk; 412 } 413 414 /* Get current aclk rate that specified by state */ 415 unsigned long komeda_crtc_get_aclk(struct komeda_crtc_state *kcrtc_st) 416 { 417 struct drm_crtc *crtc = kcrtc_st->base.crtc; 418 struct komeda_dev *mdev = crtc->dev->dev_private; 419 unsigned long pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000; 420 unsigned long min_aclk; 421 422 min_aclk = komeda_calc_min_aclk_rate(to_kcrtc(crtc), pxlclk); 423 424 return clk_round_rate(mdev->aclk, min_aclk); 425 } 426 427 static enum drm_mode_status 428 komeda_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *m) 429 { 430 struct komeda_dev *mdev = crtc->dev->dev_private; 431 struct komeda_crtc *kcrtc = to_kcrtc(crtc); 432 struct komeda_pipeline *master = kcrtc->master; 433 unsigned long min_pxlclk, min_aclk; 434 435 if (m->flags & DRM_MODE_FLAG_INTERLACE) 436 return MODE_NO_INTERLACE; 437 438 min_pxlclk = m->clock * 1000; 439 if (master->dual_link) 440 min_pxlclk /= 2; 441 442 if (min_pxlclk != clk_round_rate(master->pxlclk, min_pxlclk)) { 443 DRM_DEBUG_ATOMIC("pxlclk doesn't support %lu Hz\n", min_pxlclk); 444 445 return MODE_NOCLOCK; 446 } 447 448 min_aclk = komeda_calc_min_aclk_rate(to_kcrtc(crtc), min_pxlclk); 449 if (clk_round_rate(mdev->aclk, min_aclk) < min_aclk) { 450 DRM_DEBUG_ATOMIC("engine clk can't satisfy the requirement of %s-clk: %lu.\n", 451 m->name, min_pxlclk); 452 453 return MODE_CLOCK_HIGH; 454 } 455 456 return MODE_OK; 457 } 458 459 static bool komeda_crtc_mode_fixup(struct drm_crtc *crtc, 460 const struct drm_display_mode *m, 461 struct drm_display_mode *adjusted_mode) 462 { 463 struct komeda_crtc *kcrtc = to_kcrtc(crtc); 464 unsigned long clk_rate; 465 466 drm_mode_set_crtcinfo(adjusted_mode, 0); 467 /* In dual link half the horizontal settings */ 468 if (kcrtc->master->dual_link) { 469 adjusted_mode->crtc_clock /= 2; 470 adjusted_mode->crtc_hdisplay /= 2; 471 adjusted_mode->crtc_hsync_start /= 2; 472 adjusted_mode->crtc_hsync_end /= 2; 473 adjusted_mode->crtc_htotal /= 2; 474 } 475 476 clk_rate = adjusted_mode->crtc_clock * 1000; 477 /* crtc_clock will be used as the komeda output pixel clock */ 478 adjusted_mode->crtc_clock = clk_round_rate(kcrtc->master->pxlclk, 479 clk_rate) / 1000; 480 481 return true; 482 } 483 484 static const struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = { 485 .atomic_check = komeda_crtc_atomic_check, 486 .atomic_flush = komeda_crtc_atomic_flush, 487 .atomic_enable = komeda_crtc_atomic_enable, 488 .atomic_disable = komeda_crtc_atomic_disable, 489 .mode_valid = komeda_crtc_mode_valid, 490 .mode_fixup = komeda_crtc_mode_fixup, 491 }; 492 493 static void komeda_crtc_reset(struct drm_crtc *crtc) 494 { 495 struct komeda_crtc_state *state; 496 497 if (crtc->state) 498 __drm_atomic_helper_crtc_destroy_state(crtc->state); 499 500 kfree(to_kcrtc_st(crtc->state)); 501 crtc->state = NULL; 502 503 state = kzalloc(sizeof(*state), GFP_KERNEL); 504 if (state) 505 __drm_atomic_helper_crtc_reset(crtc, &state->base); 506 } 507 508 static struct drm_crtc_state * 509 komeda_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 510 { 511 struct komeda_crtc_state *old = to_kcrtc_st(crtc->state); 512 struct komeda_crtc_state *new; 513 514 new = kzalloc(sizeof(*new), GFP_KERNEL); 515 if (!new) 516 return NULL; 517 518 __drm_atomic_helper_crtc_duplicate_state(crtc, &new->base); 519 520 new->affected_pipes = old->active_pipes; 521 new->clock_ratio = old->clock_ratio; 522 new->max_slave_zorder = old->max_slave_zorder; 523 524 return &new->base; 525 } 526 527 static void komeda_crtc_atomic_destroy_state(struct drm_crtc *crtc, 528 struct drm_crtc_state *state) 529 { 530 __drm_atomic_helper_crtc_destroy_state(state); 531 kfree(to_kcrtc_st(state)); 532 } 533 534 static int komeda_crtc_vblank_enable(struct drm_crtc *crtc) 535 { 536 struct komeda_dev *mdev = crtc->dev->dev_private; 537 struct komeda_crtc *kcrtc = to_kcrtc(crtc); 538 539 mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, true); 540 return 0; 541 } 542 543 static void komeda_crtc_vblank_disable(struct drm_crtc *crtc) 544 { 545 struct komeda_dev *mdev = crtc->dev->dev_private; 546 struct komeda_crtc *kcrtc = to_kcrtc(crtc); 547 548 mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, false); 549 } 550 551 static const struct drm_crtc_funcs komeda_crtc_funcs = { 552 .destroy = drm_crtc_cleanup, 553 .set_config = drm_atomic_helper_set_config, 554 .page_flip = drm_atomic_helper_page_flip, 555 .reset = komeda_crtc_reset, 556 .atomic_duplicate_state = komeda_crtc_atomic_duplicate_state, 557 .atomic_destroy_state = komeda_crtc_atomic_destroy_state, 558 .enable_vblank = komeda_crtc_vblank_enable, 559 .disable_vblank = komeda_crtc_vblank_disable, 560 }; 561 562 int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms, 563 struct komeda_dev *mdev) 564 { 565 struct komeda_crtc *crtc; 566 struct komeda_pipeline *master; 567 char str[16]; 568 int i; 569 570 kms->n_crtcs = 0; 571 572 for (i = 0; i < mdev->n_pipelines; i++) { 573 crtc = &kms->crtcs[kms->n_crtcs]; 574 master = mdev->pipelines[i]; 575 576 crtc->master = master; 577 crtc->slave = komeda_pipeline_get_slave(master); 578 579 if (crtc->slave) 580 sprintf(str, "pipe-%d", crtc->slave->id); 581 else 582 sprintf(str, "None"); 583 584 DRM_INFO("CRTC-%d: master(pipe-%d) slave(%s).\n", 585 kms->n_crtcs, master->id, str); 586 587 kms->n_crtcs++; 588 } 589 590 return 0; 591 } 592 593 static struct drm_plane * 594 get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc) 595 { 596 struct komeda_plane *kplane; 597 struct drm_plane *plane; 598 599 drm_for_each_plane(plane, &kms->base) { 600 if (plane->type != DRM_PLANE_TYPE_PRIMARY) 601 continue; 602 603 kplane = to_kplane(plane); 604 /* only master can be primary */ 605 if (kplane->layer->base.pipeline == crtc->master) 606 return plane; 607 } 608 609 return NULL; 610 } 611 612 static int komeda_crtc_add(struct komeda_kms_dev *kms, 613 struct komeda_crtc *kcrtc) 614 { 615 struct drm_crtc *crtc = &kcrtc->base; 616 int err; 617 618 err = drm_crtc_init_with_planes(&kms->base, crtc, 619 get_crtc_primary(kms, kcrtc), NULL, 620 &komeda_crtc_funcs, NULL); 621 if (err) 622 return err; 623 624 drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs); 625 626 crtc->port = kcrtc->master->of_output_port; 627 628 drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE); 629 630 return err; 631 } 632 633 int komeda_kms_add_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev) 634 { 635 int i, err; 636 637 for (i = 0; i < kms->n_crtcs; i++) { 638 err = komeda_crtc_add(kms, &kms->crtcs[i]); 639 if (err) 640 return err; 641 } 642 643 return 0; 644 } 645