1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __SMU_CMN_H__ 24 #define __SMU_CMN_H__ 25 26 #include "amdgpu_smu.h" 27 28 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4) 29 30 #define FDO_PWM_MODE_STATIC 1 31 #define FDO_PWM_MODE_STATIC_RPM 5 32 33 int smu_cmn_send_msg_without_waiting(struct smu_context *smu, 34 uint16_t msg_index, 35 uint32_t param); 36 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, 37 enum smu_message_type msg, 38 uint32_t param, 39 uint32_t *read_arg); 40 41 int smu_cmn_send_smc_msg(struct smu_context *smu, 42 enum smu_message_type msg, 43 uint32_t *read_arg); 44 45 int smu_cmn_wait_for_response(struct smu_context *smu); 46 47 int smu_cmn_to_asic_specific_index(struct smu_context *smu, 48 enum smu_cmn2asic_mapping_type type, 49 uint32_t index); 50 51 int smu_cmn_feature_is_supported(struct smu_context *smu, 52 enum smu_feature_mask mask); 53 54 int smu_cmn_feature_is_enabled(struct smu_context *smu, 55 enum smu_feature_mask mask); 56 57 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, 58 enum smu_clk_type clk_type); 59 60 int smu_cmn_get_enabled_mask(struct smu_context *smu, 61 uint64_t *feature_mask); 62 63 uint64_t smu_cmn_get_indep_throttler_status( 64 const unsigned long dep_status, 65 const uint8_t *throttler_map); 66 67 int smu_cmn_feature_update_enable_state(struct smu_context *smu, 68 uint64_t feature_mask, 69 bool enabled); 70 71 int smu_cmn_feature_set_enabled(struct smu_context *smu, 72 enum smu_feature_mask mask, 73 bool enable); 74 75 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, 76 char *buf); 77 78 int smu_cmn_set_pp_feature_mask(struct smu_context *smu, 79 uint64_t new_mask); 80 81 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu, 82 enum smu_feature_mask mask); 83 84 int smu_cmn_get_smc_version(struct smu_context *smu, 85 uint32_t *if_version, 86 uint32_t *smu_version); 87 88 int smu_cmn_update_table(struct smu_context *smu, 89 enum smu_table_id table_index, 90 int argument, 91 void *table_data, 92 bool drv2smu); 93 94 int smu_cmn_write_watermarks_table(struct smu_context *smu); 95 96 int smu_cmn_write_pptable(struct smu_context *smu); 97 98 int smu_cmn_get_metrics_table(struct smu_context *smu, 99 void *metrics_table, 100 bool bypass_cache); 101 102 int smu_cmn_get_combo_pptable(struct smu_context *smu); 103 104 void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev); 105 106 int smu_cmn_set_mp1_state(struct smu_context *smu, 107 enum pp_mp1_state mp1_state); 108 109 /* 110 * Helper function to make sysfs_emit_at() happy. Align buf to 111 * the current page boundary and record the offset. 112 */ 113 static inline void smu_cmn_get_sysfs_buf(char **buf, int *offset) 114 { 115 if (!*buf || !offset) 116 return; 117 118 *offset = offset_in_page(*buf); 119 *buf -= *offset; 120 } 121 122 bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev); 123 124 #endif 125 #endif 126