1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L4 24 25 #include "amdgpu.h" 26 #include "amdgpu_smu.h" 27 #include "smu_cmn.h" 28 #include "soc15_common.h" 29 30 /* 31 * DO NOT use these for err/warn/info/debug messages. 32 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 33 * They are more MGPU friendly. 34 */ 35 #undef pr_err 36 #undef pr_warn 37 #undef pr_info 38 #undef pr_debug 39 40 /* 41 * Although these are defined in each ASIC's specific header file. 42 * They share the same definitions and values. That makes common 43 * APIs for SMC messages issuing for all ASICs possible. 44 */ 45 #define mmMP1_SMN_C2PMSG_66 0x0282 46 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 47 48 #define mmMP1_SMN_C2PMSG_82 0x0292 49 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 50 51 #define mmMP1_SMN_C2PMSG_90 0x029a 52 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 53 54 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 55 56 #undef __SMU_DUMMY_MAP 57 #define __SMU_DUMMY_MAP(type) #type 58 static const char* __smu_message_names[] = { 59 SMU_MESSAGE_TYPES 60 }; 61 62 static const char *smu_get_message_name(struct smu_context *smu, 63 enum smu_message_type type) 64 { 65 if (type < 0 || type >= SMU_MSG_MAX_COUNT) 66 return "unknown smu message"; 67 68 return __smu_message_names[type]; 69 } 70 71 static void smu_cmn_send_msg_without_waiting(struct smu_context *smu, 72 uint16_t msg) 73 { 74 struct amdgpu_device *adev = smu->adev; 75 76 WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); 77 } 78 79 static void smu_cmn_read_arg(struct smu_context *smu, 80 uint32_t *arg) 81 { 82 struct amdgpu_device *adev = smu->adev; 83 84 *arg = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82); 85 } 86 87 static int smu_cmn_wait_for_response(struct smu_context *smu) 88 { 89 struct amdgpu_device *adev = smu->adev; 90 uint32_t cur_value, i, timeout = adev->usec_timeout * 10; 91 92 for (i = 0; i < timeout; i++) { 93 cur_value = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90); 94 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0) 95 return cur_value == 0x1 ? 0 : -EIO; 96 97 udelay(1); 98 } 99 100 /* timeout means wrong logic */ 101 if (i == timeout) 102 return -ETIME; 103 104 return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO; 105 } 106 107 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, 108 enum smu_message_type msg, 109 uint32_t param, 110 uint32_t *read_arg) 111 { 112 struct amdgpu_device *adev = smu->adev; 113 int ret = 0, index = 0; 114 115 if (smu->adev->in_pci_err_recovery) 116 return 0; 117 118 index = smu_cmn_to_asic_specific_index(smu, 119 CMN2ASIC_MAPPING_MSG, 120 msg); 121 if (index < 0) 122 return index == -EACCES ? 0 : index; 123 124 mutex_lock(&smu->message_lock); 125 ret = smu_cmn_wait_for_response(smu); 126 if (ret) { 127 dev_err(adev->dev, "Msg issuing pre-check failed and " 128 "SMU may be not in the right state!\n"); 129 goto out; 130 } 131 132 WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 133 134 WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param); 135 136 smu_cmn_send_msg_without_waiting(smu, (uint16_t)index); 137 138 ret = smu_cmn_wait_for_response(smu); 139 if (ret) { 140 dev_err(adev->dev, "failed send message: %10s (%d) \tparam: 0x%08x response %#x\n", 141 smu_get_message_name(smu, msg), index, param, ret); 142 goto out; 143 } 144 145 if (read_arg) 146 smu_cmn_read_arg(smu, read_arg); 147 148 out: 149 mutex_unlock(&smu->message_lock); 150 return ret; 151 } 152 153 int smu_cmn_send_smc_msg(struct smu_context *smu, 154 enum smu_message_type msg, 155 uint32_t *read_arg) 156 { 157 return smu_cmn_send_smc_msg_with_param(smu, 158 msg, 159 0, 160 read_arg); 161 } 162 163 int smu_cmn_to_asic_specific_index(struct smu_context *smu, 164 enum smu_cmn2asic_mapping_type type, 165 uint32_t index) 166 { 167 struct cmn2asic_msg_mapping msg_mapping; 168 struct cmn2asic_mapping mapping; 169 170 switch (type) { 171 case CMN2ASIC_MAPPING_MSG: 172 if (index >= SMU_MSG_MAX_COUNT || 173 !smu->message_map) 174 return -EINVAL; 175 176 msg_mapping = smu->message_map[index]; 177 if (!msg_mapping.valid_mapping) 178 return -EINVAL; 179 180 if (amdgpu_sriov_vf(smu->adev) && 181 !msg_mapping.valid_in_vf) 182 return -EACCES; 183 184 return msg_mapping.map_to; 185 186 case CMN2ASIC_MAPPING_CLK: 187 if (index >= SMU_CLK_COUNT || 188 !smu->clock_map) 189 return -EINVAL; 190 191 mapping = smu->clock_map[index]; 192 if (!mapping.valid_mapping) 193 return -EINVAL; 194 195 return mapping.map_to; 196 197 case CMN2ASIC_MAPPING_FEATURE: 198 if (index >= SMU_FEATURE_COUNT || 199 !smu->feature_map) 200 return -EINVAL; 201 202 mapping = smu->feature_map[index]; 203 if (!mapping.valid_mapping) 204 return -EINVAL; 205 206 return mapping.map_to; 207 208 case CMN2ASIC_MAPPING_TABLE: 209 if (index >= SMU_TABLE_COUNT || 210 !smu->table_map) 211 return -EINVAL; 212 213 mapping = smu->table_map[index]; 214 if (!mapping.valid_mapping) 215 return -EINVAL; 216 217 return mapping.map_to; 218 219 case CMN2ASIC_MAPPING_PWR: 220 if (index >= SMU_POWER_SOURCE_COUNT || 221 !smu->pwr_src_map) 222 return -EINVAL; 223 224 mapping = smu->pwr_src_map[index]; 225 if (!mapping.valid_mapping) 226 return -EINVAL; 227 228 return mapping.map_to; 229 230 case CMN2ASIC_MAPPING_WORKLOAD: 231 if (index > PP_SMC_POWER_PROFILE_CUSTOM || 232 !smu->workload_map) 233 return -EINVAL; 234 235 mapping = smu->workload_map[index]; 236 if (!mapping.valid_mapping) 237 return -EINVAL; 238 239 return mapping.map_to; 240 241 default: 242 return -EINVAL; 243 } 244 } 245 246 int smu_cmn_feature_is_supported(struct smu_context *smu, 247 enum smu_feature_mask mask) 248 { 249 struct smu_feature *feature = &smu->smu_feature; 250 int feature_id; 251 int ret = 0; 252 253 feature_id = smu_cmn_to_asic_specific_index(smu, 254 CMN2ASIC_MAPPING_FEATURE, 255 mask); 256 if (feature_id < 0) 257 return 0; 258 259 WARN_ON(feature_id > feature->feature_num); 260 261 mutex_lock(&feature->mutex); 262 ret = test_bit(feature_id, feature->supported); 263 mutex_unlock(&feature->mutex); 264 265 return ret; 266 } 267 268 int smu_cmn_feature_is_enabled(struct smu_context *smu, 269 enum smu_feature_mask mask) 270 { 271 struct smu_feature *feature = &smu->smu_feature; 272 int feature_id; 273 int ret = 0; 274 275 if (smu->is_apu) 276 return 1; 277 feature_id = smu_cmn_to_asic_specific_index(smu, 278 CMN2ASIC_MAPPING_FEATURE, 279 mask); 280 if (feature_id < 0) 281 return 0; 282 283 WARN_ON(feature_id > feature->feature_num); 284 285 mutex_lock(&feature->mutex); 286 ret = test_bit(feature_id, feature->enabled); 287 mutex_unlock(&feature->mutex); 288 289 return ret; 290 } 291 292 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, 293 enum smu_clk_type clk_type) 294 { 295 enum smu_feature_mask feature_id = 0; 296 297 switch (clk_type) { 298 case SMU_MCLK: 299 case SMU_UCLK: 300 feature_id = SMU_FEATURE_DPM_UCLK_BIT; 301 break; 302 case SMU_GFXCLK: 303 case SMU_SCLK: 304 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 305 break; 306 case SMU_SOCCLK: 307 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 308 break; 309 default: 310 return true; 311 } 312 313 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 314 return false; 315 316 return true; 317 } 318 319 int smu_cmn_get_enabled_mask(struct smu_context *smu, 320 uint32_t *feature_mask, 321 uint32_t num) 322 { 323 uint32_t feature_mask_high = 0, feature_mask_low = 0; 324 struct smu_feature *feature = &smu->smu_feature; 325 int ret = 0; 326 327 if (!feature_mask || num < 2) 328 return -EINVAL; 329 330 if (bitmap_empty(feature->enabled, feature->feature_num)) { 331 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &feature_mask_high); 332 if (ret) 333 return ret; 334 335 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow, &feature_mask_low); 336 if (ret) 337 return ret; 338 339 feature_mask[0] = feature_mask_low; 340 feature_mask[1] = feature_mask_high; 341 } else { 342 bitmap_copy((unsigned long *)feature_mask, feature->enabled, 343 feature->feature_num); 344 } 345 346 return ret; 347 } 348 349 static int smu_cmn_feature_update_enable_state(struct smu_context *smu, 350 uint64_t feature_mask, 351 bool enabled) 352 { 353 struct smu_feature *feature = &smu->smu_feature; 354 int ret = 0; 355 356 if (enabled) { 357 ret = smu_cmn_send_smc_msg_with_param(smu, 358 SMU_MSG_EnableSmuFeaturesLow, 359 lower_32_bits(feature_mask), 360 NULL); 361 if (ret) 362 return ret; 363 ret = smu_cmn_send_smc_msg_with_param(smu, 364 SMU_MSG_EnableSmuFeaturesHigh, 365 upper_32_bits(feature_mask), 366 NULL); 367 if (ret) 368 return ret; 369 } else { 370 ret = smu_cmn_send_smc_msg_with_param(smu, 371 SMU_MSG_DisableSmuFeaturesLow, 372 lower_32_bits(feature_mask), 373 NULL); 374 if (ret) 375 return ret; 376 ret = smu_cmn_send_smc_msg_with_param(smu, 377 SMU_MSG_DisableSmuFeaturesHigh, 378 upper_32_bits(feature_mask), 379 NULL); 380 if (ret) 381 return ret; 382 } 383 384 mutex_lock(&feature->mutex); 385 if (enabled) 386 bitmap_or(feature->enabled, feature->enabled, 387 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX); 388 else 389 bitmap_andnot(feature->enabled, feature->enabled, 390 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX); 391 mutex_unlock(&feature->mutex); 392 393 return ret; 394 } 395 396 int smu_cmn_feature_set_enabled(struct smu_context *smu, 397 enum smu_feature_mask mask, 398 bool enable) 399 { 400 struct smu_feature *feature = &smu->smu_feature; 401 int feature_id; 402 403 feature_id = smu_cmn_to_asic_specific_index(smu, 404 CMN2ASIC_MAPPING_FEATURE, 405 mask); 406 if (feature_id < 0) 407 return -EINVAL; 408 409 WARN_ON(feature_id > feature->feature_num); 410 411 return smu_cmn_feature_update_enable_state(smu, 412 1ULL << feature_id, 413 enable); 414 } 415 416 #undef __SMU_DUMMY_MAP 417 #define __SMU_DUMMY_MAP(fea) #fea 418 static const char* __smu_feature_names[] = { 419 SMU_FEATURE_MASKS 420 }; 421 422 static const char *smu_get_feature_name(struct smu_context *smu, 423 enum smu_feature_mask feature) 424 { 425 if (feature < 0 || feature >= SMU_FEATURE_COUNT) 426 return "unknown smu feature"; 427 return __smu_feature_names[feature]; 428 } 429 430 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, 431 char *buf) 432 { 433 uint32_t feature_mask[2] = { 0 }; 434 int32_t feature_index = 0; 435 uint32_t count = 0; 436 uint32_t sort_feature[SMU_FEATURE_COUNT]; 437 uint64_t hw_feature_count = 0; 438 size_t size = 0; 439 int ret = 0, i; 440 441 ret = smu_cmn_get_enabled_mask(smu, 442 feature_mask, 443 2); 444 if (ret) 445 return 0; 446 447 size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n", 448 feature_mask[1], feature_mask[0]); 449 450 for (i = 0; i < SMU_FEATURE_COUNT; i++) { 451 feature_index = smu_cmn_to_asic_specific_index(smu, 452 CMN2ASIC_MAPPING_FEATURE, 453 i); 454 if (feature_index < 0) 455 continue; 456 sort_feature[feature_index] = i; 457 hw_feature_count++; 458 } 459 460 for (i = 0; i < hw_feature_count; i++) { 461 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n", 462 count++, 463 smu_get_feature_name(smu, sort_feature[i]), 464 i, 465 !!smu_cmn_feature_is_enabled(smu, sort_feature[i]) ? 466 "enabled" : "disabled"); 467 } 468 469 return size; 470 } 471 472 int smu_cmn_set_pp_feature_mask(struct smu_context *smu, 473 uint64_t new_mask) 474 { 475 int ret = 0; 476 uint32_t feature_mask[2] = { 0 }; 477 uint64_t feature_2_enabled = 0; 478 uint64_t feature_2_disabled = 0; 479 uint64_t feature_enables = 0; 480 481 ret = smu_cmn_get_enabled_mask(smu, 482 feature_mask, 483 2); 484 if (ret) 485 return ret; 486 487 feature_enables = ((uint64_t)feature_mask[1] << 32 | 488 (uint64_t)feature_mask[0]); 489 490 feature_2_enabled = ~feature_enables & new_mask; 491 feature_2_disabled = feature_enables & ~new_mask; 492 493 if (feature_2_enabled) { 494 ret = smu_cmn_feature_update_enable_state(smu, 495 feature_2_enabled, 496 true); 497 if (ret) 498 return ret; 499 } 500 if (feature_2_disabled) { 501 ret = smu_cmn_feature_update_enable_state(smu, 502 feature_2_disabled, 503 false); 504 if (ret) 505 return ret; 506 } 507 508 return ret; 509 } 510 511 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu, 512 enum smu_feature_mask mask) 513 { 514 uint64_t features_to_disable = U64_MAX; 515 int skipped_feature_id; 516 517 skipped_feature_id = smu_cmn_to_asic_specific_index(smu, 518 CMN2ASIC_MAPPING_FEATURE, 519 mask); 520 if (skipped_feature_id < 0) 521 return -EINVAL; 522 523 features_to_disable &= ~(1ULL << skipped_feature_id); 524 525 return smu_cmn_feature_update_enable_state(smu, 526 features_to_disable, 527 0); 528 } 529 530 int smu_cmn_get_smc_version(struct smu_context *smu, 531 uint32_t *if_version, 532 uint32_t *smu_version) 533 { 534 int ret = 0; 535 536 if (!if_version && !smu_version) 537 return -EINVAL; 538 539 if (smu->smc_fw_if_version && smu->smc_fw_version) 540 { 541 if (if_version) 542 *if_version = smu->smc_fw_if_version; 543 544 if (smu_version) 545 *smu_version = smu->smc_fw_version; 546 547 return 0; 548 } 549 550 if (if_version) { 551 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version); 552 if (ret) 553 return ret; 554 555 smu->smc_fw_if_version = *if_version; 556 } 557 558 if (smu_version) { 559 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version); 560 if (ret) 561 return ret; 562 563 smu->smc_fw_version = *smu_version; 564 } 565 566 return ret; 567 } 568 569 int smu_cmn_update_table(struct smu_context *smu, 570 enum smu_table_id table_index, 571 int argument, 572 void *table_data, 573 bool drv2smu) 574 { 575 struct smu_table_context *smu_table = &smu->smu_table; 576 struct amdgpu_device *adev = smu->adev; 577 struct smu_table *table = &smu_table->driver_table; 578 int table_id = smu_cmn_to_asic_specific_index(smu, 579 CMN2ASIC_MAPPING_TABLE, 580 table_index); 581 uint32_t table_size; 582 int ret = 0; 583 if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0) 584 return -EINVAL; 585 586 table_size = smu_table->tables[table_index].size; 587 588 if (drv2smu) { 589 memcpy(table->cpu_addr, table_data, table_size); 590 /* 591 * Flush hdp cache: to guard the content seen by 592 * GPU is consitent with CPU. 593 */ 594 amdgpu_asic_flush_hdp(adev, NULL); 595 } 596 597 ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ? 598 SMU_MSG_TransferTableDram2Smu : 599 SMU_MSG_TransferTableSmu2Dram, 600 table_id | ((argument & 0xFFFF) << 16), 601 NULL); 602 if (ret) 603 return ret; 604 605 if (!drv2smu) { 606 amdgpu_asic_flush_hdp(adev, NULL); 607 memcpy(table_data, table->cpu_addr, table_size); 608 } 609 610 return 0; 611 } 612 613 int smu_cmn_write_watermarks_table(struct smu_context *smu) 614 { 615 void *watermarks_table = smu->smu_table.watermarks_table; 616 617 if (!watermarks_table) 618 return -EINVAL; 619 620 return smu_cmn_update_table(smu, 621 SMU_TABLE_WATERMARKS, 622 0, 623 watermarks_table, 624 true); 625 } 626 627 int smu_cmn_write_pptable(struct smu_context *smu) 628 { 629 void *pptable = smu->smu_table.driver_pptable; 630 631 return smu_cmn_update_table(smu, 632 SMU_TABLE_PPTABLE, 633 0, 634 pptable, 635 true); 636 } 637 638 int smu_cmn_get_metrics_table_locked(struct smu_context *smu, 639 void *metrics_table, 640 bool bypass_cache) 641 { 642 struct smu_table_context *smu_table= &smu->smu_table; 643 uint32_t table_size = 644 smu_table->tables[SMU_TABLE_SMU_METRICS].size; 645 int ret = 0; 646 647 if (bypass_cache || 648 !smu_table->metrics_time || 649 time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) { 650 ret = smu_cmn_update_table(smu, 651 SMU_TABLE_SMU_METRICS, 652 0, 653 smu_table->metrics_table, 654 false); 655 if (ret) { 656 dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n"); 657 return ret; 658 } 659 smu_table->metrics_time = jiffies; 660 } 661 662 if (metrics_table) 663 memcpy(metrics_table, smu_table->metrics_table, table_size); 664 665 return 0; 666 } 667 668 int smu_cmn_get_metrics_table(struct smu_context *smu, 669 void *metrics_table, 670 bool bypass_cache) 671 { 672 int ret = 0; 673 674 mutex_lock(&smu->metrics_lock); 675 ret = smu_cmn_get_metrics_table_locked(smu, 676 metrics_table, 677 bypass_cache); 678 mutex_unlock(&smu->metrics_lock); 679 680 return ret; 681 } 682