1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v13_0.h" 29 #include "smu13_driver_if_yellow_carp.h" 30 #include "yellow_carp_ppt.h" 31 #include "smu_v13_0_1_ppsmc.h" 32 #include "smu_v13_0_1_pmfw.h" 33 #include "smu_cmn.h" 34 35 /* 36 * DO NOT use these for err/warn/info/debug messages. 37 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 38 * They are more MGPU friendly. 39 */ 40 #undef pr_err 41 #undef pr_warn 42 #undef pr_info 43 #undef pr_debug 44 45 #define FEATURE_MASK(feature) (1ULL << feature) 46 #define SMC_DPM_FEATURE ( \ 47 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 48 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 49 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 50 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 51 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 52 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 53 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 54 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 55 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 56 57 static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = { 58 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 59 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 60 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 61 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1), 62 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1), 63 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1), 64 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 65 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 66 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 67 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 68 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 69 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 70 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 71 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 72 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 73 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), 74 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 75 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 76 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 77 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 78 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 79 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 80 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 81 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 82 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 83 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 84 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 85 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 86 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 87 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1), 88 }; 89 90 static struct cmn2asic_mapping yellow_carp_feature_mask_map[SMU_FEATURE_COUNT] = { 91 FEA_MAP(CCLK_DPM), 92 FEA_MAP(FAN_CONTROLLER), 93 FEA_MAP(PPT), 94 FEA_MAP(TDC), 95 FEA_MAP(THERMAL), 96 FEA_MAP(ULV), 97 FEA_MAP(VCN_DPM), 98 FEA_MAP_REVERSE(FCLK), 99 FEA_MAP_REVERSE(SOCCLK), 100 FEA_MAP(LCLK_DPM), 101 FEA_MAP(SHUBCLK_DPM), 102 FEA_MAP(DCFCLK_DPM), 103 FEA_MAP_HALF_REVERSE(GFX), 104 FEA_MAP(DS_GFXCLK), 105 FEA_MAP(DS_SOCCLK), 106 FEA_MAP(DS_LCLK), 107 FEA_MAP(DS_DCFCLK), 108 FEA_MAP(DS_FCLK), 109 FEA_MAP(DS_MP1CLK), 110 FEA_MAP(DS_MP0CLK), 111 FEA_MAP(GFX_DEM), 112 FEA_MAP(PSI), 113 FEA_MAP(PROCHOT), 114 FEA_MAP(CPUOFF), 115 FEA_MAP(STAPM), 116 FEA_MAP(S0I3), 117 FEA_MAP(PERF_LIMIT), 118 FEA_MAP(CORE_DLDO), 119 FEA_MAP(RSMU_LOW_POWER), 120 FEA_MAP(SMN_LOW_POWER), 121 FEA_MAP(THM_LOW_POWER), 122 FEA_MAP(SMUIO_LOW_POWER), 123 FEA_MAP(MP1_LOW_POWER), 124 FEA_MAP(DS_VCN), 125 FEA_MAP(CPPC), 126 FEA_MAP(DF_CSTATES), 127 FEA_MAP(MSMU_LOW_POWER), 128 FEA_MAP(ATHUB_PG), 129 }; 130 131 static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = { 132 TAB_MAP_VALID(WATERMARKS), 133 TAB_MAP_VALID(SMU_METRICS), 134 TAB_MAP_VALID(CUSTOM_DPM), 135 TAB_MAP_VALID(DPMCLOCKS), 136 }; 137 138 static int yellow_carp_init_smc_tables(struct smu_context *smu) 139 { 140 struct smu_table_context *smu_table = &smu->smu_table; 141 struct smu_table *tables = smu_table->tables; 142 143 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 144 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 145 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 146 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 147 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 148 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 149 150 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 151 if (!smu_table->clocks_table) 152 goto err0_out; 153 154 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 155 if (!smu_table->metrics_table) 156 goto err1_out; 157 smu_table->metrics_time = 0; 158 159 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 160 if (!smu_table->watermarks_table) 161 goto err2_out; 162 163 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); 164 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 165 if (!smu_table->gpu_metrics_table) 166 goto err3_out; 167 168 return 0; 169 170 err3_out: 171 kfree(smu_table->watermarks_table); 172 err2_out: 173 kfree(smu_table->metrics_table); 174 err1_out: 175 kfree(smu_table->clocks_table); 176 err0_out: 177 return -ENOMEM; 178 } 179 180 static int yellow_carp_fini_smc_tables(struct smu_context *smu) 181 { 182 struct smu_table_context *smu_table = &smu->smu_table; 183 184 kfree(smu_table->clocks_table); 185 smu_table->clocks_table = NULL; 186 187 kfree(smu_table->metrics_table); 188 smu_table->metrics_table = NULL; 189 190 kfree(smu_table->watermarks_table); 191 smu_table->watermarks_table = NULL; 192 193 return 0; 194 } 195 196 static int yellow_carp_system_features_control(struct smu_context *smu, bool en) 197 { 198 struct smu_feature *feature = &smu->smu_feature; 199 struct amdgpu_device *adev = smu->adev; 200 uint32_t feature_mask[2]; 201 int ret = 0; 202 203 if (!en && !adev->in_s0ix) 204 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); 205 206 bitmap_zero(feature->enabled, feature->feature_num); 207 bitmap_zero(feature->supported, feature->feature_num); 208 209 if (!en) 210 return ret; 211 212 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 213 if (ret) 214 return ret; 215 216 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, 217 feature->feature_num); 218 bitmap_copy(feature->supported, (unsigned long *)&feature_mask, 219 feature->feature_num); 220 221 return 0; 222 } 223 224 static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 225 { 226 int ret = 0; 227 228 /* vcn dpm on is a prerequisite for vcn power gate messages */ 229 if (enable) 230 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 231 0, NULL); 232 else 233 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 234 0, NULL); 235 236 return ret; 237 } 238 239 static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 240 { 241 int ret = 0; 242 243 if (enable) 244 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 245 0, NULL); 246 else 247 ret = smu_cmn_send_smc_msg_with_param(smu, 248 SMU_MSG_PowerDownJpeg, 0, 249 NULL); 250 251 return ret; 252 } 253 254 255 static bool yellow_carp_is_dpm_running(struct smu_context *smu) 256 { 257 int ret = 0; 258 uint32_t feature_mask[2]; 259 uint64_t feature_enabled; 260 261 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 262 263 if (ret) 264 return false; 265 266 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; 267 268 return !!(feature_enabled & SMC_DPM_FEATURE); 269 } 270 271 static int yellow_carp_post_smu_init(struct smu_context *smu) 272 { 273 struct amdgpu_device *adev = smu->adev; 274 int ret = 0; 275 276 /* allow message will be sent after enable message on Yellow Carp*/ 277 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 278 if (ret) 279 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 280 return ret; 281 } 282 283 static int yellow_carp_mode_reset(struct smu_context *smu, int type) 284 { 285 int ret = 0, index = 0; 286 287 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 288 SMU_MSG_GfxDeviceDriverReset); 289 if (index < 0) 290 return index == -EACCES ? 0 : index; 291 292 ret = smu_cmn_send_smc_msg_with_param(smu, (uint16_t)index, type, NULL); 293 if (ret) 294 dev_err(smu->adev->dev, "Failed to mode reset!\n"); 295 296 return ret; 297 } 298 299 static int yellow_carp_mode2_reset(struct smu_context *smu) 300 { 301 return yellow_carp_mode_reset(smu, SMU_RESET_MODE_2); 302 } 303 304 static int yellow_carp_get_smu_metrics_data(struct smu_context *smu, 305 MetricsMember_t member, 306 uint32_t *value) 307 { 308 struct smu_table_context *smu_table = &smu->smu_table; 309 310 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 311 int ret = 0; 312 313 mutex_lock(&smu->metrics_lock); 314 315 ret = smu_cmn_get_metrics_table_locked(smu, NULL, false); 316 if (ret) { 317 mutex_unlock(&smu->metrics_lock); 318 return ret; 319 } 320 321 switch (member) { 322 case METRICS_AVERAGE_GFXCLK: 323 *value = metrics->GfxclkFrequency; 324 break; 325 case METRICS_AVERAGE_SOCCLK: 326 *value = metrics->SocclkFrequency; 327 break; 328 case METRICS_AVERAGE_VCLK: 329 *value = metrics->VclkFrequency; 330 break; 331 case METRICS_AVERAGE_DCLK: 332 *value = metrics->DclkFrequency; 333 break; 334 case METRICS_AVERAGE_UCLK: 335 *value = metrics->MemclkFrequency; 336 break; 337 case METRICS_AVERAGE_GFXACTIVITY: 338 *value = metrics->GfxActivity / 100; 339 break; 340 case METRICS_AVERAGE_VCNACTIVITY: 341 *value = metrics->UvdActivity; 342 break; 343 case METRICS_AVERAGE_SOCKETPOWER: 344 *value = (metrics->CurrentSocketPower << 8) / 1000; 345 break; 346 case METRICS_TEMPERATURE_EDGE: 347 *value = metrics->GfxTemperature / 100 * 348 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 349 break; 350 case METRICS_TEMPERATURE_HOTSPOT: 351 *value = metrics->SocTemperature / 100 * 352 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 353 break; 354 case METRICS_THROTTLER_STATUS: 355 *value = metrics->ThrottlerStatus; 356 break; 357 case METRICS_VOLTAGE_VDDGFX: 358 *value = metrics->Voltage[0]; 359 break; 360 case METRICS_VOLTAGE_VDDSOC: 361 *value = metrics->Voltage[1]; 362 break; 363 case METRICS_SS_APU_SHARE: 364 /* return the percentage of APU power with respect to APU's power limit. 365 * percentage is reported, this isn't boost value. Smartshift power 366 * boost/shift is only when the percentage is more than 100. 367 */ 368 if (metrics->StapmOpnLimit > 0) 369 *value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit; 370 else 371 *value = 0; 372 break; 373 case METRICS_SS_DGPU_SHARE: 374 /* return the percentage of dGPU power with respect to dGPU's power limit. 375 * percentage is reported, this isn't boost value. Smartshift power 376 * boost/shift is only when the percentage is more than 100. 377 */ 378 if ((metrics->dGpuPower > 0) && 379 (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)) 380 *value = (metrics->dGpuPower * 100) / 381 (metrics->StapmCurrentLimit - metrics->StapmOpnLimit); 382 else 383 *value = 0; 384 break; 385 default: 386 *value = UINT_MAX; 387 break; 388 } 389 390 mutex_unlock(&smu->metrics_lock); 391 392 return ret; 393 } 394 395 static int yellow_carp_read_sensor(struct smu_context *smu, 396 enum amd_pp_sensors sensor, 397 void *data, uint32_t *size) 398 { 399 int ret = 0; 400 401 if (!data || !size) 402 return -EINVAL; 403 404 mutex_lock(&smu->sensor_lock); 405 switch (sensor) { 406 case AMDGPU_PP_SENSOR_GPU_LOAD: 407 ret = yellow_carp_get_smu_metrics_data(smu, 408 METRICS_AVERAGE_GFXACTIVITY, 409 (uint32_t *)data); 410 *size = 4; 411 break; 412 case AMDGPU_PP_SENSOR_GPU_POWER: 413 ret = yellow_carp_get_smu_metrics_data(smu, 414 METRICS_AVERAGE_SOCKETPOWER, 415 (uint32_t *)data); 416 *size = 4; 417 break; 418 case AMDGPU_PP_SENSOR_EDGE_TEMP: 419 ret = yellow_carp_get_smu_metrics_data(smu, 420 METRICS_TEMPERATURE_EDGE, 421 (uint32_t *)data); 422 *size = 4; 423 break; 424 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 425 ret = yellow_carp_get_smu_metrics_data(smu, 426 METRICS_TEMPERATURE_HOTSPOT, 427 (uint32_t *)data); 428 *size = 4; 429 break; 430 case AMDGPU_PP_SENSOR_GFX_MCLK: 431 ret = yellow_carp_get_smu_metrics_data(smu, 432 METRICS_AVERAGE_UCLK, 433 (uint32_t *)data); 434 *(uint32_t *)data *= 100; 435 *size = 4; 436 break; 437 case AMDGPU_PP_SENSOR_GFX_SCLK: 438 ret = yellow_carp_get_smu_metrics_data(smu, 439 METRICS_AVERAGE_GFXCLK, 440 (uint32_t *)data); 441 *(uint32_t *)data *= 100; 442 *size = 4; 443 break; 444 case AMDGPU_PP_SENSOR_VDDGFX: 445 ret = yellow_carp_get_smu_metrics_data(smu, 446 METRICS_VOLTAGE_VDDGFX, 447 (uint32_t *)data); 448 *size = 4; 449 break; 450 case AMDGPU_PP_SENSOR_VDDNB: 451 ret = yellow_carp_get_smu_metrics_data(smu, 452 METRICS_VOLTAGE_VDDSOC, 453 (uint32_t *)data); 454 *size = 4; 455 break; 456 case AMDGPU_PP_SENSOR_SS_APU_SHARE: 457 ret = yellow_carp_get_smu_metrics_data(smu, 458 METRICS_SS_APU_SHARE, 459 (uint32_t *)data); 460 *size = 4; 461 break; 462 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 463 ret = yellow_carp_get_smu_metrics_data(smu, 464 METRICS_SS_DGPU_SHARE, 465 (uint32_t *)data); 466 *size = 4; 467 break; 468 default: 469 ret = -EOPNOTSUPP; 470 break; 471 } 472 mutex_unlock(&smu->sensor_lock); 473 474 return ret; 475 } 476 477 static int yellow_carp_set_watermarks_table(struct smu_context *smu, 478 struct pp_smu_wm_range_sets *clock_ranges) 479 { 480 int i; 481 int ret = 0; 482 Watermarks_t *table = smu->smu_table.watermarks_table; 483 484 if (!table || !clock_ranges) 485 return -EINVAL; 486 487 if (clock_ranges) { 488 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 489 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 490 return -EINVAL; 491 492 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 493 table->WatermarkRow[WM_DCFCLK][i].MinClock = 494 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 495 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 496 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 497 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 498 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 499 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 500 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 501 502 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 503 clock_ranges->reader_wm_sets[i].wm_inst; 504 } 505 506 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 507 table->WatermarkRow[WM_SOCCLK][i].MinClock = 508 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 509 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 510 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 511 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 512 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 513 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 514 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 515 516 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 517 clock_ranges->writer_wm_sets[i].wm_inst; 518 } 519 520 smu->watermarks_bitmap |= WATERMARKS_EXIST; 521 } 522 523 /* pass data to smu controller */ 524 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 525 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 526 ret = smu_cmn_write_watermarks_table(smu); 527 if (ret) { 528 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 529 return ret; 530 } 531 smu->watermarks_bitmap |= WATERMARKS_LOADED; 532 } 533 534 return 0; 535 } 536 537 static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu, 538 void **table) 539 { 540 struct smu_table_context *smu_table = &smu->smu_table; 541 struct gpu_metrics_v2_1 *gpu_metrics = 542 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; 543 SmuMetrics_t metrics; 544 int ret = 0; 545 546 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 547 if (ret) 548 return ret; 549 550 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); 551 552 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 553 gpu_metrics->temperature_soc = metrics.SocTemperature; 554 memcpy(&gpu_metrics->temperature_core[0], 555 &metrics.CoreTemperature[0], 556 sizeof(uint16_t) * 8); 557 gpu_metrics->temperature_l3[0] = metrics.L3Temperature; 558 559 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 560 gpu_metrics->average_mm_activity = metrics.UvdActivity; 561 562 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 563 gpu_metrics->average_gfx_power = metrics.Power[0]; 564 gpu_metrics->average_soc_power = metrics.Power[1]; 565 memcpy(&gpu_metrics->average_core_power[0], 566 &metrics.CorePower[0], 567 sizeof(uint16_t) * 8); 568 569 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 570 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 571 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 572 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 573 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 574 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 575 576 memcpy(&gpu_metrics->current_coreclk[0], 577 &metrics.CoreFrequency[0], 578 sizeof(uint16_t) * 8); 579 gpu_metrics->current_l3clk[0] = metrics.L3Frequency; 580 581 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 582 583 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 584 585 *table = (void *)gpu_metrics; 586 587 return sizeof(struct gpu_metrics_v2_1); 588 } 589 590 static int yellow_carp_set_default_dpm_tables(struct smu_context *smu) 591 { 592 struct smu_table_context *smu_table = &smu->smu_table; 593 594 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 595 } 596 597 static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 598 long input[], uint32_t size) 599 { 600 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 601 int ret = 0; 602 603 /* Only allowed in manual mode */ 604 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 605 return -EINVAL; 606 607 switch (type) { 608 case PP_OD_EDIT_SCLK_VDDC_TABLE: 609 if (size != 2) { 610 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 611 return -EINVAL; 612 } 613 614 if (input[0] == 0) { 615 if (input[1] < smu->gfx_default_hard_min_freq) { 616 dev_warn(smu->adev->dev, 617 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 618 input[1], smu->gfx_default_hard_min_freq); 619 return -EINVAL; 620 } 621 smu->gfx_actual_hard_min_freq = input[1]; 622 } else if (input[0] == 1) { 623 if (input[1] > smu->gfx_default_soft_max_freq) { 624 dev_warn(smu->adev->dev, 625 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 626 input[1], smu->gfx_default_soft_max_freq); 627 return -EINVAL; 628 } 629 smu->gfx_actual_soft_max_freq = input[1]; 630 } else { 631 return -EINVAL; 632 } 633 break; 634 case PP_OD_RESTORE_DEFAULT_TABLE: 635 if (size != 0) { 636 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 637 return -EINVAL; 638 } else { 639 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 640 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 641 } 642 break; 643 case PP_OD_COMMIT_DPM_TABLE: 644 if (size != 0) { 645 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 646 return -EINVAL; 647 } else { 648 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 649 dev_err(smu->adev->dev, 650 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 651 smu->gfx_actual_hard_min_freq, 652 smu->gfx_actual_soft_max_freq); 653 return -EINVAL; 654 } 655 656 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 657 smu->gfx_actual_hard_min_freq, NULL); 658 if (ret) { 659 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 660 return ret; 661 } 662 663 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 664 smu->gfx_actual_soft_max_freq, NULL); 665 if (ret) { 666 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 667 return ret; 668 } 669 } 670 break; 671 default: 672 return -ENOSYS; 673 } 674 675 return ret; 676 } 677 678 static int yellow_carp_get_current_clk_freq(struct smu_context *smu, 679 enum smu_clk_type clk_type, 680 uint32_t *value) 681 { 682 MetricsMember_t member_type; 683 684 switch (clk_type) { 685 case SMU_SOCCLK: 686 member_type = METRICS_AVERAGE_SOCCLK; 687 break; 688 case SMU_VCLK: 689 member_type = METRICS_AVERAGE_VCLK; 690 break; 691 case SMU_DCLK: 692 member_type = METRICS_AVERAGE_DCLK; 693 break; 694 case SMU_MCLK: 695 member_type = METRICS_AVERAGE_UCLK; 696 break; 697 case SMU_FCLK: 698 return smu_cmn_send_smc_msg_with_param(smu, 699 SMU_MSG_GetFclkFrequency, 0, value); 700 default: 701 return -EINVAL; 702 } 703 704 return yellow_carp_get_smu_metrics_data(smu, member_type, value); 705 } 706 707 static int yellow_carp_get_dpm_level_count(struct smu_context *smu, 708 enum smu_clk_type clk_type, 709 uint32_t *count) 710 { 711 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 712 713 switch (clk_type) { 714 case SMU_SOCCLK: 715 *count = clk_table->NumSocClkLevelsEnabled; 716 break; 717 case SMU_VCLK: 718 *count = clk_table->VcnClkLevelsEnabled; 719 break; 720 case SMU_DCLK: 721 *count = clk_table->VcnClkLevelsEnabled; 722 break; 723 case SMU_MCLK: 724 *count = clk_table->NumDfPstatesEnabled; 725 break; 726 case SMU_FCLK: 727 *count = clk_table->NumDfPstatesEnabled; 728 break; 729 default: 730 break; 731 } 732 733 return 0; 734 } 735 736 static int yellow_carp_get_dpm_freq_by_index(struct smu_context *smu, 737 enum smu_clk_type clk_type, 738 uint32_t dpm_level, 739 uint32_t *freq) 740 { 741 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 742 743 if (!clk_table || clk_type >= SMU_CLK_COUNT) 744 return -EINVAL; 745 746 switch (clk_type) { 747 case SMU_SOCCLK: 748 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 749 return -EINVAL; 750 *freq = clk_table->SocClocks[dpm_level]; 751 break; 752 case SMU_VCLK: 753 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 754 return -EINVAL; 755 *freq = clk_table->VClocks[dpm_level]; 756 break; 757 case SMU_DCLK: 758 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 759 return -EINVAL; 760 *freq = clk_table->DClocks[dpm_level]; 761 break; 762 case SMU_UCLK: 763 case SMU_MCLK: 764 if (dpm_level >= clk_table->NumDfPstatesEnabled) 765 return -EINVAL; 766 *freq = clk_table->DfPstateTable[dpm_level].MemClk; 767 break; 768 case SMU_FCLK: 769 if (dpm_level >= clk_table->NumDfPstatesEnabled) 770 return -EINVAL; 771 *freq = clk_table->DfPstateTable[dpm_level].FClk; 772 break; 773 default: 774 return -EINVAL; 775 } 776 777 return 0; 778 } 779 780 static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu, 781 enum smu_clk_type clk_type) 782 { 783 enum smu_feature_mask feature_id = 0; 784 785 switch (clk_type) { 786 case SMU_MCLK: 787 case SMU_UCLK: 788 case SMU_FCLK: 789 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 790 break; 791 case SMU_GFXCLK: 792 case SMU_SCLK: 793 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 794 break; 795 case SMU_SOCCLK: 796 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 797 break; 798 case SMU_VCLK: 799 case SMU_DCLK: 800 feature_id = SMU_FEATURE_VCN_DPM_BIT; 801 break; 802 default: 803 return true; 804 } 805 806 return smu_cmn_feature_is_enabled(smu, feature_id); 807 } 808 809 static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu, 810 enum smu_clk_type clk_type, 811 uint32_t *min, 812 uint32_t *max) 813 { 814 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 815 uint32_t clock_limit; 816 uint32_t max_dpm_level, min_dpm_level; 817 int ret = 0; 818 819 if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) { 820 switch (clk_type) { 821 case SMU_MCLK: 822 case SMU_UCLK: 823 clock_limit = smu->smu_table.boot_values.uclk; 824 break; 825 case SMU_FCLK: 826 clock_limit = smu->smu_table.boot_values.fclk; 827 break; 828 case SMU_GFXCLK: 829 case SMU_SCLK: 830 clock_limit = smu->smu_table.boot_values.gfxclk; 831 break; 832 case SMU_SOCCLK: 833 clock_limit = smu->smu_table.boot_values.socclk; 834 break; 835 case SMU_VCLK: 836 clock_limit = smu->smu_table.boot_values.vclk; 837 break; 838 case SMU_DCLK: 839 clock_limit = smu->smu_table.boot_values.dclk; 840 break; 841 default: 842 clock_limit = 0; 843 break; 844 } 845 846 /* clock in Mhz unit */ 847 if (min) 848 *min = clock_limit / 100; 849 if (max) 850 *max = clock_limit / 100; 851 852 return 0; 853 } 854 855 if (max) { 856 switch (clk_type) { 857 case SMU_GFXCLK: 858 case SMU_SCLK: 859 *max = clk_table->MaxGfxClk; 860 break; 861 case SMU_MCLK: 862 case SMU_UCLK: 863 case SMU_FCLK: 864 max_dpm_level = 0; 865 break; 866 case SMU_SOCCLK: 867 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1; 868 break; 869 case SMU_VCLK: 870 case SMU_DCLK: 871 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1; 872 break; 873 default: 874 ret = -EINVAL; 875 goto failed; 876 } 877 878 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 879 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max); 880 if (ret) 881 goto failed; 882 } 883 } 884 885 if (min) { 886 switch (clk_type) { 887 case SMU_GFXCLK: 888 case SMU_SCLK: 889 *min = clk_table->MinGfxClk; 890 break; 891 case SMU_MCLK: 892 case SMU_UCLK: 893 case SMU_FCLK: 894 min_dpm_level = clk_table->NumDfPstatesEnabled - 1; 895 break; 896 case SMU_SOCCLK: 897 min_dpm_level = 0; 898 break; 899 case SMU_VCLK: 900 case SMU_DCLK: 901 min_dpm_level = 0; 902 break; 903 default: 904 ret = -EINVAL; 905 goto failed; 906 } 907 908 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 909 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min); 910 if (ret) 911 goto failed; 912 } 913 } 914 915 failed: 916 return ret; 917 } 918 919 static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu, 920 enum smu_clk_type clk_type, 921 uint32_t min, 922 uint32_t max) 923 { 924 enum smu_message_type msg_set_min, msg_set_max; 925 int ret = 0; 926 927 if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) 928 return -EINVAL; 929 930 switch (clk_type) { 931 case SMU_GFXCLK: 932 case SMU_SCLK: 933 msg_set_min = SMU_MSG_SetHardMinGfxClk; 934 msg_set_max = SMU_MSG_SetSoftMaxGfxClk; 935 break; 936 case SMU_FCLK: 937 msg_set_min = SMU_MSG_SetHardMinFclkByFreq; 938 msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq; 939 break; 940 case SMU_SOCCLK: 941 msg_set_min = SMU_MSG_SetHardMinSocclkByFreq; 942 msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq; 943 break; 944 case SMU_VCLK: 945 case SMU_DCLK: 946 msg_set_min = SMU_MSG_SetHardMinVcn; 947 msg_set_max = SMU_MSG_SetSoftMaxVcn; 948 break; 949 default: 950 return -EINVAL; 951 } 952 953 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL); 954 if (ret) 955 goto out; 956 957 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL); 958 if (ret) 959 goto out; 960 961 out: 962 return ret; 963 } 964 965 static int yellow_carp_print_clk_levels(struct smu_context *smu, 966 enum smu_clk_type clk_type, char *buf) 967 { 968 int i, size = 0, ret = 0; 969 uint32_t cur_value = 0, value = 0, count = 0; 970 971 smu_cmn_get_sysfs_buf(&buf, &size); 972 973 switch (clk_type) { 974 case SMU_OD_SCLK: 975 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 976 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 977 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 978 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 979 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 980 break; 981 case SMU_OD_RANGE: 982 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 983 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 984 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 985 break; 986 case SMU_SOCCLK: 987 case SMU_VCLK: 988 case SMU_DCLK: 989 case SMU_MCLK: 990 case SMU_FCLK: 991 ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value); 992 if (ret) 993 goto print_clk_out; 994 995 ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count); 996 if (ret) 997 goto print_clk_out; 998 999 for (i = 0; i < count; i++) { 1000 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, i, &value); 1001 if (ret) 1002 goto print_clk_out; 1003 1004 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1005 cur_value == value ? "*" : ""); 1006 } 1007 break; 1008 default: 1009 break; 1010 } 1011 1012 print_clk_out: 1013 return size; 1014 } 1015 1016 static int yellow_carp_force_clk_levels(struct smu_context *smu, 1017 enum smu_clk_type clk_type, uint32_t mask) 1018 { 1019 uint32_t soft_min_level = 0, soft_max_level = 0; 1020 uint32_t min_freq = 0, max_freq = 0; 1021 int ret = 0; 1022 1023 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1024 soft_max_level = mask ? (fls(mask) - 1) : 0; 1025 1026 switch (clk_type) { 1027 case SMU_SOCCLK: 1028 case SMU_FCLK: 1029 case SMU_VCLK: 1030 case SMU_DCLK: 1031 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1032 if (ret) 1033 goto force_level_out; 1034 1035 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1036 if (ret) 1037 goto force_level_out; 1038 1039 ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1040 if (ret) 1041 goto force_level_out; 1042 break; 1043 default: 1044 ret = -EINVAL; 1045 break; 1046 } 1047 1048 force_level_out: 1049 return ret; 1050 } 1051 1052 static int yellow_carp_set_performance_level(struct smu_context *smu, 1053 enum amd_dpm_forced_level level) 1054 { 1055 struct amdgpu_device *adev = smu->adev; 1056 uint32_t sclk_min = 0, sclk_max = 0; 1057 uint32_t fclk_min = 0, fclk_max = 0; 1058 uint32_t socclk_min = 0, socclk_max = 0; 1059 int ret = 0; 1060 1061 switch (level) { 1062 case AMD_DPM_FORCED_LEVEL_HIGH: 1063 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max); 1064 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max); 1065 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max); 1066 sclk_min = sclk_max; 1067 fclk_min = fclk_max; 1068 socclk_min = socclk_max; 1069 break; 1070 case AMD_DPM_FORCED_LEVEL_LOW: 1071 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL); 1072 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL); 1073 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL); 1074 sclk_max = sclk_min; 1075 fclk_max = fclk_min; 1076 socclk_max = socclk_min; 1077 break; 1078 case AMD_DPM_FORCED_LEVEL_AUTO: 1079 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max); 1080 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max); 1081 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max); 1082 break; 1083 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1084 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1085 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1086 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1087 /* Temporarily do nothing since the optimal clocks haven't been provided yet */ 1088 break; 1089 case AMD_DPM_FORCED_LEVEL_MANUAL: 1090 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1091 return 0; 1092 default: 1093 dev_err(adev->dev, "Invalid performance level %d\n", level); 1094 return -EINVAL; 1095 } 1096 1097 if (sclk_min && sclk_max) { 1098 ret = yellow_carp_set_soft_freq_limited_range(smu, 1099 SMU_SCLK, 1100 sclk_min, 1101 sclk_max); 1102 if (ret) 1103 return ret; 1104 1105 smu->gfx_actual_hard_min_freq = sclk_min; 1106 smu->gfx_actual_soft_max_freq = sclk_max; 1107 } 1108 1109 if (fclk_min && fclk_max) { 1110 ret = yellow_carp_set_soft_freq_limited_range(smu, 1111 SMU_FCLK, 1112 fclk_min, 1113 fclk_max); 1114 if (ret) 1115 return ret; 1116 } 1117 1118 if (socclk_min && socclk_max) { 1119 ret = yellow_carp_set_soft_freq_limited_range(smu, 1120 SMU_SOCCLK, 1121 socclk_min, 1122 socclk_max); 1123 if (ret) 1124 return ret; 1125 } 1126 1127 return ret; 1128 } 1129 1130 static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1131 { 1132 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1133 1134 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1135 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1136 smu->gfx_actual_hard_min_freq = 0; 1137 smu->gfx_actual_soft_max_freq = 0; 1138 1139 return 0; 1140 } 1141 1142 static const struct pptable_funcs yellow_carp_ppt_funcs = { 1143 .check_fw_status = smu_v13_0_check_fw_status, 1144 .check_fw_version = smu_v13_0_check_fw_version, 1145 .init_smc_tables = yellow_carp_init_smc_tables, 1146 .fini_smc_tables = yellow_carp_fini_smc_tables, 1147 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1148 .system_features_control = yellow_carp_system_features_control, 1149 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1150 .send_smc_msg = smu_cmn_send_smc_msg, 1151 .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable, 1152 .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable, 1153 .set_default_dpm_table = yellow_carp_set_default_dpm_tables, 1154 .read_sensor = yellow_carp_read_sensor, 1155 .is_dpm_running = yellow_carp_is_dpm_running, 1156 .set_watermarks_table = yellow_carp_set_watermarks_table, 1157 .get_gpu_metrics = yellow_carp_get_gpu_metrics, 1158 .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask, 1159 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1160 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1161 .gfx_off_control = smu_v13_0_gfx_off_control, 1162 .post_init = yellow_carp_post_smu_init, 1163 .mode2_reset = yellow_carp_mode2_reset, 1164 .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq, 1165 .od_edit_dpm_table = yellow_carp_od_edit_dpm_table, 1166 .print_clk_levels = yellow_carp_print_clk_levels, 1167 .force_clk_levels = yellow_carp_force_clk_levels, 1168 .set_performance_level = yellow_carp_set_performance_level, 1169 .set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters, 1170 }; 1171 1172 void yellow_carp_set_ppt_funcs(struct smu_context *smu) 1173 { 1174 smu->ppt_funcs = &yellow_carp_ppt_funcs; 1175 smu->message_map = yellow_carp_message_map; 1176 smu->feature_map = yellow_carp_feature_mask_map; 1177 smu->table_map = yellow_carp_table_map; 1178 smu->is_apu = true; 1179 } 1180