1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v13_0.h" 35 #include "smu13_driver_if_v13_0_7.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "smu_v13_0_7_ppt.h" 39 #include "smu_v13_0_7_pptable.h" 40 #include "smu_v13_0_7_ppsmc.h" 41 #include "nbio/nbio_4_3_0_offset.h" 42 #include "nbio/nbio_4_3_0_sh_mask.h" 43 #include "mp/mp_13_0_0_offset.h" 44 #include "mp/mp_13_0_0_sh_mask.h" 45 46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "amdgpu_ras.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 70 71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028 72 73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 74 75 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = { 76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 79 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 80 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 81 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 82 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 83 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 84 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 85 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 86 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 89 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 98 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 100 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 108 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 109 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 110 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 111 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 112 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 113 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 114 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 115 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0), 116 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 117 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 118 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 119 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 120 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 121 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 122 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 123 }; 124 125 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = { 126 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 127 CLK_MAP(SCLK, PPCLK_GFXCLK), 128 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 129 CLK_MAP(FCLK, PPCLK_FCLK), 130 CLK_MAP(UCLK, PPCLK_UCLK), 131 CLK_MAP(MCLK, PPCLK_UCLK), 132 CLK_MAP(VCLK, PPCLK_VCLK_0), 133 CLK_MAP(VCLK1, PPCLK_VCLK_1), 134 CLK_MAP(DCLK, PPCLK_DCLK_0), 135 CLK_MAP(DCLK1, PPCLK_DCLK_1), 136 }; 137 138 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = { 139 FEA_MAP(FW_DATA_READ), 140 FEA_MAP(DPM_GFXCLK), 141 FEA_MAP(DPM_GFX_POWER_OPTIMIZER), 142 FEA_MAP(DPM_UCLK), 143 FEA_MAP(DPM_FCLK), 144 FEA_MAP(DPM_SOCCLK), 145 FEA_MAP(DPM_MP0CLK), 146 FEA_MAP(DPM_LINK), 147 FEA_MAP(DPM_DCN), 148 FEA_MAP(VMEMP_SCALING), 149 FEA_MAP(VDDIO_MEM_SCALING), 150 FEA_MAP(DS_GFXCLK), 151 FEA_MAP(DS_SOCCLK), 152 FEA_MAP(DS_FCLK), 153 FEA_MAP(DS_LCLK), 154 FEA_MAP(DS_DCFCLK), 155 FEA_MAP(DS_UCLK), 156 FEA_MAP(GFX_ULV), 157 FEA_MAP(FW_DSTATE), 158 FEA_MAP(GFXOFF), 159 FEA_MAP(BACO), 160 FEA_MAP(MM_DPM), 161 FEA_MAP(SOC_MPCLK_DS), 162 FEA_MAP(BACO_MPCLK_DS), 163 FEA_MAP(THROTTLERS), 164 FEA_MAP(SMARTSHIFT), 165 FEA_MAP(GTHR), 166 FEA_MAP(ACDC), 167 FEA_MAP(VR0HOT), 168 FEA_MAP(FW_CTF), 169 FEA_MAP(FAN_CONTROL), 170 FEA_MAP(GFX_DCS), 171 FEA_MAP(GFX_READ_MARGIN), 172 FEA_MAP(LED_DISPLAY), 173 FEA_MAP(GFXCLK_SPREAD_SPECTRUM), 174 FEA_MAP(OUT_OF_BAND_MONITOR), 175 FEA_MAP(OPTIMIZED_VMIN), 176 FEA_MAP(GFX_IMU), 177 FEA_MAP(BOOT_TIME_CAL), 178 FEA_MAP(GFX_PCC_DFLL), 179 FEA_MAP(SOC_CG), 180 FEA_MAP(DF_CSTATE), 181 FEA_MAP(GFX_EDC), 182 FEA_MAP(BOOT_POWER_OPT), 183 FEA_MAP(CLOCK_POWER_DOWN_BYPASS), 184 FEA_MAP(DS_VCN), 185 FEA_MAP(BACO_CG), 186 FEA_MAP(MEM_TEMP_READ), 187 FEA_MAP(ATHUB_MMHUB_PG), 188 FEA_MAP(SOC_PCC), 189 }; 190 191 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = { 192 TAB_MAP(PPTABLE), 193 TAB_MAP(WATERMARKS), 194 TAB_MAP(AVFS_PSM_DEBUG), 195 TAB_MAP(PMSTATUSLOG), 196 TAB_MAP(SMU_METRICS), 197 TAB_MAP(DRIVER_SMU_CONFIG), 198 TAB_MAP(ACTIVITY_MONITOR_COEFF), 199 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE}, 200 }; 201 202 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 203 PWR_MAP(AC), 204 PWR_MAP(DC), 205 }; 206 207 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 212 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 213 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 214 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 215 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT), 216 }; 217 218 static const uint8_t smu_v13_0_7_throttler_map[] = { 219 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 220 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 221 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 222 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 223 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 224 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 225 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 226 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 227 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 228 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 229 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 230 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 231 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 232 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 233 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 234 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT), 235 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 236 }; 237 238 static int 239 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, 240 uint32_t *feature_mask, uint32_t num) 241 { 242 struct amdgpu_device *adev = smu->adev; 243 244 if (num > 2) 245 return -EINVAL; 246 247 memset(feature_mask, 0, sizeof(uint32_t) * num); 248 249 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); 250 251 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 252 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 253 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); 254 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); 255 } 256 257 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 258 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 259 260 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { 261 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 262 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); 263 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 264 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 265 } 266 267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 268 269 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 271 272 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 274 275 if (adev->pm.pp_feature & PP_ULV_MASK) 276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 277 278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); 280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); 281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); 282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); 283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT); 284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT); 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); 286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); 287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT); 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); 290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); 291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); 292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT); 293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); 294 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT); 295 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); 297 298 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); 300 301 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) && 302 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 304 305 return 0; 306 } 307 308 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu) 309 { 310 struct smu_table_context *table_context = &smu->smu_table; 311 struct smu_13_0_7_powerplay_table *powerplay_table = 312 table_context->power_play_table; 313 struct smu_baco_context *smu_baco = &smu->smu_baco; 314 PPTable_t *smc_pptable = table_context->driver_pptable; 315 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 316 317 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC) 318 smu->dc_controlled_by_gpio = true; 319 320 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO || 321 powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) 322 smu_baco->platform_support = true; 323 324 if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) 325 smu_baco->maco_support = true; 326 327 table_context->thermal_controller_type = 328 powerplay_table->thermal_controller_type; 329 330 /* 331 * Instead of having its own buffer space and get overdrive_table copied, 332 * smu->od_settings just points to the actual overdrive_table 333 */ 334 smu->od_settings = &powerplay_table->overdrive_table; 335 336 return 0; 337 } 338 339 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu) 340 { 341 struct smu_table_context *table_context = &smu->smu_table; 342 struct smu_13_0_7_powerplay_table *powerplay_table = 343 table_context->power_play_table; 344 struct amdgpu_device *adev = smu->adev; 345 346 if (adev->pdev->device == 0x51) 347 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080; 348 349 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 350 sizeof(PPTable_t)); 351 352 return 0; 353 } 354 355 static int smu_v13_0_7_check_fw_status(struct smu_context *smu) 356 { 357 struct amdgpu_device *adev = smu->adev; 358 uint32_t mp1_fw_flags; 359 360 mp1_fw_flags = RREG32_PCIE(MP1_Public | 361 (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff)); 362 363 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 364 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 365 return 0; 366 367 return -EIO; 368 } 369 370 #ifndef atom_smc_dpm_info_table_13_0_7 371 struct atom_smc_dpm_info_table_13_0_7 372 { 373 struct atom_common_table_header table_header; 374 BoardTable_t BoardTable; 375 }; 376 #endif 377 378 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu) 379 { 380 struct smu_table_context *table_context = &smu->smu_table; 381 382 PPTable_t *smc_pptable = table_context->driver_pptable; 383 384 struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table; 385 386 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 387 388 int index, ret; 389 390 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 391 smc_dpm_info); 392 393 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 394 (uint8_t **)&smc_dpm_table); 395 if (ret) 396 return ret; 397 398 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 399 400 return 0; 401 } 402 403 404 static int smu_v13_0_7_setup_pptable(struct smu_context *smu) 405 { 406 struct smu_table_context *smu_table = &smu->smu_table; 407 void *combo_pptable = smu_table->combo_pptable; 408 struct amdgpu_device *adev = smu->adev; 409 int ret = 0; 410 411 /* 412 * With SCPM enabled, the pptable used will be signed. It cannot 413 * be used directly by driver. To get the raw pptable, we need to 414 * rely on the combo pptable(and its revelant SMU message). 415 */ 416 if (adev->scpm_enabled) { 417 ret = smu_cmn_get_combo_pptable(smu); 418 if (ret) 419 return ret; 420 421 smu->smu_table.power_play_table = combo_pptable; 422 smu->smu_table.power_play_table_size = sizeof(struct smu_13_0_7_powerplay_table); 423 } else { 424 ret = smu_v13_0_setup_pptable(smu); 425 if (ret) 426 return ret; 427 } 428 429 ret = smu_v13_0_7_store_powerplay_table(smu); 430 if (ret) 431 return ret; 432 433 /* 434 * With SCPM enabled, the operation below will be handled 435 * by PSP. Driver involvment is unnecessary and useless. 436 */ 437 if (!adev->scpm_enabled) { 438 ret = smu_v13_0_7_append_powerplay_table(smu); 439 if (ret) 440 return ret; 441 } 442 443 ret = smu_v13_0_7_check_powerplay_table(smu); 444 if (ret) 445 return ret; 446 447 return ret; 448 } 449 450 static int smu_v13_0_7_tables_init(struct smu_context *smu) 451 { 452 struct smu_table_context *smu_table = &smu->smu_table; 453 struct smu_table *tables = smu_table->tables; 454 455 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 456 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 457 458 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 459 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 460 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 461 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 462 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 463 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 464 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 465 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 466 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 467 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 468 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 469 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 470 AMDGPU_GEM_DOMAIN_VRAM); 471 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE, 472 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 473 474 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 475 if (!smu_table->metrics_table) 476 goto err0_out; 477 smu_table->metrics_time = 0; 478 479 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 480 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 481 if (!smu_table->gpu_metrics_table) 482 goto err1_out; 483 484 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 485 if (!smu_table->watermarks_table) 486 goto err2_out; 487 488 return 0; 489 490 err2_out: 491 kfree(smu_table->gpu_metrics_table); 492 err1_out: 493 kfree(smu_table->metrics_table); 494 err0_out: 495 return -ENOMEM; 496 } 497 498 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu) 499 { 500 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 501 502 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 503 GFP_KERNEL); 504 if (!smu_dpm->dpm_context) 505 return -ENOMEM; 506 507 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 508 509 return 0; 510 } 511 512 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu) 513 { 514 int ret = 0; 515 516 ret = smu_v13_0_7_tables_init(smu); 517 if (ret) 518 return ret; 519 520 ret = smu_v13_0_7_allocate_dpm_context(smu); 521 if (ret) 522 return ret; 523 524 return smu_v13_0_init_smc_tables(smu); 525 } 526 527 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) 528 { 529 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 530 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 531 SkuTable_t *skutable = &driver_ppt->SkuTable; 532 struct smu_13_0_dpm_table *dpm_table; 533 struct smu_13_0_pcie_table *pcie_table; 534 uint32_t link_level; 535 int ret = 0; 536 537 /* socclk dpm table setup */ 538 dpm_table = &dpm_context->dpm_tables.soc_table; 539 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 540 ret = smu_v13_0_set_single_dpm_table(smu, 541 SMU_SOCCLK, 542 dpm_table); 543 if (ret) 544 return ret; 545 } else { 546 dpm_table->count = 1; 547 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 548 dpm_table->dpm_levels[0].enabled = true; 549 dpm_table->min = dpm_table->dpm_levels[0].value; 550 dpm_table->max = dpm_table->dpm_levels[0].value; 551 } 552 553 /* gfxclk dpm table setup */ 554 dpm_table = &dpm_context->dpm_tables.gfx_table; 555 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 556 ret = smu_v13_0_set_single_dpm_table(smu, 557 SMU_GFXCLK, 558 dpm_table); 559 if (ret) 560 return ret; 561 } else { 562 dpm_table->count = 1; 563 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 564 dpm_table->dpm_levels[0].enabled = true; 565 dpm_table->min = dpm_table->dpm_levels[0].value; 566 dpm_table->max = dpm_table->dpm_levels[0].value; 567 } 568 569 /* uclk dpm table setup */ 570 dpm_table = &dpm_context->dpm_tables.uclk_table; 571 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 572 ret = smu_v13_0_set_single_dpm_table(smu, 573 SMU_UCLK, 574 dpm_table); 575 if (ret) 576 return ret; 577 } else { 578 dpm_table->count = 1; 579 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 580 dpm_table->dpm_levels[0].enabled = true; 581 dpm_table->min = dpm_table->dpm_levels[0].value; 582 dpm_table->max = dpm_table->dpm_levels[0].value; 583 } 584 585 /* fclk dpm table setup */ 586 dpm_table = &dpm_context->dpm_tables.fclk_table; 587 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 588 ret = smu_v13_0_set_single_dpm_table(smu, 589 SMU_FCLK, 590 dpm_table); 591 if (ret) 592 return ret; 593 } else { 594 dpm_table->count = 1; 595 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 596 dpm_table->dpm_levels[0].enabled = true; 597 dpm_table->min = dpm_table->dpm_levels[0].value; 598 dpm_table->max = dpm_table->dpm_levels[0].value; 599 } 600 601 /* vclk dpm table setup */ 602 dpm_table = &dpm_context->dpm_tables.vclk_table; 603 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { 604 ret = smu_v13_0_set_single_dpm_table(smu, 605 SMU_VCLK, 606 dpm_table); 607 if (ret) 608 return ret; 609 } else { 610 dpm_table->count = 1; 611 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 612 dpm_table->dpm_levels[0].enabled = true; 613 dpm_table->min = dpm_table->dpm_levels[0].value; 614 dpm_table->max = dpm_table->dpm_levels[0].value; 615 } 616 617 /* dclk dpm table setup */ 618 dpm_table = &dpm_context->dpm_tables.dclk_table; 619 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { 620 ret = smu_v13_0_set_single_dpm_table(smu, 621 SMU_DCLK, 622 dpm_table); 623 if (ret) 624 return ret; 625 } else { 626 dpm_table->count = 1; 627 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 628 dpm_table->dpm_levels[0].enabled = true; 629 dpm_table->min = dpm_table->dpm_levels[0].value; 630 dpm_table->max = dpm_table->dpm_levels[0].value; 631 } 632 633 /* lclk dpm table setup */ 634 pcie_table = &dpm_context->dpm_tables.pcie_table; 635 pcie_table->num_of_link_levels = 0; 636 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { 637 if (!skutable->PcieGenSpeed[link_level] && 638 !skutable->PcieLaneCount[link_level] && 639 !skutable->LclkFreq[link_level]) 640 continue; 641 642 pcie_table->pcie_gen[pcie_table->num_of_link_levels] = 643 skutable->PcieGenSpeed[link_level]; 644 pcie_table->pcie_lane[pcie_table->num_of_link_levels] = 645 skutable->PcieLaneCount[link_level]; 646 pcie_table->clk_freq[pcie_table->num_of_link_levels] = 647 skutable->LclkFreq[link_level]; 648 pcie_table->num_of_link_levels++; 649 } 650 651 return 0; 652 } 653 654 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu) 655 { 656 int ret = 0; 657 uint64_t feature_enabled; 658 659 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 660 if (ret) 661 return false; 662 663 return !!(feature_enabled & SMC_DPM_FEATURE); 664 } 665 666 static void smu_v13_0_7_dump_pptable(struct smu_context *smu) 667 { 668 struct smu_table_context *table_context = &smu->smu_table; 669 PPTable_t *pptable = table_context->driver_pptable; 670 SkuTable_t *skutable = &pptable->SkuTable; 671 672 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 673 674 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version); 675 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]); 676 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]); 677 } 678 679 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics) 680 { 681 uint32_t throttler_status = 0; 682 int i; 683 684 for (i = 0; i < THROTTLER_COUNT; i++) 685 throttler_status |= 686 (metrics->ThrottlingPercentage[i] ? 1U << i : 0); 687 688 return throttler_status; 689 } 690 691 #define SMU_13_0_7_BUSY_THRESHOLD 15 692 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu, 693 MetricsMember_t member, 694 uint32_t *value) 695 { 696 struct smu_table_context *smu_table= &smu->smu_table; 697 SmuMetrics_t *metrics = 698 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 699 int ret = 0; 700 701 ret = smu_cmn_get_metrics_table(smu, 702 NULL, 703 false); 704 if (ret) 705 return ret; 706 707 switch (member) { 708 case METRICS_CURR_GFXCLK: 709 *value = metrics->CurrClock[PPCLK_GFXCLK]; 710 break; 711 case METRICS_CURR_SOCCLK: 712 *value = metrics->CurrClock[PPCLK_SOCCLK]; 713 break; 714 case METRICS_CURR_UCLK: 715 *value = metrics->CurrClock[PPCLK_UCLK]; 716 break; 717 case METRICS_CURR_VCLK: 718 *value = metrics->CurrClock[PPCLK_VCLK_0]; 719 break; 720 case METRICS_CURR_VCLK1: 721 *value = metrics->CurrClock[PPCLK_VCLK_1]; 722 break; 723 case METRICS_CURR_DCLK: 724 *value = metrics->CurrClock[PPCLK_DCLK_0]; 725 break; 726 case METRICS_CURR_DCLK1: 727 *value = metrics->CurrClock[PPCLK_DCLK_1]; 728 break; 729 case METRICS_CURR_FCLK: 730 *value = metrics->CurrClock[PPCLK_FCLK]; 731 break; 732 case METRICS_AVERAGE_GFXCLK: 733 *value = metrics->AverageGfxclkFrequencyPreDs; 734 break; 735 case METRICS_AVERAGE_FCLK: 736 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 737 *value = metrics->AverageFclkFrequencyPostDs; 738 else 739 *value = metrics->AverageFclkFrequencyPreDs; 740 break; 741 case METRICS_AVERAGE_UCLK: 742 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 743 *value = metrics->AverageMemclkFrequencyPostDs; 744 else 745 *value = metrics->AverageMemclkFrequencyPreDs; 746 break; 747 case METRICS_AVERAGE_VCLK: 748 *value = metrics->AverageVclk0Frequency; 749 break; 750 case METRICS_AVERAGE_DCLK: 751 *value = metrics->AverageDclk0Frequency; 752 break; 753 case METRICS_AVERAGE_VCLK1: 754 *value = metrics->AverageVclk1Frequency; 755 break; 756 case METRICS_AVERAGE_DCLK1: 757 *value = metrics->AverageDclk1Frequency; 758 break; 759 case METRICS_AVERAGE_GFXACTIVITY: 760 *value = metrics->AverageGfxActivity; 761 break; 762 case METRICS_AVERAGE_MEMACTIVITY: 763 *value = metrics->AverageUclkActivity; 764 break; 765 case METRICS_AVERAGE_SOCKETPOWER: 766 *value = metrics->AverageSocketPower << 8; 767 break; 768 case METRICS_TEMPERATURE_EDGE: 769 *value = metrics->AvgTemperature[TEMP_EDGE] * 770 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 771 break; 772 case METRICS_TEMPERATURE_HOTSPOT: 773 *value = metrics->AvgTemperature[TEMP_HOTSPOT] * 774 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 775 break; 776 case METRICS_TEMPERATURE_MEM: 777 *value = metrics->AvgTemperature[TEMP_MEM] * 778 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 779 break; 780 case METRICS_TEMPERATURE_VRGFX: 781 *value = metrics->AvgTemperature[TEMP_VR_GFX] * 782 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 783 break; 784 case METRICS_TEMPERATURE_VRSOC: 785 *value = metrics->AvgTemperature[TEMP_VR_SOC] * 786 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 787 break; 788 case METRICS_THROTTLER_STATUS: 789 *value = smu_v13_0_7_get_throttler_status(metrics); 790 break; 791 case METRICS_CURR_FANSPEED: 792 *value = metrics->AvgFanRpm; 793 break; 794 case METRICS_CURR_FANPWM: 795 *value = metrics->AvgFanPwm; 796 break; 797 case METRICS_VOLTAGE_VDDGFX: 798 *value = metrics->AvgVoltage[SVI_PLANE_GFX]; 799 break; 800 case METRICS_PCIE_RATE: 801 *value = metrics->PcieRate; 802 break; 803 case METRICS_PCIE_WIDTH: 804 *value = metrics->PcieWidth; 805 break; 806 default: 807 *value = UINT_MAX; 808 break; 809 } 810 811 return ret; 812 } 813 814 static int smu_v13_0_7_read_sensor(struct smu_context *smu, 815 enum amd_pp_sensors sensor, 816 void *data, 817 uint32_t *size) 818 { 819 struct smu_table_context *table_context = &smu->smu_table; 820 PPTable_t *smc_pptable = table_context->driver_pptable; 821 int ret = 0; 822 823 switch (sensor) { 824 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 825 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm; 826 *size = 4; 827 break; 828 case AMDGPU_PP_SENSOR_MEM_LOAD: 829 ret = smu_v13_0_7_get_smu_metrics_data(smu, 830 METRICS_AVERAGE_MEMACTIVITY, 831 (uint32_t *)data); 832 *size = 4; 833 break; 834 case AMDGPU_PP_SENSOR_GPU_LOAD: 835 ret = smu_v13_0_7_get_smu_metrics_data(smu, 836 METRICS_AVERAGE_GFXACTIVITY, 837 (uint32_t *)data); 838 *size = 4; 839 break; 840 case AMDGPU_PP_SENSOR_GPU_POWER: 841 ret = smu_v13_0_7_get_smu_metrics_data(smu, 842 METRICS_AVERAGE_SOCKETPOWER, 843 (uint32_t *)data); 844 *size = 4; 845 break; 846 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 847 ret = smu_v13_0_7_get_smu_metrics_data(smu, 848 METRICS_TEMPERATURE_HOTSPOT, 849 (uint32_t *)data); 850 *size = 4; 851 break; 852 case AMDGPU_PP_SENSOR_EDGE_TEMP: 853 ret = smu_v13_0_7_get_smu_metrics_data(smu, 854 METRICS_TEMPERATURE_EDGE, 855 (uint32_t *)data); 856 *size = 4; 857 break; 858 case AMDGPU_PP_SENSOR_MEM_TEMP: 859 ret = smu_v13_0_7_get_smu_metrics_data(smu, 860 METRICS_TEMPERATURE_MEM, 861 (uint32_t *)data); 862 *size = 4; 863 break; 864 case AMDGPU_PP_SENSOR_GFX_MCLK: 865 ret = smu_v13_0_7_get_smu_metrics_data(smu, 866 METRICS_AVERAGE_UCLK, 867 (uint32_t *)data); 868 *(uint32_t *)data *= 100; 869 *size = 4; 870 break; 871 case AMDGPU_PP_SENSOR_GFX_SCLK: 872 ret = smu_v13_0_7_get_smu_metrics_data(smu, 873 METRICS_AVERAGE_GFXCLK, 874 (uint32_t *)data); 875 *(uint32_t *)data *= 100; 876 *size = 4; 877 break; 878 case AMDGPU_PP_SENSOR_VDDGFX: 879 ret = smu_v13_0_7_get_smu_metrics_data(smu, 880 METRICS_VOLTAGE_VDDGFX, 881 (uint32_t *)data); 882 *size = 4; 883 break; 884 default: 885 ret = -EOPNOTSUPP; 886 break; 887 } 888 889 return ret; 890 } 891 892 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu, 893 enum smu_clk_type clk_type, 894 uint32_t *value) 895 { 896 MetricsMember_t member_type; 897 int clk_id = 0; 898 899 clk_id = smu_cmn_to_asic_specific_index(smu, 900 CMN2ASIC_MAPPING_CLK, 901 clk_type); 902 if (clk_id < 0) 903 return -EINVAL; 904 905 switch (clk_id) { 906 case PPCLK_GFXCLK: 907 member_type = METRICS_AVERAGE_GFXCLK; 908 break; 909 case PPCLK_UCLK: 910 member_type = METRICS_CURR_UCLK; 911 break; 912 case PPCLK_FCLK: 913 member_type = METRICS_CURR_FCLK; 914 break; 915 case PPCLK_SOCCLK: 916 member_type = METRICS_CURR_SOCCLK; 917 break; 918 case PPCLK_VCLK_0: 919 member_type = METRICS_CURR_VCLK; 920 break; 921 case PPCLK_DCLK_0: 922 member_type = METRICS_CURR_DCLK; 923 break; 924 case PPCLK_VCLK_1: 925 member_type = METRICS_CURR_VCLK1; 926 break; 927 case PPCLK_DCLK_1: 928 member_type = METRICS_CURR_DCLK1; 929 break; 930 default: 931 return -EINVAL; 932 } 933 934 return smu_v13_0_7_get_smu_metrics_data(smu, 935 member_type, 936 value); 937 } 938 939 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, 940 enum smu_clk_type clk_type, 941 char *buf) 942 { 943 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 944 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 945 struct smu_13_0_dpm_table *single_dpm_table; 946 struct smu_13_0_pcie_table *pcie_table; 947 uint32_t gen_speed, lane_width; 948 int i, curr_freq, size = 0; 949 int ret = 0; 950 951 smu_cmn_get_sysfs_buf(&buf, &size); 952 953 if (amdgpu_ras_intr_triggered()) { 954 size += sysfs_emit_at(buf, size, "unavailable\n"); 955 return size; 956 } 957 958 switch (clk_type) { 959 case SMU_SCLK: 960 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 961 break; 962 case SMU_MCLK: 963 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 964 break; 965 case SMU_SOCCLK: 966 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 967 break; 968 case SMU_FCLK: 969 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 970 break; 971 case SMU_VCLK: 972 case SMU_VCLK1: 973 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 974 break; 975 case SMU_DCLK: 976 case SMU_DCLK1: 977 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 978 break; 979 default: 980 break; 981 } 982 983 switch (clk_type) { 984 case SMU_SCLK: 985 case SMU_MCLK: 986 case SMU_SOCCLK: 987 case SMU_FCLK: 988 case SMU_VCLK: 989 case SMU_VCLK1: 990 case SMU_DCLK: 991 case SMU_DCLK1: 992 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); 993 if (ret) { 994 dev_err(smu->adev->dev, "Failed to get current clock freq!"); 995 return ret; 996 } 997 998 if (single_dpm_table->is_fine_grained) { 999 /* 1000 * For fine grained dpms, there are only two dpm levels: 1001 * - level 0 -> min clock freq 1002 * - level 1 -> max clock freq 1003 * And the current clock frequency can be any value between them. 1004 * So, if the current clock frequency is not at level 0 or level 1, 1005 * we will fake it as three dpm levels: 1006 * - level 0 -> min clock freq 1007 * - level 1 -> current actual clock freq 1008 * - level 2 -> max clock freq 1009 */ 1010 if ((single_dpm_table->dpm_levels[0].value != curr_freq) && 1011 (single_dpm_table->dpm_levels[1].value != curr_freq)) { 1012 size += sysfs_emit_at(buf, size, "0: %uMhz\n", 1013 single_dpm_table->dpm_levels[0].value); 1014 size += sysfs_emit_at(buf, size, "1: %uMhz *\n", 1015 curr_freq); 1016 size += sysfs_emit_at(buf, size, "2: %uMhz\n", 1017 single_dpm_table->dpm_levels[1].value); 1018 } else { 1019 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 1020 single_dpm_table->dpm_levels[0].value, 1021 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); 1022 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 1023 single_dpm_table->dpm_levels[1].value, 1024 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); 1025 } 1026 } else { 1027 for (i = 0; i < single_dpm_table->count; i++) 1028 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 1029 i, single_dpm_table->dpm_levels[i].value, 1030 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); 1031 } 1032 break; 1033 case SMU_PCIE: 1034 ret = smu_v13_0_7_get_smu_metrics_data(smu, 1035 METRICS_PCIE_RATE, 1036 &gen_speed); 1037 if (ret) 1038 return ret; 1039 1040 ret = smu_v13_0_7_get_smu_metrics_data(smu, 1041 METRICS_PCIE_WIDTH, 1042 &lane_width); 1043 if (ret) 1044 return ret; 1045 1046 pcie_table = &(dpm_context->dpm_tables.pcie_table); 1047 for (i = 0; i < pcie_table->num_of_link_levels; i++) 1048 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1049 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : 1050 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : 1051 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : 1052 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", 1053 (pcie_table->pcie_lane[i] == 1) ? "x1" : 1054 (pcie_table->pcie_lane[i] == 2) ? "x2" : 1055 (pcie_table->pcie_lane[i] == 3) ? "x4" : 1056 (pcie_table->pcie_lane[i] == 4) ? "x8" : 1057 (pcie_table->pcie_lane[i] == 5) ? "x12" : 1058 (pcie_table->pcie_lane[i] == 6) ? "x16" : "", 1059 pcie_table->clk_freq[i], 1060 (gen_speed == pcie_table->pcie_gen[i]) && 1061 (lane_width == pcie_table->pcie_lane[i]) ? 1062 "*" : ""); 1063 break; 1064 1065 default: 1066 break; 1067 } 1068 1069 return size; 1070 } 1071 1072 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu, 1073 enum smu_clk_type clk_type, 1074 uint32_t mask) 1075 { 1076 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1077 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1078 struct smu_13_0_dpm_table *single_dpm_table; 1079 uint32_t soft_min_level, soft_max_level; 1080 uint32_t min_freq, max_freq; 1081 int ret = 0; 1082 1083 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1084 soft_max_level = mask ? (fls(mask) - 1) : 0; 1085 1086 switch (clk_type) { 1087 case SMU_GFXCLK: 1088 case SMU_SCLK: 1089 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1090 break; 1091 case SMU_MCLK: 1092 case SMU_UCLK: 1093 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1094 break; 1095 case SMU_SOCCLK: 1096 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1097 break; 1098 case SMU_FCLK: 1099 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1100 break; 1101 case SMU_VCLK: 1102 case SMU_VCLK1: 1103 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1104 break; 1105 case SMU_DCLK: 1106 case SMU_DCLK1: 1107 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1108 break; 1109 default: 1110 break; 1111 } 1112 1113 switch (clk_type) { 1114 case SMU_GFXCLK: 1115 case SMU_SCLK: 1116 case SMU_MCLK: 1117 case SMU_UCLK: 1118 case SMU_SOCCLK: 1119 case SMU_FCLK: 1120 case SMU_VCLK: 1121 case SMU_VCLK1: 1122 case SMU_DCLK: 1123 case SMU_DCLK1: 1124 if (single_dpm_table->is_fine_grained) { 1125 /* There is only 2 levels for fine grained DPM */ 1126 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1127 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1128 } else { 1129 if ((soft_max_level >= single_dpm_table->count) || 1130 (soft_min_level >= single_dpm_table->count)) 1131 return -EINVAL; 1132 } 1133 1134 min_freq = single_dpm_table->dpm_levels[soft_min_level].value; 1135 max_freq = single_dpm_table->dpm_levels[soft_max_level].value; 1136 1137 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1138 clk_type, 1139 min_freq, 1140 max_freq); 1141 break; 1142 case SMU_DCEFCLK: 1143 case SMU_PCIE: 1144 default: 1145 break; 1146 } 1147 1148 return ret; 1149 } 1150 1151 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, 1152 uint32_t pcie_gen_cap, 1153 uint32_t pcie_width_cap) 1154 { 1155 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1156 struct smu_13_0_pcie_table *pcie_table = 1157 &dpm_context->dpm_tables.pcie_table; 1158 uint32_t smu_pcie_arg; 1159 int ret, i; 1160 1161 for (i = 0; i < pcie_table->num_of_link_levels; i++) { 1162 if (pcie_table->pcie_gen[i] > pcie_gen_cap) 1163 pcie_table->pcie_gen[i] = pcie_gen_cap; 1164 if (pcie_table->pcie_lane[i] > pcie_width_cap) 1165 pcie_table->pcie_lane[i] = pcie_width_cap; 1166 1167 smu_pcie_arg = i << 16; 1168 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8; 1169 smu_pcie_arg |= pcie_table->pcie_lane[i]; 1170 1171 ret = smu_cmn_send_smc_msg_with_param(smu, 1172 SMU_MSG_OverridePcieParameters, 1173 smu_pcie_arg, 1174 NULL); 1175 if (ret) 1176 return ret; 1177 } 1178 1179 return 0; 1180 } 1181 1182 static const struct smu_temperature_range smu13_thermal_policy[] = 1183 { 1184 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 1185 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 1186 }; 1187 1188 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu, 1189 struct smu_temperature_range *range) 1190 { 1191 struct smu_table_context *table_context = &smu->smu_table; 1192 struct smu_13_0_7_powerplay_table *powerplay_table = 1193 table_context->power_play_table; 1194 PPTable_t *pptable = smu->smu_table.driver_pptable; 1195 1196 if (!range) 1197 return -EINVAL; 1198 1199 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1200 1201 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] * 1202 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1203 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1204 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1205 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] * 1206 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1207 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1208 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1209 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] * 1210 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1211 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1212 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1213 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1214 1215 return 0; 1216 } 1217 1218 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 1219 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu, 1220 void **table) 1221 { 1222 struct smu_table_context *smu_table = &smu->smu_table; 1223 struct gpu_metrics_v1_3 *gpu_metrics = 1224 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1225 SmuMetricsExternal_t metrics_ext; 1226 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 1227 int ret = 0; 1228 1229 ret = smu_cmn_get_metrics_table(smu, 1230 &metrics_ext, 1231 true); 1232 if (ret) 1233 return ret; 1234 1235 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1236 1237 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE]; 1238 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT]; 1239 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM]; 1240 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX]; 1241 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC]; 1242 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0], 1243 metrics->AvgTemperature[TEMP_VR_MEM1]); 1244 1245 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 1246 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 1247 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage, 1248 metrics->Vcn1ActivityPercentage); 1249 1250 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 1251 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 1252 1253 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD) 1254 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 1255 else 1256 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 1257 1258 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 1259 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 1260 else 1261 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs; 1262 1263 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 1264 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 1265 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 1266 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 1267 1268 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; 1269 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 1270 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 1271 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 1272 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 1273 1274 gpu_metrics->throttle_status = 1275 smu_v13_0_7_get_throttler_status(metrics); 1276 gpu_metrics->indep_throttle_status = 1277 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 1278 smu_v13_0_7_throttler_map); 1279 1280 gpu_metrics->current_fan_speed = metrics->AvgFanRpm; 1281 1282 gpu_metrics->pcie_link_width = metrics->PcieWidth; 1283 gpu_metrics->pcie_link_speed = metrics->PcieRate; 1284 1285 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1286 1287 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX]; 1288 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC]; 1289 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP]; 1290 1291 *table = (void *)gpu_metrics; 1292 1293 return sizeof(struct gpu_metrics_v1_3); 1294 } 1295 1296 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu) 1297 { 1298 struct smu_13_0_dpm_context *dpm_context = 1299 smu->smu_dpm.dpm_context; 1300 struct smu_13_0_dpm_table *gfx_table = 1301 &dpm_context->dpm_tables.gfx_table; 1302 struct smu_13_0_dpm_table *mem_table = 1303 &dpm_context->dpm_tables.uclk_table; 1304 struct smu_13_0_dpm_table *soc_table = 1305 &dpm_context->dpm_tables.soc_table; 1306 struct smu_13_0_dpm_table *vclk_table = 1307 &dpm_context->dpm_tables.vclk_table; 1308 struct smu_13_0_dpm_table *dclk_table = 1309 &dpm_context->dpm_tables.dclk_table; 1310 struct smu_13_0_dpm_table *fclk_table = 1311 &dpm_context->dpm_tables.fclk_table; 1312 struct smu_umd_pstate_table *pstate_table = 1313 &smu->pstate_table; 1314 1315 pstate_table->gfxclk_pstate.min = gfx_table->min; 1316 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1317 1318 pstate_table->uclk_pstate.min = mem_table->min; 1319 pstate_table->uclk_pstate.peak = mem_table->max; 1320 1321 pstate_table->socclk_pstate.min = soc_table->min; 1322 pstate_table->socclk_pstate.peak = soc_table->max; 1323 1324 pstate_table->vclk_pstate.min = vclk_table->min; 1325 pstate_table->vclk_pstate.peak = vclk_table->max; 1326 1327 pstate_table->dclk_pstate.min = dclk_table->min; 1328 pstate_table->dclk_pstate.peak = dclk_table->max; 1329 1330 pstate_table->fclk_pstate.min = fclk_table->min; 1331 pstate_table->fclk_pstate.peak = fclk_table->max; 1332 1333 /* 1334 * For now, just use the mininum clock frequency. 1335 * TODO: update them when the real pstate settings available 1336 */ 1337 pstate_table->gfxclk_pstate.standard = gfx_table->min; 1338 pstate_table->uclk_pstate.standard = mem_table->min; 1339 pstate_table->socclk_pstate.standard = soc_table->min; 1340 pstate_table->vclk_pstate.standard = vclk_table->min; 1341 pstate_table->dclk_pstate.standard = dclk_table->min; 1342 pstate_table->fclk_pstate.standard = fclk_table->min; 1343 1344 return 0; 1345 } 1346 1347 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu, 1348 uint32_t *speed) 1349 { 1350 if (!speed) 1351 return -EINVAL; 1352 1353 return smu_v13_0_7_get_smu_metrics_data(smu, 1354 METRICS_CURR_FANPWM, 1355 speed); 1356 } 1357 1358 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu, 1359 uint32_t *speed) 1360 { 1361 if (!speed) 1362 return -EINVAL; 1363 1364 return smu_v13_0_7_get_smu_metrics_data(smu, 1365 METRICS_CURR_FANSPEED, 1366 speed); 1367 } 1368 1369 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu) 1370 { 1371 struct smu_table_context *table_context = &smu->smu_table; 1372 PPTable_t *pptable = table_context->driver_pptable; 1373 SkuTable_t *skutable = &pptable->SkuTable; 1374 1375 /* 1376 * Skip the MGpuFanBoost setting for those ASICs 1377 * which do not support it 1378 */ 1379 if (skutable->MGpuAcousticLimitRpmThreshold == 0) 1380 return 0; 1381 1382 return smu_cmn_send_smc_msg_with_param(smu, 1383 SMU_MSG_SetMGpuFanBoostLimitRpm, 1384 0, 1385 NULL); 1386 } 1387 1388 static int smu_v13_0_7_get_power_limit(struct smu_context *smu, 1389 uint32_t *current_power_limit, 1390 uint32_t *default_power_limit, 1391 uint32_t *max_power_limit) 1392 { 1393 struct smu_table_context *table_context = &smu->smu_table; 1394 struct smu_13_0_7_powerplay_table *powerplay_table = 1395 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table; 1396 PPTable_t *pptable = table_context->driver_pptable; 1397 SkuTable_t *skutable = &pptable->SkuTable; 1398 uint32_t power_limit, od_percent; 1399 1400 if (smu_v13_0_get_current_power_limit(smu, &power_limit)) 1401 power_limit = smu->adev->pm.ac_power ? 1402 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] : 1403 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0]; 1404 1405 if (current_power_limit) 1406 *current_power_limit = power_limit; 1407 if (default_power_limit) 1408 *default_power_limit = power_limit; 1409 1410 if (max_power_limit) { 1411 if (smu->od_enabled) { 1412 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]); 1413 1414 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1415 1416 power_limit *= (100 + od_percent); 1417 power_limit /= 100; 1418 } 1419 *max_power_limit = power_limit; 1420 } 1421 1422 return 0; 1423 } 1424 1425 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf) 1426 { 1427 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external[PP_SMC_POWER_PROFILE_COUNT]; 1428 uint32_t i, j, size = 0; 1429 int16_t workload_type = 0; 1430 int result = 0; 1431 1432 if (!buf) 1433 return -EINVAL; 1434 1435 size += sysfs_emit_at(buf, size, " "); 1436 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) 1437 size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i], 1438 (i == smu->power_profile_mode) ? "* " : " "); 1439 1440 size += sysfs_emit_at(buf, size, "\n"); 1441 1442 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) { 1443 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1444 workload_type = smu_cmn_to_asic_specific_index(smu, 1445 CMN2ASIC_MAPPING_WORKLOAD, 1446 i); 1447 if (workload_type < 0) 1448 return -EINVAL; 1449 1450 result = smu_cmn_update_table(smu, 1451 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1452 (void *)(&activity_monitor_external[i]), false); 1453 if (result) { 1454 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1455 return result; 1456 } 1457 } 1458 1459 #define PRINT_DPM_MONITOR(field) \ 1460 do { \ 1461 size += sysfs_emit_at(buf, size, "%-30s", #field); \ 1462 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \ 1463 size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \ 1464 size += sysfs_emit_at(buf, size, "\n"); \ 1465 } while (0) 1466 1467 PRINT_DPM_MONITOR(Gfx_ActiveHystLimit); 1468 PRINT_DPM_MONITOR(Gfx_IdleHystLimit); 1469 PRINT_DPM_MONITOR(Gfx_FPS); 1470 PRINT_DPM_MONITOR(Gfx_MinActiveFreqType); 1471 PRINT_DPM_MONITOR(Gfx_BoosterFreqType); 1472 PRINT_DPM_MONITOR(Gfx_MinActiveFreq); 1473 PRINT_DPM_MONITOR(Gfx_BoosterFreq); 1474 PRINT_DPM_MONITOR(Fclk_ActiveHystLimit); 1475 PRINT_DPM_MONITOR(Fclk_IdleHystLimit); 1476 PRINT_DPM_MONITOR(Fclk_FPS); 1477 PRINT_DPM_MONITOR(Fclk_MinActiveFreqType); 1478 PRINT_DPM_MONITOR(Fclk_BoosterFreqType); 1479 PRINT_DPM_MONITOR(Fclk_MinActiveFreq); 1480 PRINT_DPM_MONITOR(Fclk_BoosterFreq); 1481 #undef PRINT_DPM_MONITOR 1482 1483 return size; 1484 } 1485 1486 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1487 { 1488 1489 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1490 DpmActivityMonitorCoeffInt_t *activity_monitor = 1491 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1492 int workload_type, ret = 0; 1493 1494 smu->power_profile_mode = input[size]; 1495 1496 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) { 1497 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1498 return -EINVAL; 1499 } 1500 1501 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1502 1503 ret = smu_cmn_update_table(smu, 1504 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1505 (void *)(&activity_monitor_external), false); 1506 if (ret) { 1507 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1508 return ret; 1509 } 1510 1511 switch (input[0]) { 1512 case 0: /* Gfxclk */ 1513 activity_monitor->Gfx_ActiveHystLimit = input[1]; 1514 activity_monitor->Gfx_IdleHystLimit = input[2]; 1515 activity_monitor->Gfx_FPS = input[3]; 1516 activity_monitor->Gfx_MinActiveFreqType = input[4]; 1517 activity_monitor->Gfx_BoosterFreqType = input[5]; 1518 activity_monitor->Gfx_MinActiveFreq = input[6]; 1519 activity_monitor->Gfx_BoosterFreq = input[7]; 1520 break; 1521 case 1: /* Fclk */ 1522 activity_monitor->Fclk_ActiveHystLimit = input[1]; 1523 activity_monitor->Fclk_IdleHystLimit = input[2]; 1524 activity_monitor->Fclk_FPS = input[3]; 1525 activity_monitor->Fclk_MinActiveFreqType = input[4]; 1526 activity_monitor->Fclk_BoosterFreqType = input[5]; 1527 activity_monitor->Fclk_MinActiveFreq = input[6]; 1528 activity_monitor->Fclk_BoosterFreq = input[7]; 1529 break; 1530 } 1531 1532 ret = smu_cmn_update_table(smu, 1533 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1534 (void *)(&activity_monitor_external), true); 1535 if (ret) { 1536 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1537 return ret; 1538 } 1539 } 1540 1541 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1542 workload_type = smu_cmn_to_asic_specific_index(smu, 1543 CMN2ASIC_MAPPING_WORKLOAD, 1544 smu->power_profile_mode); 1545 if (workload_type < 0) 1546 return -EINVAL; 1547 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1548 1 << workload_type, NULL); 1549 1550 return ret; 1551 } 1552 1553 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu, 1554 enum pp_mp1_state mp1_state) 1555 { 1556 int ret; 1557 1558 switch (mp1_state) { 1559 case PP_MP1_STATE_UNLOAD: 1560 ret = smu_cmn_set_mp1_state(smu, mp1_state); 1561 break; 1562 default: 1563 /* Ignore others */ 1564 ret = 0; 1565 } 1566 1567 return ret; 1568 } 1569 1570 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu) 1571 { 1572 struct amdgpu_device *adev = smu->adev; 1573 1574 /* SRIOV does not support SMU mode1 reset */ 1575 if (amdgpu_sriov_vf(adev)) 1576 return false; 1577 1578 return true; 1579 } 1580 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { 1581 .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, 1582 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, 1583 .is_dpm_running = smu_v13_0_7_is_dpm_running, 1584 .dump_pptable = smu_v13_0_7_dump_pptable, 1585 .init_microcode = smu_v13_0_init_microcode, 1586 .load_microcode = smu_v13_0_load_microcode, 1587 .fini_microcode = smu_v13_0_fini_microcode, 1588 .init_smc_tables = smu_v13_0_7_init_smc_tables, 1589 .fini_smc_tables = smu_v13_0_fini_smc_tables, 1590 .init_power = smu_v13_0_init_power, 1591 .fini_power = smu_v13_0_fini_power, 1592 .check_fw_status = smu_v13_0_7_check_fw_status, 1593 .setup_pptable = smu_v13_0_7_setup_pptable, 1594 .check_fw_version = smu_v13_0_check_fw_version, 1595 .write_pptable = smu_cmn_write_pptable, 1596 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1597 .system_features_control = smu_v13_0_system_features_control, 1598 .set_allowed_mask = smu_v13_0_set_allowed_mask, 1599 .get_enabled_mask = smu_cmn_get_enabled_mask, 1600 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 1601 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 1602 .init_pptable_microcode = smu_v13_0_init_pptable_microcode, 1603 .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk, 1604 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 1605 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1606 .read_sensor = smu_v13_0_7_read_sensor, 1607 .feature_is_enabled = smu_cmn_feature_is_enabled, 1608 .print_clk_levels = smu_v13_0_7_print_clk_levels, 1609 .force_clk_levels = smu_v13_0_7_force_clk_levels, 1610 .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters, 1611 .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range, 1612 .register_irq_handler = smu_v13_0_register_irq_handler, 1613 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 1614 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 1615 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 1616 .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics, 1617 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, 1618 .set_performance_level = smu_v13_0_set_performance_level, 1619 .gfx_off_control = smu_v13_0_gfx_off_control, 1620 .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm, 1621 .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm, 1622 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, 1623 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm, 1624 .get_fan_control_mode = smu_v13_0_get_fan_control_mode, 1625 .set_fan_control_mode = smu_v13_0_set_fan_control_mode, 1626 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost, 1627 .get_power_limit = smu_v13_0_7_get_power_limit, 1628 .set_power_limit = smu_v13_0_set_power_limit, 1629 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode, 1630 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode, 1631 .set_tool_table_location = smu_v13_0_set_tool_table_location, 1632 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1633 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1634 .baco_is_support = smu_v13_0_baco_is_support, 1635 .baco_get_state = smu_v13_0_baco_get_state, 1636 .baco_set_state = smu_v13_0_baco_set_state, 1637 .baco_enter = smu_v13_0_baco_enter, 1638 .baco_exit = smu_v13_0_baco_exit, 1639 .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported, 1640 .mode1_reset = smu_v13_0_mode1_reset, 1641 .set_mp1_state = smu_v13_0_7_set_mp1_state, 1642 }; 1643 1644 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) 1645 { 1646 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs; 1647 smu->message_map = smu_v13_0_7_message_map; 1648 smu->clock_map = smu_v13_0_7_clk_map; 1649 smu->feature_map = smu_v13_0_7_feature_mask_map; 1650 smu->table_map = smu_v13_0_7_table_map; 1651 smu->pwr_src_map = smu_v13_0_7_pwr_src_map; 1652 smu->workload_map = smu_v13_0_7_workload_map; 1653 smu_v13_0_set_smu_mailbox_registers(smu); 1654 } 1655