1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v13_0.h" 35 #include "smu13_driver_if_v13_0_7.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "smu_v13_0_7_ppt.h" 39 #include "smu_v13_0_7_pptable.h" 40 #include "smu_v13_0_7_ppsmc.h" 41 #include "nbio/nbio_4_3_0_offset.h" 42 #include "nbio/nbio_4_3_0_sh_mask.h" 43 #include "mp/mp_13_0_0_offset.h" 44 #include "mp/mp_13_0_0_sh_mask.h" 45 46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "amdgpu_ras.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 70 71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028 72 73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 74 75 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = { 76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 79 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 80 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 81 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 82 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 83 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 84 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 85 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 86 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 89 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 98 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 100 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 108 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 109 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 110 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 111 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 112 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 113 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 114 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 115 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0), 116 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 117 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 118 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 119 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 120 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 121 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 122 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 123 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 124 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), 125 }; 126 127 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = { 128 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 129 CLK_MAP(SCLK, PPCLK_GFXCLK), 130 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 131 CLK_MAP(FCLK, PPCLK_FCLK), 132 CLK_MAP(UCLK, PPCLK_UCLK), 133 CLK_MAP(MCLK, PPCLK_UCLK), 134 CLK_MAP(VCLK, PPCLK_VCLK_0), 135 CLK_MAP(VCLK1, PPCLK_VCLK_1), 136 CLK_MAP(DCLK, PPCLK_DCLK_0), 137 CLK_MAP(DCLK1, PPCLK_DCLK_1), 138 }; 139 140 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = { 141 FEA_MAP(FW_DATA_READ), 142 FEA_MAP(DPM_GFXCLK), 143 FEA_MAP(DPM_GFX_POWER_OPTIMIZER), 144 FEA_MAP(DPM_UCLK), 145 FEA_MAP(DPM_FCLK), 146 FEA_MAP(DPM_SOCCLK), 147 FEA_MAP(DPM_MP0CLK), 148 FEA_MAP(DPM_LINK), 149 FEA_MAP(DPM_DCN), 150 FEA_MAP(VMEMP_SCALING), 151 FEA_MAP(VDDIO_MEM_SCALING), 152 FEA_MAP(DS_GFXCLK), 153 FEA_MAP(DS_SOCCLK), 154 FEA_MAP(DS_FCLK), 155 FEA_MAP(DS_LCLK), 156 FEA_MAP(DS_DCFCLK), 157 FEA_MAP(DS_UCLK), 158 FEA_MAP(GFX_ULV), 159 FEA_MAP(FW_DSTATE), 160 FEA_MAP(GFXOFF), 161 FEA_MAP(BACO), 162 FEA_MAP(MM_DPM), 163 FEA_MAP(SOC_MPCLK_DS), 164 FEA_MAP(BACO_MPCLK_DS), 165 FEA_MAP(THROTTLERS), 166 FEA_MAP(SMARTSHIFT), 167 FEA_MAP(GTHR), 168 FEA_MAP(ACDC), 169 FEA_MAP(VR0HOT), 170 FEA_MAP(FW_CTF), 171 FEA_MAP(FAN_CONTROL), 172 FEA_MAP(GFX_DCS), 173 FEA_MAP(GFX_READ_MARGIN), 174 FEA_MAP(LED_DISPLAY), 175 FEA_MAP(GFXCLK_SPREAD_SPECTRUM), 176 FEA_MAP(OUT_OF_BAND_MONITOR), 177 FEA_MAP(OPTIMIZED_VMIN), 178 FEA_MAP(GFX_IMU), 179 FEA_MAP(BOOT_TIME_CAL), 180 FEA_MAP(GFX_PCC_DFLL), 181 FEA_MAP(SOC_CG), 182 FEA_MAP(DF_CSTATE), 183 FEA_MAP(GFX_EDC), 184 FEA_MAP(BOOT_POWER_OPT), 185 FEA_MAP(CLOCK_POWER_DOWN_BYPASS), 186 FEA_MAP(DS_VCN), 187 FEA_MAP(BACO_CG), 188 FEA_MAP(MEM_TEMP_READ), 189 FEA_MAP(ATHUB_MMHUB_PG), 190 FEA_MAP(SOC_PCC), 191 }; 192 193 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = { 194 TAB_MAP(PPTABLE), 195 TAB_MAP(WATERMARKS), 196 TAB_MAP(AVFS_PSM_DEBUG), 197 TAB_MAP(PMSTATUSLOG), 198 TAB_MAP(SMU_METRICS), 199 TAB_MAP(DRIVER_SMU_CONFIG), 200 TAB_MAP(ACTIVITY_MONITOR_COEFF), 201 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE}, 202 }; 203 204 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 205 PWR_MAP(AC), 206 PWR_MAP(DC), 207 }; 208 209 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 212 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 213 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 214 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 215 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 216 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT), 218 }; 219 220 static const uint8_t smu_v13_0_7_throttler_map[] = { 221 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 222 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 223 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 224 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 225 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 226 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 227 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 228 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 229 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 230 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 231 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 232 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 233 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 234 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 235 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 236 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT), 237 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 238 }; 239 240 static int 241 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, 242 uint32_t *feature_mask, uint32_t num) 243 { 244 struct amdgpu_device *adev = smu->adev; 245 246 if (num > 2) 247 return -EINVAL; 248 249 memset(feature_mask, 0, sizeof(uint32_t) * num); 250 251 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); 252 253 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 254 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 255 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); 256 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); 257 } 258 259 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 260 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 261 262 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { 263 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 264 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); 265 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 266 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 267 } 268 269 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 270 271 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 272 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 273 274 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 275 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 276 277 if (adev->pm.pp_feature & PP_ULV_MASK) 278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 279 280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); 282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); 283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); 284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT); 286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT); 287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); 289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT); 290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); 292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); 293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); 294 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT); 295 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT); 297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); 298 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); 299 300 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 301 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); 302 303 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) && 304 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 305 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 306 307 return 0; 308 } 309 310 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu) 311 { 312 struct smu_table_context *table_context = &smu->smu_table; 313 struct smu_13_0_7_powerplay_table *powerplay_table = 314 table_context->power_play_table; 315 struct smu_baco_context *smu_baco = &smu->smu_baco; 316 PPTable_t *smc_pptable = table_context->driver_pptable; 317 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 318 319 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC) 320 smu->dc_controlled_by_gpio = true; 321 322 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO || 323 powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) 324 smu_baco->platform_support = true; 325 326 if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) 327 smu_baco->maco_support = true; 328 329 table_context->thermal_controller_type = 330 powerplay_table->thermal_controller_type; 331 332 /* 333 * Instead of having its own buffer space and get overdrive_table copied, 334 * smu->od_settings just points to the actual overdrive_table 335 */ 336 smu->od_settings = &powerplay_table->overdrive_table; 337 338 return 0; 339 } 340 341 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu) 342 { 343 struct smu_table_context *table_context = &smu->smu_table; 344 struct smu_13_0_7_powerplay_table *powerplay_table = 345 table_context->power_play_table; 346 struct amdgpu_device *adev = smu->adev; 347 348 if (adev->pdev->device == 0x51) 349 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080; 350 351 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 352 sizeof(PPTable_t)); 353 354 return 0; 355 } 356 357 static int smu_v13_0_7_check_fw_status(struct smu_context *smu) 358 { 359 struct amdgpu_device *adev = smu->adev; 360 uint32_t mp1_fw_flags; 361 362 mp1_fw_flags = RREG32_PCIE(MP1_Public | 363 (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff)); 364 365 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 366 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 367 return 0; 368 369 return -EIO; 370 } 371 372 #ifndef atom_smc_dpm_info_table_13_0_7 373 struct atom_smc_dpm_info_table_13_0_7 374 { 375 struct atom_common_table_header table_header; 376 BoardTable_t BoardTable; 377 }; 378 #endif 379 380 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu) 381 { 382 struct smu_table_context *table_context = &smu->smu_table; 383 384 PPTable_t *smc_pptable = table_context->driver_pptable; 385 386 struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table; 387 388 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 389 390 int index, ret; 391 392 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 393 smc_dpm_info); 394 395 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 396 (uint8_t **)&smc_dpm_table); 397 if (ret) 398 return ret; 399 400 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 401 402 return 0; 403 } 404 405 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu, 406 void **table, 407 uint32_t *size) 408 { 409 struct smu_table_context *smu_table = &smu->smu_table; 410 void *combo_pptable = smu_table->combo_pptable; 411 int ret = 0; 412 413 ret = smu_cmn_get_combo_pptable(smu); 414 if (ret) 415 return ret; 416 417 *table = combo_pptable; 418 *size = sizeof(struct smu_13_0_7_powerplay_table); 419 420 return 0; 421 } 422 423 static int smu_v13_0_7_setup_pptable(struct smu_context *smu) 424 { 425 struct smu_table_context *smu_table = &smu->smu_table; 426 struct amdgpu_device *adev = smu->adev; 427 int ret = 0; 428 429 /* 430 * With SCPM enabled, the pptable used will be signed. It cannot 431 * be used directly by driver. To get the raw pptable, we need to 432 * rely on the combo pptable(and its revelant SMU message). 433 */ 434 ret = smu_v13_0_7_get_pptable_from_pmfw(smu, 435 &smu_table->power_play_table, 436 &smu_table->power_play_table_size); 437 if (ret) 438 return ret; 439 440 ret = smu_v13_0_7_store_powerplay_table(smu); 441 if (ret) 442 return ret; 443 444 /* 445 * With SCPM enabled, the operation below will be handled 446 * by PSP. Driver involvment is unnecessary and useless. 447 */ 448 if (!adev->scpm_enabled) { 449 ret = smu_v13_0_7_append_powerplay_table(smu); 450 if (ret) 451 return ret; 452 } 453 454 ret = smu_v13_0_7_check_powerplay_table(smu); 455 if (ret) 456 return ret; 457 458 return ret; 459 } 460 461 static int smu_v13_0_7_tables_init(struct smu_context *smu) 462 { 463 struct smu_table_context *smu_table = &smu->smu_table; 464 struct smu_table *tables = smu_table->tables; 465 466 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 467 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 468 469 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 470 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 471 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 472 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 473 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 474 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 475 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 476 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 477 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 478 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 479 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 480 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 481 AMDGPU_GEM_DOMAIN_VRAM); 482 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE, 483 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 484 485 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 486 if (!smu_table->metrics_table) 487 goto err0_out; 488 smu_table->metrics_time = 0; 489 490 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 491 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 492 if (!smu_table->gpu_metrics_table) 493 goto err1_out; 494 495 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 496 if (!smu_table->watermarks_table) 497 goto err2_out; 498 499 return 0; 500 501 err2_out: 502 kfree(smu_table->gpu_metrics_table); 503 err1_out: 504 kfree(smu_table->metrics_table); 505 err0_out: 506 return -ENOMEM; 507 } 508 509 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu) 510 { 511 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 512 513 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 514 GFP_KERNEL); 515 if (!smu_dpm->dpm_context) 516 return -ENOMEM; 517 518 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 519 520 return 0; 521 } 522 523 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu) 524 { 525 int ret = 0; 526 527 ret = smu_v13_0_7_tables_init(smu); 528 if (ret) 529 return ret; 530 531 ret = smu_v13_0_7_allocate_dpm_context(smu); 532 if (ret) 533 return ret; 534 535 return smu_v13_0_init_smc_tables(smu); 536 } 537 538 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) 539 { 540 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 541 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 542 SkuTable_t *skutable = &driver_ppt->SkuTable; 543 struct smu_13_0_dpm_table *dpm_table; 544 struct smu_13_0_pcie_table *pcie_table; 545 uint32_t link_level; 546 int ret = 0; 547 548 /* socclk dpm table setup */ 549 dpm_table = &dpm_context->dpm_tables.soc_table; 550 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 551 ret = smu_v13_0_set_single_dpm_table(smu, 552 SMU_SOCCLK, 553 dpm_table); 554 if (ret) 555 return ret; 556 } else { 557 dpm_table->count = 1; 558 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 559 dpm_table->dpm_levels[0].enabled = true; 560 dpm_table->min = dpm_table->dpm_levels[0].value; 561 dpm_table->max = dpm_table->dpm_levels[0].value; 562 } 563 564 /* gfxclk dpm table setup */ 565 dpm_table = &dpm_context->dpm_tables.gfx_table; 566 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 567 ret = smu_v13_0_set_single_dpm_table(smu, 568 SMU_GFXCLK, 569 dpm_table); 570 if (ret) 571 return ret; 572 } else { 573 dpm_table->count = 1; 574 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 575 dpm_table->dpm_levels[0].enabled = true; 576 dpm_table->min = dpm_table->dpm_levels[0].value; 577 dpm_table->max = dpm_table->dpm_levels[0].value; 578 } 579 580 /* uclk dpm table setup */ 581 dpm_table = &dpm_context->dpm_tables.uclk_table; 582 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 583 ret = smu_v13_0_set_single_dpm_table(smu, 584 SMU_UCLK, 585 dpm_table); 586 if (ret) 587 return ret; 588 } else { 589 dpm_table->count = 1; 590 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 591 dpm_table->dpm_levels[0].enabled = true; 592 dpm_table->min = dpm_table->dpm_levels[0].value; 593 dpm_table->max = dpm_table->dpm_levels[0].value; 594 } 595 596 /* fclk dpm table setup */ 597 dpm_table = &dpm_context->dpm_tables.fclk_table; 598 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 599 ret = smu_v13_0_set_single_dpm_table(smu, 600 SMU_FCLK, 601 dpm_table); 602 if (ret) 603 return ret; 604 } else { 605 dpm_table->count = 1; 606 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 607 dpm_table->dpm_levels[0].enabled = true; 608 dpm_table->min = dpm_table->dpm_levels[0].value; 609 dpm_table->max = dpm_table->dpm_levels[0].value; 610 } 611 612 /* vclk dpm table setup */ 613 dpm_table = &dpm_context->dpm_tables.vclk_table; 614 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { 615 ret = smu_v13_0_set_single_dpm_table(smu, 616 SMU_VCLK, 617 dpm_table); 618 if (ret) 619 return ret; 620 } else { 621 dpm_table->count = 1; 622 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 623 dpm_table->dpm_levels[0].enabled = true; 624 dpm_table->min = dpm_table->dpm_levels[0].value; 625 dpm_table->max = dpm_table->dpm_levels[0].value; 626 } 627 628 /* dclk dpm table setup */ 629 dpm_table = &dpm_context->dpm_tables.dclk_table; 630 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { 631 ret = smu_v13_0_set_single_dpm_table(smu, 632 SMU_DCLK, 633 dpm_table); 634 if (ret) 635 return ret; 636 } else { 637 dpm_table->count = 1; 638 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 639 dpm_table->dpm_levels[0].enabled = true; 640 dpm_table->min = dpm_table->dpm_levels[0].value; 641 dpm_table->max = dpm_table->dpm_levels[0].value; 642 } 643 644 /* lclk dpm table setup */ 645 pcie_table = &dpm_context->dpm_tables.pcie_table; 646 pcie_table->num_of_link_levels = 0; 647 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { 648 if (!skutable->PcieGenSpeed[link_level] && 649 !skutable->PcieLaneCount[link_level] && 650 !skutable->LclkFreq[link_level]) 651 continue; 652 653 pcie_table->pcie_gen[pcie_table->num_of_link_levels] = 654 skutable->PcieGenSpeed[link_level]; 655 pcie_table->pcie_lane[pcie_table->num_of_link_levels] = 656 skutable->PcieLaneCount[link_level]; 657 pcie_table->clk_freq[pcie_table->num_of_link_levels] = 658 skutable->LclkFreq[link_level]; 659 pcie_table->num_of_link_levels++; 660 } 661 662 return 0; 663 } 664 665 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu) 666 { 667 int ret = 0; 668 uint64_t feature_enabled; 669 670 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 671 if (ret) 672 return false; 673 674 return !!(feature_enabled & SMC_DPM_FEATURE); 675 } 676 677 static void smu_v13_0_7_dump_pptable(struct smu_context *smu) 678 { 679 struct smu_table_context *table_context = &smu->smu_table; 680 PPTable_t *pptable = table_context->driver_pptable; 681 SkuTable_t *skutable = &pptable->SkuTable; 682 683 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 684 685 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version); 686 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]); 687 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]); 688 } 689 690 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics) 691 { 692 uint32_t throttler_status = 0; 693 int i; 694 695 for (i = 0; i < THROTTLER_COUNT; i++) 696 throttler_status |= 697 (metrics->ThrottlingPercentage[i] ? 1U << i : 0); 698 699 return throttler_status; 700 } 701 702 #define SMU_13_0_7_BUSY_THRESHOLD 15 703 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu, 704 MetricsMember_t member, 705 uint32_t *value) 706 { 707 struct smu_table_context *smu_table= &smu->smu_table; 708 SmuMetrics_t *metrics = 709 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 710 int ret = 0; 711 712 ret = smu_cmn_get_metrics_table(smu, 713 NULL, 714 false); 715 if (ret) 716 return ret; 717 718 switch (member) { 719 case METRICS_CURR_GFXCLK: 720 *value = metrics->CurrClock[PPCLK_GFXCLK]; 721 break; 722 case METRICS_CURR_SOCCLK: 723 *value = metrics->CurrClock[PPCLK_SOCCLK]; 724 break; 725 case METRICS_CURR_UCLK: 726 *value = metrics->CurrClock[PPCLK_UCLK]; 727 break; 728 case METRICS_CURR_VCLK: 729 *value = metrics->CurrClock[PPCLK_VCLK_0]; 730 break; 731 case METRICS_CURR_VCLK1: 732 *value = metrics->CurrClock[PPCLK_VCLK_1]; 733 break; 734 case METRICS_CURR_DCLK: 735 *value = metrics->CurrClock[PPCLK_DCLK_0]; 736 break; 737 case METRICS_CURR_DCLK1: 738 *value = metrics->CurrClock[PPCLK_DCLK_1]; 739 break; 740 case METRICS_CURR_FCLK: 741 *value = metrics->CurrClock[PPCLK_FCLK]; 742 break; 743 case METRICS_AVERAGE_GFXCLK: 744 *value = metrics->AverageGfxclkFrequencyPreDs; 745 break; 746 case METRICS_AVERAGE_FCLK: 747 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 748 *value = metrics->AverageFclkFrequencyPostDs; 749 else 750 *value = metrics->AverageFclkFrequencyPreDs; 751 break; 752 case METRICS_AVERAGE_UCLK: 753 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 754 *value = metrics->AverageMemclkFrequencyPostDs; 755 else 756 *value = metrics->AverageMemclkFrequencyPreDs; 757 break; 758 case METRICS_AVERAGE_VCLK: 759 *value = metrics->AverageVclk0Frequency; 760 break; 761 case METRICS_AVERAGE_DCLK: 762 *value = metrics->AverageDclk0Frequency; 763 break; 764 case METRICS_AVERAGE_VCLK1: 765 *value = metrics->AverageVclk1Frequency; 766 break; 767 case METRICS_AVERAGE_DCLK1: 768 *value = metrics->AverageDclk1Frequency; 769 break; 770 case METRICS_AVERAGE_GFXACTIVITY: 771 *value = metrics->AverageGfxActivity; 772 break; 773 case METRICS_AVERAGE_MEMACTIVITY: 774 *value = metrics->AverageUclkActivity; 775 break; 776 case METRICS_AVERAGE_SOCKETPOWER: 777 *value = metrics->AverageSocketPower << 8; 778 break; 779 case METRICS_TEMPERATURE_EDGE: 780 *value = metrics->AvgTemperature[TEMP_EDGE] * 781 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 782 break; 783 case METRICS_TEMPERATURE_HOTSPOT: 784 *value = metrics->AvgTemperature[TEMP_HOTSPOT] * 785 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 786 break; 787 case METRICS_TEMPERATURE_MEM: 788 *value = metrics->AvgTemperature[TEMP_MEM] * 789 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 790 break; 791 case METRICS_TEMPERATURE_VRGFX: 792 *value = metrics->AvgTemperature[TEMP_VR_GFX] * 793 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 794 break; 795 case METRICS_TEMPERATURE_VRSOC: 796 *value = metrics->AvgTemperature[TEMP_VR_SOC] * 797 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 798 break; 799 case METRICS_THROTTLER_STATUS: 800 *value = smu_v13_0_7_get_throttler_status(metrics); 801 break; 802 case METRICS_CURR_FANSPEED: 803 *value = metrics->AvgFanRpm; 804 break; 805 case METRICS_CURR_FANPWM: 806 *value = metrics->AvgFanPwm; 807 break; 808 case METRICS_VOLTAGE_VDDGFX: 809 *value = metrics->AvgVoltage[SVI_PLANE_GFX]; 810 break; 811 case METRICS_PCIE_RATE: 812 *value = metrics->PcieRate; 813 break; 814 case METRICS_PCIE_WIDTH: 815 *value = metrics->PcieWidth; 816 break; 817 default: 818 *value = UINT_MAX; 819 break; 820 } 821 822 return ret; 823 } 824 825 static int smu_v13_0_7_read_sensor(struct smu_context *smu, 826 enum amd_pp_sensors sensor, 827 void *data, 828 uint32_t *size) 829 { 830 struct smu_table_context *table_context = &smu->smu_table; 831 PPTable_t *smc_pptable = table_context->driver_pptable; 832 int ret = 0; 833 834 switch (sensor) { 835 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 836 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm; 837 *size = 4; 838 break; 839 case AMDGPU_PP_SENSOR_MEM_LOAD: 840 ret = smu_v13_0_7_get_smu_metrics_data(smu, 841 METRICS_AVERAGE_MEMACTIVITY, 842 (uint32_t *)data); 843 *size = 4; 844 break; 845 case AMDGPU_PP_SENSOR_GPU_LOAD: 846 ret = smu_v13_0_7_get_smu_metrics_data(smu, 847 METRICS_AVERAGE_GFXACTIVITY, 848 (uint32_t *)data); 849 *size = 4; 850 break; 851 case AMDGPU_PP_SENSOR_GPU_POWER: 852 ret = smu_v13_0_7_get_smu_metrics_data(smu, 853 METRICS_AVERAGE_SOCKETPOWER, 854 (uint32_t *)data); 855 *size = 4; 856 break; 857 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 858 ret = smu_v13_0_7_get_smu_metrics_data(smu, 859 METRICS_TEMPERATURE_HOTSPOT, 860 (uint32_t *)data); 861 *size = 4; 862 break; 863 case AMDGPU_PP_SENSOR_EDGE_TEMP: 864 ret = smu_v13_0_7_get_smu_metrics_data(smu, 865 METRICS_TEMPERATURE_EDGE, 866 (uint32_t *)data); 867 *size = 4; 868 break; 869 case AMDGPU_PP_SENSOR_MEM_TEMP: 870 ret = smu_v13_0_7_get_smu_metrics_data(smu, 871 METRICS_TEMPERATURE_MEM, 872 (uint32_t *)data); 873 *size = 4; 874 break; 875 case AMDGPU_PP_SENSOR_GFX_MCLK: 876 ret = smu_v13_0_7_get_smu_metrics_data(smu, 877 METRICS_AVERAGE_UCLK, 878 (uint32_t *)data); 879 *(uint32_t *)data *= 100; 880 *size = 4; 881 break; 882 case AMDGPU_PP_SENSOR_GFX_SCLK: 883 ret = smu_v13_0_7_get_smu_metrics_data(smu, 884 METRICS_AVERAGE_GFXCLK, 885 (uint32_t *)data); 886 *(uint32_t *)data *= 100; 887 *size = 4; 888 break; 889 case AMDGPU_PP_SENSOR_VDDGFX: 890 ret = smu_v13_0_7_get_smu_metrics_data(smu, 891 METRICS_VOLTAGE_VDDGFX, 892 (uint32_t *)data); 893 *size = 4; 894 break; 895 default: 896 ret = -EOPNOTSUPP; 897 break; 898 } 899 900 return ret; 901 } 902 903 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu, 904 enum smu_clk_type clk_type, 905 uint32_t *value) 906 { 907 MetricsMember_t member_type; 908 int clk_id = 0; 909 910 clk_id = smu_cmn_to_asic_specific_index(smu, 911 CMN2ASIC_MAPPING_CLK, 912 clk_type); 913 if (clk_id < 0) 914 return -EINVAL; 915 916 switch (clk_id) { 917 case PPCLK_GFXCLK: 918 member_type = METRICS_AVERAGE_GFXCLK; 919 break; 920 case PPCLK_UCLK: 921 member_type = METRICS_CURR_UCLK; 922 break; 923 case PPCLK_FCLK: 924 member_type = METRICS_CURR_FCLK; 925 break; 926 case PPCLK_SOCCLK: 927 member_type = METRICS_CURR_SOCCLK; 928 break; 929 case PPCLK_VCLK_0: 930 member_type = METRICS_CURR_VCLK; 931 break; 932 case PPCLK_DCLK_0: 933 member_type = METRICS_CURR_DCLK; 934 break; 935 case PPCLK_VCLK_1: 936 member_type = METRICS_CURR_VCLK1; 937 break; 938 case PPCLK_DCLK_1: 939 member_type = METRICS_CURR_DCLK1; 940 break; 941 default: 942 return -EINVAL; 943 } 944 945 return smu_v13_0_7_get_smu_metrics_data(smu, 946 member_type, 947 value); 948 } 949 950 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, 951 enum smu_clk_type clk_type, 952 char *buf) 953 { 954 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 955 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 956 struct smu_13_0_dpm_table *single_dpm_table; 957 struct smu_13_0_pcie_table *pcie_table; 958 uint32_t gen_speed, lane_width; 959 int i, curr_freq, size = 0; 960 int ret = 0; 961 962 smu_cmn_get_sysfs_buf(&buf, &size); 963 964 if (amdgpu_ras_intr_triggered()) { 965 size += sysfs_emit_at(buf, size, "unavailable\n"); 966 return size; 967 } 968 969 switch (clk_type) { 970 case SMU_SCLK: 971 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 972 break; 973 case SMU_MCLK: 974 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 975 break; 976 case SMU_SOCCLK: 977 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 978 break; 979 case SMU_FCLK: 980 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 981 break; 982 case SMU_VCLK: 983 case SMU_VCLK1: 984 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 985 break; 986 case SMU_DCLK: 987 case SMU_DCLK1: 988 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 989 break; 990 default: 991 break; 992 } 993 994 switch (clk_type) { 995 case SMU_SCLK: 996 case SMU_MCLK: 997 case SMU_SOCCLK: 998 case SMU_FCLK: 999 case SMU_VCLK: 1000 case SMU_VCLK1: 1001 case SMU_DCLK: 1002 case SMU_DCLK1: 1003 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); 1004 if (ret) { 1005 dev_err(smu->adev->dev, "Failed to get current clock freq!"); 1006 return ret; 1007 } 1008 1009 if (single_dpm_table->is_fine_grained) { 1010 /* 1011 * For fine grained dpms, there are only two dpm levels: 1012 * - level 0 -> min clock freq 1013 * - level 1 -> max clock freq 1014 * And the current clock frequency can be any value between them. 1015 * So, if the current clock frequency is not at level 0 or level 1, 1016 * we will fake it as three dpm levels: 1017 * - level 0 -> min clock freq 1018 * - level 1 -> current actual clock freq 1019 * - level 2 -> max clock freq 1020 */ 1021 if ((single_dpm_table->dpm_levels[0].value != curr_freq) && 1022 (single_dpm_table->dpm_levels[1].value != curr_freq)) { 1023 size += sysfs_emit_at(buf, size, "0: %uMhz\n", 1024 single_dpm_table->dpm_levels[0].value); 1025 size += sysfs_emit_at(buf, size, "1: %uMhz *\n", 1026 curr_freq); 1027 size += sysfs_emit_at(buf, size, "2: %uMhz\n", 1028 single_dpm_table->dpm_levels[1].value); 1029 } else { 1030 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 1031 single_dpm_table->dpm_levels[0].value, 1032 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); 1033 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 1034 single_dpm_table->dpm_levels[1].value, 1035 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); 1036 } 1037 } else { 1038 for (i = 0; i < single_dpm_table->count; i++) 1039 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 1040 i, single_dpm_table->dpm_levels[i].value, 1041 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); 1042 } 1043 break; 1044 case SMU_PCIE: 1045 ret = smu_v13_0_7_get_smu_metrics_data(smu, 1046 METRICS_PCIE_RATE, 1047 &gen_speed); 1048 if (ret) 1049 return ret; 1050 1051 ret = smu_v13_0_7_get_smu_metrics_data(smu, 1052 METRICS_PCIE_WIDTH, 1053 &lane_width); 1054 if (ret) 1055 return ret; 1056 1057 pcie_table = &(dpm_context->dpm_tables.pcie_table); 1058 for (i = 0; i < pcie_table->num_of_link_levels; i++) 1059 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1060 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : 1061 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : 1062 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : 1063 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", 1064 (pcie_table->pcie_lane[i] == 1) ? "x1" : 1065 (pcie_table->pcie_lane[i] == 2) ? "x2" : 1066 (pcie_table->pcie_lane[i] == 3) ? "x4" : 1067 (pcie_table->pcie_lane[i] == 4) ? "x8" : 1068 (pcie_table->pcie_lane[i] == 5) ? "x12" : 1069 (pcie_table->pcie_lane[i] == 6) ? "x16" : "", 1070 pcie_table->clk_freq[i], 1071 (gen_speed == pcie_table->pcie_gen[i]) && 1072 (lane_width == pcie_table->pcie_lane[i]) ? 1073 "*" : ""); 1074 break; 1075 1076 default: 1077 break; 1078 } 1079 1080 return size; 1081 } 1082 1083 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu, 1084 enum smu_clk_type clk_type, 1085 uint32_t mask) 1086 { 1087 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1088 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1089 struct smu_13_0_dpm_table *single_dpm_table; 1090 uint32_t soft_min_level, soft_max_level; 1091 uint32_t min_freq, max_freq; 1092 int ret = 0; 1093 1094 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1095 soft_max_level = mask ? (fls(mask) - 1) : 0; 1096 1097 switch (clk_type) { 1098 case SMU_GFXCLK: 1099 case SMU_SCLK: 1100 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1101 break; 1102 case SMU_MCLK: 1103 case SMU_UCLK: 1104 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1105 break; 1106 case SMU_SOCCLK: 1107 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1108 break; 1109 case SMU_FCLK: 1110 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1111 break; 1112 case SMU_VCLK: 1113 case SMU_VCLK1: 1114 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1115 break; 1116 case SMU_DCLK: 1117 case SMU_DCLK1: 1118 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1119 break; 1120 default: 1121 break; 1122 } 1123 1124 switch (clk_type) { 1125 case SMU_GFXCLK: 1126 case SMU_SCLK: 1127 case SMU_MCLK: 1128 case SMU_UCLK: 1129 case SMU_SOCCLK: 1130 case SMU_FCLK: 1131 case SMU_VCLK: 1132 case SMU_VCLK1: 1133 case SMU_DCLK: 1134 case SMU_DCLK1: 1135 if (single_dpm_table->is_fine_grained) { 1136 /* There is only 2 levels for fine grained DPM */ 1137 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1138 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1139 } else { 1140 if ((soft_max_level >= single_dpm_table->count) || 1141 (soft_min_level >= single_dpm_table->count)) 1142 return -EINVAL; 1143 } 1144 1145 min_freq = single_dpm_table->dpm_levels[soft_min_level].value; 1146 max_freq = single_dpm_table->dpm_levels[soft_max_level].value; 1147 1148 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1149 clk_type, 1150 min_freq, 1151 max_freq); 1152 break; 1153 case SMU_DCEFCLK: 1154 case SMU_PCIE: 1155 default: 1156 break; 1157 } 1158 1159 return ret; 1160 } 1161 1162 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, 1163 uint32_t pcie_gen_cap, 1164 uint32_t pcie_width_cap) 1165 { 1166 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1167 struct smu_13_0_pcie_table *pcie_table = 1168 &dpm_context->dpm_tables.pcie_table; 1169 uint32_t smu_pcie_arg; 1170 int ret, i; 1171 1172 for (i = 0; i < pcie_table->num_of_link_levels; i++) { 1173 if (pcie_table->pcie_gen[i] > pcie_gen_cap) 1174 pcie_table->pcie_gen[i] = pcie_gen_cap; 1175 if (pcie_table->pcie_lane[i] > pcie_width_cap) 1176 pcie_table->pcie_lane[i] = pcie_width_cap; 1177 1178 smu_pcie_arg = i << 16; 1179 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8; 1180 smu_pcie_arg |= pcie_table->pcie_lane[i]; 1181 1182 ret = smu_cmn_send_smc_msg_with_param(smu, 1183 SMU_MSG_OverridePcieParameters, 1184 smu_pcie_arg, 1185 NULL); 1186 if (ret) 1187 return ret; 1188 } 1189 1190 return 0; 1191 } 1192 1193 static const struct smu_temperature_range smu13_thermal_policy[] = 1194 { 1195 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 1196 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 1197 }; 1198 1199 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu, 1200 struct smu_temperature_range *range) 1201 { 1202 struct smu_table_context *table_context = &smu->smu_table; 1203 struct smu_13_0_7_powerplay_table *powerplay_table = 1204 table_context->power_play_table; 1205 PPTable_t *pptable = smu->smu_table.driver_pptable; 1206 1207 if (!range) 1208 return -EINVAL; 1209 1210 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1211 1212 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] * 1213 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1214 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1215 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1216 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] * 1217 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1218 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1219 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1220 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] * 1221 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1222 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1223 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1224 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1225 1226 return 0; 1227 } 1228 1229 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 1230 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu, 1231 void **table) 1232 { 1233 struct smu_table_context *smu_table = &smu->smu_table; 1234 struct gpu_metrics_v1_3 *gpu_metrics = 1235 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1236 SmuMetricsExternal_t metrics_ext; 1237 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 1238 int ret = 0; 1239 1240 ret = smu_cmn_get_metrics_table(smu, 1241 &metrics_ext, 1242 true); 1243 if (ret) 1244 return ret; 1245 1246 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1247 1248 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE]; 1249 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT]; 1250 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM]; 1251 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX]; 1252 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC]; 1253 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0], 1254 metrics->AvgTemperature[TEMP_VR_MEM1]); 1255 1256 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 1257 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 1258 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage, 1259 metrics->Vcn1ActivityPercentage); 1260 1261 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 1262 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 1263 1264 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD) 1265 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 1266 else 1267 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 1268 1269 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 1270 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 1271 else 1272 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs; 1273 1274 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 1275 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 1276 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 1277 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 1278 1279 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; 1280 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 1281 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 1282 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 1283 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 1284 1285 gpu_metrics->throttle_status = 1286 smu_v13_0_7_get_throttler_status(metrics); 1287 gpu_metrics->indep_throttle_status = 1288 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 1289 smu_v13_0_7_throttler_map); 1290 1291 gpu_metrics->current_fan_speed = metrics->AvgFanRpm; 1292 1293 gpu_metrics->pcie_link_width = metrics->PcieWidth; 1294 gpu_metrics->pcie_link_speed = metrics->PcieRate; 1295 1296 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1297 1298 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX]; 1299 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC]; 1300 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP]; 1301 1302 *table = (void *)gpu_metrics; 1303 1304 return sizeof(struct gpu_metrics_v1_3); 1305 } 1306 1307 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu) 1308 { 1309 struct smu_13_0_dpm_context *dpm_context = 1310 smu->smu_dpm.dpm_context; 1311 struct smu_13_0_dpm_table *gfx_table = 1312 &dpm_context->dpm_tables.gfx_table; 1313 struct smu_13_0_dpm_table *mem_table = 1314 &dpm_context->dpm_tables.uclk_table; 1315 struct smu_13_0_dpm_table *soc_table = 1316 &dpm_context->dpm_tables.soc_table; 1317 struct smu_13_0_dpm_table *vclk_table = 1318 &dpm_context->dpm_tables.vclk_table; 1319 struct smu_13_0_dpm_table *dclk_table = 1320 &dpm_context->dpm_tables.dclk_table; 1321 struct smu_13_0_dpm_table *fclk_table = 1322 &dpm_context->dpm_tables.fclk_table; 1323 struct smu_umd_pstate_table *pstate_table = 1324 &smu->pstate_table; 1325 1326 pstate_table->gfxclk_pstate.min = gfx_table->min; 1327 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1328 1329 pstate_table->uclk_pstate.min = mem_table->min; 1330 pstate_table->uclk_pstate.peak = mem_table->max; 1331 1332 pstate_table->socclk_pstate.min = soc_table->min; 1333 pstate_table->socclk_pstate.peak = soc_table->max; 1334 1335 pstate_table->vclk_pstate.min = vclk_table->min; 1336 pstate_table->vclk_pstate.peak = vclk_table->max; 1337 1338 pstate_table->dclk_pstate.min = dclk_table->min; 1339 pstate_table->dclk_pstate.peak = dclk_table->max; 1340 1341 pstate_table->fclk_pstate.min = fclk_table->min; 1342 pstate_table->fclk_pstate.peak = fclk_table->max; 1343 1344 /* 1345 * For now, just use the mininum clock frequency. 1346 * TODO: update them when the real pstate settings available 1347 */ 1348 pstate_table->gfxclk_pstate.standard = gfx_table->min; 1349 pstate_table->uclk_pstate.standard = mem_table->min; 1350 pstate_table->socclk_pstate.standard = soc_table->min; 1351 pstate_table->vclk_pstate.standard = vclk_table->min; 1352 pstate_table->dclk_pstate.standard = dclk_table->min; 1353 pstate_table->fclk_pstate.standard = fclk_table->min; 1354 1355 return 0; 1356 } 1357 1358 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu, 1359 uint32_t *speed) 1360 { 1361 if (!speed) 1362 return -EINVAL; 1363 1364 return smu_v13_0_7_get_smu_metrics_data(smu, 1365 METRICS_CURR_FANPWM, 1366 speed); 1367 } 1368 1369 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu, 1370 uint32_t *speed) 1371 { 1372 if (!speed) 1373 return -EINVAL; 1374 1375 return smu_v13_0_7_get_smu_metrics_data(smu, 1376 METRICS_CURR_FANSPEED, 1377 speed); 1378 } 1379 1380 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu) 1381 { 1382 struct smu_table_context *table_context = &smu->smu_table; 1383 PPTable_t *pptable = table_context->driver_pptable; 1384 SkuTable_t *skutable = &pptable->SkuTable; 1385 1386 /* 1387 * Skip the MGpuFanBoost setting for those ASICs 1388 * which do not support it 1389 */ 1390 if (skutable->MGpuAcousticLimitRpmThreshold == 0) 1391 return 0; 1392 1393 return smu_cmn_send_smc_msg_with_param(smu, 1394 SMU_MSG_SetMGpuFanBoostLimitRpm, 1395 0, 1396 NULL); 1397 } 1398 1399 static int smu_v13_0_7_get_power_limit(struct smu_context *smu, 1400 uint32_t *current_power_limit, 1401 uint32_t *default_power_limit, 1402 uint32_t *max_power_limit) 1403 { 1404 struct smu_table_context *table_context = &smu->smu_table; 1405 struct smu_13_0_7_powerplay_table *powerplay_table = 1406 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table; 1407 PPTable_t *pptable = table_context->driver_pptable; 1408 SkuTable_t *skutable = &pptable->SkuTable; 1409 uint32_t power_limit, od_percent; 1410 1411 if (smu_v13_0_get_current_power_limit(smu, &power_limit)) 1412 power_limit = smu->adev->pm.ac_power ? 1413 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] : 1414 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0]; 1415 1416 if (current_power_limit) 1417 *current_power_limit = power_limit; 1418 if (default_power_limit) 1419 *default_power_limit = power_limit; 1420 1421 if (max_power_limit) { 1422 if (smu->od_enabled) { 1423 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]); 1424 1425 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1426 1427 power_limit *= (100 + od_percent); 1428 power_limit /= 100; 1429 } 1430 *max_power_limit = power_limit; 1431 } 1432 1433 return 0; 1434 } 1435 1436 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf) 1437 { 1438 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external[PP_SMC_POWER_PROFILE_COUNT]; 1439 uint32_t i, j, size = 0; 1440 int16_t workload_type = 0; 1441 int result = 0; 1442 1443 if (!buf) 1444 return -EINVAL; 1445 1446 size += sysfs_emit_at(buf, size, " "); 1447 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) 1448 size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i], 1449 (i == smu->power_profile_mode) ? "* " : " "); 1450 1451 size += sysfs_emit_at(buf, size, "\n"); 1452 1453 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) { 1454 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1455 workload_type = smu_cmn_to_asic_specific_index(smu, 1456 CMN2ASIC_MAPPING_WORKLOAD, 1457 i); 1458 if (workload_type < 0) 1459 return -EINVAL; 1460 1461 result = smu_cmn_update_table(smu, 1462 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1463 (void *)(&activity_monitor_external[i]), false); 1464 if (result) { 1465 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1466 return result; 1467 } 1468 } 1469 1470 #define PRINT_DPM_MONITOR(field) \ 1471 do { \ 1472 size += sysfs_emit_at(buf, size, "%-30s", #field); \ 1473 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \ 1474 size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \ 1475 size += sysfs_emit_at(buf, size, "\n"); \ 1476 } while (0) 1477 1478 PRINT_DPM_MONITOR(Gfx_ActiveHystLimit); 1479 PRINT_DPM_MONITOR(Gfx_IdleHystLimit); 1480 PRINT_DPM_MONITOR(Gfx_FPS); 1481 PRINT_DPM_MONITOR(Gfx_MinActiveFreqType); 1482 PRINT_DPM_MONITOR(Gfx_BoosterFreqType); 1483 PRINT_DPM_MONITOR(Gfx_MinActiveFreq); 1484 PRINT_DPM_MONITOR(Gfx_BoosterFreq); 1485 PRINT_DPM_MONITOR(Fclk_ActiveHystLimit); 1486 PRINT_DPM_MONITOR(Fclk_IdleHystLimit); 1487 PRINT_DPM_MONITOR(Fclk_FPS); 1488 PRINT_DPM_MONITOR(Fclk_MinActiveFreqType); 1489 PRINT_DPM_MONITOR(Fclk_BoosterFreqType); 1490 PRINT_DPM_MONITOR(Fclk_MinActiveFreq); 1491 PRINT_DPM_MONITOR(Fclk_BoosterFreq); 1492 #undef PRINT_DPM_MONITOR 1493 1494 return size; 1495 } 1496 1497 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1498 { 1499 1500 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1501 DpmActivityMonitorCoeffInt_t *activity_monitor = 1502 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1503 int workload_type, ret = 0; 1504 1505 smu->power_profile_mode = input[size]; 1506 1507 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) { 1508 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1509 return -EINVAL; 1510 } 1511 1512 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1513 1514 ret = smu_cmn_update_table(smu, 1515 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1516 (void *)(&activity_monitor_external), false); 1517 if (ret) { 1518 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1519 return ret; 1520 } 1521 1522 switch (input[0]) { 1523 case 0: /* Gfxclk */ 1524 activity_monitor->Gfx_ActiveHystLimit = input[1]; 1525 activity_monitor->Gfx_IdleHystLimit = input[2]; 1526 activity_monitor->Gfx_FPS = input[3]; 1527 activity_monitor->Gfx_MinActiveFreqType = input[4]; 1528 activity_monitor->Gfx_BoosterFreqType = input[5]; 1529 activity_monitor->Gfx_MinActiveFreq = input[6]; 1530 activity_monitor->Gfx_BoosterFreq = input[7]; 1531 break; 1532 case 1: /* Fclk */ 1533 activity_monitor->Fclk_ActiveHystLimit = input[1]; 1534 activity_monitor->Fclk_IdleHystLimit = input[2]; 1535 activity_monitor->Fclk_FPS = input[3]; 1536 activity_monitor->Fclk_MinActiveFreqType = input[4]; 1537 activity_monitor->Fclk_BoosterFreqType = input[5]; 1538 activity_monitor->Fclk_MinActiveFreq = input[6]; 1539 activity_monitor->Fclk_BoosterFreq = input[7]; 1540 break; 1541 } 1542 1543 ret = smu_cmn_update_table(smu, 1544 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1545 (void *)(&activity_monitor_external), true); 1546 if (ret) { 1547 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1548 return ret; 1549 } 1550 } 1551 1552 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1553 workload_type = smu_cmn_to_asic_specific_index(smu, 1554 CMN2ASIC_MAPPING_WORKLOAD, 1555 smu->power_profile_mode); 1556 if (workload_type < 0) 1557 return -EINVAL; 1558 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1559 1 << workload_type, NULL); 1560 1561 return ret; 1562 } 1563 1564 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu, 1565 enum pp_mp1_state mp1_state) 1566 { 1567 int ret; 1568 1569 switch (mp1_state) { 1570 case PP_MP1_STATE_UNLOAD: 1571 ret = smu_cmn_set_mp1_state(smu, mp1_state); 1572 break; 1573 default: 1574 /* Ignore others */ 1575 ret = 0; 1576 } 1577 1578 return ret; 1579 } 1580 1581 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu) 1582 { 1583 struct amdgpu_device *adev = smu->adev; 1584 1585 /* SRIOV does not support SMU mode1 reset */ 1586 if (amdgpu_sriov_vf(adev)) 1587 return false; 1588 1589 return true; 1590 } 1591 1592 static int smu_v13_0_7_set_df_cstate(struct smu_context *smu, 1593 enum pp_df_cstate state) 1594 { 1595 return smu_cmn_send_smc_msg_with_param(smu, 1596 SMU_MSG_DFCstateControl, 1597 state, 1598 NULL); 1599 } 1600 1601 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { 1602 .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, 1603 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, 1604 .is_dpm_running = smu_v13_0_7_is_dpm_running, 1605 .dump_pptable = smu_v13_0_7_dump_pptable, 1606 .init_microcode = smu_v13_0_init_microcode, 1607 .load_microcode = smu_v13_0_load_microcode, 1608 .fini_microcode = smu_v13_0_fini_microcode, 1609 .init_smc_tables = smu_v13_0_7_init_smc_tables, 1610 .fini_smc_tables = smu_v13_0_fini_smc_tables, 1611 .init_power = smu_v13_0_init_power, 1612 .fini_power = smu_v13_0_fini_power, 1613 .check_fw_status = smu_v13_0_7_check_fw_status, 1614 .setup_pptable = smu_v13_0_7_setup_pptable, 1615 .check_fw_version = smu_v13_0_check_fw_version, 1616 .write_pptable = smu_cmn_write_pptable, 1617 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1618 .system_features_control = smu_v13_0_system_features_control, 1619 .set_allowed_mask = smu_v13_0_set_allowed_mask, 1620 .get_enabled_mask = smu_cmn_get_enabled_mask, 1621 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 1622 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 1623 .init_pptable_microcode = smu_v13_0_init_pptable_microcode, 1624 .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk, 1625 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 1626 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1627 .read_sensor = smu_v13_0_7_read_sensor, 1628 .feature_is_enabled = smu_cmn_feature_is_enabled, 1629 .print_clk_levels = smu_v13_0_7_print_clk_levels, 1630 .force_clk_levels = smu_v13_0_7_force_clk_levels, 1631 .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters, 1632 .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range, 1633 .register_irq_handler = smu_v13_0_register_irq_handler, 1634 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 1635 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 1636 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 1637 .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics, 1638 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, 1639 .set_performance_level = smu_v13_0_set_performance_level, 1640 .gfx_off_control = smu_v13_0_gfx_off_control, 1641 .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm, 1642 .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm, 1643 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, 1644 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm, 1645 .get_fan_control_mode = smu_v13_0_get_fan_control_mode, 1646 .set_fan_control_mode = smu_v13_0_set_fan_control_mode, 1647 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost, 1648 .get_power_limit = smu_v13_0_7_get_power_limit, 1649 .set_power_limit = smu_v13_0_set_power_limit, 1650 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode, 1651 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode, 1652 .set_tool_table_location = smu_v13_0_set_tool_table_location, 1653 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1654 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1655 .baco_is_support = smu_v13_0_baco_is_support, 1656 .baco_get_state = smu_v13_0_baco_get_state, 1657 .baco_set_state = smu_v13_0_baco_set_state, 1658 .baco_enter = smu_v13_0_baco_enter, 1659 .baco_exit = smu_v13_0_baco_exit, 1660 .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported, 1661 .mode1_reset = smu_v13_0_mode1_reset, 1662 .set_mp1_state = smu_v13_0_7_set_mp1_state, 1663 .set_df_cstate = smu_v13_0_7_set_df_cstate, 1664 }; 1665 1666 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) 1667 { 1668 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs; 1669 smu->message_map = smu_v13_0_7_message_map; 1670 smu->clock_map = smu_v13_0_7_clk_map; 1671 smu->feature_map = smu_v13_0_7_feature_mask_map; 1672 smu->table_map = smu_v13_0_7_table_map; 1673 smu->pwr_src_map = smu_v13_0_7_pwr_src_map; 1674 smu->workload_map = smu_v13_0_7_workload_map; 1675 smu_v13_0_set_smu_mailbox_registers(smu); 1676 } 1677