1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v13_0.h" 35 #include "smu13_driver_if_v13_0_7.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "smu_v13_0_7_ppt.h" 39 #include "smu_v13_0_7_pptable.h" 40 #include "smu_v13_0_7_ppsmc.h" 41 #include "nbio/nbio_4_3_0_offset.h" 42 #include "nbio/nbio_4_3_0_sh_mask.h" 43 #include "mp/mp_13_0_0_offset.h" 44 #include "mp/mp_13_0_0_sh_mask.h" 45 46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "amdgpu_ras.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 70 71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028 72 73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 74 75 #define PP_OD_FEATURE_GFXCLK_FMIN 0 76 #define PP_OD_FEATURE_GFXCLK_FMAX 1 77 #define PP_OD_FEATURE_UCLK_FMIN 2 78 #define PP_OD_FEATURE_UCLK_FMAX 3 79 #define PP_OD_FEATURE_GFX_VF_CURVE 4 80 81 #define LINK_SPEED_MAX 3 82 83 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = { 84 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 85 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 86 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 87 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 88 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 89 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 90 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 91 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 92 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 93 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 94 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 95 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 96 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 97 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 98 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 99 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 100 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 101 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 102 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 103 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 104 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 105 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 106 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 107 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 108 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 109 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 110 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 111 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 112 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 113 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 114 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 115 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 116 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 117 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 118 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 119 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 120 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 121 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 122 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 123 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0), 124 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 125 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 126 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 127 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 128 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 129 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 130 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 131 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 132 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), 133 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 134 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0), 135 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 136 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 137 }; 138 139 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = { 140 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 141 CLK_MAP(SCLK, PPCLK_GFXCLK), 142 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 143 CLK_MAP(FCLK, PPCLK_FCLK), 144 CLK_MAP(UCLK, PPCLK_UCLK), 145 CLK_MAP(MCLK, PPCLK_UCLK), 146 CLK_MAP(VCLK, PPCLK_VCLK_0), 147 CLK_MAP(VCLK1, PPCLK_VCLK_1), 148 CLK_MAP(DCLK, PPCLK_DCLK_0), 149 CLK_MAP(DCLK1, PPCLK_DCLK_1), 150 }; 151 152 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = { 153 FEA_MAP(FW_DATA_READ), 154 FEA_MAP(DPM_GFXCLK), 155 FEA_MAP(DPM_GFX_POWER_OPTIMIZER), 156 FEA_MAP(DPM_UCLK), 157 FEA_MAP(DPM_FCLK), 158 FEA_MAP(DPM_SOCCLK), 159 FEA_MAP(DPM_MP0CLK), 160 FEA_MAP(DPM_LINK), 161 FEA_MAP(DPM_DCN), 162 FEA_MAP(VMEMP_SCALING), 163 FEA_MAP(VDDIO_MEM_SCALING), 164 FEA_MAP(DS_GFXCLK), 165 FEA_MAP(DS_SOCCLK), 166 FEA_MAP(DS_FCLK), 167 FEA_MAP(DS_LCLK), 168 FEA_MAP(DS_DCFCLK), 169 FEA_MAP(DS_UCLK), 170 FEA_MAP(GFX_ULV), 171 FEA_MAP(FW_DSTATE), 172 FEA_MAP(GFXOFF), 173 FEA_MAP(BACO), 174 FEA_MAP(MM_DPM), 175 FEA_MAP(SOC_MPCLK_DS), 176 FEA_MAP(BACO_MPCLK_DS), 177 FEA_MAP(THROTTLERS), 178 FEA_MAP(SMARTSHIFT), 179 FEA_MAP(GTHR), 180 FEA_MAP(ACDC), 181 FEA_MAP(VR0HOT), 182 FEA_MAP(FW_CTF), 183 FEA_MAP(FAN_CONTROL), 184 FEA_MAP(GFX_DCS), 185 FEA_MAP(GFX_READ_MARGIN), 186 FEA_MAP(LED_DISPLAY), 187 FEA_MAP(GFXCLK_SPREAD_SPECTRUM), 188 FEA_MAP(OUT_OF_BAND_MONITOR), 189 FEA_MAP(OPTIMIZED_VMIN), 190 FEA_MAP(GFX_IMU), 191 FEA_MAP(BOOT_TIME_CAL), 192 FEA_MAP(GFX_PCC_DFLL), 193 FEA_MAP(SOC_CG), 194 FEA_MAP(DF_CSTATE), 195 FEA_MAP(GFX_EDC), 196 FEA_MAP(BOOT_POWER_OPT), 197 FEA_MAP(CLOCK_POWER_DOWN_BYPASS), 198 FEA_MAP(DS_VCN), 199 FEA_MAP(BACO_CG), 200 FEA_MAP(MEM_TEMP_READ), 201 FEA_MAP(ATHUB_MMHUB_PG), 202 FEA_MAP(SOC_PCC), 203 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, 204 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, 205 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT}, 206 }; 207 208 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = { 209 TAB_MAP(PPTABLE), 210 TAB_MAP(WATERMARKS), 211 TAB_MAP(AVFS_PSM_DEBUG), 212 TAB_MAP(PMSTATUSLOG), 213 TAB_MAP(SMU_METRICS), 214 TAB_MAP(DRIVER_SMU_CONFIG), 215 TAB_MAP(ACTIVITY_MONITOR_COEFF), 216 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE}, 217 TAB_MAP(OVERDRIVE), 218 }; 219 220 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 221 PWR_MAP(AC), 222 PWR_MAP(DC), 223 }; 224 225 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 226 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 227 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 228 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 229 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 230 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT), 234 }; 235 236 static const uint8_t smu_v13_0_7_throttler_map[] = { 237 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 238 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 239 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 240 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 241 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 242 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 243 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 244 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 245 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 246 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 247 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 248 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 249 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 250 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 251 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 252 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT), 253 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 254 }; 255 256 static int 257 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, 258 uint32_t *feature_mask, uint32_t num) 259 { 260 struct amdgpu_device *adev = smu->adev; 261 262 if (num > 2) 263 return -EINVAL; 264 265 memset(feature_mask, 0, sizeof(uint32_t) * num); 266 267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); 268 269 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); 272 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); 273 } 274 275 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 277 278 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { 279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); 281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 283 } 284 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 286 287 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 289 290 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 292 293 if (adev->pm.pp_feature & PP_ULV_MASK) 294 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 295 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); 298 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); 299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); 300 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); 301 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT); 302 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT); 303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); 304 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); 305 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT); 306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); 308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); 309 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); 310 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT); 311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); 312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT); 313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); 315 316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); 318 319 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) && 320 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 322 323 return 0; 324 } 325 326 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu) 327 { 328 struct smu_table_context *table_context = &smu->smu_table; 329 struct smu_13_0_7_powerplay_table *powerplay_table = 330 table_context->power_play_table; 331 struct smu_baco_context *smu_baco = &smu->smu_baco; 332 PPTable_t *smc_pptable = table_context->driver_pptable; 333 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 334 #if 0 335 const OverDriveLimits_t * const overdrive_upperlimits = 336 &smc_pptable->SkuTable.OverDriveLimitsBasicMax; 337 const OverDriveLimits_t * const overdrive_lowerlimits = 338 &smc_pptable->SkuTable.OverDriveLimitsMin; 339 #endif 340 341 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC) 342 smu->dc_controlled_by_gpio = true; 343 344 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO || 345 powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) 346 smu_baco->platform_support = true; 347 348 if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) 349 smu_baco->maco_support = true; 350 351 #if 0 352 if (!overdrive_lowerlimits->FeatureCtrlMask || 353 !overdrive_upperlimits->FeatureCtrlMask) 354 smu->od_enabled = false; 355 356 /* 357 * Instead of having its own buffer space and get overdrive_table copied, 358 * smu->od_settings just points to the actual overdrive_table 359 */ 360 smu->od_settings = &powerplay_table->overdrive_table; 361 #else 362 smu->od_enabled = false; 363 #endif 364 365 table_context->thermal_controller_type = 366 powerplay_table->thermal_controller_type; 367 368 return 0; 369 } 370 371 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu) 372 { 373 struct smu_table_context *table_context = &smu->smu_table; 374 struct smu_13_0_7_powerplay_table *powerplay_table = 375 table_context->power_play_table; 376 struct amdgpu_device *adev = smu->adev; 377 378 if (adev->pdev->device == 0x51) 379 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080; 380 381 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 382 sizeof(PPTable_t)); 383 384 return 0; 385 } 386 387 static int smu_v13_0_7_check_fw_status(struct smu_context *smu) 388 { 389 struct amdgpu_device *adev = smu->adev; 390 uint32_t mp1_fw_flags; 391 392 mp1_fw_flags = RREG32_PCIE(MP1_Public | 393 (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff)); 394 395 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 396 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 397 return 0; 398 399 return -EIO; 400 } 401 402 #ifndef atom_smc_dpm_info_table_13_0_7 403 struct atom_smc_dpm_info_table_13_0_7 { 404 struct atom_common_table_header table_header; 405 BoardTable_t BoardTable; 406 }; 407 #endif 408 409 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu) 410 { 411 struct smu_table_context *table_context = &smu->smu_table; 412 413 PPTable_t *smc_pptable = table_context->driver_pptable; 414 415 struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table; 416 417 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 418 419 int index, ret; 420 421 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 422 smc_dpm_info); 423 424 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 425 (uint8_t **)&smc_dpm_table); 426 if (ret) 427 return ret; 428 429 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 430 431 return 0; 432 } 433 434 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu, 435 void **table, 436 uint32_t *size) 437 { 438 struct smu_table_context *smu_table = &smu->smu_table; 439 void *combo_pptable = smu_table->combo_pptable; 440 int ret = 0; 441 442 ret = smu_cmn_get_combo_pptable(smu); 443 if (ret) 444 return ret; 445 446 *table = combo_pptable; 447 *size = sizeof(struct smu_13_0_7_powerplay_table); 448 449 return 0; 450 } 451 452 static int smu_v13_0_7_setup_pptable(struct smu_context *smu) 453 { 454 struct smu_table_context *smu_table = &smu->smu_table; 455 struct amdgpu_device *adev = smu->adev; 456 int ret = 0; 457 458 /* 459 * With SCPM enabled, the pptable used will be signed. It cannot 460 * be used directly by driver. To get the raw pptable, we need to 461 * rely on the combo pptable(and its revelant SMU message). 462 */ 463 ret = smu_v13_0_7_get_pptable_from_pmfw(smu, 464 &smu_table->power_play_table, 465 &smu_table->power_play_table_size); 466 if (ret) 467 return ret; 468 469 ret = smu_v13_0_7_store_powerplay_table(smu); 470 if (ret) 471 return ret; 472 473 /* 474 * With SCPM enabled, the operation below will be handled 475 * by PSP. Driver involvment is unnecessary and useless. 476 */ 477 if (!adev->scpm_enabled) { 478 ret = smu_v13_0_7_append_powerplay_table(smu); 479 if (ret) 480 return ret; 481 } 482 483 ret = smu_v13_0_7_check_powerplay_table(smu); 484 if (ret) 485 return ret; 486 487 return ret; 488 } 489 490 static int smu_v13_0_7_tables_init(struct smu_context *smu) 491 { 492 struct smu_table_context *smu_table = &smu->smu_table; 493 struct smu_table *tables = smu_table->tables; 494 495 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 496 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 497 498 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 499 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 500 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 501 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 502 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 503 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 504 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t), 505 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 506 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 507 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 508 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 509 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 510 AMDGPU_GEM_DOMAIN_VRAM); 511 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE, 512 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 513 514 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 515 if (!smu_table->metrics_table) 516 goto err0_out; 517 smu_table->metrics_time = 0; 518 519 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 520 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 521 if (!smu_table->gpu_metrics_table) 522 goto err1_out; 523 524 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 525 if (!smu_table->watermarks_table) 526 goto err2_out; 527 528 return 0; 529 530 err2_out: 531 kfree(smu_table->gpu_metrics_table); 532 err1_out: 533 kfree(smu_table->metrics_table); 534 err0_out: 535 return -ENOMEM; 536 } 537 538 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu) 539 { 540 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 541 542 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 543 GFP_KERNEL); 544 if (!smu_dpm->dpm_context) 545 return -ENOMEM; 546 547 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 548 549 return 0; 550 } 551 552 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu) 553 { 554 int ret = 0; 555 556 ret = smu_v13_0_7_tables_init(smu); 557 if (ret) 558 return ret; 559 560 ret = smu_v13_0_7_allocate_dpm_context(smu); 561 if (ret) 562 return ret; 563 564 return smu_v13_0_init_smc_tables(smu); 565 } 566 567 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) 568 { 569 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 570 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 571 SkuTable_t *skutable = &driver_ppt->SkuTable; 572 struct smu_13_0_dpm_table *dpm_table; 573 struct smu_13_0_pcie_table *pcie_table; 574 uint32_t link_level; 575 int ret = 0; 576 577 /* socclk dpm table setup */ 578 dpm_table = &dpm_context->dpm_tables.soc_table; 579 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 580 ret = smu_v13_0_set_single_dpm_table(smu, 581 SMU_SOCCLK, 582 dpm_table); 583 if (ret) 584 return ret; 585 } else { 586 dpm_table->count = 1; 587 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 588 dpm_table->dpm_levels[0].enabled = true; 589 dpm_table->min = dpm_table->dpm_levels[0].value; 590 dpm_table->max = dpm_table->dpm_levels[0].value; 591 } 592 593 /* gfxclk dpm table setup */ 594 dpm_table = &dpm_context->dpm_tables.gfx_table; 595 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 596 ret = smu_v13_0_set_single_dpm_table(smu, 597 SMU_GFXCLK, 598 dpm_table); 599 if (ret) 600 return ret; 601 602 if (skutable->DriverReportedClocks.GameClockAc && 603 (dpm_table->dpm_levels[dpm_table->count - 1].value > 604 skutable->DriverReportedClocks.GameClockAc)) { 605 dpm_table->dpm_levels[dpm_table->count - 1].value = 606 skutable->DriverReportedClocks.GameClockAc; 607 dpm_table->max = skutable->DriverReportedClocks.GameClockAc; 608 } 609 } else { 610 dpm_table->count = 1; 611 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 612 dpm_table->dpm_levels[0].enabled = true; 613 dpm_table->min = dpm_table->dpm_levels[0].value; 614 dpm_table->max = dpm_table->dpm_levels[0].value; 615 } 616 617 /* uclk dpm table setup */ 618 dpm_table = &dpm_context->dpm_tables.uclk_table; 619 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 620 ret = smu_v13_0_set_single_dpm_table(smu, 621 SMU_UCLK, 622 dpm_table); 623 if (ret) 624 return ret; 625 } else { 626 dpm_table->count = 1; 627 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 628 dpm_table->dpm_levels[0].enabled = true; 629 dpm_table->min = dpm_table->dpm_levels[0].value; 630 dpm_table->max = dpm_table->dpm_levels[0].value; 631 } 632 633 /* fclk dpm table setup */ 634 dpm_table = &dpm_context->dpm_tables.fclk_table; 635 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 636 ret = smu_v13_0_set_single_dpm_table(smu, 637 SMU_FCLK, 638 dpm_table); 639 if (ret) 640 return ret; 641 } else { 642 dpm_table->count = 1; 643 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 644 dpm_table->dpm_levels[0].enabled = true; 645 dpm_table->min = dpm_table->dpm_levels[0].value; 646 dpm_table->max = dpm_table->dpm_levels[0].value; 647 } 648 649 /* vclk dpm table setup */ 650 dpm_table = &dpm_context->dpm_tables.vclk_table; 651 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { 652 ret = smu_v13_0_set_single_dpm_table(smu, 653 SMU_VCLK, 654 dpm_table); 655 if (ret) 656 return ret; 657 } else { 658 dpm_table->count = 1; 659 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 660 dpm_table->dpm_levels[0].enabled = true; 661 dpm_table->min = dpm_table->dpm_levels[0].value; 662 dpm_table->max = dpm_table->dpm_levels[0].value; 663 } 664 665 /* dclk dpm table setup */ 666 dpm_table = &dpm_context->dpm_tables.dclk_table; 667 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { 668 ret = smu_v13_0_set_single_dpm_table(smu, 669 SMU_DCLK, 670 dpm_table); 671 if (ret) 672 return ret; 673 } else { 674 dpm_table->count = 1; 675 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 676 dpm_table->dpm_levels[0].enabled = true; 677 dpm_table->min = dpm_table->dpm_levels[0].value; 678 dpm_table->max = dpm_table->dpm_levels[0].value; 679 } 680 681 /* lclk dpm table setup */ 682 pcie_table = &dpm_context->dpm_tables.pcie_table; 683 pcie_table->num_of_link_levels = 0; 684 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { 685 if (!skutable->PcieGenSpeed[link_level] && 686 !skutable->PcieLaneCount[link_level] && 687 !skutable->LclkFreq[link_level]) 688 continue; 689 690 pcie_table->pcie_gen[pcie_table->num_of_link_levels] = 691 skutable->PcieGenSpeed[link_level]; 692 pcie_table->pcie_lane[pcie_table->num_of_link_levels] = 693 skutable->PcieLaneCount[link_level]; 694 pcie_table->clk_freq[pcie_table->num_of_link_levels] = 695 skutable->LclkFreq[link_level]; 696 pcie_table->num_of_link_levels++; 697 } 698 699 return 0; 700 } 701 702 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu) 703 { 704 int ret = 0; 705 uint64_t feature_enabled; 706 707 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 708 if (ret) 709 return false; 710 711 return !!(feature_enabled & SMC_DPM_FEATURE); 712 } 713 714 static void smu_v13_0_7_dump_pptable(struct smu_context *smu) 715 { 716 struct smu_table_context *table_context = &smu->smu_table; 717 PPTable_t *pptable = table_context->driver_pptable; 718 SkuTable_t *skutable = &pptable->SkuTable; 719 720 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 721 722 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version); 723 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]); 724 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]); 725 } 726 727 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics) 728 { 729 uint32_t throttler_status = 0; 730 int i; 731 732 for (i = 0; i < THROTTLER_COUNT; i++) 733 throttler_status |= 734 (metrics->ThrottlingPercentage[i] ? 1U << i : 0); 735 736 return throttler_status; 737 } 738 739 #define SMU_13_0_7_BUSY_THRESHOLD 15 740 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu, 741 MetricsMember_t member, 742 uint32_t *value) 743 { 744 struct smu_table_context *smu_table = &smu->smu_table; 745 SmuMetrics_t *metrics = 746 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 747 int ret = 0; 748 749 ret = smu_cmn_get_metrics_table(smu, 750 NULL, 751 false); 752 if (ret) 753 return ret; 754 755 switch (member) { 756 case METRICS_CURR_GFXCLK: 757 *value = metrics->CurrClock[PPCLK_GFXCLK]; 758 break; 759 case METRICS_CURR_SOCCLK: 760 *value = metrics->CurrClock[PPCLK_SOCCLK]; 761 break; 762 case METRICS_CURR_UCLK: 763 *value = metrics->CurrClock[PPCLK_UCLK]; 764 break; 765 case METRICS_CURR_VCLK: 766 *value = metrics->CurrClock[PPCLK_VCLK_0]; 767 break; 768 case METRICS_CURR_VCLK1: 769 *value = metrics->CurrClock[PPCLK_VCLK_1]; 770 break; 771 case METRICS_CURR_DCLK: 772 *value = metrics->CurrClock[PPCLK_DCLK_0]; 773 break; 774 case METRICS_CURR_DCLK1: 775 *value = metrics->CurrClock[PPCLK_DCLK_1]; 776 break; 777 case METRICS_CURR_FCLK: 778 *value = metrics->CurrClock[PPCLK_FCLK]; 779 break; 780 case METRICS_AVERAGE_GFXCLK: 781 *value = metrics->AverageGfxclkFrequencyPreDs; 782 break; 783 case METRICS_AVERAGE_FCLK: 784 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 785 *value = metrics->AverageFclkFrequencyPostDs; 786 else 787 *value = metrics->AverageFclkFrequencyPreDs; 788 break; 789 case METRICS_AVERAGE_UCLK: 790 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 791 *value = metrics->AverageMemclkFrequencyPostDs; 792 else 793 *value = metrics->AverageMemclkFrequencyPreDs; 794 break; 795 case METRICS_AVERAGE_VCLK: 796 *value = metrics->AverageVclk0Frequency; 797 break; 798 case METRICS_AVERAGE_DCLK: 799 *value = metrics->AverageDclk0Frequency; 800 break; 801 case METRICS_AVERAGE_VCLK1: 802 *value = metrics->AverageVclk1Frequency; 803 break; 804 case METRICS_AVERAGE_DCLK1: 805 *value = metrics->AverageDclk1Frequency; 806 break; 807 case METRICS_AVERAGE_GFXACTIVITY: 808 *value = metrics->AverageGfxActivity; 809 break; 810 case METRICS_AVERAGE_MEMACTIVITY: 811 *value = metrics->AverageUclkActivity; 812 break; 813 case METRICS_AVERAGE_SOCKETPOWER: 814 *value = metrics->AverageSocketPower << 8; 815 break; 816 case METRICS_TEMPERATURE_EDGE: 817 *value = metrics->AvgTemperature[TEMP_EDGE] * 818 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 819 break; 820 case METRICS_TEMPERATURE_HOTSPOT: 821 *value = metrics->AvgTemperature[TEMP_HOTSPOT] * 822 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 823 break; 824 case METRICS_TEMPERATURE_MEM: 825 *value = metrics->AvgTemperature[TEMP_MEM] * 826 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 827 break; 828 case METRICS_TEMPERATURE_VRGFX: 829 *value = metrics->AvgTemperature[TEMP_VR_GFX] * 830 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 831 break; 832 case METRICS_TEMPERATURE_VRSOC: 833 *value = metrics->AvgTemperature[TEMP_VR_SOC] * 834 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 835 break; 836 case METRICS_THROTTLER_STATUS: 837 *value = smu_v13_0_7_get_throttler_status(metrics); 838 break; 839 case METRICS_CURR_FANSPEED: 840 *value = metrics->AvgFanRpm; 841 break; 842 case METRICS_CURR_FANPWM: 843 *value = metrics->AvgFanPwm; 844 break; 845 case METRICS_VOLTAGE_VDDGFX: 846 *value = metrics->AvgVoltage[SVI_PLANE_GFX]; 847 break; 848 case METRICS_PCIE_RATE: 849 *value = metrics->PcieRate; 850 break; 851 case METRICS_PCIE_WIDTH: 852 *value = metrics->PcieWidth; 853 break; 854 default: 855 *value = UINT_MAX; 856 break; 857 } 858 859 return ret; 860 } 861 862 static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu, 863 enum smu_clk_type clk_type, 864 uint32_t *min, 865 uint32_t *max) 866 { 867 struct smu_13_0_dpm_context *dpm_context = 868 smu->smu_dpm.dpm_context; 869 struct smu_13_0_dpm_table *dpm_table; 870 871 switch (clk_type) { 872 case SMU_MCLK: 873 case SMU_UCLK: 874 /* uclk dpm table */ 875 dpm_table = &dpm_context->dpm_tables.uclk_table; 876 break; 877 case SMU_GFXCLK: 878 case SMU_SCLK: 879 /* gfxclk dpm table */ 880 dpm_table = &dpm_context->dpm_tables.gfx_table; 881 break; 882 case SMU_SOCCLK: 883 /* socclk dpm table */ 884 dpm_table = &dpm_context->dpm_tables.soc_table; 885 break; 886 case SMU_FCLK: 887 /* fclk dpm table */ 888 dpm_table = &dpm_context->dpm_tables.fclk_table; 889 break; 890 case SMU_VCLK: 891 case SMU_VCLK1: 892 /* vclk dpm table */ 893 dpm_table = &dpm_context->dpm_tables.vclk_table; 894 break; 895 case SMU_DCLK: 896 case SMU_DCLK1: 897 /* dclk dpm table */ 898 dpm_table = &dpm_context->dpm_tables.dclk_table; 899 break; 900 default: 901 dev_err(smu->adev->dev, "Unsupported clock type!\n"); 902 return -EINVAL; 903 } 904 905 if (min) 906 *min = dpm_table->min; 907 if (max) 908 *max = dpm_table->max; 909 910 return 0; 911 } 912 913 static int smu_v13_0_7_read_sensor(struct smu_context *smu, 914 enum amd_pp_sensors sensor, 915 void *data, 916 uint32_t *size) 917 { 918 struct smu_table_context *table_context = &smu->smu_table; 919 PPTable_t *smc_pptable = table_context->driver_pptable; 920 int ret = 0; 921 922 switch (sensor) { 923 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 924 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm; 925 *size = 4; 926 break; 927 case AMDGPU_PP_SENSOR_MEM_LOAD: 928 ret = smu_v13_0_7_get_smu_metrics_data(smu, 929 METRICS_AVERAGE_MEMACTIVITY, 930 (uint32_t *)data); 931 *size = 4; 932 break; 933 case AMDGPU_PP_SENSOR_GPU_LOAD: 934 ret = smu_v13_0_7_get_smu_metrics_data(smu, 935 METRICS_AVERAGE_GFXACTIVITY, 936 (uint32_t *)data); 937 *size = 4; 938 break; 939 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 940 ret = smu_v13_0_7_get_smu_metrics_data(smu, 941 METRICS_AVERAGE_SOCKETPOWER, 942 (uint32_t *)data); 943 *size = 4; 944 break; 945 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 946 ret = smu_v13_0_7_get_smu_metrics_data(smu, 947 METRICS_TEMPERATURE_HOTSPOT, 948 (uint32_t *)data); 949 *size = 4; 950 break; 951 case AMDGPU_PP_SENSOR_EDGE_TEMP: 952 ret = smu_v13_0_7_get_smu_metrics_data(smu, 953 METRICS_TEMPERATURE_EDGE, 954 (uint32_t *)data); 955 *size = 4; 956 break; 957 case AMDGPU_PP_SENSOR_MEM_TEMP: 958 ret = smu_v13_0_7_get_smu_metrics_data(smu, 959 METRICS_TEMPERATURE_MEM, 960 (uint32_t *)data); 961 *size = 4; 962 break; 963 case AMDGPU_PP_SENSOR_GFX_MCLK: 964 ret = smu_v13_0_7_get_smu_metrics_data(smu, 965 METRICS_CURR_UCLK, 966 (uint32_t *)data); 967 *(uint32_t *)data *= 100; 968 *size = 4; 969 break; 970 case AMDGPU_PP_SENSOR_GFX_SCLK: 971 ret = smu_v13_0_7_get_smu_metrics_data(smu, 972 METRICS_AVERAGE_GFXCLK, 973 (uint32_t *)data); 974 *(uint32_t *)data *= 100; 975 *size = 4; 976 break; 977 case AMDGPU_PP_SENSOR_VDDGFX: 978 ret = smu_v13_0_7_get_smu_metrics_data(smu, 979 METRICS_VOLTAGE_VDDGFX, 980 (uint32_t *)data); 981 *size = 4; 982 break; 983 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 984 default: 985 ret = -EOPNOTSUPP; 986 break; 987 } 988 989 return ret; 990 } 991 992 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu, 993 enum smu_clk_type clk_type, 994 uint32_t *value) 995 { 996 MetricsMember_t member_type; 997 int clk_id = 0; 998 999 clk_id = smu_cmn_to_asic_specific_index(smu, 1000 CMN2ASIC_MAPPING_CLK, 1001 clk_type); 1002 if (clk_id < 0) 1003 return -EINVAL; 1004 1005 switch (clk_id) { 1006 case PPCLK_GFXCLK: 1007 member_type = METRICS_AVERAGE_GFXCLK; 1008 break; 1009 case PPCLK_UCLK: 1010 member_type = METRICS_CURR_UCLK; 1011 break; 1012 case PPCLK_FCLK: 1013 member_type = METRICS_CURR_FCLK; 1014 break; 1015 case PPCLK_SOCCLK: 1016 member_type = METRICS_CURR_SOCCLK; 1017 break; 1018 case PPCLK_VCLK_0: 1019 member_type = METRICS_CURR_VCLK; 1020 break; 1021 case PPCLK_DCLK_0: 1022 member_type = METRICS_CURR_DCLK; 1023 break; 1024 case PPCLK_VCLK_1: 1025 member_type = METRICS_CURR_VCLK1; 1026 break; 1027 case PPCLK_DCLK_1: 1028 member_type = METRICS_CURR_DCLK1; 1029 break; 1030 default: 1031 return -EINVAL; 1032 } 1033 1034 return smu_v13_0_7_get_smu_metrics_data(smu, 1035 member_type, 1036 value); 1037 } 1038 1039 static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu, 1040 int od_feature_bit) 1041 { 1042 PPTable_t *pptable = smu->smu_table.driver_pptable; 1043 const OverDriveLimits_t * const overdrive_upperlimits = 1044 &pptable->SkuTable.OverDriveLimitsBasicMax; 1045 1046 return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); 1047 } 1048 1049 static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu, 1050 int od_feature_bit, 1051 int32_t *min, 1052 int32_t *max) 1053 { 1054 PPTable_t *pptable = smu->smu_table.driver_pptable; 1055 const OverDriveLimits_t * const overdrive_upperlimits = 1056 &pptable->SkuTable.OverDriveLimitsBasicMax; 1057 const OverDriveLimits_t * const overdrive_lowerlimits = 1058 &pptable->SkuTable.OverDriveLimitsMin; 1059 int32_t od_min_setting, od_max_setting; 1060 1061 switch (od_feature_bit) { 1062 case PP_OD_FEATURE_GFXCLK_FMIN: 1063 od_min_setting = overdrive_lowerlimits->GfxclkFmin; 1064 od_max_setting = overdrive_upperlimits->GfxclkFmin; 1065 break; 1066 case PP_OD_FEATURE_GFXCLK_FMAX: 1067 od_min_setting = overdrive_lowerlimits->GfxclkFmax; 1068 od_max_setting = overdrive_upperlimits->GfxclkFmax; 1069 break; 1070 case PP_OD_FEATURE_UCLK_FMIN: 1071 od_min_setting = overdrive_lowerlimits->UclkFmin; 1072 od_max_setting = overdrive_upperlimits->UclkFmin; 1073 break; 1074 case PP_OD_FEATURE_UCLK_FMAX: 1075 od_min_setting = overdrive_lowerlimits->UclkFmax; 1076 od_max_setting = overdrive_upperlimits->UclkFmax; 1077 break; 1078 case PP_OD_FEATURE_GFX_VF_CURVE: 1079 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary; 1080 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary; 1081 break; 1082 default: 1083 od_min_setting = od_max_setting = INT_MAX; 1084 break; 1085 } 1086 1087 if (min) 1088 *min = od_min_setting; 1089 if (max) 1090 *max = od_max_setting; 1091 } 1092 1093 static void smu_v13_0_7_dump_od_table(struct smu_context *smu, 1094 OverDriveTableExternal_t *od_table) 1095 { 1096 struct amdgpu_device *adev = smu->adev; 1097 1098 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin, 1099 od_table->OverDriveTable.GfxclkFmax); 1100 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin, 1101 od_table->OverDriveTable.UclkFmax); 1102 } 1103 1104 static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu, 1105 OverDriveTableExternal_t *od_table) 1106 { 1107 int ret = 0; 1108 1109 ret = smu_cmn_update_table(smu, 1110 SMU_TABLE_OVERDRIVE, 1111 0, 1112 (void *)od_table, 1113 false); 1114 if (ret) 1115 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 1116 1117 return ret; 1118 } 1119 1120 static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu, 1121 OverDriveTableExternal_t *od_table) 1122 { 1123 int ret = 0; 1124 1125 ret = smu_cmn_update_table(smu, 1126 SMU_TABLE_OVERDRIVE, 1127 0, 1128 (void *)od_table, 1129 true); 1130 if (ret) 1131 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n"); 1132 1133 return ret; 1134 } 1135 1136 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, 1137 enum smu_clk_type clk_type, 1138 char *buf) 1139 { 1140 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1141 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1142 OverDriveTableExternal_t *od_table = 1143 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; 1144 struct smu_13_0_dpm_table *single_dpm_table; 1145 struct smu_13_0_pcie_table *pcie_table; 1146 uint32_t gen_speed, lane_width; 1147 int i, curr_freq, size = 0; 1148 int32_t min_value, max_value; 1149 int ret = 0; 1150 1151 smu_cmn_get_sysfs_buf(&buf, &size); 1152 1153 if (amdgpu_ras_intr_triggered()) { 1154 size += sysfs_emit_at(buf, size, "unavailable\n"); 1155 return size; 1156 } 1157 1158 switch (clk_type) { 1159 case SMU_SCLK: 1160 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1161 break; 1162 case SMU_MCLK: 1163 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1164 break; 1165 case SMU_SOCCLK: 1166 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1167 break; 1168 case SMU_FCLK: 1169 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1170 break; 1171 case SMU_VCLK: 1172 case SMU_VCLK1: 1173 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1174 break; 1175 case SMU_DCLK: 1176 case SMU_DCLK1: 1177 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1178 break; 1179 default: 1180 break; 1181 } 1182 1183 switch (clk_type) { 1184 case SMU_SCLK: 1185 case SMU_MCLK: 1186 case SMU_SOCCLK: 1187 case SMU_FCLK: 1188 case SMU_VCLK: 1189 case SMU_VCLK1: 1190 case SMU_DCLK: 1191 case SMU_DCLK1: 1192 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); 1193 if (ret) { 1194 dev_err(smu->adev->dev, "Failed to get current clock freq!"); 1195 return ret; 1196 } 1197 1198 if (single_dpm_table->is_fine_grained) { 1199 /* 1200 * For fine grained dpms, there are only two dpm levels: 1201 * - level 0 -> min clock freq 1202 * - level 1 -> max clock freq 1203 * And the current clock frequency can be any value between them. 1204 * So, if the current clock frequency is not at level 0 or level 1, 1205 * we will fake it as three dpm levels: 1206 * - level 0 -> min clock freq 1207 * - level 1 -> current actual clock freq 1208 * - level 2 -> max clock freq 1209 */ 1210 if ((single_dpm_table->dpm_levels[0].value != curr_freq) && 1211 (single_dpm_table->dpm_levels[1].value != curr_freq)) { 1212 size += sysfs_emit_at(buf, size, "0: %uMhz\n", 1213 single_dpm_table->dpm_levels[0].value); 1214 size += sysfs_emit_at(buf, size, "1: %uMhz *\n", 1215 curr_freq); 1216 size += sysfs_emit_at(buf, size, "2: %uMhz\n", 1217 single_dpm_table->dpm_levels[1].value); 1218 } else { 1219 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 1220 single_dpm_table->dpm_levels[0].value, 1221 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); 1222 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 1223 single_dpm_table->dpm_levels[1].value, 1224 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); 1225 } 1226 } else { 1227 for (i = 0; i < single_dpm_table->count; i++) 1228 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 1229 i, single_dpm_table->dpm_levels[i].value, 1230 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); 1231 } 1232 break; 1233 case SMU_PCIE: 1234 ret = smu_v13_0_7_get_smu_metrics_data(smu, 1235 METRICS_PCIE_RATE, 1236 &gen_speed); 1237 if (ret) 1238 return ret; 1239 1240 ret = smu_v13_0_7_get_smu_metrics_data(smu, 1241 METRICS_PCIE_WIDTH, 1242 &lane_width); 1243 if (ret) 1244 return ret; 1245 1246 pcie_table = &(dpm_context->dpm_tables.pcie_table); 1247 for (i = 0; i < pcie_table->num_of_link_levels; i++) 1248 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1249 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : 1250 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : 1251 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : 1252 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", 1253 (pcie_table->pcie_lane[i] == 1) ? "x1" : 1254 (pcie_table->pcie_lane[i] == 2) ? "x2" : 1255 (pcie_table->pcie_lane[i] == 3) ? "x4" : 1256 (pcie_table->pcie_lane[i] == 4) ? "x8" : 1257 (pcie_table->pcie_lane[i] == 5) ? "x12" : 1258 (pcie_table->pcie_lane[i] == 6) ? "x16" : "", 1259 pcie_table->clk_freq[i], 1260 (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) && 1261 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? 1262 "*" : ""); 1263 break; 1264 1265 case SMU_OD_SCLK: 1266 if (!smu_v13_0_7_is_od_feature_supported(smu, 1267 PP_OD_FEATURE_GFXCLK_BIT)) 1268 break; 1269 1270 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1271 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", 1272 od_table->OverDriveTable.GfxclkFmin, 1273 od_table->OverDriveTable.GfxclkFmax); 1274 break; 1275 1276 case SMU_OD_MCLK: 1277 if (!smu_v13_0_7_is_od_feature_supported(smu, 1278 PP_OD_FEATURE_UCLK_BIT)) 1279 break; 1280 1281 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1282 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", 1283 od_table->OverDriveTable.UclkFmin, 1284 od_table->OverDriveTable.UclkFmax); 1285 break; 1286 1287 case SMU_OD_VDDC_CURVE: 1288 if (!smu_v13_0_7_is_od_feature_supported(smu, 1289 PP_OD_FEATURE_GFX_VF_CURVE_BIT)) 1290 break; 1291 1292 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n"); 1293 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++) 1294 size += sysfs_emit_at(buf, size, "%d: %dmv\n", 1295 i, 1296 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i]); 1297 break; 1298 1299 case SMU_OD_RANGE: 1300 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) && 1301 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) && 1302 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) 1303 break; 1304 1305 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1306 1307 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) { 1308 smu_v13_0_7_get_od_setting_limits(smu, 1309 PP_OD_FEATURE_GFXCLK_FMIN, 1310 &min_value, 1311 NULL); 1312 smu_v13_0_7_get_od_setting_limits(smu, 1313 PP_OD_FEATURE_GFXCLK_FMAX, 1314 NULL, 1315 &max_value); 1316 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1317 min_value, max_value); 1318 } 1319 1320 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) { 1321 smu_v13_0_7_get_od_setting_limits(smu, 1322 PP_OD_FEATURE_UCLK_FMIN, 1323 &min_value, 1324 NULL); 1325 smu_v13_0_7_get_od_setting_limits(smu, 1326 PP_OD_FEATURE_UCLK_FMAX, 1327 NULL, 1328 &max_value); 1329 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1330 min_value, max_value); 1331 } 1332 1333 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) { 1334 smu_v13_0_7_get_od_setting_limits(smu, 1335 PP_OD_FEATURE_GFX_VF_CURVE, 1336 &min_value, 1337 &max_value); 1338 size += sysfs_emit_at(buf, size, "VDDC_CURVE: %7dmv %10dmv\n", 1339 min_value, max_value); 1340 } 1341 break; 1342 1343 default: 1344 break; 1345 } 1346 1347 return size; 1348 } 1349 1350 static int smu_v13_0_7_od_edit_dpm_table(struct smu_context *smu, 1351 enum PP_OD_DPM_TABLE_COMMAND type, 1352 long input[], 1353 uint32_t size) 1354 { 1355 struct smu_table_context *table_context = &smu->smu_table; 1356 OverDriveTableExternal_t *od_table = 1357 (OverDriveTableExternal_t *)table_context->overdrive_table; 1358 struct amdgpu_device *adev = smu->adev; 1359 uint32_t offset_of_voltageoffset; 1360 int32_t minimum, maximum; 1361 uint32_t feature_ctrlmask; 1362 int i, ret = 0; 1363 1364 switch (type) { 1365 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1366 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) { 1367 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n"); 1368 return -ENOTSUPP; 1369 } 1370 1371 for (i = 0; i < size; i += 2) { 1372 if (i + 2 > size) { 1373 dev_info(adev->dev, "invalid number of input parameters %d\n", size); 1374 return -EINVAL; 1375 } 1376 1377 switch (input[i]) { 1378 case 0: 1379 smu_v13_0_7_get_od_setting_limits(smu, 1380 PP_OD_FEATURE_GFXCLK_FMIN, 1381 &minimum, 1382 &maximum); 1383 if (input[i + 1] < minimum || 1384 input[i + 1] > maximum) { 1385 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n", 1386 input[i + 1], minimum, maximum); 1387 return -EINVAL; 1388 } 1389 1390 od_table->OverDriveTable.GfxclkFmin = input[i + 1]; 1391 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT; 1392 break; 1393 1394 case 1: 1395 smu_v13_0_7_get_od_setting_limits(smu, 1396 PP_OD_FEATURE_GFXCLK_FMAX, 1397 &minimum, 1398 &maximum); 1399 if (input[i + 1] < minimum || 1400 input[i + 1] > maximum) { 1401 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n", 1402 input[i + 1], minimum, maximum); 1403 return -EINVAL; 1404 } 1405 1406 od_table->OverDriveTable.GfxclkFmax = input[i + 1]; 1407 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT; 1408 break; 1409 1410 default: 1411 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 1412 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n"); 1413 return -EINVAL; 1414 } 1415 } 1416 1417 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) { 1418 dev_err(adev->dev, 1419 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n", 1420 (uint32_t)od_table->OverDriveTable.GfxclkFmin, 1421 (uint32_t)od_table->OverDriveTable.GfxclkFmax); 1422 return -EINVAL; 1423 } 1424 break; 1425 1426 case PP_OD_EDIT_MCLK_VDDC_TABLE: 1427 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) { 1428 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n"); 1429 return -ENOTSUPP; 1430 } 1431 1432 for (i = 0; i < size; i += 2) { 1433 if (i + 2 > size) { 1434 dev_info(adev->dev, "invalid number of input parameters %d\n", size); 1435 return -EINVAL; 1436 } 1437 1438 switch (input[i]) { 1439 case 0: 1440 smu_v13_0_7_get_od_setting_limits(smu, 1441 PP_OD_FEATURE_UCLK_FMIN, 1442 &minimum, 1443 &maximum); 1444 if (input[i + 1] < minimum || 1445 input[i + 1] > maximum) { 1446 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n", 1447 input[i + 1], minimum, maximum); 1448 return -EINVAL; 1449 } 1450 1451 od_table->OverDriveTable.UclkFmin = input[i + 1]; 1452 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT; 1453 break; 1454 1455 case 1: 1456 smu_v13_0_7_get_od_setting_limits(smu, 1457 PP_OD_FEATURE_UCLK_FMAX, 1458 &minimum, 1459 &maximum); 1460 if (input[i + 1] < minimum || 1461 input[i + 1] > maximum) { 1462 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n", 1463 input[i + 1], minimum, maximum); 1464 return -EINVAL; 1465 } 1466 1467 od_table->OverDriveTable.UclkFmax = input[i + 1]; 1468 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT; 1469 break; 1470 1471 default: 1472 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 1473 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n"); 1474 return -EINVAL; 1475 } 1476 } 1477 1478 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) { 1479 dev_err(adev->dev, 1480 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n", 1481 (uint32_t)od_table->OverDriveTable.UclkFmin, 1482 (uint32_t)od_table->OverDriveTable.UclkFmax); 1483 return -EINVAL; 1484 } 1485 break; 1486 1487 case PP_OD_EDIT_VDDC_CURVE: 1488 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) { 1489 dev_warn(adev->dev, "VF curve setting not supported!\n"); 1490 return -ENOTSUPP; 1491 } 1492 1493 if (input[0] >= PP_NUM_OD_VF_CURVE_POINTS || 1494 input[0] < 0) 1495 return -EINVAL; 1496 1497 smu_v13_0_7_get_od_setting_limits(smu, 1498 PP_OD_FEATURE_GFX_VF_CURVE, 1499 &minimum, 1500 &maximum); 1501 if (input[1] < minimum || 1502 input[1] > maximum) { 1503 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n", 1504 input[1], minimum, maximum); 1505 return -EINVAL; 1506 } 1507 1508 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[input[0]] = input[1]; 1509 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFX_VF_CURVE_BIT; 1510 break; 1511 1512 case PP_OD_RESTORE_DEFAULT_TABLE: 1513 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask; 1514 memcpy(od_table, 1515 table_context->boot_overdrive_table, 1516 sizeof(OverDriveTableExternal_t)); 1517 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask; 1518 fallthrough; 1519 1520 case PP_OD_COMMIT_DPM_TABLE: 1521 /* 1522 * The member below instructs PMFW the settings focused in 1523 * this single operation. 1524 * `uint32_t FeatureCtrlMask;` 1525 * It does not contain actual informations about user's custom 1526 * settings. Thus we do not cache it. 1527 */ 1528 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary); 1529 if (memcmp((u8 *)od_table + offset_of_voltageoffset, 1530 table_context->user_overdrive_table + offset_of_voltageoffset, 1531 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) { 1532 smu_v13_0_7_dump_od_table(smu, od_table); 1533 1534 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table); 1535 if (ret) { 1536 dev_err(adev->dev, "Failed to upload overdrive table!\n"); 1537 return ret; 1538 } 1539 1540 od_table->OverDriveTable.FeatureCtrlMask = 0; 1541 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset, 1542 (u8 *)od_table + offset_of_voltageoffset, 1543 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset); 1544 1545 if (!memcmp(table_context->user_overdrive_table, 1546 table_context->boot_overdrive_table, 1547 sizeof(OverDriveTableExternal_t))) 1548 smu->user_dpm_profile.user_od = false; 1549 else 1550 smu->user_dpm_profile.user_od = true; 1551 } 1552 break; 1553 1554 default: 1555 return -ENOSYS; 1556 } 1557 1558 return ret; 1559 } 1560 1561 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu, 1562 enum smu_clk_type clk_type, 1563 uint32_t mask) 1564 { 1565 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1566 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1567 struct smu_13_0_dpm_table *single_dpm_table; 1568 uint32_t soft_min_level, soft_max_level; 1569 uint32_t min_freq, max_freq; 1570 int ret = 0; 1571 1572 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1573 soft_max_level = mask ? (fls(mask) - 1) : 0; 1574 1575 switch (clk_type) { 1576 case SMU_GFXCLK: 1577 case SMU_SCLK: 1578 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1579 break; 1580 case SMU_MCLK: 1581 case SMU_UCLK: 1582 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1583 break; 1584 case SMU_SOCCLK: 1585 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1586 break; 1587 case SMU_FCLK: 1588 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1589 break; 1590 case SMU_VCLK: 1591 case SMU_VCLK1: 1592 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1593 break; 1594 case SMU_DCLK: 1595 case SMU_DCLK1: 1596 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1597 break; 1598 default: 1599 break; 1600 } 1601 1602 switch (clk_type) { 1603 case SMU_GFXCLK: 1604 case SMU_SCLK: 1605 case SMU_MCLK: 1606 case SMU_UCLK: 1607 case SMU_SOCCLK: 1608 case SMU_FCLK: 1609 case SMU_VCLK: 1610 case SMU_VCLK1: 1611 case SMU_DCLK: 1612 case SMU_DCLK1: 1613 if (single_dpm_table->is_fine_grained) { 1614 /* There is only 2 levels for fine grained DPM */ 1615 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1616 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1617 } else { 1618 if ((soft_max_level >= single_dpm_table->count) || 1619 (soft_min_level >= single_dpm_table->count)) 1620 return -EINVAL; 1621 } 1622 1623 min_freq = single_dpm_table->dpm_levels[soft_min_level].value; 1624 max_freq = single_dpm_table->dpm_levels[soft_max_level].value; 1625 1626 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1627 clk_type, 1628 min_freq, 1629 max_freq); 1630 break; 1631 case SMU_DCEFCLK: 1632 case SMU_PCIE: 1633 default: 1634 break; 1635 } 1636 1637 return ret; 1638 } 1639 1640 static const struct smu_temperature_range smu13_thermal_policy[] = { 1641 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 1642 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 1643 }; 1644 1645 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu, 1646 struct smu_temperature_range *range) 1647 { 1648 struct smu_table_context *table_context = &smu->smu_table; 1649 struct smu_13_0_7_powerplay_table *powerplay_table = 1650 table_context->power_play_table; 1651 PPTable_t *pptable = smu->smu_table.driver_pptable; 1652 1653 if (!range) 1654 return -EINVAL; 1655 1656 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1657 1658 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] * 1659 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1660 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1661 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1662 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] * 1663 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1664 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1665 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1666 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] * 1667 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1668 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1669 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1670 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1671 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset; 1672 1673 return 0; 1674 } 1675 1676 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 1677 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu, 1678 void **table) 1679 { 1680 struct smu_table_context *smu_table = &smu->smu_table; 1681 struct gpu_metrics_v1_3 *gpu_metrics = 1682 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1683 SmuMetricsExternal_t metrics_ext; 1684 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 1685 int ret = 0; 1686 1687 ret = smu_cmn_get_metrics_table(smu, 1688 &metrics_ext, 1689 true); 1690 if (ret) 1691 return ret; 1692 1693 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1694 1695 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE]; 1696 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT]; 1697 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM]; 1698 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX]; 1699 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC]; 1700 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0], 1701 metrics->AvgTemperature[TEMP_VR_MEM1]); 1702 1703 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 1704 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 1705 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage, 1706 metrics->Vcn1ActivityPercentage); 1707 1708 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 1709 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 1710 1711 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD) 1712 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 1713 else 1714 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 1715 1716 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 1717 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 1718 else 1719 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs; 1720 1721 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 1722 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 1723 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 1724 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 1725 1726 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; 1727 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 1728 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 1729 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 1730 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 1731 1732 gpu_metrics->throttle_status = 1733 smu_v13_0_7_get_throttler_status(metrics); 1734 gpu_metrics->indep_throttle_status = 1735 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 1736 smu_v13_0_7_throttler_map); 1737 1738 gpu_metrics->current_fan_speed = metrics->AvgFanRpm; 1739 1740 gpu_metrics->pcie_link_width = metrics->PcieWidth; 1741 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX) 1742 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1); 1743 else 1744 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate); 1745 1746 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1747 1748 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX]; 1749 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC]; 1750 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP]; 1751 1752 *table = (void *)gpu_metrics; 1753 1754 return sizeof(struct gpu_metrics_v1_3); 1755 } 1756 1757 static int smu_v13_0_7_set_default_od_settings(struct smu_context *smu) 1758 { 1759 OverDriveTableExternal_t *od_table = 1760 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; 1761 OverDriveTableExternal_t *boot_od_table = 1762 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table; 1763 OverDriveTableExternal_t *user_od_table = 1764 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table; 1765 OverDriveTableExternal_t user_od_table_bak; 1766 int ret = 0; 1767 int i; 1768 1769 ret = smu_v13_0_7_get_overdrive_table(smu, boot_od_table); 1770 if (ret) 1771 return ret; 1772 1773 smu_v13_0_7_dump_od_table(smu, boot_od_table); 1774 1775 memcpy(od_table, 1776 boot_od_table, 1777 sizeof(OverDriveTableExternal_t)); 1778 1779 /* 1780 * For S3/S4/Runpm resume, we need to setup those overdrive tables again, 1781 * but we have to preserve user defined values in "user_od_table". 1782 */ 1783 if (!smu->adev->in_suspend) { 1784 memcpy(user_od_table, 1785 boot_od_table, 1786 sizeof(OverDriveTableExternal_t)); 1787 smu->user_dpm_profile.user_od = false; 1788 } else if (smu->user_dpm_profile.user_od) { 1789 memcpy(&user_od_table_bak, 1790 user_od_table, 1791 sizeof(OverDriveTableExternal_t)); 1792 memcpy(user_od_table, 1793 boot_od_table, 1794 sizeof(OverDriveTableExternal_t)); 1795 user_od_table->OverDriveTable.GfxclkFmin = 1796 user_od_table_bak.OverDriveTable.GfxclkFmin; 1797 user_od_table->OverDriveTable.GfxclkFmax = 1798 user_od_table_bak.OverDriveTable.GfxclkFmax; 1799 user_od_table->OverDriveTable.UclkFmin = 1800 user_od_table_bak.OverDriveTable.UclkFmin; 1801 user_od_table->OverDriveTable.UclkFmax = 1802 user_od_table_bak.OverDriveTable.UclkFmax; 1803 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++) 1804 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = 1805 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i]; 1806 } 1807 1808 return 0; 1809 } 1810 1811 static int smu_v13_0_7_restore_user_od_settings(struct smu_context *smu) 1812 { 1813 struct smu_table_context *table_context = &smu->smu_table; 1814 OverDriveTableExternal_t *od_table = table_context->overdrive_table; 1815 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table; 1816 int res; 1817 1818 user_od_table->OverDriveTable.FeatureCtrlMask = 1U << PP_OD_FEATURE_GFXCLK_BIT | 1819 1U << PP_OD_FEATURE_UCLK_BIT | 1820 1U << PP_OD_FEATURE_GFX_VF_CURVE_BIT; 1821 res = smu_v13_0_7_upload_overdrive_table(smu, user_od_table); 1822 user_od_table->OverDriveTable.FeatureCtrlMask = 0; 1823 if (res == 0) 1824 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t)); 1825 1826 return res; 1827 } 1828 1829 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu) 1830 { 1831 struct smu_13_0_dpm_context *dpm_context = 1832 smu->smu_dpm.dpm_context; 1833 struct smu_13_0_dpm_table *gfx_table = 1834 &dpm_context->dpm_tables.gfx_table; 1835 struct smu_13_0_dpm_table *mem_table = 1836 &dpm_context->dpm_tables.uclk_table; 1837 struct smu_13_0_dpm_table *soc_table = 1838 &dpm_context->dpm_tables.soc_table; 1839 struct smu_13_0_dpm_table *vclk_table = 1840 &dpm_context->dpm_tables.vclk_table; 1841 struct smu_13_0_dpm_table *dclk_table = 1842 &dpm_context->dpm_tables.dclk_table; 1843 struct smu_13_0_dpm_table *fclk_table = 1844 &dpm_context->dpm_tables.fclk_table; 1845 struct smu_umd_pstate_table *pstate_table = 1846 &smu->pstate_table; 1847 struct smu_table_context *table_context = &smu->smu_table; 1848 PPTable_t *pptable = table_context->driver_pptable; 1849 DriverReportedClocks_t driver_clocks = 1850 pptable->SkuTable.DriverReportedClocks; 1851 1852 pstate_table->gfxclk_pstate.min = gfx_table->min; 1853 if (driver_clocks.GameClockAc && 1854 (driver_clocks.GameClockAc < gfx_table->max)) 1855 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc; 1856 else 1857 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1858 1859 pstate_table->uclk_pstate.min = mem_table->min; 1860 pstate_table->uclk_pstate.peak = mem_table->max; 1861 1862 pstate_table->socclk_pstate.min = soc_table->min; 1863 pstate_table->socclk_pstate.peak = soc_table->max; 1864 1865 pstate_table->vclk_pstate.min = vclk_table->min; 1866 pstate_table->vclk_pstate.peak = vclk_table->max; 1867 1868 pstate_table->dclk_pstate.min = dclk_table->min; 1869 pstate_table->dclk_pstate.peak = dclk_table->max; 1870 1871 pstate_table->fclk_pstate.min = fclk_table->min; 1872 pstate_table->fclk_pstate.peak = fclk_table->max; 1873 1874 if (driver_clocks.BaseClockAc && 1875 driver_clocks.BaseClockAc < gfx_table->max) 1876 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc; 1877 else 1878 pstate_table->gfxclk_pstate.standard = gfx_table->max; 1879 pstate_table->uclk_pstate.standard = mem_table->max; 1880 pstate_table->socclk_pstate.standard = soc_table->min; 1881 pstate_table->vclk_pstate.standard = vclk_table->min; 1882 pstate_table->dclk_pstate.standard = dclk_table->min; 1883 pstate_table->fclk_pstate.standard = fclk_table->min; 1884 1885 return 0; 1886 } 1887 1888 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu, 1889 uint32_t *speed) 1890 { 1891 int ret; 1892 1893 if (!speed) 1894 return -EINVAL; 1895 1896 ret = smu_v13_0_7_get_smu_metrics_data(smu, 1897 METRICS_CURR_FANPWM, 1898 speed); 1899 if (ret) { 1900 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!"); 1901 return ret; 1902 } 1903 1904 /* Convert the PMFW output which is in percent to pwm(255) based */ 1905 *speed = MIN(*speed * 255 / 100, 255); 1906 1907 return 0; 1908 } 1909 1910 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu, 1911 uint32_t *speed) 1912 { 1913 if (!speed) 1914 return -EINVAL; 1915 1916 return smu_v13_0_7_get_smu_metrics_data(smu, 1917 METRICS_CURR_FANSPEED, 1918 speed); 1919 } 1920 1921 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu) 1922 { 1923 struct smu_table_context *table_context = &smu->smu_table; 1924 PPTable_t *pptable = table_context->driver_pptable; 1925 SkuTable_t *skutable = &pptable->SkuTable; 1926 1927 /* 1928 * Skip the MGpuFanBoost setting for those ASICs 1929 * which do not support it 1930 */ 1931 if (skutable->MGpuAcousticLimitRpmThreshold == 0) 1932 return 0; 1933 1934 return smu_cmn_send_smc_msg_with_param(smu, 1935 SMU_MSG_SetMGpuFanBoostLimitRpm, 1936 0, 1937 NULL); 1938 } 1939 1940 static int smu_v13_0_7_get_power_limit(struct smu_context *smu, 1941 uint32_t *current_power_limit, 1942 uint32_t *default_power_limit, 1943 uint32_t *max_power_limit) 1944 { 1945 struct smu_table_context *table_context = &smu->smu_table; 1946 struct smu_13_0_7_powerplay_table *powerplay_table = 1947 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table; 1948 PPTable_t *pptable = table_context->driver_pptable; 1949 SkuTable_t *skutable = &pptable->SkuTable; 1950 uint32_t power_limit, od_percent; 1951 1952 if (smu_v13_0_get_current_power_limit(smu, &power_limit)) 1953 power_limit = smu->adev->pm.ac_power ? 1954 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] : 1955 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0]; 1956 1957 if (current_power_limit) 1958 *current_power_limit = power_limit; 1959 if (default_power_limit) 1960 *default_power_limit = power_limit; 1961 1962 if (max_power_limit) { 1963 if (smu->od_enabled) { 1964 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]); 1965 1966 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1967 1968 power_limit *= (100 + od_percent); 1969 power_limit /= 100; 1970 } 1971 *max_power_limit = power_limit; 1972 } 1973 1974 return 0; 1975 } 1976 1977 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf) 1978 { 1979 DpmActivityMonitorCoeffIntExternal_t *activity_monitor_external; 1980 uint32_t i, j, size = 0; 1981 int16_t workload_type = 0; 1982 int result = 0; 1983 1984 if (!buf) 1985 return -EINVAL; 1986 1987 activity_monitor_external = kcalloc(PP_SMC_POWER_PROFILE_COUNT, 1988 sizeof(*activity_monitor_external), 1989 GFP_KERNEL); 1990 if (!activity_monitor_external) 1991 return -ENOMEM; 1992 1993 size += sysfs_emit_at(buf, size, " "); 1994 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) 1995 size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i], 1996 (i == smu->power_profile_mode) ? "* " : " "); 1997 1998 size += sysfs_emit_at(buf, size, "\n"); 1999 2000 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) { 2001 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 2002 workload_type = smu_cmn_to_asic_specific_index(smu, 2003 CMN2ASIC_MAPPING_WORKLOAD, 2004 i); 2005 if (workload_type == -ENOTSUPP) 2006 continue; 2007 else if (workload_type < 0) { 2008 result = -EINVAL; 2009 goto out; 2010 } 2011 2012 result = smu_cmn_update_table(smu, 2013 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 2014 (void *)(&activity_monitor_external[i]), false); 2015 if (result) { 2016 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2017 goto out; 2018 } 2019 } 2020 2021 #define PRINT_DPM_MONITOR(field) \ 2022 do { \ 2023 size += sysfs_emit_at(buf, size, "%-30s", #field); \ 2024 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \ 2025 size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \ 2026 size += sysfs_emit_at(buf, size, "\n"); \ 2027 } while (0) 2028 2029 PRINT_DPM_MONITOR(Gfx_ActiveHystLimit); 2030 PRINT_DPM_MONITOR(Gfx_IdleHystLimit); 2031 PRINT_DPM_MONITOR(Gfx_FPS); 2032 PRINT_DPM_MONITOR(Gfx_MinActiveFreqType); 2033 PRINT_DPM_MONITOR(Gfx_BoosterFreqType); 2034 PRINT_DPM_MONITOR(Gfx_MinActiveFreq); 2035 PRINT_DPM_MONITOR(Gfx_BoosterFreq); 2036 PRINT_DPM_MONITOR(Fclk_ActiveHystLimit); 2037 PRINT_DPM_MONITOR(Fclk_IdleHystLimit); 2038 PRINT_DPM_MONITOR(Fclk_FPS); 2039 PRINT_DPM_MONITOR(Fclk_MinActiveFreqType); 2040 PRINT_DPM_MONITOR(Fclk_BoosterFreqType); 2041 PRINT_DPM_MONITOR(Fclk_MinActiveFreq); 2042 PRINT_DPM_MONITOR(Fclk_BoosterFreq); 2043 #undef PRINT_DPM_MONITOR 2044 2045 result = size; 2046 out: 2047 kfree(activity_monitor_external); 2048 return result; 2049 } 2050 2051 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 2052 { 2053 2054 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 2055 DpmActivityMonitorCoeffInt_t *activity_monitor = 2056 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 2057 int workload_type, ret = 0; 2058 2059 smu->power_profile_mode = input[size]; 2060 2061 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) { 2062 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 2063 return -EINVAL; 2064 } 2065 2066 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 2067 2068 ret = smu_cmn_update_table(smu, 2069 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2070 (void *)(&activity_monitor_external), false); 2071 if (ret) { 2072 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2073 return ret; 2074 } 2075 2076 switch (input[0]) { 2077 case 0: /* Gfxclk */ 2078 activity_monitor->Gfx_ActiveHystLimit = input[1]; 2079 activity_monitor->Gfx_IdleHystLimit = input[2]; 2080 activity_monitor->Gfx_FPS = input[3]; 2081 activity_monitor->Gfx_MinActiveFreqType = input[4]; 2082 activity_monitor->Gfx_BoosterFreqType = input[5]; 2083 activity_monitor->Gfx_MinActiveFreq = input[6]; 2084 activity_monitor->Gfx_BoosterFreq = input[7]; 2085 break; 2086 case 1: /* Fclk */ 2087 activity_monitor->Fclk_ActiveHystLimit = input[1]; 2088 activity_monitor->Fclk_IdleHystLimit = input[2]; 2089 activity_monitor->Fclk_FPS = input[3]; 2090 activity_monitor->Fclk_MinActiveFreqType = input[4]; 2091 activity_monitor->Fclk_BoosterFreqType = input[5]; 2092 activity_monitor->Fclk_MinActiveFreq = input[6]; 2093 activity_monitor->Fclk_BoosterFreq = input[7]; 2094 break; 2095 } 2096 2097 ret = smu_cmn_update_table(smu, 2098 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2099 (void *)(&activity_monitor_external), true); 2100 if (ret) { 2101 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 2102 return ret; 2103 } 2104 } 2105 2106 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 2107 workload_type = smu_cmn_to_asic_specific_index(smu, 2108 CMN2ASIC_MAPPING_WORKLOAD, 2109 smu->power_profile_mode); 2110 if (workload_type < 0) 2111 return -EINVAL; 2112 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 2113 1 << workload_type, NULL); 2114 2115 return ret; 2116 } 2117 2118 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu, 2119 enum pp_mp1_state mp1_state) 2120 { 2121 int ret; 2122 2123 switch (mp1_state) { 2124 case PP_MP1_STATE_UNLOAD: 2125 ret = smu_cmn_set_mp1_state(smu, mp1_state); 2126 break; 2127 default: 2128 /* Ignore others */ 2129 ret = 0; 2130 } 2131 2132 return ret; 2133 } 2134 2135 static int smu_v13_0_7_baco_enter(struct smu_context *smu) 2136 { 2137 struct smu_baco_context *smu_baco = &smu->smu_baco; 2138 struct amdgpu_device *adev = smu->adev; 2139 2140 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2141 return smu_v13_0_baco_set_armd3_sequence(smu, 2142 (smu_baco->maco_support && amdgpu_runtime_pm != 1) ? 2143 BACO_SEQ_BAMACO : BACO_SEQ_BACO); 2144 else 2145 return smu_v13_0_baco_enter(smu); 2146 } 2147 2148 static int smu_v13_0_7_baco_exit(struct smu_context *smu) 2149 { 2150 struct amdgpu_device *adev = smu->adev; 2151 2152 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2153 /* Wait for PMFW handling for the Dstate change */ 2154 usleep_range(10000, 11000); 2155 return smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2156 } else { 2157 return smu_v13_0_baco_exit(smu); 2158 } 2159 } 2160 2161 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu) 2162 { 2163 struct amdgpu_device *adev = smu->adev; 2164 2165 /* SRIOV does not support SMU mode1 reset */ 2166 if (amdgpu_sriov_vf(adev)) 2167 return false; 2168 2169 return true; 2170 } 2171 2172 static int smu_v13_0_7_set_df_cstate(struct smu_context *smu, 2173 enum pp_df_cstate state) 2174 { 2175 return smu_cmn_send_smc_msg_with_param(smu, 2176 SMU_MSG_DFCstateControl, 2177 state, 2178 NULL); 2179 } 2180 2181 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { 2182 .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, 2183 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, 2184 .is_dpm_running = smu_v13_0_7_is_dpm_running, 2185 .dump_pptable = smu_v13_0_7_dump_pptable, 2186 .init_microcode = smu_v13_0_init_microcode, 2187 .load_microcode = smu_v13_0_load_microcode, 2188 .fini_microcode = smu_v13_0_fini_microcode, 2189 .init_smc_tables = smu_v13_0_7_init_smc_tables, 2190 .fini_smc_tables = smu_v13_0_fini_smc_tables, 2191 .init_power = smu_v13_0_init_power, 2192 .fini_power = smu_v13_0_fini_power, 2193 .check_fw_status = smu_v13_0_7_check_fw_status, 2194 .setup_pptable = smu_v13_0_7_setup_pptable, 2195 .check_fw_version = smu_v13_0_check_fw_version, 2196 .write_pptable = smu_cmn_write_pptable, 2197 .set_driver_table_location = smu_v13_0_set_driver_table_location, 2198 .system_features_control = smu_v13_0_system_features_control, 2199 .set_allowed_mask = smu_v13_0_set_allowed_mask, 2200 .get_enabled_mask = smu_cmn_get_enabled_mask, 2201 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 2202 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 2203 .init_pptable_microcode = smu_v13_0_init_pptable_microcode, 2204 .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk, 2205 .get_dpm_ultimate_freq = smu_v13_0_7_get_dpm_ultimate_freq, 2206 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 2207 .read_sensor = smu_v13_0_7_read_sensor, 2208 .feature_is_enabled = smu_cmn_feature_is_enabled, 2209 .print_clk_levels = smu_v13_0_7_print_clk_levels, 2210 .force_clk_levels = smu_v13_0_7_force_clk_levels, 2211 .update_pcie_parameters = smu_v13_0_update_pcie_parameters, 2212 .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range, 2213 .register_irq_handler = smu_v13_0_register_irq_handler, 2214 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2215 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2216 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2217 .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics, 2218 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, 2219 .set_default_od_settings = smu_v13_0_7_set_default_od_settings, 2220 .restore_user_od_settings = smu_v13_0_7_restore_user_od_settings, 2221 .od_edit_dpm_table = smu_v13_0_7_od_edit_dpm_table, 2222 .set_performance_level = smu_v13_0_set_performance_level, 2223 .gfx_off_control = smu_v13_0_gfx_off_control, 2224 .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm, 2225 .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm, 2226 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, 2227 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm, 2228 .get_fan_control_mode = smu_v13_0_get_fan_control_mode, 2229 .set_fan_control_mode = smu_v13_0_set_fan_control_mode, 2230 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost, 2231 .get_power_limit = smu_v13_0_7_get_power_limit, 2232 .set_power_limit = smu_v13_0_set_power_limit, 2233 .set_power_source = smu_v13_0_set_power_source, 2234 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode, 2235 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode, 2236 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2237 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2238 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2239 .baco_is_support = smu_v13_0_baco_is_support, 2240 .baco_get_state = smu_v13_0_baco_get_state, 2241 .baco_set_state = smu_v13_0_baco_set_state, 2242 .baco_enter = smu_v13_0_7_baco_enter, 2243 .baco_exit = smu_v13_0_7_baco_exit, 2244 .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported, 2245 .mode1_reset = smu_v13_0_mode1_reset, 2246 .set_mp1_state = smu_v13_0_7_set_mp1_state, 2247 .set_df_cstate = smu_v13_0_7_set_df_cstate, 2248 .gpo_control = smu_v13_0_gpo_control, 2249 }; 2250 2251 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) 2252 { 2253 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs; 2254 smu->message_map = smu_v13_0_7_message_map; 2255 smu->clock_map = smu_v13_0_7_clk_map; 2256 smu->feature_map = smu_v13_0_7_feature_mask_map; 2257 smu->table_map = smu_v13_0_7_table_map; 2258 smu->pwr_src_map = smu_v13_0_7_pwr_src_map; 2259 smu->workload_map = smu_v13_0_7_workload_map; 2260 smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION; 2261 smu_v13_0_set_smu_mailbox_registers(smu); 2262 } 2263