1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v13_0.h" 35 #include "smu13_driver_if_v13_0_0.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "smu_v13_0_0_ppt.h" 39 #include "smu_v13_0_0_pptable.h" 40 #include "smu_v13_0_0_ppsmc.h" 41 #include "nbio/nbio_4_3_0_offset.h" 42 #include "nbio/nbio_4_3_0_sh_mask.h" 43 #include "mp/mp_13_0_0_offset.h" 44 #include "mp/mp_13_0_0_sh_mask.h" 45 46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "amdgpu_ras.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 70 71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 72 73 #define mmMP1_SMN_C2PMSG_66 0x0282 74 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 75 76 #define mmMP1_SMN_C2PMSG_82 0x0292 77 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 78 79 #define mmMP1_SMN_C2PMSG_90 0x029a 80 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 81 82 #define mmMP1_SMN_C2PMSG_75 0x028b 83 #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 84 85 #define mmMP1_SMN_C2PMSG_53 0x0275 86 #define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 87 88 #define mmMP1_SMN_C2PMSG_54 0x0276 89 #define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 90 91 #define DEBUGSMC_MSG_Mode1Reset 2 92 93 /* 94 * SMU_v13_0_10 supports ECCTABLE since version 80.34.0, 95 * use this to check ECCTABLE feature whether support 96 */ 97 #define SUPPORT_ECCTABLE_SMU_13_0_10_VERSION 0x00502200 98 99 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = { 100 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 101 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 102 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 103 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 104 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 105 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 106 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 107 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 108 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 109 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 110 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 111 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 112 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 113 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 114 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 115 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 116 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 117 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 118 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 119 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 120 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 121 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 122 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 123 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 124 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 132 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 133 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 134 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 135 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 136 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 137 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 138 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 139 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 140 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 141 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 142 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 143 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 144 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 145 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 146 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 147 MSG_MAP(Mode2Reset, PPSMC_MSG_Mode2Reset, 0), 148 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 149 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), 150 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 151 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0), 152 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel, 153 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0), 154 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0), 155 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0), 156 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 157 }; 158 159 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { 160 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 161 CLK_MAP(SCLK, PPCLK_GFXCLK), 162 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 163 CLK_MAP(FCLK, PPCLK_FCLK), 164 CLK_MAP(UCLK, PPCLK_UCLK), 165 CLK_MAP(MCLK, PPCLK_UCLK), 166 CLK_MAP(VCLK, PPCLK_VCLK_0), 167 CLK_MAP(VCLK1, PPCLK_VCLK_1), 168 CLK_MAP(DCLK, PPCLK_DCLK_0), 169 CLK_MAP(DCLK1, PPCLK_DCLK_1), 170 }; 171 172 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = { 173 FEA_MAP(FW_DATA_READ), 174 FEA_MAP(DPM_GFXCLK), 175 FEA_MAP(DPM_GFX_POWER_OPTIMIZER), 176 FEA_MAP(DPM_UCLK), 177 FEA_MAP(DPM_FCLK), 178 FEA_MAP(DPM_SOCCLK), 179 FEA_MAP(DPM_MP0CLK), 180 FEA_MAP(DPM_LINK), 181 FEA_MAP(DPM_DCN), 182 FEA_MAP(VMEMP_SCALING), 183 FEA_MAP(VDDIO_MEM_SCALING), 184 FEA_MAP(DS_GFXCLK), 185 FEA_MAP(DS_SOCCLK), 186 FEA_MAP(DS_FCLK), 187 FEA_MAP(DS_LCLK), 188 FEA_MAP(DS_DCFCLK), 189 FEA_MAP(DS_UCLK), 190 FEA_MAP(GFX_ULV), 191 FEA_MAP(FW_DSTATE), 192 FEA_MAP(GFXOFF), 193 FEA_MAP(BACO), 194 FEA_MAP(MM_DPM), 195 FEA_MAP(SOC_MPCLK_DS), 196 FEA_MAP(BACO_MPCLK_DS), 197 FEA_MAP(THROTTLERS), 198 FEA_MAP(SMARTSHIFT), 199 FEA_MAP(GTHR), 200 FEA_MAP(ACDC), 201 FEA_MAP(VR0HOT), 202 FEA_MAP(FW_CTF), 203 FEA_MAP(FAN_CONTROL), 204 FEA_MAP(GFX_DCS), 205 FEA_MAP(GFX_READ_MARGIN), 206 FEA_MAP(LED_DISPLAY), 207 FEA_MAP(GFXCLK_SPREAD_SPECTRUM), 208 FEA_MAP(OUT_OF_BAND_MONITOR), 209 FEA_MAP(OPTIMIZED_VMIN), 210 FEA_MAP(GFX_IMU), 211 FEA_MAP(BOOT_TIME_CAL), 212 FEA_MAP(GFX_PCC_DFLL), 213 FEA_MAP(SOC_CG), 214 FEA_MAP(DF_CSTATE), 215 FEA_MAP(GFX_EDC), 216 FEA_MAP(BOOT_POWER_OPT), 217 FEA_MAP(CLOCK_POWER_DOWN_BYPASS), 218 FEA_MAP(DS_VCN), 219 FEA_MAP(BACO_CG), 220 FEA_MAP(MEM_TEMP_READ), 221 FEA_MAP(ATHUB_MMHUB_PG), 222 FEA_MAP(SOC_PCC), 223 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, 224 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, 225 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT}, 226 }; 227 228 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = { 229 TAB_MAP(PPTABLE), 230 TAB_MAP(WATERMARKS), 231 TAB_MAP(AVFS_PSM_DEBUG), 232 TAB_MAP(PMSTATUSLOG), 233 TAB_MAP(SMU_METRICS), 234 TAB_MAP(DRIVER_SMU_CONFIG), 235 TAB_MAP(ACTIVITY_MONITOR_COEFF), 236 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE}, 237 TAB_MAP(I2C_COMMANDS), 238 TAB_MAP(ECCINFO), 239 TAB_MAP(OVERDRIVE), 240 }; 241 242 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 243 PWR_MAP(AC), 244 PWR_MAP(DC), 245 }; 246 247 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 251 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 252 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 253 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 254 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 255 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT), 256 }; 257 258 static const uint8_t smu_v13_0_0_throttler_map[] = { 259 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 260 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 261 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 262 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 263 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 264 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 265 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 266 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 267 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 268 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 269 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 270 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 271 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 272 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 273 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 274 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT), 275 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 276 }; 277 278 static int 279 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, 280 uint32_t *feature_mask, uint32_t num) 281 { 282 struct amdgpu_device *adev = smu->adev; 283 u32 smu_version; 284 285 if (num > 2) 286 return -EINVAL; 287 288 memset(feature_mask, 0xff, sizeof(uint32_t) * num); 289 290 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) { 291 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 292 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); 293 } 294 295 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || 296 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 297 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 298 299 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) 300 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 301 302 /* PMFW 78.58 contains a critical fix for gfxoff feature */ 303 smu_cmn_get_smc_version(smu, NULL, &smu_version); 304 if ((smu_version < 0x004e3a00) || 305 !(adev->pm.pp_feature & PP_GFXOFF_MASK)) 306 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); 307 308 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { 309 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 310 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 311 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 312 } 313 314 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) 315 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 316 317 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { 318 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); 319 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); 320 } 321 322 if (!(adev->pm.pp_feature & PP_ULV_MASK)) 323 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); 324 325 return 0; 326 } 327 328 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu) 329 { 330 struct smu_table_context *table_context = &smu->smu_table; 331 struct smu_13_0_0_powerplay_table *powerplay_table = 332 table_context->power_play_table; 333 struct smu_baco_context *smu_baco = &smu->smu_baco; 334 PPTable_t *pptable = smu->smu_table.driver_pptable; 335 const OverDriveLimits_t * const overdrive_upperlimits = 336 &pptable->SkuTable.OverDriveLimitsBasicMax; 337 const OverDriveLimits_t * const overdrive_lowerlimits = 338 &pptable->SkuTable.OverDriveLimitsMin; 339 340 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC) 341 smu->dc_controlled_by_gpio = true; 342 343 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO || 344 powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) 345 smu_baco->platform_support = true; 346 347 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) 348 smu_baco->maco_support = true; 349 350 if (!overdrive_lowerlimits->FeatureCtrlMask || 351 !overdrive_upperlimits->FeatureCtrlMask) 352 smu->od_enabled = false; 353 354 table_context->thermal_controller_type = 355 powerplay_table->thermal_controller_type; 356 357 /* 358 * Instead of having its own buffer space and get overdrive_table copied, 359 * smu->od_settings just points to the actual overdrive_table 360 */ 361 smu->od_settings = &powerplay_table->overdrive_table; 362 363 return 0; 364 } 365 366 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu) 367 { 368 struct smu_table_context *table_context = &smu->smu_table; 369 struct smu_13_0_0_powerplay_table *powerplay_table = 370 table_context->power_play_table; 371 372 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 373 sizeof(PPTable_t)); 374 375 return 0; 376 } 377 378 #ifndef atom_smc_dpm_info_table_13_0_0 379 struct atom_smc_dpm_info_table_13_0_0 { 380 struct atom_common_table_header table_header; 381 BoardTable_t BoardTable; 382 }; 383 #endif 384 385 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu) 386 { 387 struct smu_table_context *table_context = &smu->smu_table; 388 PPTable_t *smc_pptable = table_context->driver_pptable; 389 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table; 390 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 391 int index, ret; 392 393 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 394 smc_dpm_info); 395 396 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 397 (uint8_t **)&smc_dpm_table); 398 if (ret) 399 return ret; 400 401 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 402 403 return 0; 404 } 405 406 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu, 407 void **table, 408 uint32_t *size) 409 { 410 struct smu_table_context *smu_table = &smu->smu_table; 411 void *combo_pptable = smu_table->combo_pptable; 412 int ret = 0; 413 414 ret = smu_cmn_get_combo_pptable(smu); 415 if (ret) 416 return ret; 417 418 *table = combo_pptable; 419 *size = sizeof(struct smu_13_0_0_powerplay_table); 420 421 return 0; 422 } 423 424 static int smu_v13_0_0_setup_pptable(struct smu_context *smu) 425 { 426 struct smu_table_context *smu_table = &smu->smu_table; 427 struct amdgpu_device *adev = smu->adev; 428 int ret = 0; 429 430 if (amdgpu_sriov_vf(smu->adev)) 431 return 0; 432 433 ret = smu_v13_0_0_get_pptable_from_pmfw(smu, 434 &smu_table->power_play_table, 435 &smu_table->power_play_table_size); 436 if (ret) 437 return ret; 438 439 ret = smu_v13_0_0_store_powerplay_table(smu); 440 if (ret) 441 return ret; 442 443 /* 444 * With SCPM enabled, the operation below will be handled 445 * by PSP. Driver involvment is unnecessary and useless. 446 */ 447 if (!adev->scpm_enabled) { 448 ret = smu_v13_0_0_append_powerplay_table(smu); 449 if (ret) 450 return ret; 451 } 452 453 ret = smu_v13_0_0_check_powerplay_table(smu); 454 if (ret) 455 return ret; 456 457 return ret; 458 } 459 460 static int smu_v13_0_0_tables_init(struct smu_context *smu) 461 { 462 struct smu_table_context *smu_table = &smu->smu_table; 463 struct smu_table *tables = smu_table->tables; 464 465 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 466 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 467 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 468 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 469 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 470 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 471 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 472 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 473 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t), 474 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 475 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 476 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 477 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 478 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 479 AMDGPU_GEM_DOMAIN_VRAM); 480 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE, 481 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 482 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 483 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 484 485 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 486 if (!smu_table->metrics_table) 487 goto err0_out; 488 smu_table->metrics_time = 0; 489 490 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 491 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 492 if (!smu_table->gpu_metrics_table) 493 goto err1_out; 494 495 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 496 if (!smu_table->watermarks_table) 497 goto err2_out; 498 499 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 500 if (!smu_table->ecc_table) 501 goto err3_out; 502 503 return 0; 504 505 err3_out: 506 kfree(smu_table->watermarks_table); 507 err2_out: 508 kfree(smu_table->gpu_metrics_table); 509 err1_out: 510 kfree(smu_table->metrics_table); 511 err0_out: 512 return -ENOMEM; 513 } 514 515 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu) 516 { 517 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 518 519 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 520 GFP_KERNEL); 521 if (!smu_dpm->dpm_context) 522 return -ENOMEM; 523 524 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 525 526 return 0; 527 } 528 529 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu) 530 { 531 int ret = 0; 532 533 ret = smu_v13_0_0_tables_init(smu); 534 if (ret) 535 return ret; 536 537 ret = smu_v13_0_0_allocate_dpm_context(smu); 538 if (ret) 539 return ret; 540 541 return smu_v13_0_init_smc_tables(smu); 542 } 543 544 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) 545 { 546 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 547 struct smu_table_context *table_context = &smu->smu_table; 548 PPTable_t *pptable = table_context->driver_pptable; 549 SkuTable_t *skutable = &pptable->SkuTable; 550 struct smu_13_0_dpm_table *dpm_table; 551 struct smu_13_0_pcie_table *pcie_table; 552 uint32_t link_level; 553 int ret = 0; 554 555 /* socclk dpm table setup */ 556 dpm_table = &dpm_context->dpm_tables.soc_table; 557 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 558 ret = smu_v13_0_set_single_dpm_table(smu, 559 SMU_SOCCLK, 560 dpm_table); 561 if (ret) 562 return ret; 563 } else { 564 dpm_table->count = 1; 565 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 566 dpm_table->dpm_levels[0].enabled = true; 567 dpm_table->min = dpm_table->dpm_levels[0].value; 568 dpm_table->max = dpm_table->dpm_levels[0].value; 569 } 570 571 /* gfxclk dpm table setup */ 572 dpm_table = &dpm_context->dpm_tables.gfx_table; 573 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 574 ret = smu_v13_0_set_single_dpm_table(smu, 575 SMU_GFXCLK, 576 dpm_table); 577 if (ret) 578 return ret; 579 580 /* 581 * Update the reported maximum shader clock to the value 582 * which can be guarded to be achieved on all cards. This 583 * is aligned with Window setting. And considering that value 584 * might be not the peak frequency the card can achieve, it 585 * is normal some real-time clock frequency can overtake this 586 * labelled maximum clock frequency(for example in pp_dpm_sclk 587 * sysfs output). 588 */ 589 if (skutable->DriverReportedClocks.GameClockAc && 590 (dpm_table->dpm_levels[dpm_table->count - 1].value > 591 skutable->DriverReportedClocks.GameClockAc)) { 592 dpm_table->dpm_levels[dpm_table->count - 1].value = 593 skutable->DriverReportedClocks.GameClockAc; 594 dpm_table->max = skutable->DriverReportedClocks.GameClockAc; 595 } 596 } else { 597 dpm_table->count = 1; 598 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 599 dpm_table->dpm_levels[0].enabled = true; 600 dpm_table->min = dpm_table->dpm_levels[0].value; 601 dpm_table->max = dpm_table->dpm_levels[0].value; 602 } 603 604 /* uclk dpm table setup */ 605 dpm_table = &dpm_context->dpm_tables.uclk_table; 606 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 607 ret = smu_v13_0_set_single_dpm_table(smu, 608 SMU_UCLK, 609 dpm_table); 610 if (ret) 611 return ret; 612 } else { 613 dpm_table->count = 1; 614 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 615 dpm_table->dpm_levels[0].enabled = true; 616 dpm_table->min = dpm_table->dpm_levels[0].value; 617 dpm_table->max = dpm_table->dpm_levels[0].value; 618 } 619 620 /* fclk dpm table setup */ 621 dpm_table = &dpm_context->dpm_tables.fclk_table; 622 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 623 ret = smu_v13_0_set_single_dpm_table(smu, 624 SMU_FCLK, 625 dpm_table); 626 if (ret) 627 return ret; 628 } else { 629 dpm_table->count = 1; 630 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 631 dpm_table->dpm_levels[0].enabled = true; 632 dpm_table->min = dpm_table->dpm_levels[0].value; 633 dpm_table->max = dpm_table->dpm_levels[0].value; 634 } 635 636 /* vclk dpm table setup */ 637 dpm_table = &dpm_context->dpm_tables.vclk_table; 638 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { 639 ret = smu_v13_0_set_single_dpm_table(smu, 640 SMU_VCLK, 641 dpm_table); 642 if (ret) 643 return ret; 644 } else { 645 dpm_table->count = 1; 646 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 647 dpm_table->dpm_levels[0].enabled = true; 648 dpm_table->min = dpm_table->dpm_levels[0].value; 649 dpm_table->max = dpm_table->dpm_levels[0].value; 650 } 651 652 /* dclk dpm table setup */ 653 dpm_table = &dpm_context->dpm_tables.dclk_table; 654 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { 655 ret = smu_v13_0_set_single_dpm_table(smu, 656 SMU_DCLK, 657 dpm_table); 658 if (ret) 659 return ret; 660 } else { 661 dpm_table->count = 1; 662 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 663 dpm_table->dpm_levels[0].enabled = true; 664 dpm_table->min = dpm_table->dpm_levels[0].value; 665 dpm_table->max = dpm_table->dpm_levels[0].value; 666 } 667 668 /* lclk dpm table setup */ 669 pcie_table = &dpm_context->dpm_tables.pcie_table; 670 pcie_table->num_of_link_levels = 0; 671 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { 672 if (!skutable->PcieGenSpeed[link_level] && 673 !skutable->PcieLaneCount[link_level] && 674 !skutable->LclkFreq[link_level]) 675 continue; 676 677 pcie_table->pcie_gen[pcie_table->num_of_link_levels] = 678 skutable->PcieGenSpeed[link_level]; 679 pcie_table->pcie_lane[pcie_table->num_of_link_levels] = 680 skutable->PcieLaneCount[link_level]; 681 pcie_table->clk_freq[pcie_table->num_of_link_levels] = 682 skutable->LclkFreq[link_level]; 683 pcie_table->num_of_link_levels++; 684 } 685 686 return 0; 687 } 688 689 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) 690 { 691 int ret = 0; 692 uint64_t feature_enabled; 693 694 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 695 if (ret) 696 return false; 697 698 return !!(feature_enabled & SMC_DPM_FEATURE); 699 } 700 701 static void smu_v13_0_0_dump_pptable(struct smu_context *smu) 702 { 703 struct smu_table_context *table_context = &smu->smu_table; 704 PPTable_t *pptable = table_context->driver_pptable; 705 SkuTable_t *skutable = &pptable->SkuTable; 706 707 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 708 709 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version); 710 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]); 711 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]); 712 } 713 714 static int smu_v13_0_0_system_features_control(struct smu_context *smu, 715 bool en) 716 { 717 return smu_v13_0_system_features_control(smu, en); 718 } 719 720 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics) 721 { 722 uint32_t throttler_status = 0; 723 int i; 724 725 for (i = 0; i < THROTTLER_COUNT; i++) 726 throttler_status |= 727 (metrics->ThrottlingPercentage[i] ? 1U << i : 0); 728 729 return throttler_status; 730 } 731 732 #define SMU_13_0_0_BUSY_THRESHOLD 15 733 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu, 734 MetricsMember_t member, 735 uint32_t *value) 736 { 737 struct smu_table_context *smu_table = &smu->smu_table; 738 SmuMetrics_t *metrics = 739 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 740 int ret = 0; 741 742 ret = smu_cmn_get_metrics_table(smu, 743 NULL, 744 false); 745 if (ret) 746 return ret; 747 748 switch (member) { 749 case METRICS_CURR_GFXCLK: 750 *value = metrics->CurrClock[PPCLK_GFXCLK]; 751 break; 752 case METRICS_CURR_SOCCLK: 753 *value = metrics->CurrClock[PPCLK_SOCCLK]; 754 break; 755 case METRICS_CURR_UCLK: 756 *value = metrics->CurrClock[PPCLK_UCLK]; 757 break; 758 case METRICS_CURR_VCLK: 759 *value = metrics->CurrClock[PPCLK_VCLK_0]; 760 break; 761 case METRICS_CURR_VCLK1: 762 *value = metrics->CurrClock[PPCLK_VCLK_1]; 763 break; 764 case METRICS_CURR_DCLK: 765 *value = metrics->CurrClock[PPCLK_DCLK_0]; 766 break; 767 case METRICS_CURR_DCLK1: 768 *value = metrics->CurrClock[PPCLK_DCLK_1]; 769 break; 770 case METRICS_CURR_FCLK: 771 *value = metrics->CurrClock[PPCLK_FCLK]; 772 break; 773 case METRICS_AVERAGE_GFXCLK: 774 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 775 *value = metrics->AverageGfxclkFrequencyPostDs; 776 else 777 *value = metrics->AverageGfxclkFrequencyPreDs; 778 break; 779 case METRICS_AVERAGE_FCLK: 780 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 781 *value = metrics->AverageFclkFrequencyPostDs; 782 else 783 *value = metrics->AverageFclkFrequencyPreDs; 784 break; 785 case METRICS_AVERAGE_UCLK: 786 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 787 *value = metrics->AverageMemclkFrequencyPostDs; 788 else 789 *value = metrics->AverageMemclkFrequencyPreDs; 790 break; 791 case METRICS_AVERAGE_VCLK: 792 *value = metrics->AverageVclk0Frequency; 793 break; 794 case METRICS_AVERAGE_DCLK: 795 *value = metrics->AverageDclk0Frequency; 796 break; 797 case METRICS_AVERAGE_VCLK1: 798 *value = metrics->AverageVclk1Frequency; 799 break; 800 case METRICS_AVERAGE_DCLK1: 801 *value = metrics->AverageDclk1Frequency; 802 break; 803 case METRICS_AVERAGE_GFXACTIVITY: 804 *value = metrics->AverageGfxActivity; 805 break; 806 case METRICS_AVERAGE_MEMACTIVITY: 807 *value = metrics->AverageUclkActivity; 808 break; 809 case METRICS_AVERAGE_SOCKETPOWER: 810 *value = metrics->AverageSocketPower << 8; 811 break; 812 case METRICS_TEMPERATURE_EDGE: 813 *value = metrics->AvgTemperature[TEMP_EDGE] * 814 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 815 break; 816 case METRICS_TEMPERATURE_HOTSPOT: 817 *value = metrics->AvgTemperature[TEMP_HOTSPOT] * 818 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 819 break; 820 case METRICS_TEMPERATURE_MEM: 821 *value = metrics->AvgTemperature[TEMP_MEM] * 822 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 823 break; 824 case METRICS_TEMPERATURE_VRGFX: 825 *value = metrics->AvgTemperature[TEMP_VR_GFX] * 826 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 827 break; 828 case METRICS_TEMPERATURE_VRSOC: 829 *value = metrics->AvgTemperature[TEMP_VR_SOC] * 830 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 831 break; 832 case METRICS_THROTTLER_STATUS: 833 *value = smu_v13_0_get_throttler_status(metrics); 834 break; 835 case METRICS_CURR_FANSPEED: 836 *value = metrics->AvgFanRpm; 837 break; 838 case METRICS_CURR_FANPWM: 839 *value = metrics->AvgFanPwm; 840 break; 841 case METRICS_VOLTAGE_VDDGFX: 842 *value = metrics->AvgVoltage[SVI_PLANE_GFX]; 843 break; 844 case METRICS_PCIE_RATE: 845 *value = metrics->PcieRate; 846 break; 847 case METRICS_PCIE_WIDTH: 848 *value = metrics->PcieWidth; 849 break; 850 default: 851 *value = UINT_MAX; 852 break; 853 } 854 855 return ret; 856 } 857 858 static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu, 859 enum smu_clk_type clk_type, 860 uint32_t *min, 861 uint32_t *max) 862 { 863 struct smu_13_0_dpm_context *dpm_context = 864 smu->smu_dpm.dpm_context; 865 struct smu_13_0_dpm_table *dpm_table; 866 867 switch (clk_type) { 868 case SMU_MCLK: 869 case SMU_UCLK: 870 /* uclk dpm table */ 871 dpm_table = &dpm_context->dpm_tables.uclk_table; 872 break; 873 case SMU_GFXCLK: 874 case SMU_SCLK: 875 /* gfxclk dpm table */ 876 dpm_table = &dpm_context->dpm_tables.gfx_table; 877 break; 878 case SMU_SOCCLK: 879 /* socclk dpm table */ 880 dpm_table = &dpm_context->dpm_tables.soc_table; 881 break; 882 case SMU_FCLK: 883 /* fclk dpm table */ 884 dpm_table = &dpm_context->dpm_tables.fclk_table; 885 break; 886 case SMU_VCLK: 887 case SMU_VCLK1: 888 /* vclk dpm table */ 889 dpm_table = &dpm_context->dpm_tables.vclk_table; 890 break; 891 case SMU_DCLK: 892 case SMU_DCLK1: 893 /* dclk dpm table */ 894 dpm_table = &dpm_context->dpm_tables.dclk_table; 895 break; 896 default: 897 dev_err(smu->adev->dev, "Unsupported clock type!\n"); 898 return -EINVAL; 899 } 900 901 if (min) 902 *min = dpm_table->min; 903 if (max) 904 *max = dpm_table->max; 905 906 return 0; 907 } 908 909 static int smu_v13_0_0_read_sensor(struct smu_context *smu, 910 enum amd_pp_sensors sensor, 911 void *data, 912 uint32_t *size) 913 { 914 struct smu_table_context *table_context = &smu->smu_table; 915 PPTable_t *smc_pptable = table_context->driver_pptable; 916 int ret = 0; 917 918 switch (sensor) { 919 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 920 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm; 921 *size = 4; 922 break; 923 case AMDGPU_PP_SENSOR_MEM_LOAD: 924 ret = smu_v13_0_0_get_smu_metrics_data(smu, 925 METRICS_AVERAGE_MEMACTIVITY, 926 (uint32_t *)data); 927 *size = 4; 928 break; 929 case AMDGPU_PP_SENSOR_GPU_LOAD: 930 ret = smu_v13_0_0_get_smu_metrics_data(smu, 931 METRICS_AVERAGE_GFXACTIVITY, 932 (uint32_t *)data); 933 *size = 4; 934 break; 935 case AMDGPU_PP_SENSOR_GPU_POWER: 936 ret = smu_v13_0_0_get_smu_metrics_data(smu, 937 METRICS_AVERAGE_SOCKETPOWER, 938 (uint32_t *)data); 939 *size = 4; 940 break; 941 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 942 ret = smu_v13_0_0_get_smu_metrics_data(smu, 943 METRICS_TEMPERATURE_HOTSPOT, 944 (uint32_t *)data); 945 *size = 4; 946 break; 947 case AMDGPU_PP_SENSOR_EDGE_TEMP: 948 ret = smu_v13_0_0_get_smu_metrics_data(smu, 949 METRICS_TEMPERATURE_EDGE, 950 (uint32_t *)data); 951 *size = 4; 952 break; 953 case AMDGPU_PP_SENSOR_MEM_TEMP: 954 ret = smu_v13_0_0_get_smu_metrics_data(smu, 955 METRICS_TEMPERATURE_MEM, 956 (uint32_t *)data); 957 *size = 4; 958 break; 959 case AMDGPU_PP_SENSOR_GFX_MCLK: 960 ret = smu_v13_0_0_get_smu_metrics_data(smu, 961 METRICS_CURR_UCLK, 962 (uint32_t *)data); 963 *(uint32_t *)data *= 100; 964 *size = 4; 965 break; 966 case AMDGPU_PP_SENSOR_GFX_SCLK: 967 ret = smu_v13_0_0_get_smu_metrics_data(smu, 968 METRICS_AVERAGE_GFXCLK, 969 (uint32_t *)data); 970 *(uint32_t *)data *= 100; 971 *size = 4; 972 break; 973 case AMDGPU_PP_SENSOR_VDDGFX: 974 ret = smu_v13_0_0_get_smu_metrics_data(smu, 975 METRICS_VOLTAGE_VDDGFX, 976 (uint32_t *)data); 977 *size = 4; 978 break; 979 default: 980 ret = -EOPNOTSUPP; 981 break; 982 } 983 984 return ret; 985 } 986 987 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu, 988 enum smu_clk_type clk_type, 989 uint32_t *value) 990 { 991 MetricsMember_t member_type; 992 int clk_id = 0; 993 994 clk_id = smu_cmn_to_asic_specific_index(smu, 995 CMN2ASIC_MAPPING_CLK, 996 clk_type); 997 if (clk_id < 0) 998 return -EINVAL; 999 1000 switch (clk_id) { 1001 case PPCLK_GFXCLK: 1002 member_type = METRICS_AVERAGE_GFXCLK; 1003 break; 1004 case PPCLK_UCLK: 1005 member_type = METRICS_CURR_UCLK; 1006 break; 1007 case PPCLK_FCLK: 1008 member_type = METRICS_CURR_FCLK; 1009 break; 1010 case PPCLK_SOCCLK: 1011 member_type = METRICS_CURR_SOCCLK; 1012 break; 1013 case PPCLK_VCLK_0: 1014 member_type = METRICS_AVERAGE_VCLK; 1015 break; 1016 case PPCLK_DCLK_0: 1017 member_type = METRICS_AVERAGE_DCLK; 1018 break; 1019 case PPCLK_VCLK_1: 1020 member_type = METRICS_AVERAGE_VCLK1; 1021 break; 1022 case PPCLK_DCLK_1: 1023 member_type = METRICS_AVERAGE_DCLK1; 1024 break; 1025 default: 1026 return -EINVAL; 1027 } 1028 1029 return smu_v13_0_0_get_smu_metrics_data(smu, 1030 member_type, 1031 value); 1032 } 1033 1034 static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu, 1035 int od_feature_bit) 1036 { 1037 PPTable_t *pptable = smu->smu_table.driver_pptable; 1038 const OverDriveLimits_t * const overdrive_upperlimits = 1039 &pptable->SkuTable.OverDriveLimitsBasicMax; 1040 1041 return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); 1042 } 1043 1044 static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu, 1045 int od_feature_bit, 1046 bool lower_boundary, 1047 int32_t *min, 1048 int32_t *max) 1049 { 1050 PPTable_t *pptable = smu->smu_table.driver_pptable; 1051 const OverDriveLimits_t * const overdrive_upperlimits = 1052 &pptable->SkuTable.OverDriveLimitsBasicMax; 1053 const OverDriveLimits_t * const overdrive_lowerlimits = 1054 &pptable->SkuTable.OverDriveLimitsMin; 1055 int32_t od_min_setting, od_max_setting; 1056 1057 switch (od_feature_bit) { 1058 case PP_OD_FEATURE_GFXCLK_BIT: 1059 if (lower_boundary) { 1060 od_min_setting = overdrive_lowerlimits->GfxclkFmin; 1061 od_max_setting = overdrive_upperlimits->GfxclkFmin; 1062 } else { 1063 od_min_setting = overdrive_lowerlimits->GfxclkFmax; 1064 od_max_setting = overdrive_upperlimits->GfxclkFmax; 1065 } 1066 break; 1067 case PP_OD_FEATURE_UCLK_BIT: 1068 if (lower_boundary) { 1069 od_min_setting = overdrive_lowerlimits->UclkFmin; 1070 od_max_setting = overdrive_upperlimits->UclkFmin; 1071 } else { 1072 od_min_setting = overdrive_lowerlimits->UclkFmax; 1073 od_max_setting = overdrive_upperlimits->UclkFmax; 1074 } 1075 break; 1076 case PP_OD_FEATURE_GFX_VF_CURVE_BIT: 1077 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary; 1078 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary; 1079 break; 1080 default: 1081 break; 1082 } 1083 1084 if (min) 1085 *min = od_min_setting; 1086 if (max) 1087 *max = od_max_setting; 1088 } 1089 1090 static void smu_v13_0_0_dump_od_table(struct smu_context *smu, 1091 OverDriveTableExternal_t *od_table) 1092 { 1093 struct amdgpu_device *adev = smu->adev; 1094 1095 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin, 1096 od_table->OverDriveTable.GfxclkFmax); 1097 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin, 1098 od_table->OverDriveTable.UclkFmax); 1099 } 1100 1101 static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu, 1102 OverDriveTableExternal_t *od_table) 1103 { 1104 int ret = 0; 1105 1106 ret = smu_cmn_update_table(smu, 1107 SMU_TABLE_OVERDRIVE, 1108 0, 1109 (void *)od_table, 1110 false); 1111 if (ret) 1112 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 1113 1114 return ret; 1115 } 1116 1117 static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu, 1118 OverDriveTableExternal_t *od_table) 1119 { 1120 int ret = 0; 1121 1122 ret = smu_cmn_update_table(smu, 1123 SMU_TABLE_OVERDRIVE, 1124 0, 1125 (void *)od_table, 1126 true); 1127 if (ret) 1128 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n"); 1129 1130 return ret; 1131 } 1132 1133 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, 1134 enum smu_clk_type clk_type, 1135 char *buf) 1136 { 1137 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1138 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1139 OverDriveTableExternal_t *od_table = 1140 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; 1141 struct smu_13_0_dpm_table *single_dpm_table; 1142 struct smu_13_0_pcie_table *pcie_table; 1143 uint32_t gen_speed, lane_width; 1144 int i, curr_freq, size = 0; 1145 int32_t min_value, max_value; 1146 int ret = 0; 1147 1148 smu_cmn_get_sysfs_buf(&buf, &size); 1149 1150 if (amdgpu_ras_intr_triggered()) { 1151 size += sysfs_emit_at(buf, size, "unavailable\n"); 1152 return size; 1153 } 1154 1155 switch (clk_type) { 1156 case SMU_SCLK: 1157 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1158 break; 1159 case SMU_MCLK: 1160 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1161 break; 1162 case SMU_SOCCLK: 1163 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1164 break; 1165 case SMU_FCLK: 1166 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1167 break; 1168 case SMU_VCLK: 1169 case SMU_VCLK1: 1170 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1171 break; 1172 case SMU_DCLK: 1173 case SMU_DCLK1: 1174 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1175 break; 1176 default: 1177 break; 1178 } 1179 1180 switch (clk_type) { 1181 case SMU_SCLK: 1182 case SMU_MCLK: 1183 case SMU_SOCCLK: 1184 case SMU_FCLK: 1185 case SMU_VCLK: 1186 case SMU_VCLK1: 1187 case SMU_DCLK: 1188 case SMU_DCLK1: 1189 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); 1190 if (ret) { 1191 dev_err(smu->adev->dev, "Failed to get current clock freq!"); 1192 return ret; 1193 } 1194 1195 if (single_dpm_table->is_fine_grained) { 1196 /* 1197 * For fine grained dpms, there are only two dpm levels: 1198 * - level 0 -> min clock freq 1199 * - level 1 -> max clock freq 1200 * And the current clock frequency can be any value between them. 1201 * So, if the current clock frequency is not at level 0 or level 1, 1202 * we will fake it as three dpm levels: 1203 * - level 0 -> min clock freq 1204 * - level 1 -> current actual clock freq 1205 * - level 2 -> max clock freq 1206 */ 1207 if ((single_dpm_table->dpm_levels[0].value != curr_freq) && 1208 (single_dpm_table->dpm_levels[1].value != curr_freq)) { 1209 size += sysfs_emit_at(buf, size, "0: %uMhz\n", 1210 single_dpm_table->dpm_levels[0].value); 1211 size += sysfs_emit_at(buf, size, "1: %uMhz *\n", 1212 curr_freq); 1213 size += sysfs_emit_at(buf, size, "2: %uMhz\n", 1214 single_dpm_table->dpm_levels[1].value); 1215 } else { 1216 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 1217 single_dpm_table->dpm_levels[0].value, 1218 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); 1219 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 1220 single_dpm_table->dpm_levels[1].value, 1221 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); 1222 } 1223 } else { 1224 for (i = 0; i < single_dpm_table->count; i++) 1225 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 1226 i, single_dpm_table->dpm_levels[i].value, 1227 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); 1228 } 1229 break; 1230 case SMU_PCIE: 1231 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1232 METRICS_PCIE_RATE, 1233 &gen_speed); 1234 if (ret) 1235 return ret; 1236 1237 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1238 METRICS_PCIE_WIDTH, 1239 &lane_width); 1240 if (ret) 1241 return ret; 1242 1243 pcie_table = &(dpm_context->dpm_tables.pcie_table); 1244 for (i = 0; i < pcie_table->num_of_link_levels; i++) 1245 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1246 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : 1247 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : 1248 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : 1249 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", 1250 (pcie_table->pcie_lane[i] == 1) ? "x1" : 1251 (pcie_table->pcie_lane[i] == 2) ? "x2" : 1252 (pcie_table->pcie_lane[i] == 3) ? "x4" : 1253 (pcie_table->pcie_lane[i] == 4) ? "x8" : 1254 (pcie_table->pcie_lane[i] == 5) ? "x12" : 1255 (pcie_table->pcie_lane[i] == 6) ? "x16" : "", 1256 pcie_table->clk_freq[i], 1257 (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) && 1258 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? 1259 "*" : ""); 1260 break; 1261 1262 case SMU_OD_SCLK: 1263 if (!smu_v13_0_0_is_od_feature_supported(smu, 1264 PP_OD_FEATURE_GFXCLK_BIT)) 1265 break; 1266 1267 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1268 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", 1269 od_table->OverDriveTable.GfxclkFmin, 1270 od_table->OverDriveTable.GfxclkFmax); 1271 break; 1272 1273 case SMU_OD_MCLK: 1274 if (!smu_v13_0_0_is_od_feature_supported(smu, 1275 PP_OD_FEATURE_UCLK_BIT)) 1276 break; 1277 1278 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1279 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", 1280 od_table->OverDriveTable.UclkFmin, 1281 od_table->OverDriveTable.UclkFmax); 1282 break; 1283 1284 case SMU_OD_VDDC_CURVE: 1285 if (!smu_v13_0_0_is_od_feature_supported(smu, 1286 PP_OD_FEATURE_GFX_VF_CURVE_BIT)) 1287 break; 1288 1289 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n"); 1290 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++) 1291 size += sysfs_emit_at(buf, size, "%d: %dmv\n", 1292 i, 1293 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i]); 1294 break; 1295 1296 case SMU_OD_RANGE: 1297 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) && 1298 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) && 1299 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) 1300 break; 1301 1302 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1303 1304 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) { 1305 smu_v13_0_0_get_od_setting_limits(smu, 1306 PP_OD_FEATURE_GFXCLK_BIT, 1307 true, 1308 &min_value, 1309 NULL); 1310 smu_v13_0_0_get_od_setting_limits(smu, 1311 PP_OD_FEATURE_GFXCLK_BIT, 1312 false, 1313 NULL, 1314 &max_value); 1315 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1316 min_value, max_value); 1317 } 1318 1319 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) { 1320 smu_v13_0_0_get_od_setting_limits(smu, 1321 PP_OD_FEATURE_UCLK_BIT, 1322 true, 1323 &min_value, 1324 NULL); 1325 smu_v13_0_0_get_od_setting_limits(smu, 1326 PP_OD_FEATURE_UCLK_BIT, 1327 false, 1328 NULL, 1329 &max_value); 1330 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1331 min_value, max_value); 1332 } 1333 1334 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) { 1335 smu_v13_0_0_get_od_setting_limits(smu, 1336 PP_OD_FEATURE_GFX_VF_CURVE_BIT, 1337 true, 1338 &min_value, 1339 &max_value); 1340 size += sysfs_emit_at(buf, size, "VDDC_CURVE: %7dmv %10dmv\n", 1341 min_value, max_value); 1342 } 1343 break; 1344 1345 default: 1346 break; 1347 } 1348 1349 return size; 1350 } 1351 1352 static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu, 1353 enum PP_OD_DPM_TABLE_COMMAND type, 1354 long input[], 1355 uint32_t size) 1356 { 1357 struct smu_table_context *table_context = &smu->smu_table; 1358 OverDriveTableExternal_t *od_table = 1359 (OverDriveTableExternal_t *)table_context->overdrive_table; 1360 struct amdgpu_device *adev = smu->adev; 1361 uint32_t offset_of_featurectrlmask; 1362 int32_t minimum, maximum; 1363 uint32_t feature_ctrlmask; 1364 int i, ret = 0; 1365 1366 switch (type) { 1367 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1368 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) { 1369 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n"); 1370 return -ENOTSUPP; 1371 } 1372 1373 for (i = 0; i < size; i += 2) { 1374 if (i + 2 > size) { 1375 dev_info(adev->dev, "invalid number of input parameters %d\n", size); 1376 return -EINVAL; 1377 } 1378 1379 switch (input[i]) { 1380 case 0: 1381 smu_v13_0_0_get_od_setting_limits(smu, 1382 PP_OD_FEATURE_GFXCLK_BIT, 1383 true, 1384 &minimum, 1385 &maximum); 1386 if (input[i + 1] < minimum || 1387 input[i + 1] > maximum) { 1388 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n", 1389 input[i + 1], minimum, maximum); 1390 return -EINVAL; 1391 } 1392 1393 od_table->OverDriveTable.GfxclkFmin = input[i + 1]; 1394 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT; 1395 break; 1396 1397 case 1: 1398 smu_v13_0_0_get_od_setting_limits(smu, 1399 PP_OD_FEATURE_GFXCLK_BIT, 1400 false, 1401 &minimum, 1402 &maximum); 1403 if (input[i + 1] < minimum || 1404 input[i + 1] > maximum) { 1405 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n", 1406 input[i + 1], minimum, maximum); 1407 return -EINVAL; 1408 } 1409 1410 od_table->OverDriveTable.GfxclkFmax = input[i + 1]; 1411 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT; 1412 break; 1413 1414 default: 1415 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 1416 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n"); 1417 return -EINVAL; 1418 } 1419 } 1420 1421 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) { 1422 dev_err(adev->dev, 1423 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n", 1424 (uint32_t)od_table->OverDriveTable.GfxclkFmin, 1425 (uint32_t)od_table->OverDriveTable.GfxclkFmax); 1426 return -EINVAL; 1427 } 1428 break; 1429 1430 case PP_OD_EDIT_MCLK_VDDC_TABLE: 1431 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) { 1432 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n"); 1433 return -ENOTSUPP; 1434 } 1435 1436 for (i = 0; i < size; i += 2) { 1437 if (i + 2 > size) { 1438 dev_info(adev->dev, "invalid number of input parameters %d\n", size); 1439 return -EINVAL; 1440 } 1441 1442 switch (input[i]) { 1443 case 0: 1444 smu_v13_0_0_get_od_setting_limits(smu, 1445 PP_OD_FEATURE_UCLK_BIT, 1446 true, 1447 &minimum, 1448 &maximum); 1449 if (input[i + 1] < minimum || 1450 input[i + 1] > maximum) { 1451 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n", 1452 input[i + 1], minimum, maximum); 1453 return -EINVAL; 1454 } 1455 1456 od_table->OverDriveTable.UclkFmin = input[i + 1]; 1457 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT; 1458 break; 1459 1460 case 1: 1461 smu_v13_0_0_get_od_setting_limits(smu, 1462 PP_OD_FEATURE_UCLK_BIT, 1463 false, 1464 &minimum, 1465 &maximum); 1466 if (input[i + 1] < minimum || 1467 input[i + 1] > maximum) { 1468 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n", 1469 input[i + 1], minimum, maximum); 1470 return -EINVAL; 1471 } 1472 1473 od_table->OverDriveTable.UclkFmax = input[i + 1]; 1474 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT; 1475 break; 1476 1477 default: 1478 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 1479 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n"); 1480 return -EINVAL; 1481 } 1482 } 1483 1484 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) { 1485 dev_err(adev->dev, 1486 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n", 1487 (uint32_t)od_table->OverDriveTable.UclkFmin, 1488 (uint32_t)od_table->OverDriveTable.UclkFmax); 1489 return -EINVAL; 1490 } 1491 break; 1492 1493 case PP_OD_EDIT_VDDC_CURVE: 1494 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) { 1495 dev_warn(adev->dev, "VF curve setting not supported!\n"); 1496 return -ENOTSUPP; 1497 } 1498 1499 if (input[0] >= PP_NUM_OD_VF_CURVE_POINTS || 1500 input[0] < 0) 1501 return -EINVAL; 1502 1503 smu_v13_0_0_get_od_setting_limits(smu, 1504 PP_OD_FEATURE_GFX_VF_CURVE_BIT, 1505 true, 1506 &minimum, 1507 &maximum); 1508 if (input[1] < minimum || 1509 input[1] > maximum) { 1510 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n", 1511 input[1], minimum, maximum); 1512 return -EINVAL; 1513 } 1514 1515 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[input[0]] = input[1]; 1516 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFX_VF_CURVE_BIT; 1517 break; 1518 1519 case PP_OD_RESTORE_DEFAULT_TABLE: 1520 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask; 1521 memcpy(od_table, 1522 table_context->boot_overdrive_table, 1523 sizeof(OverDriveTableExternal_t)); 1524 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask; 1525 fallthrough; 1526 1527 case PP_OD_COMMIT_DPM_TABLE: 1528 /* 1529 * The member below instructs PMFW the settings focused in 1530 * this single operation. 1531 * `uint32_t FeatureCtrlMask;` 1532 * It does not contain actual informations about user's custom 1533 * settings. Thus we do not cache it. 1534 */ 1535 offset_of_featurectrlmask = offsetof(OverDriveTable_t, FeatureCtrlMask); 1536 if (memcmp((u8 *)od_table + offset_of_featurectrlmask, 1537 table_context->user_overdrive_table + offset_of_featurectrlmask, 1538 sizeof(OverDriveTableExternal_t) - offset_of_featurectrlmask)) { 1539 smu_v13_0_0_dump_od_table(smu, od_table); 1540 1541 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table); 1542 if (ret) { 1543 dev_err(adev->dev, "Failed to upload overdrive table!\n"); 1544 return ret; 1545 } 1546 1547 od_table->OverDriveTable.FeatureCtrlMask = 0; 1548 memcpy(table_context->user_overdrive_table + offset_of_featurectrlmask, 1549 (u8 *)od_table + offset_of_featurectrlmask, 1550 sizeof(OverDriveTableExternal_t) - offset_of_featurectrlmask); 1551 1552 if (!memcmp(table_context->user_overdrive_table, 1553 table_context->boot_overdrive_table, 1554 sizeof(OverDriveTableExternal_t))) 1555 smu->user_dpm_profile.user_od = false; 1556 else 1557 smu->user_dpm_profile.user_od = true; 1558 } 1559 break; 1560 1561 default: 1562 return -ENOSYS; 1563 } 1564 1565 return ret; 1566 } 1567 1568 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu, 1569 enum smu_clk_type clk_type, 1570 uint32_t mask) 1571 { 1572 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1573 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1574 struct smu_13_0_dpm_table *single_dpm_table; 1575 uint32_t soft_min_level, soft_max_level; 1576 uint32_t min_freq, max_freq; 1577 int ret = 0; 1578 1579 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1580 soft_max_level = mask ? (fls(mask) - 1) : 0; 1581 1582 switch (clk_type) { 1583 case SMU_GFXCLK: 1584 case SMU_SCLK: 1585 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1586 break; 1587 case SMU_MCLK: 1588 case SMU_UCLK: 1589 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1590 break; 1591 case SMU_SOCCLK: 1592 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1593 break; 1594 case SMU_FCLK: 1595 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1596 break; 1597 case SMU_VCLK: 1598 case SMU_VCLK1: 1599 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1600 break; 1601 case SMU_DCLK: 1602 case SMU_DCLK1: 1603 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1604 break; 1605 default: 1606 break; 1607 } 1608 1609 switch (clk_type) { 1610 case SMU_GFXCLK: 1611 case SMU_SCLK: 1612 case SMU_MCLK: 1613 case SMU_UCLK: 1614 case SMU_SOCCLK: 1615 case SMU_FCLK: 1616 case SMU_VCLK: 1617 case SMU_VCLK1: 1618 case SMU_DCLK: 1619 case SMU_DCLK1: 1620 if (single_dpm_table->is_fine_grained) { 1621 /* There is only 2 levels for fine grained DPM */ 1622 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1623 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1624 } else { 1625 if ((soft_max_level >= single_dpm_table->count) || 1626 (soft_min_level >= single_dpm_table->count)) 1627 return -EINVAL; 1628 } 1629 1630 min_freq = single_dpm_table->dpm_levels[soft_min_level].value; 1631 max_freq = single_dpm_table->dpm_levels[soft_max_level].value; 1632 1633 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1634 clk_type, 1635 min_freq, 1636 max_freq); 1637 break; 1638 case SMU_DCEFCLK: 1639 case SMU_PCIE: 1640 default: 1641 break; 1642 } 1643 1644 return ret; 1645 } 1646 1647 static const struct smu_temperature_range smu13_thermal_policy[] = { 1648 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 1649 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 1650 }; 1651 1652 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu, 1653 struct smu_temperature_range *range) 1654 { 1655 struct smu_table_context *table_context = &smu->smu_table; 1656 struct smu_13_0_0_powerplay_table *powerplay_table = 1657 table_context->power_play_table; 1658 PPTable_t *pptable = smu->smu_table.driver_pptable; 1659 1660 if (amdgpu_sriov_vf(smu->adev)) 1661 return 0; 1662 1663 if (!range) 1664 return -EINVAL; 1665 1666 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1667 1668 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] * 1669 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1670 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1671 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1672 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] * 1673 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1674 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1675 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1676 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] * 1677 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1678 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1679 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1680 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1681 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset; 1682 1683 return 0; 1684 } 1685 1686 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 1687 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, 1688 void **table) 1689 { 1690 struct smu_table_context *smu_table = &smu->smu_table; 1691 struct gpu_metrics_v1_3 *gpu_metrics = 1692 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1693 SmuMetricsExternal_t metrics_ext; 1694 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 1695 int ret = 0; 1696 1697 ret = smu_cmn_get_metrics_table(smu, 1698 &metrics_ext, 1699 true); 1700 if (ret) 1701 return ret; 1702 1703 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1704 1705 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE]; 1706 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT]; 1707 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM]; 1708 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX]; 1709 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC]; 1710 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0], 1711 metrics->AvgTemperature[TEMP_VR_MEM1]); 1712 1713 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 1714 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 1715 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage, 1716 metrics->Vcn1ActivityPercentage); 1717 1718 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 1719 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 1720 1721 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 1722 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 1723 else 1724 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 1725 1726 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 1727 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 1728 else 1729 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs; 1730 1731 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 1732 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 1733 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 1734 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 1735 1736 gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency; 1737 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK]; 1738 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; 1739 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 1740 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 1741 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 1742 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 1743 1744 gpu_metrics->throttle_status = 1745 smu_v13_0_get_throttler_status(metrics); 1746 gpu_metrics->indep_throttle_status = 1747 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 1748 smu_v13_0_0_throttler_map); 1749 1750 gpu_metrics->current_fan_speed = metrics->AvgFanRpm; 1751 1752 gpu_metrics->pcie_link_width = metrics->PcieWidth; 1753 gpu_metrics->pcie_link_speed = metrics->PcieRate; 1754 1755 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1756 1757 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX]; 1758 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC]; 1759 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP]; 1760 1761 *table = (void *)gpu_metrics; 1762 1763 return sizeof(struct gpu_metrics_v1_3); 1764 } 1765 1766 static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu) 1767 { 1768 OverDriveTableExternal_t *od_table = 1769 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; 1770 OverDriveTableExternal_t *boot_od_table = 1771 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table; 1772 OverDriveTableExternal_t *user_od_table = 1773 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table; 1774 OverDriveTableExternal_t user_od_table_bak; 1775 int ret = 0; 1776 int i; 1777 1778 ret = smu_v13_0_0_get_overdrive_table(smu, boot_od_table); 1779 if (ret) 1780 return ret; 1781 1782 smu_v13_0_0_dump_od_table(smu, boot_od_table); 1783 1784 memcpy(od_table, 1785 boot_od_table, 1786 sizeof(OverDriveTableExternal_t)); 1787 1788 /* 1789 * For S3/S4/Runpm resume, we need to setup those overdrive tables again, 1790 * but we have to preserve user defined values in "user_od_table". 1791 */ 1792 if (!smu->adev->in_suspend) { 1793 memcpy(user_od_table, 1794 boot_od_table, 1795 sizeof(OverDriveTableExternal_t)); 1796 smu->user_dpm_profile.user_od = false; 1797 } else if (smu->user_dpm_profile.user_od) { 1798 memcpy(&user_od_table_bak, 1799 user_od_table, 1800 sizeof(OverDriveTableExternal_t)); 1801 memcpy(user_od_table, 1802 boot_od_table, 1803 sizeof(OverDriveTableExternal_t)); 1804 user_od_table->OverDriveTable.GfxclkFmin = 1805 user_od_table_bak.OverDriveTable.GfxclkFmin; 1806 user_od_table->OverDriveTable.GfxclkFmax = 1807 user_od_table_bak.OverDriveTable.GfxclkFmax; 1808 user_od_table->OverDriveTable.UclkFmin = 1809 user_od_table_bak.OverDriveTable.UclkFmin; 1810 user_od_table->OverDriveTable.UclkFmax = 1811 user_od_table_bak.OverDriveTable.UclkFmax; 1812 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++) 1813 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = 1814 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i]; 1815 } 1816 1817 return 0; 1818 } 1819 1820 static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu) 1821 { 1822 struct smu_table_context *table_context = &smu->smu_table; 1823 OverDriveTableExternal_t *od_table = table_context->overdrive_table; 1824 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table; 1825 int res; 1826 1827 user_od_table->OverDriveTable.FeatureCtrlMask = 1U << PP_OD_FEATURE_GFXCLK_BIT | 1828 1U << PP_OD_FEATURE_UCLK_BIT | 1829 1U << PP_OD_FEATURE_GFX_VF_CURVE_BIT; 1830 res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table); 1831 user_od_table->OverDriveTable.FeatureCtrlMask = 0; 1832 if (res == 0) 1833 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t)); 1834 1835 return res; 1836 } 1837 1838 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu) 1839 { 1840 struct smu_13_0_dpm_context *dpm_context = 1841 smu->smu_dpm.dpm_context; 1842 struct smu_13_0_dpm_table *gfx_table = 1843 &dpm_context->dpm_tables.gfx_table; 1844 struct smu_13_0_dpm_table *mem_table = 1845 &dpm_context->dpm_tables.uclk_table; 1846 struct smu_13_0_dpm_table *soc_table = 1847 &dpm_context->dpm_tables.soc_table; 1848 struct smu_13_0_dpm_table *vclk_table = 1849 &dpm_context->dpm_tables.vclk_table; 1850 struct smu_13_0_dpm_table *dclk_table = 1851 &dpm_context->dpm_tables.dclk_table; 1852 struct smu_13_0_dpm_table *fclk_table = 1853 &dpm_context->dpm_tables.fclk_table; 1854 struct smu_umd_pstate_table *pstate_table = 1855 &smu->pstate_table; 1856 struct smu_table_context *table_context = &smu->smu_table; 1857 PPTable_t *pptable = table_context->driver_pptable; 1858 DriverReportedClocks_t driver_clocks = 1859 pptable->SkuTable.DriverReportedClocks; 1860 1861 pstate_table->gfxclk_pstate.min = gfx_table->min; 1862 if (driver_clocks.GameClockAc && 1863 (driver_clocks.GameClockAc < gfx_table->max)) 1864 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc; 1865 else 1866 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1867 1868 pstate_table->uclk_pstate.min = mem_table->min; 1869 pstate_table->uclk_pstate.peak = mem_table->max; 1870 1871 pstate_table->socclk_pstate.min = soc_table->min; 1872 pstate_table->socclk_pstate.peak = soc_table->max; 1873 1874 pstate_table->vclk_pstate.min = vclk_table->min; 1875 pstate_table->vclk_pstate.peak = vclk_table->max; 1876 1877 pstate_table->dclk_pstate.min = dclk_table->min; 1878 pstate_table->dclk_pstate.peak = dclk_table->max; 1879 1880 pstate_table->fclk_pstate.min = fclk_table->min; 1881 pstate_table->fclk_pstate.peak = fclk_table->max; 1882 1883 if (driver_clocks.BaseClockAc && 1884 driver_clocks.BaseClockAc < gfx_table->max) 1885 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc; 1886 else 1887 pstate_table->gfxclk_pstate.standard = gfx_table->max; 1888 pstate_table->uclk_pstate.standard = mem_table->max; 1889 pstate_table->socclk_pstate.standard = soc_table->min; 1890 pstate_table->vclk_pstate.standard = vclk_table->min; 1891 pstate_table->dclk_pstate.standard = dclk_table->min; 1892 pstate_table->fclk_pstate.standard = fclk_table->min; 1893 1894 return 0; 1895 } 1896 1897 static void smu_v13_0_0_get_unique_id(struct smu_context *smu) 1898 { 1899 struct smu_table_context *smu_table = &smu->smu_table; 1900 SmuMetrics_t *metrics = 1901 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 1902 struct amdgpu_device *adev = smu->adev; 1903 uint32_t upper32 = 0, lower32 = 0; 1904 int ret; 1905 1906 ret = smu_cmn_get_metrics_table(smu, NULL, false); 1907 if (ret) 1908 goto out; 1909 1910 upper32 = metrics->PublicSerialNumberUpper; 1911 lower32 = metrics->PublicSerialNumberLower; 1912 1913 out: 1914 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1915 if (adev->serial[0] == '\0') 1916 sprintf(adev->serial, "%016llx", adev->unique_id); 1917 } 1918 1919 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu, 1920 uint32_t *speed) 1921 { 1922 int ret; 1923 1924 if (!speed) 1925 return -EINVAL; 1926 1927 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1928 METRICS_CURR_FANPWM, 1929 speed); 1930 if (ret) { 1931 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!"); 1932 return ret; 1933 } 1934 1935 /* Convert the PMFW output which is in percent to pwm(255) based */ 1936 *speed = MIN(*speed * 255 / 100, 255); 1937 1938 return 0; 1939 } 1940 1941 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu, 1942 uint32_t *speed) 1943 { 1944 if (!speed) 1945 return -EINVAL; 1946 1947 return smu_v13_0_0_get_smu_metrics_data(smu, 1948 METRICS_CURR_FANSPEED, 1949 speed); 1950 } 1951 1952 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu) 1953 { 1954 struct smu_table_context *table_context = &smu->smu_table; 1955 PPTable_t *pptable = table_context->driver_pptable; 1956 SkuTable_t *skutable = &pptable->SkuTable; 1957 1958 /* 1959 * Skip the MGpuFanBoost setting for those ASICs 1960 * which do not support it 1961 */ 1962 if (skutable->MGpuAcousticLimitRpmThreshold == 0) 1963 return 0; 1964 1965 return smu_cmn_send_smc_msg_with_param(smu, 1966 SMU_MSG_SetMGpuFanBoostLimitRpm, 1967 0, 1968 NULL); 1969 } 1970 1971 static int smu_v13_0_0_get_power_limit(struct smu_context *smu, 1972 uint32_t *current_power_limit, 1973 uint32_t *default_power_limit, 1974 uint32_t *max_power_limit) 1975 { 1976 struct smu_table_context *table_context = &smu->smu_table; 1977 struct smu_13_0_0_powerplay_table *powerplay_table = 1978 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table; 1979 PPTable_t *pptable = table_context->driver_pptable; 1980 SkuTable_t *skutable = &pptable->SkuTable; 1981 uint32_t power_limit, od_percent; 1982 1983 if (smu_v13_0_get_current_power_limit(smu, &power_limit)) 1984 power_limit = smu->adev->pm.ac_power ? 1985 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] : 1986 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0]; 1987 1988 if (current_power_limit) 1989 *current_power_limit = power_limit; 1990 if (default_power_limit) 1991 *default_power_limit = power_limit; 1992 1993 if (max_power_limit) { 1994 if (smu->od_enabled) { 1995 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]); 1996 1997 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1998 1999 power_limit *= (100 + od_percent); 2000 power_limit /= 100; 2001 } 2002 *max_power_limit = power_limit; 2003 } 2004 2005 return 0; 2006 } 2007 2008 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu, 2009 char *buf) 2010 { 2011 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 2012 DpmActivityMonitorCoeffInt_t *activity_monitor = 2013 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 2014 static const char *title[] = { 2015 "PROFILE_INDEX(NAME)", 2016 "CLOCK_TYPE(NAME)", 2017 "FPS", 2018 "MinActiveFreqType", 2019 "MinActiveFreq", 2020 "BoosterFreqType", 2021 "BoosterFreq", 2022 "PD_Data_limit_c", 2023 "PD_Data_error_coeff", 2024 "PD_Data_error_rate_coeff"}; 2025 int16_t workload_type = 0; 2026 uint32_t i, size = 0; 2027 int result = 0; 2028 2029 if (!buf) 2030 return -EINVAL; 2031 2032 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n", 2033 title[0], title[1], title[2], title[3], title[4], title[5], 2034 title[6], title[7], title[8], title[9]); 2035 2036 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2037 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 2038 workload_type = smu_cmn_to_asic_specific_index(smu, 2039 CMN2ASIC_MAPPING_WORKLOAD, 2040 i); 2041 if (workload_type == -ENOTSUPP) 2042 continue; 2043 else if (workload_type < 0) 2044 return -EINVAL; 2045 2046 result = smu_cmn_update_table(smu, 2047 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 2048 workload_type, 2049 (void *)(&activity_monitor_external), 2050 false); 2051 if (result) { 2052 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2053 return result; 2054 } 2055 2056 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 2057 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 2058 2059 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 2060 " ", 2061 0, 2062 "GFXCLK", 2063 activity_monitor->Gfx_FPS, 2064 activity_monitor->Gfx_MinActiveFreqType, 2065 activity_monitor->Gfx_MinActiveFreq, 2066 activity_monitor->Gfx_BoosterFreqType, 2067 activity_monitor->Gfx_BoosterFreq, 2068 activity_monitor->Gfx_PD_Data_limit_c, 2069 activity_monitor->Gfx_PD_Data_error_coeff, 2070 activity_monitor->Gfx_PD_Data_error_rate_coeff); 2071 2072 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 2073 " ", 2074 1, 2075 "FCLK", 2076 activity_monitor->Fclk_FPS, 2077 activity_monitor->Fclk_MinActiveFreqType, 2078 activity_monitor->Fclk_MinActiveFreq, 2079 activity_monitor->Fclk_BoosterFreqType, 2080 activity_monitor->Fclk_BoosterFreq, 2081 activity_monitor->Fclk_PD_Data_limit_c, 2082 activity_monitor->Fclk_PD_Data_error_coeff, 2083 activity_monitor->Fclk_PD_Data_error_rate_coeff); 2084 } 2085 2086 return size; 2087 } 2088 2089 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, 2090 long *input, 2091 uint32_t size) 2092 { 2093 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 2094 DpmActivityMonitorCoeffInt_t *activity_monitor = 2095 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 2096 int workload_type, ret = 0; 2097 2098 smu->power_profile_mode = input[size]; 2099 2100 if (smu->power_profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { 2101 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 2102 return -EINVAL; 2103 } 2104 2105 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 2106 ret = smu_cmn_update_table(smu, 2107 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 2108 WORKLOAD_PPLIB_CUSTOM_BIT, 2109 (void *)(&activity_monitor_external), 2110 false); 2111 if (ret) { 2112 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2113 return ret; 2114 } 2115 2116 switch (input[0]) { 2117 case 0: /* Gfxclk */ 2118 activity_monitor->Gfx_FPS = input[1]; 2119 activity_monitor->Gfx_MinActiveFreqType = input[2]; 2120 activity_monitor->Gfx_MinActiveFreq = input[3]; 2121 activity_monitor->Gfx_BoosterFreqType = input[4]; 2122 activity_monitor->Gfx_BoosterFreq = input[5]; 2123 activity_monitor->Gfx_PD_Data_limit_c = input[6]; 2124 activity_monitor->Gfx_PD_Data_error_coeff = input[7]; 2125 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8]; 2126 break; 2127 case 1: /* Fclk */ 2128 activity_monitor->Fclk_FPS = input[1]; 2129 activity_monitor->Fclk_MinActiveFreqType = input[2]; 2130 activity_monitor->Fclk_MinActiveFreq = input[3]; 2131 activity_monitor->Fclk_BoosterFreqType = input[4]; 2132 activity_monitor->Fclk_BoosterFreq = input[5]; 2133 activity_monitor->Fclk_PD_Data_limit_c = input[6]; 2134 activity_monitor->Fclk_PD_Data_error_coeff = input[7]; 2135 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; 2136 break; 2137 } 2138 2139 ret = smu_cmn_update_table(smu, 2140 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 2141 WORKLOAD_PPLIB_CUSTOM_BIT, 2142 (void *)(&activity_monitor_external), 2143 true); 2144 if (ret) { 2145 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 2146 return ret; 2147 } 2148 } 2149 2150 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE && 2151 (((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xC8)) || 2152 ((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xCC)))) { 2153 ret = smu_cmn_update_table(smu, 2154 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 2155 WORKLOAD_PPLIB_COMPUTE_BIT, 2156 (void *)(&activity_monitor_external), 2157 false); 2158 if (ret) { 2159 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2160 return ret; 2161 } 2162 2163 ret = smu_cmn_update_table(smu, 2164 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 2165 WORKLOAD_PPLIB_CUSTOM_BIT, 2166 (void *)(&activity_monitor_external), 2167 true); 2168 if (ret) { 2169 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 2170 return ret; 2171 } 2172 2173 workload_type = smu_cmn_to_asic_specific_index(smu, 2174 CMN2ASIC_MAPPING_WORKLOAD, 2175 PP_SMC_POWER_PROFILE_CUSTOM); 2176 } else { 2177 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 2178 workload_type = smu_cmn_to_asic_specific_index(smu, 2179 CMN2ASIC_MAPPING_WORKLOAD, 2180 smu->power_profile_mode); 2181 } 2182 2183 if (workload_type < 0) 2184 return -EINVAL; 2185 2186 return smu_cmn_send_smc_msg_with_param(smu, 2187 SMU_MSG_SetWorkloadMask, 2188 1 << workload_type, 2189 NULL); 2190 } 2191 2192 static int smu_v13_0_0_baco_enter(struct smu_context *smu) 2193 { 2194 struct smu_baco_context *smu_baco = &smu->smu_baco; 2195 struct amdgpu_device *adev = smu->adev; 2196 2197 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2198 return smu_v13_0_baco_set_armd3_sequence(smu, 2199 smu_baco->maco_support ? BACO_SEQ_BAMACO : BACO_SEQ_BACO); 2200 else 2201 return smu_v13_0_baco_enter(smu); 2202 } 2203 2204 static int smu_v13_0_0_baco_exit(struct smu_context *smu) 2205 { 2206 struct amdgpu_device *adev = smu->adev; 2207 2208 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2209 /* Wait for PMFW handling for the Dstate change */ 2210 usleep_range(10000, 11000); 2211 return smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2212 } else { 2213 return smu_v13_0_baco_exit(smu); 2214 } 2215 } 2216 2217 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) 2218 { 2219 struct amdgpu_device *adev = smu->adev; 2220 u32 smu_version; 2221 2222 /* SRIOV does not support SMU mode1 reset */ 2223 if (amdgpu_sriov_vf(adev)) 2224 return false; 2225 2226 /* PMFW support is available since 78.41 */ 2227 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2228 if (smu_version < 0x004e2900) 2229 return false; 2230 2231 return true; 2232 } 2233 2234 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap, 2235 struct i2c_msg *msg, int num_msgs) 2236 { 2237 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2238 struct amdgpu_device *adev = smu_i2c->adev; 2239 struct smu_context *smu = adev->powerplay.pp_handle; 2240 struct smu_table_context *smu_table = &smu->smu_table; 2241 struct smu_table *table = &smu_table->driver_table; 2242 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2243 int i, j, r, c; 2244 u16 dir; 2245 2246 if (!adev->pm.dpm_enabled) 2247 return -EBUSY; 2248 2249 req = kzalloc(sizeof(*req), GFP_KERNEL); 2250 if (!req) 2251 return -ENOMEM; 2252 2253 req->I2CcontrollerPort = smu_i2c->port; 2254 req->I2CSpeed = I2C_SPEED_FAST_400K; 2255 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2256 dir = msg[0].flags & I2C_M_RD; 2257 2258 for (c = i = 0; i < num_msgs; i++) { 2259 for (j = 0; j < msg[i].len; j++, c++) { 2260 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 2261 2262 if (!(msg[i].flags & I2C_M_RD)) { 2263 /* write */ 2264 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 2265 cmd->ReadWriteData = msg[i].buf[j]; 2266 } 2267 2268 if ((dir ^ msg[i].flags) & I2C_M_RD) { 2269 /* The direction changes. 2270 */ 2271 dir = msg[i].flags & I2C_M_RD; 2272 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 2273 } 2274 2275 req->NumCmds++; 2276 2277 /* 2278 * Insert STOP if we are at the last byte of either last 2279 * message for the transaction or the client explicitly 2280 * requires a STOP at this particular message. 2281 */ 2282 if ((j == msg[i].len - 1) && 2283 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 2284 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 2285 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 2286 } 2287 } 2288 } 2289 mutex_lock(&adev->pm.mutex); 2290 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2291 if (r) 2292 goto fail; 2293 2294 for (c = i = 0; i < num_msgs; i++) { 2295 if (!(msg[i].flags & I2C_M_RD)) { 2296 c += msg[i].len; 2297 continue; 2298 } 2299 for (j = 0; j < msg[i].len; j++, c++) { 2300 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 2301 2302 msg[i].buf[j] = cmd->ReadWriteData; 2303 } 2304 } 2305 r = num_msgs; 2306 fail: 2307 mutex_unlock(&adev->pm.mutex); 2308 kfree(req); 2309 return r; 2310 } 2311 2312 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap) 2313 { 2314 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 2315 } 2316 2317 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = { 2318 .master_xfer = smu_v13_0_0_i2c_xfer, 2319 .functionality = smu_v13_0_0_i2c_func, 2320 }; 2321 2322 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = { 2323 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 2324 .max_read_len = MAX_SW_I2C_COMMANDS, 2325 .max_write_len = MAX_SW_I2C_COMMANDS, 2326 .max_comb_1st_msg_len = 2, 2327 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 2328 }; 2329 2330 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu) 2331 { 2332 struct amdgpu_device *adev = smu->adev; 2333 int res, i; 2334 2335 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2336 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2337 struct i2c_adapter *control = &smu_i2c->adapter; 2338 2339 smu_i2c->adev = adev; 2340 smu_i2c->port = i; 2341 mutex_init(&smu_i2c->mutex); 2342 control->owner = THIS_MODULE; 2343 control->class = I2C_CLASS_SPD; 2344 control->dev.parent = &adev->pdev->dev; 2345 control->algo = &smu_v13_0_0_i2c_algo; 2346 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 2347 control->quirks = &smu_v13_0_0_i2c_control_quirks; 2348 i2c_set_adapdata(control, smu_i2c); 2349 2350 res = i2c_add_adapter(control); 2351 if (res) { 2352 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2353 goto Out_err; 2354 } 2355 } 2356 2357 /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 2358 /* XXX ideally this would be something in a vbios data table */ 2359 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 2360 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 2361 2362 return 0; 2363 Out_err: 2364 for ( ; i >= 0; i--) { 2365 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2366 struct i2c_adapter *control = &smu_i2c->adapter; 2367 2368 i2c_del_adapter(control); 2369 } 2370 return res; 2371 } 2372 2373 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu) 2374 { 2375 struct amdgpu_device *adev = smu->adev; 2376 int i; 2377 2378 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2379 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2380 struct i2c_adapter *control = &smu_i2c->adapter; 2381 2382 i2c_del_adapter(control); 2383 } 2384 adev->pm.ras_eeprom_i2c_bus = NULL; 2385 adev->pm.fru_eeprom_i2c_bus = NULL; 2386 } 2387 2388 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu, 2389 enum pp_mp1_state mp1_state) 2390 { 2391 int ret; 2392 2393 switch (mp1_state) { 2394 case PP_MP1_STATE_UNLOAD: 2395 ret = smu_cmn_set_mp1_state(smu, mp1_state); 2396 break; 2397 default: 2398 /* Ignore others */ 2399 ret = 0; 2400 } 2401 2402 return ret; 2403 } 2404 2405 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu, 2406 enum pp_df_cstate state) 2407 { 2408 return smu_cmn_send_smc_msg_with_param(smu, 2409 SMU_MSG_DFCstateControl, 2410 state, 2411 NULL); 2412 } 2413 2414 static void smu_v13_0_0_set_mode1_reset_param(struct smu_context *smu, 2415 uint32_t supported_version, 2416 uint32_t *param) 2417 { 2418 uint32_t smu_version; 2419 struct amdgpu_device *adev = smu->adev; 2420 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 2421 2422 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2423 2424 if ((smu_version >= supported_version) && 2425 ras && atomic_read(&ras->in_recovery)) 2426 /* Set RAS fatal error reset flag */ 2427 *param = 1 << 16; 2428 else 2429 *param = 0; 2430 } 2431 2432 static int smu_v13_0_0_mode1_reset(struct smu_context *smu) 2433 { 2434 int ret; 2435 uint32_t param; 2436 struct amdgpu_device *adev = smu->adev; 2437 2438 switch (adev->ip_versions[MP1_HWIP][0]) { 2439 case IP_VERSION(13, 0, 0): 2440 /* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */ 2441 smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, ¶m); 2442 2443 ret = smu_cmn_send_smc_msg_with_param(smu, 2444 SMU_MSG_Mode1Reset, param, NULL); 2445 break; 2446 2447 case IP_VERSION(13, 0, 10): 2448 /* SMU 13_0_10 PMFW supports RAS fatal error reset from 80.28 */ 2449 smu_v13_0_0_set_mode1_reset_param(smu, 0x00501c00, ¶m); 2450 2451 ret = smu_cmn_send_debug_smc_msg_with_param(smu, 2452 DEBUGSMC_MSG_Mode1Reset, param); 2453 break; 2454 2455 default: 2456 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 2457 break; 2458 } 2459 2460 if (!ret) 2461 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 2462 2463 return ret; 2464 } 2465 2466 static int smu_v13_0_0_mode2_reset(struct smu_context *smu) 2467 { 2468 int ret; 2469 struct amdgpu_device *adev = smu->adev; 2470 2471 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) 2472 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode2Reset, NULL); 2473 else 2474 return -EOPNOTSUPP; 2475 2476 return ret; 2477 } 2478 2479 static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu) 2480 { 2481 struct amdgpu_device *adev = smu->adev; 2482 2483 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) 2484 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures, 2485 FEATURE_PWR_GFX, NULL); 2486 else 2487 return -EOPNOTSUPP; 2488 } 2489 2490 static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu) 2491 { 2492 struct amdgpu_device *adev = smu->adev; 2493 2494 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2495 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2496 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2497 2498 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); 2499 smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); 2500 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); 2501 } 2502 2503 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu, 2504 uint32_t size) 2505 { 2506 int ret = 0; 2507 2508 /* message SMU to update the bad page number on SMUBUS */ 2509 ret = smu_cmn_send_smc_msg_with_param(smu, 2510 SMU_MSG_SetNumBadMemoryPagesRetired, 2511 size, NULL); 2512 if (ret) 2513 dev_err(smu->adev->dev, 2514 "[%s] failed to message SMU to update bad memory pages number\n", 2515 __func__); 2516 2517 return ret; 2518 } 2519 2520 static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu, 2521 uint32_t size) 2522 { 2523 int ret = 0; 2524 2525 /* message SMU to update the bad channel info on SMUBUS */ 2526 ret = smu_cmn_send_smc_msg_with_param(smu, 2527 SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 2528 size, NULL); 2529 if (ret) 2530 dev_err(smu->adev->dev, 2531 "[%s] failed to message SMU to update bad memory pages channel info\n", 2532 __func__); 2533 2534 return ret; 2535 } 2536 2537 static int smu_v13_0_0_check_ecc_table_support(struct smu_context *smu) 2538 { 2539 struct amdgpu_device *adev = smu->adev; 2540 uint32_t if_version = 0xff, smu_version = 0xff; 2541 int ret = 0; 2542 2543 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 2544 if (ret) 2545 return -EOPNOTSUPP; 2546 2547 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) && 2548 (smu_version >= SUPPORT_ECCTABLE_SMU_13_0_10_VERSION)) 2549 return ret; 2550 else 2551 return -EOPNOTSUPP; 2552 } 2553 2554 static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu, 2555 void *table) 2556 { 2557 struct smu_table_context *smu_table = &smu->smu_table; 2558 struct amdgpu_device *adev = smu->adev; 2559 EccInfoTable_t *ecc_table = NULL; 2560 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 2561 int i, ret = 0; 2562 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 2563 2564 ret = smu_v13_0_0_check_ecc_table_support(smu); 2565 if (ret) 2566 return ret; 2567 2568 ret = smu_cmn_update_table(smu, 2569 SMU_TABLE_ECCINFO, 2570 0, 2571 smu_table->ecc_table, 2572 false); 2573 if (ret) { 2574 dev_info(adev->dev, "Failed to export SMU ecc table!\n"); 2575 return ret; 2576 } 2577 2578 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 2579 2580 for (i = 0; i < ARRAY_SIZE(ecc_table->EccInfo); i++) { 2581 ecc_info_per_channel = &(eccinfo->ecc[i]); 2582 ecc_info_per_channel->ce_count_lo_chip = 2583 ecc_table->EccInfo[i].ce_count_lo_chip; 2584 ecc_info_per_channel->ce_count_hi_chip = 2585 ecc_table->EccInfo[i].ce_count_hi_chip; 2586 ecc_info_per_channel->mca_umc_status = 2587 ecc_table->EccInfo[i].mca_umc_status; 2588 ecc_info_per_channel->mca_umc_addr = 2589 ecc_table->EccInfo[i].mca_umc_addr; 2590 } 2591 2592 return ret; 2593 } 2594 2595 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { 2596 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, 2597 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, 2598 .i2c_init = smu_v13_0_0_i2c_control_init, 2599 .i2c_fini = smu_v13_0_0_i2c_control_fini, 2600 .is_dpm_running = smu_v13_0_0_is_dpm_running, 2601 .dump_pptable = smu_v13_0_0_dump_pptable, 2602 .init_microcode = smu_v13_0_init_microcode, 2603 .load_microcode = smu_v13_0_load_microcode, 2604 .fini_microcode = smu_v13_0_fini_microcode, 2605 .init_smc_tables = smu_v13_0_0_init_smc_tables, 2606 .fini_smc_tables = smu_v13_0_fini_smc_tables, 2607 .init_power = smu_v13_0_init_power, 2608 .fini_power = smu_v13_0_fini_power, 2609 .check_fw_status = smu_v13_0_check_fw_status, 2610 .setup_pptable = smu_v13_0_0_setup_pptable, 2611 .check_fw_version = smu_v13_0_check_fw_version, 2612 .write_pptable = smu_cmn_write_pptable, 2613 .set_driver_table_location = smu_v13_0_set_driver_table_location, 2614 .system_features_control = smu_v13_0_0_system_features_control, 2615 .set_allowed_mask = smu_v13_0_set_allowed_mask, 2616 .get_enabled_mask = smu_cmn_get_enabled_mask, 2617 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 2618 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 2619 .get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq, 2620 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 2621 .read_sensor = smu_v13_0_0_read_sensor, 2622 .feature_is_enabled = smu_cmn_feature_is_enabled, 2623 .print_clk_levels = smu_v13_0_0_print_clk_levels, 2624 .force_clk_levels = smu_v13_0_0_force_clk_levels, 2625 .update_pcie_parameters = smu_v13_0_update_pcie_parameters, 2626 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range, 2627 .register_irq_handler = smu_v13_0_register_irq_handler, 2628 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2629 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2630 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2631 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics, 2632 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, 2633 .set_default_od_settings = smu_v13_0_0_set_default_od_settings, 2634 .restore_user_od_settings = smu_v13_0_0_restore_user_od_settings, 2635 .od_edit_dpm_table = smu_v13_0_0_od_edit_dpm_table, 2636 .init_pptable_microcode = smu_v13_0_init_pptable_microcode, 2637 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk, 2638 .set_performance_level = smu_v13_0_set_performance_level, 2639 .gfx_off_control = smu_v13_0_gfx_off_control, 2640 .get_unique_id = smu_v13_0_0_get_unique_id, 2641 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm, 2642 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm, 2643 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, 2644 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm, 2645 .get_fan_control_mode = smu_v13_0_get_fan_control_mode, 2646 .set_fan_control_mode = smu_v13_0_set_fan_control_mode, 2647 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, 2648 .get_power_limit = smu_v13_0_0_get_power_limit, 2649 .set_power_limit = smu_v13_0_set_power_limit, 2650 .set_power_source = smu_v13_0_set_power_source, 2651 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, 2652 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, 2653 .run_btc = smu_v13_0_run_btc, 2654 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2655 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2656 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2657 .deep_sleep_control = smu_v13_0_deep_sleep_control, 2658 .gfx_ulv_control = smu_v13_0_gfx_ulv_control, 2659 .baco_is_support = smu_v13_0_baco_is_support, 2660 .baco_get_state = smu_v13_0_baco_get_state, 2661 .baco_set_state = smu_v13_0_baco_set_state, 2662 .baco_enter = smu_v13_0_0_baco_enter, 2663 .baco_exit = smu_v13_0_0_baco_exit, 2664 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported, 2665 .mode1_reset = smu_v13_0_0_mode1_reset, 2666 .mode2_reset = smu_v13_0_0_mode2_reset, 2667 .enable_gfx_features = smu_v13_0_0_enable_gfx_features, 2668 .set_mp1_state = smu_v13_0_0_set_mp1_state, 2669 .set_df_cstate = smu_v13_0_0_set_df_cstate, 2670 .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num, 2671 .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag, 2672 .gpo_control = smu_v13_0_gpo_control, 2673 .get_ecc_info = smu_v13_0_0_get_ecc_info, 2674 }; 2675 2676 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) 2677 { 2678 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs; 2679 smu->message_map = smu_v13_0_0_message_map; 2680 smu->clock_map = smu_v13_0_0_clk_map; 2681 smu->feature_map = smu_v13_0_0_feature_mask_map; 2682 smu->table_map = smu_v13_0_0_table_map; 2683 smu->pwr_src_map = smu_v13_0_0_pwr_src_map; 2684 smu->workload_map = smu_v13_0_0_workload_map; 2685 smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION; 2686 smu_v13_0_0_set_smu_mailbox_registers(smu); 2687 } 2688