1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v13_0.h" 35 #include "smu13_driver_if_v13_0_0.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "smu_v13_0_0_ppt.h" 39 #include "smu_v13_0_0_pptable.h" 40 #include "smu_v13_0_0_ppsmc.h" 41 #include "nbio/nbio_4_3_0_offset.h" 42 #include "nbio/nbio_4_3_0_sh_mask.h" 43 #include "mp/mp_13_0_0_offset.h" 44 #include "mp/mp_13_0_0_sh_mask.h" 45 46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "amdgpu_ras.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 70 71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 72 73 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = { 74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 77 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 78 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 79 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 80 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 81 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 82 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 83 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 84 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 85 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 86 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 87 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 88 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 89 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 90 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 91 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 92 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 93 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 94 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 95 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 96 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 97 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 98 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 99 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 100 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 101 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 102 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 103 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 104 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 105 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 106 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 107 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 108 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 109 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 110 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 112 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 113 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 114 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 115 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 116 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 117 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 118 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 119 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 120 }; 121 122 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { 123 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 124 CLK_MAP(SCLK, PPCLK_GFXCLK), 125 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 126 CLK_MAP(FCLK, PPCLK_FCLK), 127 CLK_MAP(UCLK, PPCLK_UCLK), 128 CLK_MAP(MCLK, PPCLK_UCLK), 129 CLK_MAP(VCLK, PPCLK_VCLK_0), 130 CLK_MAP(VCLK1, PPCLK_VCLK_1), 131 CLK_MAP(DCLK, PPCLK_DCLK_0), 132 CLK_MAP(DCLK1, PPCLK_DCLK_1), 133 }; 134 135 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = { 136 FEA_MAP(FW_DATA_READ), 137 FEA_MAP(DPM_GFXCLK), 138 FEA_MAP(DPM_GFX_POWER_OPTIMIZER), 139 FEA_MAP(DPM_UCLK), 140 FEA_MAP(DPM_FCLK), 141 FEA_MAP(DPM_SOCCLK), 142 FEA_MAP(DPM_MP0CLK), 143 FEA_MAP(DPM_LINK), 144 FEA_MAP(DPM_DCN), 145 FEA_MAP(VMEMP_SCALING), 146 FEA_MAP(VDDIO_MEM_SCALING), 147 FEA_MAP(DS_GFXCLK), 148 FEA_MAP(DS_SOCCLK), 149 FEA_MAP(DS_FCLK), 150 FEA_MAP(DS_LCLK), 151 FEA_MAP(DS_DCFCLK), 152 FEA_MAP(DS_UCLK), 153 FEA_MAP(GFX_ULV), 154 FEA_MAP(FW_DSTATE), 155 FEA_MAP(GFXOFF), 156 FEA_MAP(BACO), 157 FEA_MAP(MM_DPM), 158 FEA_MAP(SOC_MPCLK_DS), 159 FEA_MAP(BACO_MPCLK_DS), 160 FEA_MAP(THROTTLERS), 161 FEA_MAP(SMARTSHIFT), 162 FEA_MAP(GTHR), 163 FEA_MAP(ACDC), 164 FEA_MAP(VR0HOT), 165 FEA_MAP(FW_CTF), 166 FEA_MAP(FAN_CONTROL), 167 FEA_MAP(GFX_DCS), 168 FEA_MAP(GFX_READ_MARGIN), 169 FEA_MAP(LED_DISPLAY), 170 FEA_MAP(GFXCLK_SPREAD_SPECTRUM), 171 FEA_MAP(OUT_OF_BAND_MONITOR), 172 FEA_MAP(OPTIMIZED_VMIN), 173 FEA_MAP(GFX_IMU), 174 FEA_MAP(BOOT_TIME_CAL), 175 FEA_MAP(GFX_PCC_DFLL), 176 FEA_MAP(SOC_CG), 177 FEA_MAP(DF_CSTATE), 178 FEA_MAP(GFX_EDC), 179 FEA_MAP(BOOT_POWER_OPT), 180 FEA_MAP(CLOCK_POWER_DOWN_BYPASS), 181 FEA_MAP(DS_VCN), 182 FEA_MAP(BACO_CG), 183 FEA_MAP(MEM_TEMP_READ), 184 FEA_MAP(ATHUB_MMHUB_PG), 185 FEA_MAP(SOC_PCC), 186 }; 187 188 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = { 189 TAB_MAP(PPTABLE), 190 TAB_MAP(WATERMARKS), 191 TAB_MAP(AVFS_PSM_DEBUG), 192 TAB_MAP(PMSTATUSLOG), 193 TAB_MAP(SMU_METRICS), 194 TAB_MAP(DRIVER_SMU_CONFIG), 195 TAB_MAP(ACTIVITY_MONITOR_COEFF), 196 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE}, 197 }; 198 199 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 200 PWR_MAP(AC), 201 PWR_MAP(DC), 202 }; 203 204 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 212 }; 213 214 static const uint8_t smu_v13_0_0_throttler_map[] = { 215 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 216 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 217 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 218 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 219 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 220 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 221 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 222 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 223 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 224 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 225 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 226 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 227 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 228 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 229 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 230 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT), 231 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 232 }; 233 234 static int 235 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, 236 uint32_t *feature_mask, uint32_t num) 237 { 238 struct amdgpu_device *adev = smu->adev; 239 240 if (num > 2) 241 return -EINVAL; 242 243 memset(feature_mask, 0, sizeof(uint32_t) * num); 244 245 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); 246 247 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 248 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 249 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); 250 } 251 252 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); 253 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); 254 255 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) && 256 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 257 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 258 259 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 260 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 261 262 #if 0 263 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 264 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 265 #endif 266 267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT); 268 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT); 269 270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT); 271 272 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { 273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 275 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 276 } 277 278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); 279 280 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT); 284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); 285 286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); 287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_DCFCLK_BIT); 289 290 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) { 291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 293 } 294 295 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); 296 297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); 298 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); 299 300 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 301 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); 302 303 return 0; 304 } 305 306 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu) 307 { 308 struct smu_table_context *table_context = &smu->smu_table; 309 struct smu_13_0_0_powerplay_table *powerplay_table = 310 table_context->power_play_table; 311 struct smu_baco_context *smu_baco = &smu->smu_baco; 312 313 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC) 314 smu->dc_controlled_by_gpio = true; 315 316 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO || 317 powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) 318 smu_baco->platform_support = true; 319 320 table_context->thermal_controller_type = 321 powerplay_table->thermal_controller_type; 322 323 /* 324 * Instead of having its own buffer space and get overdrive_table copied, 325 * smu->od_settings just points to the actual overdrive_table 326 */ 327 smu->od_settings = &powerplay_table->overdrive_table; 328 329 return 0; 330 } 331 332 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu) 333 { 334 struct smu_table_context *table_context = &smu->smu_table; 335 struct smu_13_0_0_powerplay_table *powerplay_table = 336 table_context->power_play_table; 337 338 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 339 sizeof(PPTable_t)); 340 341 return 0; 342 } 343 344 #ifndef atom_smc_dpm_info_table_13_0_0 345 struct atom_smc_dpm_info_table_13_0_0 { 346 struct atom_common_table_header table_header; 347 BoardTable_t BoardTable; 348 }; 349 #endif 350 351 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu) 352 { 353 struct smu_table_context *table_context = &smu->smu_table; 354 PPTable_t *smc_pptable = table_context->driver_pptable; 355 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table; 356 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 357 int index, ret; 358 359 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 360 smc_dpm_info); 361 362 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 363 (uint8_t **)&smc_dpm_table); 364 if (ret) 365 return ret; 366 367 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 368 369 return 0; 370 } 371 372 static int smu_v13_0_0_setup_pptable(struct smu_context *smu) 373 { 374 struct smu_table_context *smu_table = &smu->smu_table; 375 void *combo_pptable = smu_table->combo_pptable; 376 struct amdgpu_device *adev = smu->adev; 377 int ret = 0; 378 379 /* 380 * With SCPM enabled, the pptable used will be signed. It cannot 381 * be used directly by driver. To get the raw pptable, we need to 382 * rely on the combo pptable(and its revelant SMU message). 383 */ 384 if (adev->scpm_enabled) { 385 ret = smu_cmn_get_combo_pptable(smu); 386 if (ret) 387 return ret; 388 389 smu->smu_table.power_play_table = combo_pptable; 390 smu->smu_table.power_play_table_size = sizeof(struct smu_13_0_0_powerplay_table); 391 } else { 392 ret = smu_v13_0_setup_pptable(smu); 393 if (ret) 394 return ret; 395 } 396 397 ret = smu_v13_0_0_store_powerplay_table(smu); 398 if (ret) 399 return ret; 400 401 /* 402 * With SCPM enabled, the operation below will be handled 403 * by PSP. Driver involvment is unnecessary and useless. 404 */ 405 if (!adev->scpm_enabled) { 406 ret = smu_v13_0_0_append_powerplay_table(smu); 407 if (ret) 408 return ret; 409 } 410 411 ret = smu_v13_0_0_check_powerplay_table(smu); 412 if (ret) 413 return ret; 414 415 return ret; 416 } 417 418 static int smu_v13_0_0_tables_init(struct smu_context *smu) 419 { 420 struct smu_table_context *smu_table = &smu->smu_table; 421 struct smu_table *tables = smu_table->tables; 422 423 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 424 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 425 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 426 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 427 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 428 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 429 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 430 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 431 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 432 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 433 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 434 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 435 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 436 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 437 AMDGPU_GEM_DOMAIN_VRAM); 438 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE, 439 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 440 441 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 442 if (!smu_table->metrics_table) 443 goto err0_out; 444 smu_table->metrics_time = 0; 445 446 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 447 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 448 if (!smu_table->gpu_metrics_table) 449 goto err1_out; 450 451 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 452 if (!smu_table->watermarks_table) 453 goto err2_out; 454 455 return 0; 456 457 err2_out: 458 kfree(smu_table->gpu_metrics_table); 459 err1_out: 460 kfree(smu_table->metrics_table); 461 err0_out: 462 return -ENOMEM; 463 } 464 465 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu) 466 { 467 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 468 469 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 470 GFP_KERNEL); 471 if (!smu_dpm->dpm_context) 472 return -ENOMEM; 473 474 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 475 476 return 0; 477 } 478 479 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu) 480 { 481 int ret = 0; 482 483 ret = smu_v13_0_0_tables_init(smu); 484 if (ret) 485 return ret; 486 487 ret = smu_v13_0_0_allocate_dpm_context(smu); 488 if (ret) 489 return ret; 490 491 return smu_v13_0_init_smc_tables(smu); 492 } 493 494 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) 495 { 496 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 497 struct smu_table_context *table_context = &smu->smu_table; 498 PPTable_t *pptable = table_context->driver_pptable; 499 SkuTable_t *skutable = &pptable->SkuTable; 500 struct smu_13_0_dpm_table *dpm_table; 501 struct smu_13_0_pcie_table *pcie_table; 502 uint32_t link_level; 503 int ret = 0; 504 505 /* socclk dpm table setup */ 506 dpm_table = &dpm_context->dpm_tables.soc_table; 507 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 508 ret = smu_v13_0_set_single_dpm_table(smu, 509 SMU_SOCCLK, 510 dpm_table); 511 if (ret) 512 return ret; 513 } else { 514 dpm_table->count = 1; 515 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 516 dpm_table->dpm_levels[0].enabled = true; 517 dpm_table->min = dpm_table->dpm_levels[0].value; 518 dpm_table->max = dpm_table->dpm_levels[0].value; 519 } 520 521 /* gfxclk dpm table setup */ 522 dpm_table = &dpm_context->dpm_tables.gfx_table; 523 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 524 ret = smu_v13_0_set_single_dpm_table(smu, 525 SMU_GFXCLK, 526 dpm_table); 527 if (ret) 528 return ret; 529 } else { 530 dpm_table->count = 1; 531 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 532 dpm_table->dpm_levels[0].enabled = true; 533 dpm_table->min = dpm_table->dpm_levels[0].value; 534 dpm_table->max = dpm_table->dpm_levels[0].value; 535 } 536 537 /* uclk dpm table setup */ 538 dpm_table = &dpm_context->dpm_tables.uclk_table; 539 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 540 ret = smu_v13_0_set_single_dpm_table(smu, 541 SMU_UCLK, 542 dpm_table); 543 if (ret) 544 return ret; 545 } else { 546 dpm_table->count = 1; 547 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 548 dpm_table->dpm_levels[0].enabled = true; 549 dpm_table->min = dpm_table->dpm_levels[0].value; 550 dpm_table->max = dpm_table->dpm_levels[0].value; 551 } 552 553 /* fclk dpm table setup */ 554 dpm_table = &dpm_context->dpm_tables.fclk_table; 555 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 556 ret = smu_v13_0_set_single_dpm_table(smu, 557 SMU_FCLK, 558 dpm_table); 559 if (ret) 560 return ret; 561 } else { 562 dpm_table->count = 1; 563 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 564 dpm_table->dpm_levels[0].enabled = true; 565 dpm_table->min = dpm_table->dpm_levels[0].value; 566 dpm_table->max = dpm_table->dpm_levels[0].value; 567 } 568 569 /* vclk dpm table setup */ 570 dpm_table = &dpm_context->dpm_tables.vclk_table; 571 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { 572 ret = smu_v13_0_set_single_dpm_table(smu, 573 SMU_VCLK, 574 dpm_table); 575 if (ret) 576 return ret; 577 } else { 578 dpm_table->count = 1; 579 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 580 dpm_table->dpm_levels[0].enabled = true; 581 dpm_table->min = dpm_table->dpm_levels[0].value; 582 dpm_table->max = dpm_table->dpm_levels[0].value; 583 } 584 585 /* dclk dpm table setup */ 586 dpm_table = &dpm_context->dpm_tables.dclk_table; 587 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { 588 ret = smu_v13_0_set_single_dpm_table(smu, 589 SMU_DCLK, 590 dpm_table); 591 if (ret) 592 return ret; 593 } else { 594 dpm_table->count = 1; 595 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 596 dpm_table->dpm_levels[0].enabled = true; 597 dpm_table->min = dpm_table->dpm_levels[0].value; 598 dpm_table->max = dpm_table->dpm_levels[0].value; 599 } 600 601 /* lclk dpm table setup */ 602 pcie_table = &dpm_context->dpm_tables.pcie_table; 603 pcie_table->num_of_link_levels = 0; 604 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { 605 if (!skutable->PcieGenSpeed[link_level] && 606 !skutable->PcieLaneCount[link_level] && 607 !skutable->LclkFreq[link_level]) 608 continue; 609 610 pcie_table->pcie_gen[pcie_table->num_of_link_levels] = 611 skutable->PcieGenSpeed[link_level]; 612 pcie_table->pcie_lane[pcie_table->num_of_link_levels] = 613 skutable->PcieLaneCount[link_level]; 614 pcie_table->clk_freq[pcie_table->num_of_link_levels] = 615 skutable->LclkFreq[link_level]; 616 pcie_table->num_of_link_levels++; 617 } 618 619 return 0; 620 } 621 622 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) 623 { 624 int ret = 0; 625 uint64_t feature_enabled; 626 627 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 628 if (ret) 629 return false; 630 631 return !!(feature_enabled & SMC_DPM_FEATURE); 632 } 633 634 static void smu_v13_0_0_dump_pptable(struct smu_context *smu) 635 { 636 struct smu_table_context *table_context = &smu->smu_table; 637 PPTable_t *pptable = table_context->driver_pptable; 638 SkuTable_t *skutable = &pptable->SkuTable; 639 640 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 641 642 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version); 643 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]); 644 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]); 645 } 646 647 static int smu_v13_0_0_system_features_control(struct smu_context *smu, 648 bool en) 649 { 650 return smu_v13_0_system_features_control(smu, en); 651 } 652 653 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics) 654 { 655 uint32_t throttler_status = 0; 656 int i; 657 658 for (i = 0; i < THROTTLER_COUNT; i++) 659 throttler_status |= 660 (metrics->ThrottlingPercentage[i] ? 1U << i : 0); 661 662 return throttler_status; 663 } 664 665 #define SMU_13_0_0_BUSY_THRESHOLD 15 666 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu, 667 MetricsMember_t member, 668 uint32_t *value) 669 { 670 struct smu_table_context *smu_table = &smu->smu_table; 671 SmuMetrics_t *metrics = 672 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 673 int ret = 0; 674 675 ret = smu_cmn_get_metrics_table(smu, 676 NULL, 677 false); 678 if (ret) 679 return ret; 680 681 switch (member) { 682 case METRICS_CURR_GFXCLK: 683 *value = metrics->CurrClock[PPCLK_GFXCLK]; 684 break; 685 case METRICS_CURR_SOCCLK: 686 *value = metrics->CurrClock[PPCLK_SOCCLK]; 687 break; 688 case METRICS_CURR_UCLK: 689 *value = metrics->CurrClock[PPCLK_UCLK]; 690 break; 691 case METRICS_CURR_VCLK: 692 *value = metrics->CurrClock[PPCLK_VCLK_0]; 693 break; 694 case METRICS_CURR_VCLK1: 695 *value = metrics->CurrClock[PPCLK_VCLK_1]; 696 break; 697 case METRICS_CURR_DCLK: 698 *value = metrics->CurrClock[PPCLK_DCLK_0]; 699 break; 700 case METRICS_CURR_DCLK1: 701 *value = metrics->CurrClock[PPCLK_DCLK_1]; 702 break; 703 case METRICS_CURR_FCLK: 704 *value = metrics->CurrClock[PPCLK_FCLK]; 705 break; 706 case METRICS_AVERAGE_GFXCLK: 707 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 708 *value = metrics->AverageGfxclkFrequencyPostDs; 709 else 710 *value = metrics->AverageGfxclkFrequencyPreDs; 711 break; 712 case METRICS_AVERAGE_FCLK: 713 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 714 *value = metrics->AverageFclkFrequencyPostDs; 715 else 716 *value = metrics->AverageFclkFrequencyPreDs; 717 break; 718 case METRICS_AVERAGE_UCLK: 719 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 720 *value = metrics->AverageMemclkFrequencyPostDs; 721 else 722 *value = metrics->AverageMemclkFrequencyPreDs; 723 break; 724 case METRICS_AVERAGE_VCLK: 725 *value = metrics->AverageVclk0Frequency; 726 break; 727 case METRICS_AVERAGE_DCLK: 728 *value = metrics->AverageDclk0Frequency; 729 break; 730 case METRICS_AVERAGE_VCLK1: 731 *value = metrics->AverageVclk1Frequency; 732 break; 733 case METRICS_AVERAGE_DCLK1: 734 *value = metrics->AverageDclk1Frequency; 735 break; 736 case METRICS_AVERAGE_GFXACTIVITY: 737 *value = metrics->AverageGfxActivity; 738 break; 739 case METRICS_AVERAGE_MEMACTIVITY: 740 *value = metrics->AverageUclkActivity; 741 break; 742 case METRICS_AVERAGE_SOCKETPOWER: 743 *value = metrics->AverageSocketPower << 8; 744 break; 745 case METRICS_TEMPERATURE_EDGE: 746 *value = metrics->AvgTemperature[TEMP_EDGE] * 747 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 748 break; 749 case METRICS_TEMPERATURE_HOTSPOT: 750 *value = metrics->AvgTemperature[TEMP_HOTSPOT] * 751 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 752 break; 753 case METRICS_TEMPERATURE_MEM: 754 *value = metrics->AvgTemperature[TEMP_MEM] * 755 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 756 break; 757 case METRICS_TEMPERATURE_VRGFX: 758 *value = metrics->AvgTemperature[TEMP_VR_GFX] * 759 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 760 break; 761 case METRICS_TEMPERATURE_VRSOC: 762 *value = metrics->AvgTemperature[TEMP_VR_SOC] * 763 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 764 break; 765 case METRICS_THROTTLER_STATUS: 766 *value = smu_v13_0_get_throttler_status(metrics); 767 break; 768 case METRICS_CURR_FANSPEED: 769 *value = metrics->AvgFanRpm; 770 break; 771 case METRICS_CURR_FANPWM: 772 *value = metrics->AvgFanPwm; 773 break; 774 case METRICS_VOLTAGE_VDDGFX: 775 *value = metrics->AvgVoltage[SVI_PLANE_GFX]; 776 break; 777 case METRICS_PCIE_RATE: 778 *value = metrics->PcieRate; 779 break; 780 case METRICS_PCIE_WIDTH: 781 *value = metrics->PcieWidth; 782 break; 783 default: 784 *value = UINT_MAX; 785 break; 786 } 787 788 return ret; 789 } 790 791 static int smu_v13_0_0_read_sensor(struct smu_context *smu, 792 enum amd_pp_sensors sensor, 793 void *data, 794 uint32_t *size) 795 { 796 struct smu_table_context *table_context = &smu->smu_table; 797 PPTable_t *smc_pptable = table_context->driver_pptable; 798 int ret = 0; 799 800 switch (sensor) { 801 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 802 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm; 803 *size = 4; 804 break; 805 case AMDGPU_PP_SENSOR_MEM_LOAD: 806 ret = smu_v13_0_0_get_smu_metrics_data(smu, 807 METRICS_AVERAGE_MEMACTIVITY, 808 (uint32_t *)data); 809 *size = 4; 810 break; 811 case AMDGPU_PP_SENSOR_GPU_LOAD: 812 ret = smu_v13_0_0_get_smu_metrics_data(smu, 813 METRICS_AVERAGE_GFXACTIVITY, 814 (uint32_t *)data); 815 *size = 4; 816 break; 817 case AMDGPU_PP_SENSOR_GPU_POWER: 818 ret = smu_v13_0_0_get_smu_metrics_data(smu, 819 METRICS_AVERAGE_SOCKETPOWER, 820 (uint32_t *)data); 821 *size = 4; 822 break; 823 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 824 ret = smu_v13_0_0_get_smu_metrics_data(smu, 825 METRICS_TEMPERATURE_HOTSPOT, 826 (uint32_t *)data); 827 *size = 4; 828 break; 829 case AMDGPU_PP_SENSOR_EDGE_TEMP: 830 ret = smu_v13_0_0_get_smu_metrics_data(smu, 831 METRICS_TEMPERATURE_EDGE, 832 (uint32_t *)data); 833 *size = 4; 834 break; 835 case AMDGPU_PP_SENSOR_MEM_TEMP: 836 ret = smu_v13_0_0_get_smu_metrics_data(smu, 837 METRICS_TEMPERATURE_MEM, 838 (uint32_t *)data); 839 *size = 4; 840 break; 841 case AMDGPU_PP_SENSOR_GFX_MCLK: 842 ret = smu_v13_0_0_get_smu_metrics_data(smu, 843 METRICS_AVERAGE_UCLK, 844 (uint32_t *)data); 845 *(uint32_t *)data *= 100; 846 *size = 4; 847 break; 848 case AMDGPU_PP_SENSOR_GFX_SCLK: 849 ret = smu_v13_0_0_get_smu_metrics_data(smu, 850 METRICS_AVERAGE_GFXCLK, 851 (uint32_t *)data); 852 *(uint32_t *)data *= 100; 853 *size = 4; 854 break; 855 case AMDGPU_PP_SENSOR_VDDGFX: 856 ret = smu_v13_0_0_get_smu_metrics_data(smu, 857 METRICS_VOLTAGE_VDDGFX, 858 (uint32_t *)data); 859 *size = 4; 860 break; 861 default: 862 ret = -EOPNOTSUPP; 863 break; 864 } 865 866 return ret; 867 } 868 869 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu, 870 enum smu_clk_type clk_type, 871 uint32_t *value) 872 { 873 MetricsMember_t member_type; 874 int clk_id = 0; 875 876 clk_id = smu_cmn_to_asic_specific_index(smu, 877 CMN2ASIC_MAPPING_CLK, 878 clk_type); 879 if (clk_id < 0) 880 return -EINVAL; 881 882 switch (clk_id) { 883 case PPCLK_GFXCLK: 884 member_type = METRICS_AVERAGE_GFXCLK; 885 break; 886 case PPCLK_UCLK: 887 member_type = METRICS_CURR_UCLK; 888 break; 889 case PPCLK_FCLK: 890 member_type = METRICS_CURR_FCLK; 891 break; 892 case PPCLK_SOCCLK: 893 member_type = METRICS_CURR_SOCCLK; 894 break; 895 case PPCLK_VCLK_0: 896 member_type = METRICS_AVERAGE_VCLK; 897 break; 898 case PPCLK_DCLK_0: 899 member_type = METRICS_AVERAGE_DCLK; 900 break; 901 case PPCLK_VCLK_1: 902 member_type = METRICS_AVERAGE_VCLK1; 903 break; 904 case PPCLK_DCLK_1: 905 member_type = METRICS_AVERAGE_DCLK1; 906 break; 907 default: 908 return -EINVAL; 909 } 910 911 return smu_v13_0_0_get_smu_metrics_data(smu, 912 member_type, 913 value); 914 } 915 916 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, 917 enum smu_clk_type clk_type, 918 char *buf) 919 { 920 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 921 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 922 struct smu_13_0_dpm_table *single_dpm_table; 923 struct smu_13_0_pcie_table *pcie_table; 924 const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 925 uint32_t gen_speed, lane_width; 926 int i, curr_freq, size = 0; 927 int ret = 0; 928 929 smu_cmn_get_sysfs_buf(&buf, &size); 930 931 if (amdgpu_ras_intr_triggered()) { 932 size += sysfs_emit_at(buf, size, "unavailable\n"); 933 return size; 934 } 935 936 switch (clk_type) { 937 case SMU_SCLK: 938 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 939 break; 940 case SMU_MCLK: 941 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 942 break; 943 case SMU_SOCCLK: 944 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 945 break; 946 case SMU_FCLK: 947 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 948 break; 949 case SMU_VCLK: 950 case SMU_VCLK1: 951 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 952 break; 953 case SMU_DCLK: 954 case SMU_DCLK1: 955 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 956 break; 957 default: 958 break; 959 } 960 961 switch (clk_type) { 962 case SMU_SCLK: 963 case SMU_MCLK: 964 case SMU_SOCCLK: 965 case SMU_FCLK: 966 case SMU_VCLK: 967 case SMU_VCLK1: 968 case SMU_DCLK: 969 case SMU_DCLK1: 970 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); 971 if (ret) { 972 dev_err(smu->adev->dev, "Failed to get current clock freq!"); 973 return ret; 974 } 975 976 if (single_dpm_table->is_fine_grained) { 977 /* 978 * For fine grained dpms, there are only two dpm levels: 979 * - level 0 -> min clock freq 980 * - level 1 -> max clock freq 981 * And the current clock frequency can be any value between them. 982 * So, if the current clock frequency is not at level 0 or level 1, 983 * we will fake it as three dpm levels: 984 * - level 0 -> min clock freq 985 * - level 1 -> current actual clock freq 986 * - level 2 -> max clock freq 987 */ 988 if ((single_dpm_table->dpm_levels[0].value != curr_freq) && 989 (single_dpm_table->dpm_levels[1].value != curr_freq)) { 990 size += sysfs_emit_at(buf, size, "0: %uMhz\n", 991 single_dpm_table->dpm_levels[0].value); 992 size += sysfs_emit_at(buf, size, "1: %uMhz *\n", 993 curr_freq); 994 size += sysfs_emit_at(buf, size, "2: %uMhz\n", 995 single_dpm_table->dpm_levels[1].value); 996 } else { 997 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 998 single_dpm_table->dpm_levels[0].value, 999 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); 1000 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 1001 single_dpm_table->dpm_levels[1].value, 1002 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); 1003 } 1004 } else { 1005 for (i = 0; i < single_dpm_table->count; i++) 1006 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 1007 i, single_dpm_table->dpm_levels[i].value, 1008 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); 1009 } 1010 break; 1011 case SMU_PCIE: 1012 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1013 METRICS_PCIE_RATE, 1014 &gen_speed); 1015 if (ret) 1016 return ret; 1017 1018 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1019 METRICS_PCIE_WIDTH, 1020 &lane_width); 1021 if (ret) 1022 return ret; 1023 1024 pcie_table = &(dpm_context->dpm_tables.pcie_table); 1025 for (i = 0; i < pcie_table->num_of_link_levels; i++) 1026 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1027 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : 1028 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : 1029 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : 1030 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", 1031 (pcie_table->pcie_lane[i] == 1) ? "x1" : 1032 (pcie_table->pcie_lane[i] == 2) ? "x2" : 1033 (pcie_table->pcie_lane[i] == 3) ? "x4" : 1034 (pcie_table->pcie_lane[i] == 4) ? "x8" : 1035 (pcie_table->pcie_lane[i] == 5) ? "x12" : 1036 (pcie_table->pcie_lane[i] == 6) ? "x16" : "", 1037 pcie_table->clk_freq[i], 1038 ((gen_speed - 1) == pcie_table->pcie_gen[i]) && 1039 (lane_width == link_width[pcie_table->pcie_lane[i]]) ? 1040 "*" : ""); 1041 break; 1042 1043 default: 1044 break; 1045 } 1046 1047 return size; 1048 } 1049 1050 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu, 1051 enum smu_clk_type clk_type, 1052 uint32_t mask) 1053 { 1054 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1055 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1056 struct smu_13_0_dpm_table *single_dpm_table; 1057 uint32_t soft_min_level, soft_max_level; 1058 uint32_t min_freq, max_freq; 1059 int ret = 0; 1060 1061 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1062 soft_max_level = mask ? (fls(mask) - 1) : 0; 1063 1064 switch (clk_type) { 1065 case SMU_GFXCLK: 1066 case SMU_SCLK: 1067 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1068 break; 1069 case SMU_MCLK: 1070 case SMU_UCLK: 1071 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1072 break; 1073 case SMU_SOCCLK: 1074 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1075 break; 1076 case SMU_FCLK: 1077 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1078 break; 1079 case SMU_VCLK: 1080 case SMU_VCLK1: 1081 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1082 break; 1083 case SMU_DCLK: 1084 case SMU_DCLK1: 1085 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1086 break; 1087 default: 1088 break; 1089 } 1090 1091 switch (clk_type) { 1092 case SMU_GFXCLK: 1093 case SMU_SCLK: 1094 case SMU_MCLK: 1095 case SMU_UCLK: 1096 case SMU_SOCCLK: 1097 case SMU_FCLK: 1098 case SMU_VCLK: 1099 case SMU_VCLK1: 1100 case SMU_DCLK: 1101 case SMU_DCLK1: 1102 if (single_dpm_table->is_fine_grained) { 1103 /* There is only 2 levels for fine grained DPM */ 1104 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1105 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1106 } else { 1107 if ((soft_max_level >= single_dpm_table->count) || 1108 (soft_min_level >= single_dpm_table->count)) 1109 return -EINVAL; 1110 } 1111 1112 min_freq = single_dpm_table->dpm_levels[soft_min_level].value; 1113 max_freq = single_dpm_table->dpm_levels[soft_max_level].value; 1114 1115 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1116 clk_type, 1117 min_freq, 1118 max_freq); 1119 break; 1120 case SMU_DCEFCLK: 1121 case SMU_PCIE: 1122 default: 1123 break; 1124 } 1125 1126 return ret; 1127 } 1128 1129 static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, 1130 uint32_t pcie_gen_cap, 1131 uint32_t pcie_width_cap) 1132 { 1133 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1134 struct smu_13_0_pcie_table *pcie_table = 1135 &dpm_context->dpm_tables.pcie_table; 1136 uint32_t smu_pcie_arg; 1137 int ret, i; 1138 1139 for (i = 0; i < pcie_table->num_of_link_levels; i++) { 1140 if (pcie_table->pcie_gen[i] > pcie_gen_cap) 1141 pcie_table->pcie_gen[i] = pcie_gen_cap; 1142 if (pcie_table->pcie_lane[i] > pcie_width_cap) 1143 pcie_table->pcie_lane[i] = pcie_width_cap; 1144 1145 smu_pcie_arg = i << 16; 1146 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8; 1147 smu_pcie_arg |= pcie_table->pcie_lane[i]; 1148 1149 ret = smu_cmn_send_smc_msg_with_param(smu, 1150 SMU_MSG_OverridePcieParameters, 1151 smu_pcie_arg, 1152 NULL); 1153 if (ret) 1154 return ret; 1155 } 1156 1157 return 0; 1158 } 1159 1160 static const struct smu_temperature_range smu13_thermal_policy[] = { 1161 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 1162 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 1163 }; 1164 1165 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu, 1166 struct smu_temperature_range *range) 1167 { 1168 struct smu_table_context *table_context = &smu->smu_table; 1169 struct smu_13_0_0_powerplay_table *powerplay_table = 1170 table_context->power_play_table; 1171 PPTable_t *pptable = smu->smu_table.driver_pptable; 1172 1173 if (!range) 1174 return -EINVAL; 1175 1176 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1177 1178 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] * 1179 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1180 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1181 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1182 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] * 1183 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1184 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1185 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1186 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] * 1187 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1188 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1189 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1190 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1191 1192 return 0; 1193 } 1194 1195 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 1196 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, 1197 void **table) 1198 { 1199 struct smu_table_context *smu_table = &smu->smu_table; 1200 struct gpu_metrics_v1_3 *gpu_metrics = 1201 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1202 SmuMetricsExternal_t metrics_ext; 1203 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 1204 int ret = 0; 1205 1206 ret = smu_cmn_get_metrics_table(smu, 1207 &metrics_ext, 1208 true); 1209 if (ret) 1210 return ret; 1211 1212 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1213 1214 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE]; 1215 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT]; 1216 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM]; 1217 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX]; 1218 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC]; 1219 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0], 1220 metrics->AvgTemperature[TEMP_VR_MEM1]); 1221 1222 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 1223 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 1224 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage, 1225 metrics->Vcn1ActivityPercentage); 1226 1227 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 1228 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 1229 1230 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 1231 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 1232 else 1233 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 1234 1235 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 1236 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 1237 else 1238 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs; 1239 1240 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 1241 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 1242 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 1243 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 1244 1245 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; 1246 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK]; 1247 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; 1248 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 1249 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 1250 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 1251 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 1252 1253 gpu_metrics->throttle_status = 1254 smu_v13_0_get_throttler_status(metrics); 1255 gpu_metrics->indep_throttle_status = 1256 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 1257 smu_v13_0_0_throttler_map); 1258 1259 gpu_metrics->current_fan_speed = metrics->AvgFanRpm; 1260 1261 gpu_metrics->pcie_link_width = metrics->PcieWidth; 1262 gpu_metrics->pcie_link_speed = metrics->PcieRate; 1263 1264 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1265 1266 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX]; 1267 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC]; 1268 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP]; 1269 1270 *table = (void *)gpu_metrics; 1271 1272 return sizeof(struct gpu_metrics_v1_3); 1273 } 1274 1275 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu) 1276 { 1277 struct smu_13_0_dpm_context *dpm_context = 1278 smu->smu_dpm.dpm_context; 1279 struct smu_13_0_dpm_table *gfx_table = 1280 &dpm_context->dpm_tables.gfx_table; 1281 struct smu_13_0_dpm_table *mem_table = 1282 &dpm_context->dpm_tables.uclk_table; 1283 struct smu_13_0_dpm_table *soc_table = 1284 &dpm_context->dpm_tables.soc_table; 1285 struct smu_13_0_dpm_table *vclk_table = 1286 &dpm_context->dpm_tables.vclk_table; 1287 struct smu_13_0_dpm_table *dclk_table = 1288 &dpm_context->dpm_tables.dclk_table; 1289 struct smu_13_0_dpm_table *fclk_table = 1290 &dpm_context->dpm_tables.fclk_table; 1291 struct smu_umd_pstate_table *pstate_table = 1292 &smu->pstate_table; 1293 1294 pstate_table->gfxclk_pstate.min = gfx_table->min; 1295 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1296 1297 pstate_table->uclk_pstate.min = mem_table->min; 1298 pstate_table->uclk_pstate.peak = mem_table->max; 1299 1300 pstate_table->socclk_pstate.min = soc_table->min; 1301 pstate_table->socclk_pstate.peak = soc_table->max; 1302 1303 pstate_table->vclk_pstate.min = vclk_table->min; 1304 pstate_table->vclk_pstate.peak = vclk_table->max; 1305 1306 pstate_table->dclk_pstate.min = dclk_table->min; 1307 pstate_table->dclk_pstate.peak = dclk_table->max; 1308 1309 pstate_table->fclk_pstate.min = fclk_table->min; 1310 pstate_table->fclk_pstate.peak = fclk_table->max; 1311 1312 /* 1313 * For now, just use the mininum clock frequency. 1314 * TODO: update them when the real pstate settings available 1315 */ 1316 pstate_table->gfxclk_pstate.standard = gfx_table->min; 1317 pstate_table->uclk_pstate.standard = mem_table->min; 1318 pstate_table->socclk_pstate.standard = soc_table->min; 1319 pstate_table->vclk_pstate.standard = vclk_table->min; 1320 pstate_table->dclk_pstate.standard = dclk_table->min; 1321 pstate_table->fclk_pstate.standard = fclk_table->min; 1322 1323 return 0; 1324 } 1325 1326 static void smu_v13_0_0_get_unique_id(struct smu_context *smu) 1327 { 1328 struct smu_table_context *smu_table = &smu->smu_table; 1329 SmuMetrics_t *metrics = 1330 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 1331 struct amdgpu_device *adev = smu->adev; 1332 uint32_t upper32 = 0, lower32 = 0; 1333 int ret; 1334 1335 ret = smu_cmn_get_metrics_table(smu, NULL, false); 1336 if (ret) 1337 goto out; 1338 1339 upper32 = metrics->PublicSerialNumberUpper; 1340 lower32 = metrics->PublicSerialNumberLower; 1341 1342 out: 1343 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1344 if (adev->serial[0] == '\0') 1345 sprintf(adev->serial, "%016llx", adev->unique_id); 1346 } 1347 1348 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu, 1349 uint32_t *speed) 1350 { 1351 if (!speed) 1352 return -EINVAL; 1353 1354 return smu_v13_0_0_get_smu_metrics_data(smu, 1355 METRICS_CURR_FANPWM, 1356 speed); 1357 } 1358 1359 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu, 1360 uint32_t *speed) 1361 { 1362 if (!speed) 1363 return -EINVAL; 1364 1365 return smu_v13_0_0_get_smu_metrics_data(smu, 1366 METRICS_CURR_FANSPEED, 1367 speed); 1368 } 1369 1370 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu) 1371 { 1372 struct smu_table_context *table_context = &smu->smu_table; 1373 PPTable_t *pptable = table_context->driver_pptable; 1374 SkuTable_t *skutable = &pptable->SkuTable; 1375 1376 /* 1377 * Skip the MGpuFanBoost setting for those ASICs 1378 * which do not support it 1379 */ 1380 if (skutable->MGpuAcousticLimitRpmThreshold == 0) 1381 return 0; 1382 1383 return smu_cmn_send_smc_msg_with_param(smu, 1384 SMU_MSG_SetMGpuFanBoostLimitRpm, 1385 0, 1386 NULL); 1387 } 1388 1389 static int smu_v13_0_0_get_power_limit(struct smu_context *smu, 1390 uint32_t *current_power_limit, 1391 uint32_t *default_power_limit, 1392 uint32_t *max_power_limit) 1393 { 1394 struct smu_table_context *table_context = &smu->smu_table; 1395 struct smu_13_0_0_powerplay_table *powerplay_table = 1396 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table; 1397 PPTable_t *pptable = table_context->driver_pptable; 1398 SkuTable_t *skutable = &pptable->SkuTable; 1399 uint32_t power_limit, od_percent; 1400 1401 if (smu_v13_0_get_current_power_limit(smu, &power_limit)) 1402 power_limit = smu->adev->pm.ac_power ? 1403 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] : 1404 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0]; 1405 1406 if (current_power_limit) 1407 *current_power_limit = power_limit; 1408 if (default_power_limit) 1409 *default_power_limit = power_limit; 1410 1411 if (max_power_limit) { 1412 if (smu->od_enabled) { 1413 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]); 1414 1415 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1416 1417 power_limit *= (100 + od_percent); 1418 power_limit /= 100; 1419 } 1420 *max_power_limit = power_limit; 1421 } 1422 1423 return 0; 1424 } 1425 1426 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu, 1427 char *buf) 1428 { 1429 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1430 DpmActivityMonitorCoeffInt_t *activity_monitor = 1431 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1432 static const char *title[] = { 1433 "PROFILE_INDEX(NAME)", 1434 "CLOCK_TYPE(NAME)", 1435 "FPS", 1436 "MinActiveFreqType", 1437 "MinActiveFreq", 1438 "BoosterFreqType", 1439 "BoosterFreq", 1440 "PD_Data_limit_c", 1441 "PD_Data_error_coeff", 1442 "PD_Data_error_rate_coeff"}; 1443 int16_t workload_type = 0; 1444 uint32_t i, size = 0; 1445 int result = 0; 1446 1447 if (!buf) 1448 return -EINVAL; 1449 1450 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n", 1451 title[0], title[1], title[2], title[3], title[4], title[5], 1452 title[6], title[7], title[8], title[9]); 1453 1454 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1455 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1456 workload_type = smu_cmn_to_asic_specific_index(smu, 1457 CMN2ASIC_MAPPING_WORKLOAD, 1458 i); 1459 if (workload_type < 0) 1460 return -EINVAL; 1461 1462 result = smu_cmn_update_table(smu, 1463 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1464 workload_type, 1465 (void *)(&activity_monitor_external), 1466 false); 1467 if (result) { 1468 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1469 return result; 1470 } 1471 1472 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1473 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1474 1475 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 1476 " ", 1477 0, 1478 "GFXCLK", 1479 activity_monitor->Gfx_FPS, 1480 activity_monitor->Gfx_MinActiveFreqType, 1481 activity_monitor->Gfx_MinActiveFreq, 1482 activity_monitor->Gfx_BoosterFreqType, 1483 activity_monitor->Gfx_BoosterFreq, 1484 activity_monitor->Gfx_PD_Data_limit_c, 1485 activity_monitor->Gfx_PD_Data_error_coeff, 1486 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1487 1488 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 1489 " ", 1490 1, 1491 "FCLK", 1492 activity_monitor->Fclk_FPS, 1493 activity_monitor->Fclk_MinActiveFreqType, 1494 activity_monitor->Fclk_MinActiveFreq, 1495 activity_monitor->Fclk_BoosterFreqType, 1496 activity_monitor->Fclk_BoosterFreq, 1497 activity_monitor->Fclk_PD_Data_limit_c, 1498 activity_monitor->Fclk_PD_Data_error_coeff, 1499 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1500 } 1501 1502 return size; 1503 } 1504 1505 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, 1506 long *input, 1507 uint32_t size) 1508 { 1509 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1510 DpmActivityMonitorCoeffInt_t *activity_monitor = 1511 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1512 int workload_type, ret = 0; 1513 1514 smu->power_profile_mode = input[size]; 1515 1516 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1517 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1518 return -EINVAL; 1519 } 1520 1521 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1522 ret = smu_cmn_update_table(smu, 1523 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1524 WORKLOAD_PPLIB_CUSTOM_BIT, 1525 (void *)(&activity_monitor_external), 1526 false); 1527 if (ret) { 1528 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1529 return ret; 1530 } 1531 1532 switch (input[0]) { 1533 case 0: /* Gfxclk */ 1534 activity_monitor->Gfx_FPS = input[1]; 1535 activity_monitor->Gfx_MinActiveFreqType = input[2]; 1536 activity_monitor->Gfx_MinActiveFreq = input[3]; 1537 activity_monitor->Gfx_BoosterFreqType = input[4]; 1538 activity_monitor->Gfx_BoosterFreq = input[5]; 1539 activity_monitor->Gfx_PD_Data_limit_c = input[6]; 1540 activity_monitor->Gfx_PD_Data_error_coeff = input[7]; 1541 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8]; 1542 break; 1543 case 1: /* Fclk */ 1544 activity_monitor->Fclk_FPS = input[1]; 1545 activity_monitor->Fclk_MinActiveFreqType = input[2]; 1546 activity_monitor->Fclk_MinActiveFreq = input[3]; 1547 activity_monitor->Fclk_BoosterFreqType = input[4]; 1548 activity_monitor->Fclk_BoosterFreq = input[5]; 1549 activity_monitor->Fclk_PD_Data_limit_c = input[6]; 1550 activity_monitor->Fclk_PD_Data_error_coeff = input[7]; 1551 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; 1552 break; 1553 } 1554 1555 ret = smu_cmn_update_table(smu, 1556 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1557 WORKLOAD_PPLIB_CUSTOM_BIT, 1558 (void *)(&activity_monitor_external), 1559 true); 1560 if (ret) { 1561 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1562 return ret; 1563 } 1564 } 1565 1566 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1567 workload_type = smu_cmn_to_asic_specific_index(smu, 1568 CMN2ASIC_MAPPING_WORKLOAD, 1569 smu->power_profile_mode); 1570 if (workload_type < 0) 1571 return -EINVAL; 1572 1573 return smu_cmn_send_smc_msg_with_param(smu, 1574 SMU_MSG_SetWorkloadMask, 1575 1 << workload_type, 1576 NULL); 1577 } 1578 1579 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { 1580 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, 1581 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, 1582 .is_dpm_running = smu_v13_0_0_is_dpm_running, 1583 .dump_pptable = smu_v13_0_0_dump_pptable, 1584 .init_microcode = smu_v13_0_init_microcode, 1585 .load_microcode = smu_v13_0_load_microcode, 1586 .init_smc_tables = smu_v13_0_0_init_smc_tables, 1587 .init_power = smu_v13_0_init_power, 1588 .fini_power = smu_v13_0_fini_power, 1589 .check_fw_status = smu_v13_0_check_fw_status, 1590 .setup_pptable = smu_v13_0_0_setup_pptable, 1591 .check_fw_version = smu_v13_0_check_fw_version, 1592 .write_pptable = smu_cmn_write_pptable, 1593 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1594 .system_features_control = smu_v13_0_0_system_features_control, 1595 .set_allowed_mask = smu_v13_0_set_allowed_mask, 1596 .get_enabled_mask = smu_cmn_get_enabled_mask, 1597 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 1598 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 1599 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 1600 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1601 .read_sensor = smu_v13_0_0_read_sensor, 1602 .feature_is_enabled = smu_cmn_feature_is_enabled, 1603 .print_clk_levels = smu_v13_0_0_print_clk_levels, 1604 .force_clk_levels = smu_v13_0_0_force_clk_levels, 1605 .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters, 1606 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range, 1607 .register_irq_handler = smu_v13_0_register_irq_handler, 1608 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 1609 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 1610 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 1611 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics, 1612 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, 1613 .init_pptable_microcode = smu_v13_0_init_pptable_microcode, 1614 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk, 1615 .set_performance_level = smu_v13_0_set_performance_level, 1616 .gfx_off_control = smu_v13_0_gfx_off_control, 1617 .get_unique_id = smu_v13_0_0_get_unique_id, 1618 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm, 1619 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm, 1620 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, 1621 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm, 1622 .get_fan_control_mode = smu_v13_0_get_fan_control_mode, 1623 .set_fan_control_mode = smu_v13_0_set_fan_control_mode, 1624 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, 1625 .get_power_limit = smu_v13_0_0_get_power_limit, 1626 .set_power_limit = smu_v13_0_set_power_limit, 1627 .set_power_source = smu_v13_0_set_power_source, 1628 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, 1629 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, 1630 .run_btc = smu_v13_0_run_btc, 1631 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1632 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1633 .set_tool_table_location = smu_v13_0_set_tool_table_location, 1634 .deep_sleep_control = smu_v13_0_deep_sleep_control, 1635 .gfx_ulv_control = smu_v13_0_gfx_ulv_control, 1636 .baco_is_support = smu_v13_0_baco_is_support, 1637 .baco_get_state = smu_v13_0_baco_get_state, 1638 .baco_set_state = smu_v13_0_baco_set_state, 1639 .baco_enter = smu_v13_0_baco_enter, 1640 .baco_exit = smu_v13_0_baco_exit, 1641 }; 1642 1643 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) 1644 { 1645 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs; 1646 smu->message_map = smu_v13_0_0_message_map; 1647 smu->clock_map = smu_v13_0_0_clk_map; 1648 smu->feature_map = smu_v13_0_0_feature_mask_map; 1649 smu->table_map = smu_v13_0_0_table_map; 1650 smu->pwr_src_map = smu_v13_0_0_pwr_src_map; 1651 smu->workload_map = smu_v13_0_0_workload_map; 1652 } 1653