1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v13_0.h" 35 #include "smu13_driver_if_v13_0_0.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "smu_v13_0_0_ppt.h" 39 #include "smu_v13_0_0_pptable.h" 40 #include "smu_v13_0_0_ppsmc.h" 41 #include "nbio/nbio_4_3_0_offset.h" 42 #include "nbio/nbio_4_3_0_sh_mask.h" 43 #include "mp/mp_13_0_0_offset.h" 44 #include "mp/mp_13_0_0_sh_mask.h" 45 46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "amdgpu_ras.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 70 71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 72 73 #define mmMP1_SMN_C2PMSG_66 0x0282 74 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 75 76 #define mmMP1_SMN_C2PMSG_82 0x0292 77 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 78 79 #define mmMP1_SMN_C2PMSG_90 0x029a 80 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 81 82 #define mmMP1_SMN_C2PMSG_75 0x028b 83 #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 84 85 #define mmMP1_SMN_C2PMSG_53 0x0275 86 #define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 87 88 #define mmMP1_SMN_C2PMSG_54 0x0276 89 #define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 90 91 #define DEBUGSMC_MSG_Mode1Reset 2 92 93 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = { 94 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 95 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 96 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 97 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 98 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 99 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 100 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 101 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 102 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 103 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 104 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 105 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 106 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 107 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 108 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 109 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 110 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 111 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 112 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 113 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 114 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 115 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 116 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 117 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 118 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 119 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 120 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 121 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 122 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 123 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 124 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 125 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 126 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 127 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 128 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 129 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 130 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 131 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 132 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 133 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 134 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 135 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 136 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 137 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 138 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 139 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 140 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 141 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 142 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), 143 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 144 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0), 145 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel, 146 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0), 147 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0), 148 }; 149 150 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { 151 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 152 CLK_MAP(SCLK, PPCLK_GFXCLK), 153 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 154 CLK_MAP(FCLK, PPCLK_FCLK), 155 CLK_MAP(UCLK, PPCLK_UCLK), 156 CLK_MAP(MCLK, PPCLK_UCLK), 157 CLK_MAP(VCLK, PPCLK_VCLK_0), 158 CLK_MAP(VCLK1, PPCLK_VCLK_1), 159 CLK_MAP(DCLK, PPCLK_DCLK_0), 160 CLK_MAP(DCLK1, PPCLK_DCLK_1), 161 }; 162 163 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = { 164 FEA_MAP(FW_DATA_READ), 165 FEA_MAP(DPM_GFXCLK), 166 FEA_MAP(DPM_GFX_POWER_OPTIMIZER), 167 FEA_MAP(DPM_UCLK), 168 FEA_MAP(DPM_FCLK), 169 FEA_MAP(DPM_SOCCLK), 170 FEA_MAP(DPM_MP0CLK), 171 FEA_MAP(DPM_LINK), 172 FEA_MAP(DPM_DCN), 173 FEA_MAP(VMEMP_SCALING), 174 FEA_MAP(VDDIO_MEM_SCALING), 175 FEA_MAP(DS_GFXCLK), 176 FEA_MAP(DS_SOCCLK), 177 FEA_MAP(DS_FCLK), 178 FEA_MAP(DS_LCLK), 179 FEA_MAP(DS_DCFCLK), 180 FEA_MAP(DS_UCLK), 181 FEA_MAP(GFX_ULV), 182 FEA_MAP(FW_DSTATE), 183 FEA_MAP(GFXOFF), 184 FEA_MAP(BACO), 185 FEA_MAP(MM_DPM), 186 FEA_MAP(SOC_MPCLK_DS), 187 FEA_MAP(BACO_MPCLK_DS), 188 FEA_MAP(THROTTLERS), 189 FEA_MAP(SMARTSHIFT), 190 FEA_MAP(GTHR), 191 FEA_MAP(ACDC), 192 FEA_MAP(VR0HOT), 193 FEA_MAP(FW_CTF), 194 FEA_MAP(FAN_CONTROL), 195 FEA_MAP(GFX_DCS), 196 FEA_MAP(GFX_READ_MARGIN), 197 FEA_MAP(LED_DISPLAY), 198 FEA_MAP(GFXCLK_SPREAD_SPECTRUM), 199 FEA_MAP(OUT_OF_BAND_MONITOR), 200 FEA_MAP(OPTIMIZED_VMIN), 201 FEA_MAP(GFX_IMU), 202 FEA_MAP(BOOT_TIME_CAL), 203 FEA_MAP(GFX_PCC_DFLL), 204 FEA_MAP(SOC_CG), 205 FEA_MAP(DF_CSTATE), 206 FEA_MAP(GFX_EDC), 207 FEA_MAP(BOOT_POWER_OPT), 208 FEA_MAP(CLOCK_POWER_DOWN_BYPASS), 209 FEA_MAP(DS_VCN), 210 FEA_MAP(BACO_CG), 211 FEA_MAP(MEM_TEMP_READ), 212 FEA_MAP(ATHUB_MMHUB_PG), 213 FEA_MAP(SOC_PCC), 214 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, 215 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, 216 }; 217 218 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = { 219 TAB_MAP(PPTABLE), 220 TAB_MAP(WATERMARKS), 221 TAB_MAP(AVFS_PSM_DEBUG), 222 TAB_MAP(PMSTATUSLOG), 223 TAB_MAP(SMU_METRICS), 224 TAB_MAP(DRIVER_SMU_CONFIG), 225 TAB_MAP(ACTIVITY_MONITOR_COEFF), 226 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE}, 227 TAB_MAP(I2C_COMMANDS), 228 }; 229 230 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 231 PWR_MAP(AC), 232 PWR_MAP(DC), 233 }; 234 235 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 240 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 241 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 242 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 243 }; 244 245 static const uint8_t smu_v13_0_0_throttler_map[] = { 246 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 247 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 248 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 249 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 250 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 251 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 252 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 253 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 254 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 255 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 256 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 257 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 258 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 259 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 260 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 261 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT), 262 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 263 }; 264 265 static int 266 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, 267 uint32_t *feature_mask, uint32_t num) 268 { 269 struct amdgpu_device *adev = smu->adev; 270 u32 smu_version; 271 272 if (num > 2) 273 return -EINVAL; 274 275 memset(feature_mask, 0xff, sizeof(uint32_t) * num); 276 277 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) { 278 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 279 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); 280 } 281 282 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || 283 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 284 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 285 286 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) 287 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 288 289 /* PMFW 78.58 contains a critical fix for gfxoff feature */ 290 smu_cmn_get_smc_version(smu, NULL, &smu_version); 291 if ((smu_version < 0x004e3a00) || 292 !(adev->pm.pp_feature & PP_GFXOFF_MASK)) 293 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); 294 295 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { 296 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 297 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 298 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 299 } 300 301 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) 302 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 303 304 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { 305 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); 306 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); 307 } 308 309 if (!(adev->pm.pp_feature & PP_ULV_MASK)) 310 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); 311 312 return 0; 313 } 314 315 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu) 316 { 317 struct smu_table_context *table_context = &smu->smu_table; 318 struct smu_13_0_0_powerplay_table *powerplay_table = 319 table_context->power_play_table; 320 struct smu_baco_context *smu_baco = &smu->smu_baco; 321 322 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC) 323 smu->dc_controlled_by_gpio = true; 324 325 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO || 326 powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) 327 smu_baco->platform_support = true; 328 329 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) 330 smu_baco->maco_support = true; 331 332 table_context->thermal_controller_type = 333 powerplay_table->thermal_controller_type; 334 335 /* 336 * Instead of having its own buffer space and get overdrive_table copied, 337 * smu->od_settings just points to the actual overdrive_table 338 */ 339 smu->od_settings = &powerplay_table->overdrive_table; 340 341 return 0; 342 } 343 344 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu) 345 { 346 struct smu_table_context *table_context = &smu->smu_table; 347 struct smu_13_0_0_powerplay_table *powerplay_table = 348 table_context->power_play_table; 349 350 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 351 sizeof(PPTable_t)); 352 353 return 0; 354 } 355 356 #ifndef atom_smc_dpm_info_table_13_0_0 357 struct atom_smc_dpm_info_table_13_0_0 { 358 struct atom_common_table_header table_header; 359 BoardTable_t BoardTable; 360 }; 361 #endif 362 363 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu) 364 { 365 struct smu_table_context *table_context = &smu->smu_table; 366 PPTable_t *smc_pptable = table_context->driver_pptable; 367 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table; 368 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 369 int index, ret; 370 371 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 372 smc_dpm_info); 373 374 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 375 (uint8_t **)&smc_dpm_table); 376 if (ret) 377 return ret; 378 379 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 380 381 return 0; 382 } 383 384 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu, 385 void **table, 386 uint32_t *size) 387 { 388 struct smu_table_context *smu_table = &smu->smu_table; 389 void *combo_pptable = smu_table->combo_pptable; 390 int ret = 0; 391 392 ret = smu_cmn_get_combo_pptable(smu); 393 if (ret) 394 return ret; 395 396 *table = combo_pptable; 397 *size = sizeof(struct smu_13_0_0_powerplay_table); 398 399 return 0; 400 } 401 402 static int smu_v13_0_0_setup_pptable(struct smu_context *smu) 403 { 404 struct smu_table_context *smu_table = &smu->smu_table; 405 struct amdgpu_device *adev = smu->adev; 406 int ret = 0; 407 408 ret = smu_v13_0_0_get_pptable_from_pmfw(smu, 409 &smu_table->power_play_table, 410 &smu_table->power_play_table_size); 411 if (ret) 412 return ret; 413 414 ret = smu_v13_0_0_store_powerplay_table(smu); 415 if (ret) 416 return ret; 417 418 /* 419 * With SCPM enabled, the operation below will be handled 420 * by PSP. Driver involvment is unnecessary and useless. 421 */ 422 if (!adev->scpm_enabled) { 423 ret = smu_v13_0_0_append_powerplay_table(smu); 424 if (ret) 425 return ret; 426 } 427 428 ret = smu_v13_0_0_check_powerplay_table(smu); 429 if (ret) 430 return ret; 431 432 return ret; 433 } 434 435 static int smu_v13_0_0_tables_init(struct smu_context *smu) 436 { 437 struct smu_table_context *smu_table = &smu->smu_table; 438 struct smu_table *tables = smu_table->tables; 439 440 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 441 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 442 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 443 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 444 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 445 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 446 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 447 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 448 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 449 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 450 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 451 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 452 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 453 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 454 AMDGPU_GEM_DOMAIN_VRAM); 455 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE, 456 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 457 458 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 459 if (!smu_table->metrics_table) 460 goto err0_out; 461 smu_table->metrics_time = 0; 462 463 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 464 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 465 if (!smu_table->gpu_metrics_table) 466 goto err1_out; 467 468 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 469 if (!smu_table->watermarks_table) 470 goto err2_out; 471 472 return 0; 473 474 err2_out: 475 kfree(smu_table->gpu_metrics_table); 476 err1_out: 477 kfree(smu_table->metrics_table); 478 err0_out: 479 return -ENOMEM; 480 } 481 482 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu) 483 { 484 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 485 486 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 487 GFP_KERNEL); 488 if (!smu_dpm->dpm_context) 489 return -ENOMEM; 490 491 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 492 493 return 0; 494 } 495 496 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu) 497 { 498 int ret = 0; 499 500 ret = smu_v13_0_0_tables_init(smu); 501 if (ret) 502 return ret; 503 504 ret = smu_v13_0_0_allocate_dpm_context(smu); 505 if (ret) 506 return ret; 507 508 return smu_v13_0_init_smc_tables(smu); 509 } 510 511 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) 512 { 513 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 514 struct smu_table_context *table_context = &smu->smu_table; 515 PPTable_t *pptable = table_context->driver_pptable; 516 SkuTable_t *skutable = &pptable->SkuTable; 517 struct smu_13_0_dpm_table *dpm_table; 518 struct smu_13_0_pcie_table *pcie_table; 519 uint32_t link_level; 520 int ret = 0; 521 522 /* socclk dpm table setup */ 523 dpm_table = &dpm_context->dpm_tables.soc_table; 524 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 525 ret = smu_v13_0_set_single_dpm_table(smu, 526 SMU_SOCCLK, 527 dpm_table); 528 if (ret) 529 return ret; 530 } else { 531 dpm_table->count = 1; 532 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 533 dpm_table->dpm_levels[0].enabled = true; 534 dpm_table->min = dpm_table->dpm_levels[0].value; 535 dpm_table->max = dpm_table->dpm_levels[0].value; 536 } 537 538 /* gfxclk dpm table setup */ 539 dpm_table = &dpm_context->dpm_tables.gfx_table; 540 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 541 ret = smu_v13_0_set_single_dpm_table(smu, 542 SMU_GFXCLK, 543 dpm_table); 544 if (ret) 545 return ret; 546 547 /* 548 * Update the reported maximum shader clock to the value 549 * which can be guarded to be achieved on all cards. This 550 * is aligned with Window setting. And considering that value 551 * might be not the peak frequency the card can achieve, it 552 * is normal some real-time clock frequency can overtake this 553 * labelled maximum clock frequency(for example in pp_dpm_sclk 554 * sysfs output). 555 */ 556 if (skutable->DriverReportedClocks.GameClockAc && 557 (dpm_table->dpm_levels[dpm_table->count - 1].value > 558 skutable->DriverReportedClocks.GameClockAc)) { 559 dpm_table->dpm_levels[dpm_table->count - 1].value = 560 skutable->DriverReportedClocks.GameClockAc; 561 dpm_table->max = skutable->DriverReportedClocks.GameClockAc; 562 } 563 } else { 564 dpm_table->count = 1; 565 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 566 dpm_table->dpm_levels[0].enabled = true; 567 dpm_table->min = dpm_table->dpm_levels[0].value; 568 dpm_table->max = dpm_table->dpm_levels[0].value; 569 } 570 571 /* uclk dpm table setup */ 572 dpm_table = &dpm_context->dpm_tables.uclk_table; 573 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 574 ret = smu_v13_0_set_single_dpm_table(smu, 575 SMU_UCLK, 576 dpm_table); 577 if (ret) 578 return ret; 579 } else { 580 dpm_table->count = 1; 581 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 582 dpm_table->dpm_levels[0].enabled = true; 583 dpm_table->min = dpm_table->dpm_levels[0].value; 584 dpm_table->max = dpm_table->dpm_levels[0].value; 585 } 586 587 /* fclk dpm table setup */ 588 dpm_table = &dpm_context->dpm_tables.fclk_table; 589 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 590 ret = smu_v13_0_set_single_dpm_table(smu, 591 SMU_FCLK, 592 dpm_table); 593 if (ret) 594 return ret; 595 } else { 596 dpm_table->count = 1; 597 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 598 dpm_table->dpm_levels[0].enabled = true; 599 dpm_table->min = dpm_table->dpm_levels[0].value; 600 dpm_table->max = dpm_table->dpm_levels[0].value; 601 } 602 603 /* vclk dpm table setup */ 604 dpm_table = &dpm_context->dpm_tables.vclk_table; 605 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { 606 ret = smu_v13_0_set_single_dpm_table(smu, 607 SMU_VCLK, 608 dpm_table); 609 if (ret) 610 return ret; 611 } else { 612 dpm_table->count = 1; 613 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 614 dpm_table->dpm_levels[0].enabled = true; 615 dpm_table->min = dpm_table->dpm_levels[0].value; 616 dpm_table->max = dpm_table->dpm_levels[0].value; 617 } 618 619 /* dclk dpm table setup */ 620 dpm_table = &dpm_context->dpm_tables.dclk_table; 621 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { 622 ret = smu_v13_0_set_single_dpm_table(smu, 623 SMU_DCLK, 624 dpm_table); 625 if (ret) 626 return ret; 627 } else { 628 dpm_table->count = 1; 629 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 630 dpm_table->dpm_levels[0].enabled = true; 631 dpm_table->min = dpm_table->dpm_levels[0].value; 632 dpm_table->max = dpm_table->dpm_levels[0].value; 633 } 634 635 /* lclk dpm table setup */ 636 pcie_table = &dpm_context->dpm_tables.pcie_table; 637 pcie_table->num_of_link_levels = 0; 638 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { 639 if (!skutable->PcieGenSpeed[link_level] && 640 !skutable->PcieLaneCount[link_level] && 641 !skutable->LclkFreq[link_level]) 642 continue; 643 644 pcie_table->pcie_gen[pcie_table->num_of_link_levels] = 645 skutable->PcieGenSpeed[link_level]; 646 pcie_table->pcie_lane[pcie_table->num_of_link_levels] = 647 skutable->PcieLaneCount[link_level]; 648 pcie_table->clk_freq[pcie_table->num_of_link_levels] = 649 skutable->LclkFreq[link_level]; 650 pcie_table->num_of_link_levels++; 651 } 652 653 return 0; 654 } 655 656 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) 657 { 658 int ret = 0; 659 uint64_t feature_enabled; 660 661 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 662 if (ret) 663 return false; 664 665 return !!(feature_enabled & SMC_DPM_FEATURE); 666 } 667 668 static void smu_v13_0_0_dump_pptable(struct smu_context *smu) 669 { 670 struct smu_table_context *table_context = &smu->smu_table; 671 PPTable_t *pptable = table_context->driver_pptable; 672 SkuTable_t *skutable = &pptable->SkuTable; 673 674 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 675 676 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version); 677 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]); 678 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]); 679 } 680 681 static int smu_v13_0_0_system_features_control(struct smu_context *smu, 682 bool en) 683 { 684 return smu_v13_0_system_features_control(smu, en); 685 } 686 687 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics) 688 { 689 uint32_t throttler_status = 0; 690 int i; 691 692 for (i = 0; i < THROTTLER_COUNT; i++) 693 throttler_status |= 694 (metrics->ThrottlingPercentage[i] ? 1U << i : 0); 695 696 return throttler_status; 697 } 698 699 #define SMU_13_0_0_BUSY_THRESHOLD 15 700 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu, 701 MetricsMember_t member, 702 uint32_t *value) 703 { 704 struct smu_table_context *smu_table = &smu->smu_table; 705 SmuMetrics_t *metrics = 706 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 707 int ret = 0; 708 709 ret = smu_cmn_get_metrics_table(smu, 710 NULL, 711 false); 712 if (ret) 713 return ret; 714 715 switch (member) { 716 case METRICS_CURR_GFXCLK: 717 *value = metrics->CurrClock[PPCLK_GFXCLK]; 718 break; 719 case METRICS_CURR_SOCCLK: 720 *value = metrics->CurrClock[PPCLK_SOCCLK]; 721 break; 722 case METRICS_CURR_UCLK: 723 *value = metrics->CurrClock[PPCLK_UCLK]; 724 break; 725 case METRICS_CURR_VCLK: 726 *value = metrics->CurrClock[PPCLK_VCLK_0]; 727 break; 728 case METRICS_CURR_VCLK1: 729 *value = metrics->CurrClock[PPCLK_VCLK_1]; 730 break; 731 case METRICS_CURR_DCLK: 732 *value = metrics->CurrClock[PPCLK_DCLK_0]; 733 break; 734 case METRICS_CURR_DCLK1: 735 *value = metrics->CurrClock[PPCLK_DCLK_1]; 736 break; 737 case METRICS_CURR_FCLK: 738 *value = metrics->CurrClock[PPCLK_FCLK]; 739 break; 740 case METRICS_AVERAGE_GFXCLK: 741 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 742 *value = metrics->AverageGfxclkFrequencyPostDs; 743 else 744 *value = metrics->AverageGfxclkFrequencyPreDs; 745 break; 746 case METRICS_AVERAGE_FCLK: 747 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 748 *value = metrics->AverageFclkFrequencyPostDs; 749 else 750 *value = metrics->AverageFclkFrequencyPreDs; 751 break; 752 case METRICS_AVERAGE_UCLK: 753 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 754 *value = metrics->AverageMemclkFrequencyPostDs; 755 else 756 *value = metrics->AverageMemclkFrequencyPreDs; 757 break; 758 case METRICS_AVERAGE_VCLK: 759 *value = metrics->AverageVclk0Frequency; 760 break; 761 case METRICS_AVERAGE_DCLK: 762 *value = metrics->AverageDclk0Frequency; 763 break; 764 case METRICS_AVERAGE_VCLK1: 765 *value = metrics->AverageVclk1Frequency; 766 break; 767 case METRICS_AVERAGE_DCLK1: 768 *value = metrics->AverageDclk1Frequency; 769 break; 770 case METRICS_AVERAGE_GFXACTIVITY: 771 *value = metrics->AverageGfxActivity; 772 break; 773 case METRICS_AVERAGE_MEMACTIVITY: 774 *value = metrics->AverageUclkActivity; 775 break; 776 case METRICS_AVERAGE_SOCKETPOWER: 777 *value = metrics->AverageSocketPower << 8; 778 break; 779 case METRICS_TEMPERATURE_EDGE: 780 *value = metrics->AvgTemperature[TEMP_EDGE] * 781 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 782 break; 783 case METRICS_TEMPERATURE_HOTSPOT: 784 *value = metrics->AvgTemperature[TEMP_HOTSPOT] * 785 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 786 break; 787 case METRICS_TEMPERATURE_MEM: 788 *value = metrics->AvgTemperature[TEMP_MEM] * 789 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 790 break; 791 case METRICS_TEMPERATURE_VRGFX: 792 *value = metrics->AvgTemperature[TEMP_VR_GFX] * 793 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 794 break; 795 case METRICS_TEMPERATURE_VRSOC: 796 *value = metrics->AvgTemperature[TEMP_VR_SOC] * 797 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 798 break; 799 case METRICS_THROTTLER_STATUS: 800 *value = smu_v13_0_get_throttler_status(metrics); 801 break; 802 case METRICS_CURR_FANSPEED: 803 *value = metrics->AvgFanRpm; 804 break; 805 case METRICS_CURR_FANPWM: 806 *value = metrics->AvgFanPwm; 807 break; 808 case METRICS_VOLTAGE_VDDGFX: 809 *value = metrics->AvgVoltage[SVI_PLANE_GFX]; 810 break; 811 case METRICS_PCIE_RATE: 812 *value = metrics->PcieRate; 813 break; 814 case METRICS_PCIE_WIDTH: 815 *value = metrics->PcieWidth; 816 break; 817 default: 818 *value = UINT_MAX; 819 break; 820 } 821 822 return ret; 823 } 824 825 static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu, 826 enum smu_clk_type clk_type, 827 uint32_t *min, 828 uint32_t *max) 829 { 830 struct smu_13_0_dpm_context *dpm_context = 831 smu->smu_dpm.dpm_context; 832 struct smu_13_0_dpm_table *dpm_table; 833 834 switch (clk_type) { 835 case SMU_MCLK: 836 case SMU_UCLK: 837 /* uclk dpm table */ 838 dpm_table = &dpm_context->dpm_tables.uclk_table; 839 break; 840 case SMU_GFXCLK: 841 case SMU_SCLK: 842 /* gfxclk dpm table */ 843 dpm_table = &dpm_context->dpm_tables.gfx_table; 844 break; 845 case SMU_SOCCLK: 846 /* socclk dpm table */ 847 dpm_table = &dpm_context->dpm_tables.soc_table; 848 break; 849 case SMU_FCLK: 850 /* fclk dpm table */ 851 dpm_table = &dpm_context->dpm_tables.fclk_table; 852 break; 853 case SMU_VCLK: 854 case SMU_VCLK1: 855 /* vclk dpm table */ 856 dpm_table = &dpm_context->dpm_tables.vclk_table; 857 break; 858 case SMU_DCLK: 859 case SMU_DCLK1: 860 /* dclk dpm table */ 861 dpm_table = &dpm_context->dpm_tables.dclk_table; 862 break; 863 default: 864 dev_err(smu->adev->dev, "Unsupported clock type!\n"); 865 return -EINVAL; 866 } 867 868 if (min) 869 *min = dpm_table->min; 870 if (max) 871 *max = dpm_table->max; 872 873 return 0; 874 } 875 876 static int smu_v13_0_0_read_sensor(struct smu_context *smu, 877 enum amd_pp_sensors sensor, 878 void *data, 879 uint32_t *size) 880 { 881 struct smu_table_context *table_context = &smu->smu_table; 882 PPTable_t *smc_pptable = table_context->driver_pptable; 883 int ret = 0; 884 885 switch (sensor) { 886 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 887 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm; 888 *size = 4; 889 break; 890 case AMDGPU_PP_SENSOR_MEM_LOAD: 891 ret = smu_v13_0_0_get_smu_metrics_data(smu, 892 METRICS_AVERAGE_MEMACTIVITY, 893 (uint32_t *)data); 894 *size = 4; 895 break; 896 case AMDGPU_PP_SENSOR_GPU_LOAD: 897 ret = smu_v13_0_0_get_smu_metrics_data(smu, 898 METRICS_AVERAGE_GFXACTIVITY, 899 (uint32_t *)data); 900 *size = 4; 901 break; 902 case AMDGPU_PP_SENSOR_GPU_POWER: 903 ret = smu_v13_0_0_get_smu_metrics_data(smu, 904 METRICS_AVERAGE_SOCKETPOWER, 905 (uint32_t *)data); 906 *size = 4; 907 break; 908 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 909 ret = smu_v13_0_0_get_smu_metrics_data(smu, 910 METRICS_TEMPERATURE_HOTSPOT, 911 (uint32_t *)data); 912 *size = 4; 913 break; 914 case AMDGPU_PP_SENSOR_EDGE_TEMP: 915 ret = smu_v13_0_0_get_smu_metrics_data(smu, 916 METRICS_TEMPERATURE_EDGE, 917 (uint32_t *)data); 918 *size = 4; 919 break; 920 case AMDGPU_PP_SENSOR_MEM_TEMP: 921 ret = smu_v13_0_0_get_smu_metrics_data(smu, 922 METRICS_TEMPERATURE_MEM, 923 (uint32_t *)data); 924 *size = 4; 925 break; 926 case AMDGPU_PP_SENSOR_GFX_MCLK: 927 ret = smu_v13_0_0_get_smu_metrics_data(smu, 928 METRICS_CURR_UCLK, 929 (uint32_t *)data); 930 *(uint32_t *)data *= 100; 931 *size = 4; 932 break; 933 case AMDGPU_PP_SENSOR_GFX_SCLK: 934 ret = smu_v13_0_0_get_smu_metrics_data(smu, 935 METRICS_AVERAGE_GFXCLK, 936 (uint32_t *)data); 937 *(uint32_t *)data *= 100; 938 *size = 4; 939 break; 940 case AMDGPU_PP_SENSOR_VDDGFX: 941 ret = smu_v13_0_0_get_smu_metrics_data(smu, 942 METRICS_VOLTAGE_VDDGFX, 943 (uint32_t *)data); 944 *size = 4; 945 break; 946 default: 947 ret = -EOPNOTSUPP; 948 break; 949 } 950 951 return ret; 952 } 953 954 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu, 955 enum smu_clk_type clk_type, 956 uint32_t *value) 957 { 958 MetricsMember_t member_type; 959 int clk_id = 0; 960 961 clk_id = smu_cmn_to_asic_specific_index(smu, 962 CMN2ASIC_MAPPING_CLK, 963 clk_type); 964 if (clk_id < 0) 965 return -EINVAL; 966 967 switch (clk_id) { 968 case PPCLK_GFXCLK: 969 member_type = METRICS_AVERAGE_GFXCLK; 970 break; 971 case PPCLK_UCLK: 972 member_type = METRICS_CURR_UCLK; 973 break; 974 case PPCLK_FCLK: 975 member_type = METRICS_CURR_FCLK; 976 break; 977 case PPCLK_SOCCLK: 978 member_type = METRICS_CURR_SOCCLK; 979 break; 980 case PPCLK_VCLK_0: 981 member_type = METRICS_AVERAGE_VCLK; 982 break; 983 case PPCLK_DCLK_0: 984 member_type = METRICS_AVERAGE_DCLK; 985 break; 986 case PPCLK_VCLK_1: 987 member_type = METRICS_AVERAGE_VCLK1; 988 break; 989 case PPCLK_DCLK_1: 990 member_type = METRICS_AVERAGE_DCLK1; 991 break; 992 default: 993 return -EINVAL; 994 } 995 996 return smu_v13_0_0_get_smu_metrics_data(smu, 997 member_type, 998 value); 999 } 1000 1001 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, 1002 enum smu_clk_type clk_type, 1003 char *buf) 1004 { 1005 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1006 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1007 struct smu_13_0_dpm_table *single_dpm_table; 1008 struct smu_13_0_pcie_table *pcie_table; 1009 const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 1010 uint32_t gen_speed, lane_width; 1011 int i, curr_freq, size = 0; 1012 int ret = 0; 1013 1014 smu_cmn_get_sysfs_buf(&buf, &size); 1015 1016 if (amdgpu_ras_intr_triggered()) { 1017 size += sysfs_emit_at(buf, size, "unavailable\n"); 1018 return size; 1019 } 1020 1021 switch (clk_type) { 1022 case SMU_SCLK: 1023 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1024 break; 1025 case SMU_MCLK: 1026 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1027 break; 1028 case SMU_SOCCLK: 1029 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1030 break; 1031 case SMU_FCLK: 1032 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1033 break; 1034 case SMU_VCLK: 1035 case SMU_VCLK1: 1036 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1037 break; 1038 case SMU_DCLK: 1039 case SMU_DCLK1: 1040 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1041 break; 1042 default: 1043 break; 1044 } 1045 1046 switch (clk_type) { 1047 case SMU_SCLK: 1048 case SMU_MCLK: 1049 case SMU_SOCCLK: 1050 case SMU_FCLK: 1051 case SMU_VCLK: 1052 case SMU_VCLK1: 1053 case SMU_DCLK: 1054 case SMU_DCLK1: 1055 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); 1056 if (ret) { 1057 dev_err(smu->adev->dev, "Failed to get current clock freq!"); 1058 return ret; 1059 } 1060 1061 if (single_dpm_table->is_fine_grained) { 1062 /* 1063 * For fine grained dpms, there are only two dpm levels: 1064 * - level 0 -> min clock freq 1065 * - level 1 -> max clock freq 1066 * And the current clock frequency can be any value between them. 1067 * So, if the current clock frequency is not at level 0 or level 1, 1068 * we will fake it as three dpm levels: 1069 * - level 0 -> min clock freq 1070 * - level 1 -> current actual clock freq 1071 * - level 2 -> max clock freq 1072 */ 1073 if ((single_dpm_table->dpm_levels[0].value != curr_freq) && 1074 (single_dpm_table->dpm_levels[1].value != curr_freq)) { 1075 size += sysfs_emit_at(buf, size, "0: %uMhz\n", 1076 single_dpm_table->dpm_levels[0].value); 1077 size += sysfs_emit_at(buf, size, "1: %uMhz *\n", 1078 curr_freq); 1079 size += sysfs_emit_at(buf, size, "2: %uMhz\n", 1080 single_dpm_table->dpm_levels[1].value); 1081 } else { 1082 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 1083 single_dpm_table->dpm_levels[0].value, 1084 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); 1085 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 1086 single_dpm_table->dpm_levels[1].value, 1087 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); 1088 } 1089 } else { 1090 for (i = 0; i < single_dpm_table->count; i++) 1091 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 1092 i, single_dpm_table->dpm_levels[i].value, 1093 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); 1094 } 1095 break; 1096 case SMU_PCIE: 1097 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1098 METRICS_PCIE_RATE, 1099 &gen_speed); 1100 if (ret) 1101 return ret; 1102 1103 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1104 METRICS_PCIE_WIDTH, 1105 &lane_width); 1106 if (ret) 1107 return ret; 1108 1109 pcie_table = &(dpm_context->dpm_tables.pcie_table); 1110 for (i = 0; i < pcie_table->num_of_link_levels; i++) 1111 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1112 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : 1113 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : 1114 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : 1115 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", 1116 (pcie_table->pcie_lane[i] == 1) ? "x1" : 1117 (pcie_table->pcie_lane[i] == 2) ? "x2" : 1118 (pcie_table->pcie_lane[i] == 3) ? "x4" : 1119 (pcie_table->pcie_lane[i] == 4) ? "x8" : 1120 (pcie_table->pcie_lane[i] == 5) ? "x12" : 1121 (pcie_table->pcie_lane[i] == 6) ? "x16" : "", 1122 pcie_table->clk_freq[i], 1123 ((gen_speed - 1) == pcie_table->pcie_gen[i]) && 1124 (lane_width == link_width[pcie_table->pcie_lane[i]]) ? 1125 "*" : ""); 1126 break; 1127 1128 default: 1129 break; 1130 } 1131 1132 return size; 1133 } 1134 1135 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu, 1136 enum smu_clk_type clk_type, 1137 uint32_t mask) 1138 { 1139 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1140 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1141 struct smu_13_0_dpm_table *single_dpm_table; 1142 uint32_t soft_min_level, soft_max_level; 1143 uint32_t min_freq, max_freq; 1144 int ret = 0; 1145 1146 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1147 soft_max_level = mask ? (fls(mask) - 1) : 0; 1148 1149 switch (clk_type) { 1150 case SMU_GFXCLK: 1151 case SMU_SCLK: 1152 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1153 break; 1154 case SMU_MCLK: 1155 case SMU_UCLK: 1156 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1157 break; 1158 case SMU_SOCCLK: 1159 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1160 break; 1161 case SMU_FCLK: 1162 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1163 break; 1164 case SMU_VCLK: 1165 case SMU_VCLK1: 1166 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1167 break; 1168 case SMU_DCLK: 1169 case SMU_DCLK1: 1170 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1171 break; 1172 default: 1173 break; 1174 } 1175 1176 switch (clk_type) { 1177 case SMU_GFXCLK: 1178 case SMU_SCLK: 1179 case SMU_MCLK: 1180 case SMU_UCLK: 1181 case SMU_SOCCLK: 1182 case SMU_FCLK: 1183 case SMU_VCLK: 1184 case SMU_VCLK1: 1185 case SMU_DCLK: 1186 case SMU_DCLK1: 1187 if (single_dpm_table->is_fine_grained) { 1188 /* There is only 2 levels for fine grained DPM */ 1189 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1190 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1191 } else { 1192 if ((soft_max_level >= single_dpm_table->count) || 1193 (soft_min_level >= single_dpm_table->count)) 1194 return -EINVAL; 1195 } 1196 1197 min_freq = single_dpm_table->dpm_levels[soft_min_level].value; 1198 max_freq = single_dpm_table->dpm_levels[soft_max_level].value; 1199 1200 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1201 clk_type, 1202 min_freq, 1203 max_freq); 1204 break; 1205 case SMU_DCEFCLK: 1206 case SMU_PCIE: 1207 default: 1208 break; 1209 } 1210 1211 return ret; 1212 } 1213 1214 static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, 1215 uint32_t pcie_gen_cap, 1216 uint32_t pcie_width_cap) 1217 { 1218 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1219 struct smu_13_0_pcie_table *pcie_table = 1220 &dpm_context->dpm_tables.pcie_table; 1221 uint32_t smu_pcie_arg; 1222 int ret, i; 1223 1224 for (i = 0; i < pcie_table->num_of_link_levels; i++) { 1225 if (pcie_table->pcie_gen[i] > pcie_gen_cap) 1226 pcie_table->pcie_gen[i] = pcie_gen_cap; 1227 if (pcie_table->pcie_lane[i] > pcie_width_cap) 1228 pcie_table->pcie_lane[i] = pcie_width_cap; 1229 1230 smu_pcie_arg = i << 16; 1231 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8; 1232 smu_pcie_arg |= pcie_table->pcie_lane[i]; 1233 1234 ret = smu_cmn_send_smc_msg_with_param(smu, 1235 SMU_MSG_OverridePcieParameters, 1236 smu_pcie_arg, 1237 NULL); 1238 if (ret) 1239 return ret; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static const struct smu_temperature_range smu13_thermal_policy[] = { 1246 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 1247 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 1248 }; 1249 1250 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu, 1251 struct smu_temperature_range *range) 1252 { 1253 struct smu_table_context *table_context = &smu->smu_table; 1254 struct smu_13_0_0_powerplay_table *powerplay_table = 1255 table_context->power_play_table; 1256 PPTable_t *pptable = smu->smu_table.driver_pptable; 1257 1258 if (!range) 1259 return -EINVAL; 1260 1261 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1262 1263 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] * 1264 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1265 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1266 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1267 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] * 1268 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1269 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1270 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1271 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] * 1272 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1273 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1274 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1275 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1276 1277 return 0; 1278 } 1279 1280 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 1281 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, 1282 void **table) 1283 { 1284 struct smu_table_context *smu_table = &smu->smu_table; 1285 struct gpu_metrics_v1_3 *gpu_metrics = 1286 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1287 SmuMetricsExternal_t metrics_ext; 1288 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 1289 int ret = 0; 1290 1291 ret = smu_cmn_get_metrics_table(smu, 1292 &metrics_ext, 1293 true); 1294 if (ret) 1295 return ret; 1296 1297 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1298 1299 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE]; 1300 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT]; 1301 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM]; 1302 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX]; 1303 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC]; 1304 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0], 1305 metrics->AvgTemperature[TEMP_VR_MEM1]); 1306 1307 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 1308 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 1309 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage, 1310 metrics->Vcn1ActivityPercentage); 1311 1312 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 1313 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 1314 1315 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 1316 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 1317 else 1318 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 1319 1320 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 1321 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 1322 else 1323 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs; 1324 1325 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 1326 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 1327 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 1328 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 1329 1330 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; 1331 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK]; 1332 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; 1333 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 1334 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 1335 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 1336 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 1337 1338 gpu_metrics->throttle_status = 1339 smu_v13_0_get_throttler_status(metrics); 1340 gpu_metrics->indep_throttle_status = 1341 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 1342 smu_v13_0_0_throttler_map); 1343 1344 gpu_metrics->current_fan_speed = metrics->AvgFanRpm; 1345 1346 gpu_metrics->pcie_link_width = metrics->PcieWidth; 1347 gpu_metrics->pcie_link_speed = metrics->PcieRate; 1348 1349 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1350 1351 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX]; 1352 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC]; 1353 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP]; 1354 1355 *table = (void *)gpu_metrics; 1356 1357 return sizeof(struct gpu_metrics_v1_3); 1358 } 1359 1360 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu) 1361 { 1362 struct smu_13_0_dpm_context *dpm_context = 1363 smu->smu_dpm.dpm_context; 1364 struct smu_13_0_dpm_table *gfx_table = 1365 &dpm_context->dpm_tables.gfx_table; 1366 struct smu_13_0_dpm_table *mem_table = 1367 &dpm_context->dpm_tables.uclk_table; 1368 struct smu_13_0_dpm_table *soc_table = 1369 &dpm_context->dpm_tables.soc_table; 1370 struct smu_13_0_dpm_table *vclk_table = 1371 &dpm_context->dpm_tables.vclk_table; 1372 struct smu_13_0_dpm_table *dclk_table = 1373 &dpm_context->dpm_tables.dclk_table; 1374 struct smu_13_0_dpm_table *fclk_table = 1375 &dpm_context->dpm_tables.fclk_table; 1376 struct smu_umd_pstate_table *pstate_table = 1377 &smu->pstate_table; 1378 struct smu_table_context *table_context = &smu->smu_table; 1379 PPTable_t *pptable = table_context->driver_pptable; 1380 DriverReportedClocks_t driver_clocks = 1381 pptable->SkuTable.DriverReportedClocks; 1382 1383 pstate_table->gfxclk_pstate.min = gfx_table->min; 1384 if (driver_clocks.GameClockAc && 1385 (driver_clocks.GameClockAc < gfx_table->max)) 1386 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc; 1387 else 1388 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1389 1390 pstate_table->uclk_pstate.min = mem_table->min; 1391 pstate_table->uclk_pstate.peak = mem_table->max; 1392 1393 pstate_table->socclk_pstate.min = soc_table->min; 1394 pstate_table->socclk_pstate.peak = soc_table->max; 1395 1396 pstate_table->vclk_pstate.min = vclk_table->min; 1397 pstate_table->vclk_pstate.peak = vclk_table->max; 1398 1399 pstate_table->dclk_pstate.min = dclk_table->min; 1400 pstate_table->dclk_pstate.peak = dclk_table->max; 1401 1402 pstate_table->fclk_pstate.min = fclk_table->min; 1403 pstate_table->fclk_pstate.peak = fclk_table->max; 1404 1405 if (driver_clocks.BaseClockAc && 1406 driver_clocks.BaseClockAc < gfx_table->max) 1407 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc; 1408 else 1409 pstate_table->gfxclk_pstate.standard = gfx_table->max; 1410 pstate_table->uclk_pstate.standard = mem_table->max; 1411 pstate_table->socclk_pstate.standard = soc_table->min; 1412 pstate_table->vclk_pstate.standard = vclk_table->min; 1413 pstate_table->dclk_pstate.standard = dclk_table->min; 1414 pstate_table->fclk_pstate.standard = fclk_table->min; 1415 1416 return 0; 1417 } 1418 1419 static void smu_v13_0_0_get_unique_id(struct smu_context *smu) 1420 { 1421 struct smu_table_context *smu_table = &smu->smu_table; 1422 SmuMetrics_t *metrics = 1423 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 1424 struct amdgpu_device *adev = smu->adev; 1425 uint32_t upper32 = 0, lower32 = 0; 1426 int ret; 1427 1428 ret = smu_cmn_get_metrics_table(smu, NULL, false); 1429 if (ret) 1430 goto out; 1431 1432 upper32 = metrics->PublicSerialNumberUpper; 1433 lower32 = metrics->PublicSerialNumberLower; 1434 1435 out: 1436 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1437 if (adev->serial[0] == '\0') 1438 sprintf(adev->serial, "%016llx", adev->unique_id); 1439 } 1440 1441 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu, 1442 uint32_t *speed) 1443 { 1444 int ret; 1445 1446 if (!speed) 1447 return -EINVAL; 1448 1449 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1450 METRICS_CURR_FANPWM, 1451 speed); 1452 if (ret) { 1453 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!"); 1454 return ret; 1455 } 1456 1457 /* Convert the PMFW output which is in percent to pwm(255) based */ 1458 *speed = MIN(*speed * 255 / 100, 255); 1459 1460 return 0; 1461 } 1462 1463 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu, 1464 uint32_t *speed) 1465 { 1466 if (!speed) 1467 return -EINVAL; 1468 1469 return smu_v13_0_0_get_smu_metrics_data(smu, 1470 METRICS_CURR_FANSPEED, 1471 speed); 1472 } 1473 1474 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu) 1475 { 1476 struct smu_table_context *table_context = &smu->smu_table; 1477 PPTable_t *pptable = table_context->driver_pptable; 1478 SkuTable_t *skutable = &pptable->SkuTable; 1479 1480 /* 1481 * Skip the MGpuFanBoost setting for those ASICs 1482 * which do not support it 1483 */ 1484 if (skutable->MGpuAcousticLimitRpmThreshold == 0) 1485 return 0; 1486 1487 return smu_cmn_send_smc_msg_with_param(smu, 1488 SMU_MSG_SetMGpuFanBoostLimitRpm, 1489 0, 1490 NULL); 1491 } 1492 1493 static int smu_v13_0_0_get_power_limit(struct smu_context *smu, 1494 uint32_t *current_power_limit, 1495 uint32_t *default_power_limit, 1496 uint32_t *max_power_limit) 1497 { 1498 struct smu_table_context *table_context = &smu->smu_table; 1499 struct smu_13_0_0_powerplay_table *powerplay_table = 1500 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table; 1501 PPTable_t *pptable = table_context->driver_pptable; 1502 SkuTable_t *skutable = &pptable->SkuTable; 1503 uint32_t power_limit, od_percent; 1504 1505 if (smu_v13_0_get_current_power_limit(smu, &power_limit)) 1506 power_limit = smu->adev->pm.ac_power ? 1507 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] : 1508 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0]; 1509 1510 if (current_power_limit) 1511 *current_power_limit = power_limit; 1512 if (default_power_limit) 1513 *default_power_limit = power_limit; 1514 1515 if (max_power_limit) { 1516 if (smu->od_enabled) { 1517 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]); 1518 1519 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1520 1521 power_limit *= (100 + od_percent); 1522 power_limit /= 100; 1523 } 1524 *max_power_limit = power_limit; 1525 } 1526 1527 return 0; 1528 } 1529 1530 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu, 1531 char *buf) 1532 { 1533 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1534 DpmActivityMonitorCoeffInt_t *activity_monitor = 1535 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1536 static const char *title[] = { 1537 "PROFILE_INDEX(NAME)", 1538 "CLOCK_TYPE(NAME)", 1539 "FPS", 1540 "MinActiveFreqType", 1541 "MinActiveFreq", 1542 "BoosterFreqType", 1543 "BoosterFreq", 1544 "PD_Data_limit_c", 1545 "PD_Data_error_coeff", 1546 "PD_Data_error_rate_coeff"}; 1547 int16_t workload_type = 0; 1548 uint32_t i, size = 0; 1549 int result = 0; 1550 1551 if (!buf) 1552 return -EINVAL; 1553 1554 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n", 1555 title[0], title[1], title[2], title[3], title[4], title[5], 1556 title[6], title[7], title[8], title[9]); 1557 1558 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1559 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1560 workload_type = smu_cmn_to_asic_specific_index(smu, 1561 CMN2ASIC_MAPPING_WORKLOAD, 1562 i); 1563 if (workload_type < 0) 1564 return -EINVAL; 1565 1566 result = smu_cmn_update_table(smu, 1567 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1568 workload_type, 1569 (void *)(&activity_monitor_external), 1570 false); 1571 if (result) { 1572 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1573 return result; 1574 } 1575 1576 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1577 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1578 1579 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 1580 " ", 1581 0, 1582 "GFXCLK", 1583 activity_monitor->Gfx_FPS, 1584 activity_monitor->Gfx_MinActiveFreqType, 1585 activity_monitor->Gfx_MinActiveFreq, 1586 activity_monitor->Gfx_BoosterFreqType, 1587 activity_monitor->Gfx_BoosterFreq, 1588 activity_monitor->Gfx_PD_Data_limit_c, 1589 activity_monitor->Gfx_PD_Data_error_coeff, 1590 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1591 1592 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 1593 " ", 1594 1, 1595 "FCLK", 1596 activity_monitor->Fclk_FPS, 1597 activity_monitor->Fclk_MinActiveFreqType, 1598 activity_monitor->Fclk_MinActiveFreq, 1599 activity_monitor->Fclk_BoosterFreqType, 1600 activity_monitor->Fclk_BoosterFreq, 1601 activity_monitor->Fclk_PD_Data_limit_c, 1602 activity_monitor->Fclk_PD_Data_error_coeff, 1603 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1604 } 1605 1606 return size; 1607 } 1608 1609 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, 1610 long *input, 1611 uint32_t size) 1612 { 1613 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1614 DpmActivityMonitorCoeffInt_t *activity_monitor = 1615 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1616 int workload_type, ret = 0; 1617 1618 smu->power_profile_mode = input[size]; 1619 1620 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1621 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1622 return -EINVAL; 1623 } 1624 1625 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1626 ret = smu_cmn_update_table(smu, 1627 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1628 WORKLOAD_PPLIB_CUSTOM_BIT, 1629 (void *)(&activity_monitor_external), 1630 false); 1631 if (ret) { 1632 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1633 return ret; 1634 } 1635 1636 switch (input[0]) { 1637 case 0: /* Gfxclk */ 1638 activity_monitor->Gfx_FPS = input[1]; 1639 activity_monitor->Gfx_MinActiveFreqType = input[2]; 1640 activity_monitor->Gfx_MinActiveFreq = input[3]; 1641 activity_monitor->Gfx_BoosterFreqType = input[4]; 1642 activity_monitor->Gfx_BoosterFreq = input[5]; 1643 activity_monitor->Gfx_PD_Data_limit_c = input[6]; 1644 activity_monitor->Gfx_PD_Data_error_coeff = input[7]; 1645 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8]; 1646 break; 1647 case 1: /* Fclk */ 1648 activity_monitor->Fclk_FPS = input[1]; 1649 activity_monitor->Fclk_MinActiveFreqType = input[2]; 1650 activity_monitor->Fclk_MinActiveFreq = input[3]; 1651 activity_monitor->Fclk_BoosterFreqType = input[4]; 1652 activity_monitor->Fclk_BoosterFreq = input[5]; 1653 activity_monitor->Fclk_PD_Data_limit_c = input[6]; 1654 activity_monitor->Fclk_PD_Data_error_coeff = input[7]; 1655 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; 1656 break; 1657 } 1658 1659 ret = smu_cmn_update_table(smu, 1660 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1661 WORKLOAD_PPLIB_CUSTOM_BIT, 1662 (void *)(&activity_monitor_external), 1663 true); 1664 if (ret) { 1665 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1666 return ret; 1667 } 1668 } 1669 1670 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1671 workload_type = smu_cmn_to_asic_specific_index(smu, 1672 CMN2ASIC_MAPPING_WORKLOAD, 1673 smu->power_profile_mode); 1674 if (workload_type < 0) 1675 return -EINVAL; 1676 1677 return smu_cmn_send_smc_msg_with_param(smu, 1678 SMU_MSG_SetWorkloadMask, 1679 1 << workload_type, 1680 NULL); 1681 } 1682 1683 static int smu_v13_0_0_baco_enter(struct smu_context *smu) 1684 { 1685 struct smu_baco_context *smu_baco = &smu->smu_baco; 1686 struct amdgpu_device *adev = smu->adev; 1687 1688 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 1689 return smu_v13_0_baco_set_armd3_sequence(smu, 1690 smu_baco->maco_support ? BACO_SEQ_BAMACO : BACO_SEQ_BACO); 1691 else 1692 return smu_v13_0_baco_enter(smu); 1693 } 1694 1695 static int smu_v13_0_0_baco_exit(struct smu_context *smu) 1696 { 1697 struct amdgpu_device *adev = smu->adev; 1698 1699 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 1700 /* Wait for PMFW handling for the Dstate change */ 1701 usleep_range(10000, 11000); 1702 return smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 1703 } else { 1704 return smu_v13_0_baco_exit(smu); 1705 } 1706 } 1707 1708 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) 1709 { 1710 struct amdgpu_device *adev = smu->adev; 1711 u32 smu_version; 1712 1713 /* SRIOV does not support SMU mode1 reset */ 1714 if (amdgpu_sriov_vf(adev)) 1715 return false; 1716 1717 /* PMFW support is available since 78.41 */ 1718 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1719 if (smu_version < 0x004e2900) 1720 return false; 1721 1722 return true; 1723 } 1724 1725 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap, 1726 struct i2c_msg *msg, int num_msgs) 1727 { 1728 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 1729 struct amdgpu_device *adev = smu_i2c->adev; 1730 struct smu_context *smu = adev->powerplay.pp_handle; 1731 struct smu_table_context *smu_table = &smu->smu_table; 1732 struct smu_table *table = &smu_table->driver_table; 1733 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1734 int i, j, r, c; 1735 u16 dir; 1736 1737 if (!adev->pm.dpm_enabled) 1738 return -EBUSY; 1739 1740 req = kzalloc(sizeof(*req), GFP_KERNEL); 1741 if (!req) 1742 return -ENOMEM; 1743 1744 req->I2CcontrollerPort = smu_i2c->port; 1745 req->I2CSpeed = I2C_SPEED_FAST_400K; 1746 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1747 dir = msg[0].flags & I2C_M_RD; 1748 1749 for (c = i = 0; i < num_msgs; i++) { 1750 for (j = 0; j < msg[i].len; j++, c++) { 1751 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1752 1753 if (!(msg[i].flags & I2C_M_RD)) { 1754 /* write */ 1755 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1756 cmd->ReadWriteData = msg[i].buf[j]; 1757 } 1758 1759 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1760 /* The direction changes. 1761 */ 1762 dir = msg[i].flags & I2C_M_RD; 1763 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1764 } 1765 1766 req->NumCmds++; 1767 1768 /* 1769 * Insert STOP if we are at the last byte of either last 1770 * message for the transaction or the client explicitly 1771 * requires a STOP at this particular message. 1772 */ 1773 if ((j == msg[i].len - 1) && 1774 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1775 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1776 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1777 } 1778 } 1779 } 1780 mutex_lock(&adev->pm.mutex); 1781 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1782 mutex_unlock(&adev->pm.mutex); 1783 if (r) 1784 goto fail; 1785 1786 for (c = i = 0; i < num_msgs; i++) { 1787 if (!(msg[i].flags & I2C_M_RD)) { 1788 c += msg[i].len; 1789 continue; 1790 } 1791 for (j = 0; j < msg[i].len; j++, c++) { 1792 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1793 1794 msg[i].buf[j] = cmd->ReadWriteData; 1795 } 1796 } 1797 r = num_msgs; 1798 fail: 1799 kfree(req); 1800 return r; 1801 } 1802 1803 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap) 1804 { 1805 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1806 } 1807 1808 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = { 1809 .master_xfer = smu_v13_0_0_i2c_xfer, 1810 .functionality = smu_v13_0_0_i2c_func, 1811 }; 1812 1813 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = { 1814 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1815 .max_read_len = MAX_SW_I2C_COMMANDS, 1816 .max_write_len = MAX_SW_I2C_COMMANDS, 1817 .max_comb_1st_msg_len = 2, 1818 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1819 }; 1820 1821 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu) 1822 { 1823 struct amdgpu_device *adev = smu->adev; 1824 int res, i; 1825 1826 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1827 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1828 struct i2c_adapter *control = &smu_i2c->adapter; 1829 1830 smu_i2c->adev = adev; 1831 smu_i2c->port = i; 1832 mutex_init(&smu_i2c->mutex); 1833 control->owner = THIS_MODULE; 1834 control->class = I2C_CLASS_SPD; 1835 control->dev.parent = &adev->pdev->dev; 1836 control->algo = &smu_v13_0_0_i2c_algo; 1837 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 1838 control->quirks = &smu_v13_0_0_i2c_control_quirks; 1839 i2c_set_adapdata(control, smu_i2c); 1840 1841 res = i2c_add_adapter(control); 1842 if (res) { 1843 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1844 goto Out_err; 1845 } 1846 } 1847 1848 /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 1849 /* XXX ideally this would be something in a vbios data table */ 1850 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 1851 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1852 1853 return 0; 1854 Out_err: 1855 for ( ; i >= 0; i--) { 1856 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1857 struct i2c_adapter *control = &smu_i2c->adapter; 1858 1859 i2c_del_adapter(control); 1860 } 1861 return res; 1862 } 1863 1864 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu) 1865 { 1866 struct amdgpu_device *adev = smu->adev; 1867 int i; 1868 1869 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1870 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1871 struct i2c_adapter *control = &smu_i2c->adapter; 1872 1873 i2c_del_adapter(control); 1874 } 1875 adev->pm.ras_eeprom_i2c_bus = NULL; 1876 adev->pm.fru_eeprom_i2c_bus = NULL; 1877 } 1878 1879 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu, 1880 enum pp_mp1_state mp1_state) 1881 { 1882 int ret; 1883 1884 switch (mp1_state) { 1885 case PP_MP1_STATE_UNLOAD: 1886 ret = smu_cmn_set_mp1_state(smu, mp1_state); 1887 break; 1888 default: 1889 /* Ignore others */ 1890 ret = 0; 1891 } 1892 1893 return ret; 1894 } 1895 1896 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu, 1897 enum pp_df_cstate state) 1898 { 1899 return smu_cmn_send_smc_msg_with_param(smu, 1900 SMU_MSG_DFCstateControl, 1901 state, 1902 NULL); 1903 } 1904 1905 static int smu_v13_0_0_mode1_reset(struct smu_context *smu) 1906 { 1907 int ret; 1908 struct amdgpu_device *adev = smu->adev; 1909 1910 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) 1911 ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset); 1912 else 1913 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1914 1915 if (!ret) 1916 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 1917 1918 return ret; 1919 } 1920 1921 static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu) 1922 { 1923 struct amdgpu_device *adev = smu->adev; 1924 1925 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 1926 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 1927 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 1928 1929 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); 1930 smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); 1931 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); 1932 } 1933 1934 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu, 1935 uint32_t size) 1936 { 1937 int ret = 0; 1938 1939 /* message SMU to update the bad page number on SMUBUS */ 1940 ret = smu_cmn_send_smc_msg_with_param(smu, 1941 SMU_MSG_SetNumBadMemoryPagesRetired, 1942 size, NULL); 1943 if (ret) 1944 dev_err(smu->adev->dev, 1945 "[%s] failed to message SMU to update bad memory pages number\n", 1946 __func__); 1947 1948 return ret; 1949 } 1950 1951 static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu, 1952 uint32_t size) 1953 { 1954 int ret = 0; 1955 1956 /* message SMU to update the bad channel info on SMUBUS */ 1957 ret = smu_cmn_send_smc_msg_with_param(smu, 1958 SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 1959 size, NULL); 1960 if (ret) 1961 dev_err(smu->adev->dev, 1962 "[%s] failed to message SMU to update bad memory pages channel info\n", 1963 __func__); 1964 1965 return ret; 1966 } 1967 1968 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { 1969 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, 1970 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, 1971 .i2c_init = smu_v13_0_0_i2c_control_init, 1972 .i2c_fini = smu_v13_0_0_i2c_control_fini, 1973 .is_dpm_running = smu_v13_0_0_is_dpm_running, 1974 .dump_pptable = smu_v13_0_0_dump_pptable, 1975 .init_microcode = smu_v13_0_init_microcode, 1976 .load_microcode = smu_v13_0_load_microcode, 1977 .fini_microcode = smu_v13_0_fini_microcode, 1978 .init_smc_tables = smu_v13_0_0_init_smc_tables, 1979 .fini_smc_tables = smu_v13_0_fini_smc_tables, 1980 .init_power = smu_v13_0_init_power, 1981 .fini_power = smu_v13_0_fini_power, 1982 .check_fw_status = smu_v13_0_check_fw_status, 1983 .setup_pptable = smu_v13_0_0_setup_pptable, 1984 .check_fw_version = smu_v13_0_check_fw_version, 1985 .write_pptable = smu_cmn_write_pptable, 1986 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1987 .system_features_control = smu_v13_0_0_system_features_control, 1988 .set_allowed_mask = smu_v13_0_set_allowed_mask, 1989 .get_enabled_mask = smu_cmn_get_enabled_mask, 1990 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 1991 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 1992 .get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq, 1993 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1994 .read_sensor = smu_v13_0_0_read_sensor, 1995 .feature_is_enabled = smu_cmn_feature_is_enabled, 1996 .print_clk_levels = smu_v13_0_0_print_clk_levels, 1997 .force_clk_levels = smu_v13_0_0_force_clk_levels, 1998 .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters, 1999 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range, 2000 .register_irq_handler = smu_v13_0_register_irq_handler, 2001 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2002 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2003 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2004 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics, 2005 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, 2006 .init_pptable_microcode = smu_v13_0_init_pptable_microcode, 2007 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk, 2008 .set_performance_level = smu_v13_0_set_performance_level, 2009 .gfx_off_control = smu_v13_0_gfx_off_control, 2010 .get_unique_id = smu_v13_0_0_get_unique_id, 2011 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm, 2012 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm, 2013 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, 2014 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm, 2015 .get_fan_control_mode = smu_v13_0_get_fan_control_mode, 2016 .set_fan_control_mode = smu_v13_0_set_fan_control_mode, 2017 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, 2018 .get_power_limit = smu_v13_0_0_get_power_limit, 2019 .set_power_limit = smu_v13_0_set_power_limit, 2020 .set_power_source = smu_v13_0_set_power_source, 2021 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, 2022 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, 2023 .run_btc = smu_v13_0_run_btc, 2024 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2025 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2026 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2027 .deep_sleep_control = smu_v13_0_deep_sleep_control, 2028 .gfx_ulv_control = smu_v13_0_gfx_ulv_control, 2029 .baco_is_support = smu_v13_0_baco_is_support, 2030 .baco_get_state = smu_v13_0_baco_get_state, 2031 .baco_set_state = smu_v13_0_baco_set_state, 2032 .baco_enter = smu_v13_0_0_baco_enter, 2033 .baco_exit = smu_v13_0_0_baco_exit, 2034 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported, 2035 .mode1_reset = smu_v13_0_0_mode1_reset, 2036 .set_mp1_state = smu_v13_0_0_set_mp1_state, 2037 .set_df_cstate = smu_v13_0_0_set_df_cstate, 2038 .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num, 2039 .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag, 2040 .gpo_control = smu_v13_0_gpo_control, 2041 }; 2042 2043 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) 2044 { 2045 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs; 2046 smu->message_map = smu_v13_0_0_message_map; 2047 smu->clock_map = smu_v13_0_0_clk_map; 2048 smu->feature_map = smu_v13_0_0_feature_mask_map; 2049 smu->table_map = smu_v13_0_0_table_map; 2050 smu->pwr_src_map = smu_v13_0_0_pwr_src_map; 2051 smu->workload_map = smu_v13_0_0_workload_map; 2052 smu_v13_0_0_set_smu_mailbox_registers(smu); 2053 } 2054