1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/reboot.h> 27 28 #define SMU_13_0_PARTIAL_PPTABLE 29 #define SWSMU_CODE_LAYER_L3 30 31 #include "amdgpu.h" 32 #include "amdgpu_smu.h" 33 #include "atomfirmware.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_atombios.h" 36 #include "smu_v13_0.h" 37 #include "soc15_common.h" 38 #include "atom.h" 39 #include "amdgpu_ras.h" 40 #include "smu_cmn.h" 41 42 #include "asic_reg/thm/thm_13_0_2_offset.h" 43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h" 44 #include "asic_reg/mp/mp_13_0_2_offset.h" 45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h" 46 #include "asic_reg/smuio/smuio_13_0_2_offset.h" 47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h" 48 49 /* 50 * DO NOT use these for err/warn/info/debug messages. 51 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52 * They are more MGPU friendly. 53 */ 54 #undef pr_err 55 #undef pr_warn 56 #undef pr_info 57 #undef pr_debug 58 59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin"); 60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin"); 61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin"); 62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin"); 63 64 #define mmMP1_SMN_C2PMSG_66 0x0282 65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 66 67 #define mmMP1_SMN_C2PMSG_82 0x0292 68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 69 70 #define mmMP1_SMN_C2PMSG_90 0x029a 71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 72 73 #define SMU13_VOLTAGE_SCALE 4 74 75 #define LINK_WIDTH_MAX 6 76 #define LINK_SPEED_MAX 3 77 78 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L 80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 81 #define smnPCIE_LC_SPEED_CNTL 0x11140290 82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE 84 85 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 86 static const int link_speed[] = {25, 50, 80, 160}; 87 88 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5}; 89 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16}; 90 91 int smu_v13_0_init_microcode(struct smu_context *smu) 92 { 93 struct amdgpu_device *adev = smu->adev; 94 char fw_name[30]; 95 char ucode_prefix[30]; 96 int err = 0; 97 const struct smc_firmware_header_v1_0 *hdr; 98 const struct common_firmware_header *header; 99 struct amdgpu_firmware_info *ucode = NULL; 100 101 /* doesn't need to load smu firmware in IOV mode */ 102 if (amdgpu_sriov_vf(adev)) 103 return 0; 104 105 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); 106 107 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 108 109 err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name); 110 if (err) 111 goto out; 112 113 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 114 amdgpu_ucode_print_smc_hdr(&hdr->header); 115 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 116 117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 118 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 119 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 120 ucode->fw = adev->pm.fw; 121 header = (const struct common_firmware_header *)ucode->fw->data; 122 adev->firmware.fw_size += 123 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 124 } 125 126 out: 127 if (err) 128 amdgpu_ucode_release(&adev->pm.fw); 129 return err; 130 } 131 132 void smu_v13_0_fini_microcode(struct smu_context *smu) 133 { 134 struct amdgpu_device *adev = smu->adev; 135 136 amdgpu_ucode_release(&adev->pm.fw); 137 adev->pm.fw_version = 0; 138 } 139 140 int smu_v13_0_load_microcode(struct smu_context *smu) 141 { 142 #if 0 143 struct amdgpu_device *adev = smu->adev; 144 const uint32_t *src; 145 const struct smc_firmware_header_v1_0 *hdr; 146 uint32_t addr_start = MP1_SRAM; 147 uint32_t i; 148 uint32_t smc_fw_size; 149 uint32_t mp1_fw_flags; 150 151 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 152 src = (const uint32_t *)(adev->pm.fw->data + 153 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 154 smc_fw_size = hdr->header.ucode_size_bytes; 155 156 for (i = 1; i < smc_fw_size/4 - 1; i++) { 157 WREG32_PCIE(addr_start, src[i]); 158 addr_start += 4; 159 } 160 161 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 162 1 & MP1_SMN_PUB_CTRL__RESET_MASK); 163 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 164 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); 165 166 for (i = 0; i < adev->usec_timeout; i++) { 167 mp1_fw_flags = RREG32_PCIE(MP1_Public | 168 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 169 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 170 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 171 break; 172 udelay(1); 173 } 174 175 if (i == adev->usec_timeout) 176 return -ETIME; 177 #endif 178 179 return 0; 180 } 181 182 int smu_v13_0_init_pptable_microcode(struct smu_context *smu) 183 { 184 struct amdgpu_device *adev = smu->adev; 185 struct amdgpu_firmware_info *ucode = NULL; 186 uint32_t size = 0, pptable_id = 0; 187 int ret = 0; 188 void *table; 189 190 /* doesn't need to load smu firmware in IOV mode */ 191 if (amdgpu_sriov_vf(adev)) 192 return 0; 193 194 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 195 return 0; 196 197 if (!adev->scpm_enabled) 198 return 0; 199 200 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) || 201 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) || 202 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))) 203 return 0; 204 205 /* override pptable_id from driver parameter */ 206 if (amdgpu_smu_pptable_id >= 0) { 207 pptable_id = amdgpu_smu_pptable_id; 208 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 209 } else { 210 pptable_id = smu->smu_table.boot_values.pp_table_id; 211 } 212 213 /* "pptable_id == 0" means vbios carries the pptable. */ 214 if (!pptable_id) 215 return 0; 216 217 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 218 if (ret) 219 return ret; 220 221 smu->pptable_firmware.data = table; 222 smu->pptable_firmware.size = size; 223 224 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE]; 225 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE; 226 ucode->fw = &smu->pptable_firmware; 227 adev->firmware.fw_size += 228 ALIGN(smu->pptable_firmware.size, PAGE_SIZE); 229 230 return 0; 231 } 232 233 int smu_v13_0_check_fw_status(struct smu_context *smu) 234 { 235 struct amdgpu_device *adev = smu->adev; 236 uint32_t mp1_fw_flags; 237 238 switch (adev->ip_versions[MP1_HWIP][0]) { 239 case IP_VERSION(13, 0, 4): 240 case IP_VERSION(13, 0, 11): 241 mp1_fw_flags = RREG32_PCIE(MP1_Public | 242 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff)); 243 break; 244 default: 245 mp1_fw_flags = RREG32_PCIE(MP1_Public | 246 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 247 break; 248 } 249 250 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 251 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 252 return 0; 253 254 return -EIO; 255 } 256 257 int smu_v13_0_check_fw_version(struct smu_context *smu) 258 { 259 struct amdgpu_device *adev = smu->adev; 260 uint32_t if_version = 0xff, smu_version = 0xff; 261 uint8_t smu_program, smu_major, smu_minor, smu_debug; 262 int ret = 0; 263 264 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 265 if (ret) 266 return ret; 267 268 smu_program = (smu_version >> 24) & 0xff; 269 smu_major = (smu_version >> 16) & 0xff; 270 smu_minor = (smu_version >> 8) & 0xff; 271 smu_debug = (smu_version >> 0) & 0xff; 272 if (smu->is_apu) 273 adev->pm.fw_version = smu_version; 274 275 switch (adev->ip_versions[MP1_HWIP][0]) { 276 case IP_VERSION(13, 0, 2): 277 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; 278 break; 279 case IP_VERSION(13, 0, 0): 280 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0; 281 break; 282 case IP_VERSION(13, 0, 10): 283 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10; 284 break; 285 case IP_VERSION(13, 0, 7): 286 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7; 287 break; 288 case IP_VERSION(13, 0, 1): 289 case IP_VERSION(13, 0, 3): 290 case IP_VERSION(13, 0, 8): 291 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP; 292 break; 293 case IP_VERSION(13, 0, 4): 294 case IP_VERSION(13, 0, 11): 295 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4; 296 break; 297 case IP_VERSION(13, 0, 5): 298 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5; 299 break; 300 case IP_VERSION(13, 0, 6): 301 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_6; 302 adev->pm.fw_version = smu_version; 303 break; 304 default: 305 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n", 306 adev->ip_versions[MP1_HWIP][0]); 307 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV; 308 break; 309 } 310 311 /* only for dGPU w/ SMU13*/ 312 if (adev->pm.fw) 313 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n", 314 smu_program, smu_version, smu_major, smu_minor, smu_debug); 315 316 /* 317 * 1. if_version mismatch is not critical as our fw is designed 318 * to be backward compatible. 319 * 2. New fw usually brings some optimizations. But that's visible 320 * only on the paired driver. 321 * Considering above, we just leave user a verbal message instead 322 * of halt driver loading. 323 */ 324 if (if_version != smu->smc_driver_if_version) { 325 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " 326 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", 327 smu->smc_driver_if_version, if_version, 328 smu_program, smu_version, smu_major, smu_minor, smu_debug); 329 dev_info(adev->dev, "SMU driver if version not matched\n"); 330 } 331 332 return ret; 333 } 334 335 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 336 { 337 struct amdgpu_device *adev = smu->adev; 338 uint32_t ppt_offset_bytes; 339 const struct smc_firmware_header_v2_0 *v2; 340 341 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 342 343 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 344 *size = le32_to_cpu(v2->ppt_size_bytes); 345 *table = (uint8_t *)v2 + ppt_offset_bytes; 346 347 return 0; 348 } 349 350 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table, 351 uint32_t *size, uint32_t pptable_id) 352 { 353 struct amdgpu_device *adev = smu->adev; 354 const struct smc_firmware_header_v2_1 *v2_1; 355 struct smc_soft_pptable_entry *entries; 356 uint32_t pptable_count = 0; 357 int i = 0; 358 359 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 360 entries = (struct smc_soft_pptable_entry *) 361 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 362 pptable_count = le32_to_cpu(v2_1->pptable_count); 363 for (i = 0; i < pptable_count; i++) { 364 if (le32_to_cpu(entries[i].id) == pptable_id) { 365 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 366 *size = le32_to_cpu(entries[i].ppt_size_bytes); 367 break; 368 } 369 } 370 371 if (i == pptable_count) 372 return -EINVAL; 373 374 return 0; 375 } 376 377 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size) 378 { 379 struct amdgpu_device *adev = smu->adev; 380 uint16_t atom_table_size; 381 uint8_t frev, crev; 382 int ret, index; 383 384 dev_info(adev->dev, "use vbios provided pptable\n"); 385 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 386 powerplayinfo); 387 388 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 389 (uint8_t **)table); 390 if (ret) 391 return ret; 392 393 if (size) 394 *size = atom_table_size; 395 396 return 0; 397 } 398 399 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, 400 void **table, 401 uint32_t *size, 402 uint32_t pptable_id) 403 { 404 const struct smc_firmware_header_v1_0 *hdr; 405 struct amdgpu_device *adev = smu->adev; 406 uint16_t version_major, version_minor; 407 int ret; 408 409 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 410 if (!hdr) 411 return -EINVAL; 412 413 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id); 414 415 version_major = le16_to_cpu(hdr->header.header_version_major); 416 version_minor = le16_to_cpu(hdr->header.header_version_minor); 417 if (version_major != 2) { 418 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n", 419 version_major, version_minor); 420 return -EINVAL; 421 } 422 423 switch (version_minor) { 424 case 0: 425 ret = smu_v13_0_set_pptable_v2_0(smu, table, size); 426 break; 427 case 1: 428 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id); 429 break; 430 default: 431 ret = -EINVAL; 432 break; 433 } 434 435 return ret; 436 } 437 438 int smu_v13_0_setup_pptable(struct smu_context *smu) 439 { 440 struct amdgpu_device *adev = smu->adev; 441 uint32_t size = 0, pptable_id = 0; 442 void *table; 443 int ret = 0; 444 445 /* override pptable_id from driver parameter */ 446 if (amdgpu_smu_pptable_id >= 0) { 447 pptable_id = amdgpu_smu_pptable_id; 448 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 449 } else { 450 pptable_id = smu->smu_table.boot_values.pp_table_id; 451 } 452 453 /* force using vbios pptable in sriov mode */ 454 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1)) 455 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size); 456 else 457 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 458 459 if (ret) 460 return ret; 461 462 if (!smu->smu_table.power_play_table) 463 smu->smu_table.power_play_table = table; 464 if (!smu->smu_table.power_play_table_size) 465 smu->smu_table.power_play_table_size = size; 466 467 return 0; 468 } 469 470 int smu_v13_0_init_smc_tables(struct smu_context *smu) 471 { 472 struct smu_table_context *smu_table = &smu->smu_table; 473 struct smu_table *tables = smu_table->tables; 474 int ret = 0; 475 476 smu_table->driver_pptable = 477 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 478 if (!smu_table->driver_pptable) { 479 ret = -ENOMEM; 480 goto err0_out; 481 } 482 483 smu_table->max_sustainable_clocks = 484 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL); 485 if (!smu_table->max_sustainable_clocks) { 486 ret = -ENOMEM; 487 goto err1_out; 488 } 489 490 /* Aldebaran does not support OVERDRIVE */ 491 if (tables[SMU_TABLE_OVERDRIVE].size) { 492 smu_table->overdrive_table = 493 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 494 if (!smu_table->overdrive_table) { 495 ret = -ENOMEM; 496 goto err2_out; 497 } 498 499 smu_table->boot_overdrive_table = 500 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 501 if (!smu_table->boot_overdrive_table) { 502 ret = -ENOMEM; 503 goto err3_out; 504 } 505 } 506 507 smu_table->combo_pptable = 508 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL); 509 if (!smu_table->combo_pptable) { 510 ret = -ENOMEM; 511 goto err4_out; 512 } 513 514 return 0; 515 516 err4_out: 517 kfree(smu_table->boot_overdrive_table); 518 err3_out: 519 kfree(smu_table->overdrive_table); 520 err2_out: 521 kfree(smu_table->max_sustainable_clocks); 522 err1_out: 523 kfree(smu_table->driver_pptable); 524 err0_out: 525 return ret; 526 } 527 528 int smu_v13_0_fini_smc_tables(struct smu_context *smu) 529 { 530 struct smu_table_context *smu_table = &smu->smu_table; 531 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 532 533 kfree(smu_table->gpu_metrics_table); 534 kfree(smu_table->combo_pptable); 535 kfree(smu_table->boot_overdrive_table); 536 kfree(smu_table->overdrive_table); 537 kfree(smu_table->max_sustainable_clocks); 538 kfree(smu_table->driver_pptable); 539 smu_table->gpu_metrics_table = NULL; 540 smu_table->combo_pptable = NULL; 541 smu_table->boot_overdrive_table = NULL; 542 smu_table->overdrive_table = NULL; 543 smu_table->max_sustainable_clocks = NULL; 544 smu_table->driver_pptable = NULL; 545 kfree(smu_table->hardcode_pptable); 546 smu_table->hardcode_pptable = NULL; 547 548 kfree(smu_table->ecc_table); 549 kfree(smu_table->metrics_table); 550 kfree(smu_table->watermarks_table); 551 smu_table->ecc_table = NULL; 552 smu_table->metrics_table = NULL; 553 smu_table->watermarks_table = NULL; 554 smu_table->metrics_time = 0; 555 556 kfree(smu_dpm->dpm_context); 557 kfree(smu_dpm->golden_dpm_context); 558 kfree(smu_dpm->dpm_current_power_state); 559 kfree(smu_dpm->dpm_request_power_state); 560 smu_dpm->dpm_context = NULL; 561 smu_dpm->golden_dpm_context = NULL; 562 smu_dpm->dpm_context_size = 0; 563 smu_dpm->dpm_current_power_state = NULL; 564 smu_dpm->dpm_request_power_state = NULL; 565 566 return 0; 567 } 568 569 int smu_v13_0_init_power(struct smu_context *smu) 570 { 571 struct smu_power_context *smu_power = &smu->smu_power; 572 573 if (smu_power->power_context || smu_power->power_context_size != 0) 574 return -EINVAL; 575 576 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 577 GFP_KERNEL); 578 if (!smu_power->power_context) 579 return -ENOMEM; 580 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context); 581 582 return 0; 583 } 584 585 int smu_v13_0_fini_power(struct smu_context *smu) 586 { 587 struct smu_power_context *smu_power = &smu->smu_power; 588 589 if (!smu_power->power_context || smu_power->power_context_size == 0) 590 return -EINVAL; 591 592 kfree(smu_power->power_context); 593 smu_power->power_context = NULL; 594 smu_power->power_context_size = 0; 595 596 return 0; 597 } 598 599 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu) 600 { 601 int ret, index; 602 uint16_t size; 603 uint8_t frev, crev; 604 struct atom_common_table_header *header; 605 struct atom_firmware_info_v3_4 *v_3_4; 606 struct atom_firmware_info_v3_3 *v_3_3; 607 struct atom_firmware_info_v3_1 *v_3_1; 608 struct atom_smu_info_v3_6 *smu_info_v3_6; 609 struct atom_smu_info_v4_0 *smu_info_v4_0; 610 611 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 612 firmwareinfo); 613 614 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 615 (uint8_t **)&header); 616 if (ret) 617 return ret; 618 619 if (header->format_revision != 3) { 620 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n"); 621 return -EINVAL; 622 } 623 624 switch (header->content_revision) { 625 case 0: 626 case 1: 627 case 2: 628 v_3_1 = (struct atom_firmware_info_v3_1 *)header; 629 smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 630 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 631 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 632 smu->smu_table.boot_values.socclk = 0; 633 smu->smu_table.boot_values.dcefclk = 0; 634 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 635 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 636 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 637 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 638 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 639 smu->smu_table.boot_values.pp_table_id = 0; 640 break; 641 case 3: 642 v_3_3 = (struct atom_firmware_info_v3_3 *)header; 643 smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 644 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 645 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 646 smu->smu_table.boot_values.socclk = 0; 647 smu->smu_table.boot_values.dcefclk = 0; 648 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 649 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 650 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 651 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 652 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 653 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 654 break; 655 case 4: 656 default: 657 v_3_4 = (struct atom_firmware_info_v3_4 *)header; 658 smu->smu_table.boot_values.revision = v_3_4->firmware_revision; 659 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; 660 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; 661 smu->smu_table.boot_values.socclk = 0; 662 smu->smu_table.boot_values.dcefclk = 0; 663 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; 664 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; 665 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; 666 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; 667 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; 668 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id; 669 break; 670 } 671 672 smu->smu_table.boot_values.format_revision = header->format_revision; 673 smu->smu_table.boot_values.content_revision = header->content_revision; 674 675 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 676 smu_info); 677 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 678 (uint8_t **)&header)) { 679 680 if ((frev == 3) && (crev == 6)) { 681 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header; 682 683 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; 684 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz; 685 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz; 686 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; 687 } else if ((frev == 3) && (crev == 1)) { 688 return 0; 689 } else if ((frev == 4) && (crev == 0)) { 690 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header; 691 692 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; 693 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; 694 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz; 695 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz; 696 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz; 697 } else { 698 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n", 699 (uint32_t)frev, (uint32_t)crev); 700 } 701 } 702 703 return 0; 704 } 705 706 707 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu) 708 { 709 struct smu_table_context *smu_table = &smu->smu_table; 710 struct smu_table *memory_pool = &smu_table->memory_pool; 711 int ret = 0; 712 uint64_t address; 713 uint32_t address_low, address_high; 714 715 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 716 return ret; 717 718 address = memory_pool->mc_address; 719 address_high = (uint32_t)upper_32_bits(address); 720 address_low = (uint32_t)lower_32_bits(address); 721 722 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 723 address_high, NULL); 724 if (ret) 725 return ret; 726 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 727 address_low, NULL); 728 if (ret) 729 return ret; 730 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 731 (uint32_t)memory_pool->size, NULL); 732 if (ret) 733 return ret; 734 735 return ret; 736 } 737 738 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 739 { 740 int ret; 741 742 ret = smu_cmn_send_smc_msg_with_param(smu, 743 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); 744 if (ret) 745 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!"); 746 747 return ret; 748 } 749 750 int smu_v13_0_set_driver_table_location(struct smu_context *smu) 751 { 752 struct smu_table *driver_table = &smu->smu_table.driver_table; 753 int ret = 0; 754 755 if (driver_table->mc_address) { 756 ret = smu_cmn_send_smc_msg_with_param(smu, 757 SMU_MSG_SetDriverDramAddrHigh, 758 upper_32_bits(driver_table->mc_address), 759 NULL); 760 if (!ret) 761 ret = smu_cmn_send_smc_msg_with_param(smu, 762 SMU_MSG_SetDriverDramAddrLow, 763 lower_32_bits(driver_table->mc_address), 764 NULL); 765 } 766 767 return ret; 768 } 769 770 int smu_v13_0_set_tool_table_location(struct smu_context *smu) 771 { 772 int ret = 0; 773 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 774 775 if (tool_table->mc_address) { 776 ret = smu_cmn_send_smc_msg_with_param(smu, 777 SMU_MSG_SetToolsDramAddrHigh, 778 upper_32_bits(tool_table->mc_address), 779 NULL); 780 if (!ret) 781 ret = smu_cmn_send_smc_msg_with_param(smu, 782 SMU_MSG_SetToolsDramAddrLow, 783 lower_32_bits(tool_table->mc_address), 784 NULL); 785 } 786 787 return ret; 788 } 789 790 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count) 791 { 792 int ret = 0; 793 794 if (!smu->pm_enabled) 795 return ret; 796 797 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL); 798 799 return ret; 800 } 801 802 int smu_v13_0_set_allowed_mask(struct smu_context *smu) 803 { 804 struct smu_feature *feature = &smu->smu_feature; 805 int ret = 0; 806 uint32_t feature_mask[2]; 807 808 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || 809 feature->feature_num < 64) 810 return -EINVAL; 811 812 bitmap_to_arr32(feature_mask, feature->allowed, 64); 813 814 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 815 feature_mask[1], NULL); 816 if (ret) 817 return ret; 818 819 return smu_cmn_send_smc_msg_with_param(smu, 820 SMU_MSG_SetAllowedFeaturesMaskLow, 821 feature_mask[0], 822 NULL); 823 } 824 825 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable) 826 { 827 int ret = 0; 828 struct amdgpu_device *adev = smu->adev; 829 830 switch (adev->ip_versions[MP1_HWIP][0]) { 831 case IP_VERSION(13, 0, 0): 832 case IP_VERSION(13, 0, 1): 833 case IP_VERSION(13, 0, 3): 834 case IP_VERSION(13, 0, 4): 835 case IP_VERSION(13, 0, 5): 836 case IP_VERSION(13, 0, 7): 837 case IP_VERSION(13, 0, 8): 838 case IP_VERSION(13, 0, 10): 839 case IP_VERSION(13, 0, 11): 840 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 841 return 0; 842 if (enable) 843 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 844 else 845 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 846 break; 847 default: 848 break; 849 } 850 851 return ret; 852 } 853 854 int smu_v13_0_system_features_control(struct smu_context *smu, 855 bool en) 856 { 857 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 858 SMU_MSG_DisableAllSmuFeatures), NULL); 859 } 860 861 int smu_v13_0_notify_display_change(struct smu_context *smu) 862 { 863 int ret = 0; 864 865 if (!smu->pm_enabled) 866 return ret; 867 868 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 869 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 870 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 871 872 return ret; 873 } 874 875 static int 876 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, 877 enum smu_clk_type clock_select) 878 { 879 int ret = 0; 880 int clk_id; 881 882 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || 883 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) 884 return 0; 885 886 clk_id = smu_cmn_to_asic_specific_index(smu, 887 CMN2ASIC_MAPPING_CLK, 888 clock_select); 889 if (clk_id < 0) 890 return -EINVAL; 891 892 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, 893 clk_id << 16, clock); 894 if (ret) { 895 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); 896 return ret; 897 } 898 899 if (*clock != 0) 900 return 0; 901 902 /* if DC limit is zero, return AC limit */ 903 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, 904 clk_id << 16, clock); 905 if (ret) { 906 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!"); 907 return ret; 908 } 909 910 return 0; 911 } 912 913 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu) 914 { 915 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks = 916 smu->smu_table.max_sustainable_clocks; 917 int ret = 0; 918 919 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; 920 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; 921 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; 922 max_sustainable_clocks->display_clock = 0xFFFFFFFF; 923 max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 924 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 925 926 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 927 ret = smu_v13_0_get_max_sustainable_clock(smu, 928 &(max_sustainable_clocks->uclock), 929 SMU_UCLK); 930 if (ret) { 931 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!", 932 __func__); 933 return ret; 934 } 935 } 936 937 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 938 ret = smu_v13_0_get_max_sustainable_clock(smu, 939 &(max_sustainable_clocks->soc_clock), 940 SMU_SOCCLK); 941 if (ret) { 942 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!", 943 __func__); 944 return ret; 945 } 946 } 947 948 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 949 ret = smu_v13_0_get_max_sustainable_clock(smu, 950 &(max_sustainable_clocks->dcef_clock), 951 SMU_DCEFCLK); 952 if (ret) { 953 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!", 954 __func__); 955 return ret; 956 } 957 958 ret = smu_v13_0_get_max_sustainable_clock(smu, 959 &(max_sustainable_clocks->display_clock), 960 SMU_DISPCLK); 961 if (ret) { 962 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!", 963 __func__); 964 return ret; 965 } 966 ret = smu_v13_0_get_max_sustainable_clock(smu, 967 &(max_sustainable_clocks->phy_clock), 968 SMU_PHYCLK); 969 if (ret) { 970 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!", 971 __func__); 972 return ret; 973 } 974 ret = smu_v13_0_get_max_sustainable_clock(smu, 975 &(max_sustainable_clocks->pixel_clock), 976 SMU_PIXCLK); 977 if (ret) { 978 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!", 979 __func__); 980 return ret; 981 } 982 } 983 984 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 985 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 986 987 return 0; 988 } 989 990 int smu_v13_0_get_current_power_limit(struct smu_context *smu, 991 uint32_t *power_limit) 992 { 993 int power_src; 994 int ret = 0; 995 996 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 997 return -EINVAL; 998 999 power_src = smu_cmn_to_asic_specific_index(smu, 1000 CMN2ASIC_MAPPING_PWR, 1001 smu->adev->pm.ac_power ? 1002 SMU_POWER_SOURCE_AC : 1003 SMU_POWER_SOURCE_DC); 1004 if (power_src < 0) 1005 return -EINVAL; 1006 1007 ret = smu_cmn_send_smc_msg_with_param(smu, 1008 SMU_MSG_GetPptLimit, 1009 power_src << 16, 1010 power_limit); 1011 if (ret) 1012 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 1013 1014 return ret; 1015 } 1016 1017 int smu_v13_0_set_power_limit(struct smu_context *smu, 1018 enum smu_ppt_limit_type limit_type, 1019 uint32_t limit) 1020 { 1021 int ret = 0; 1022 1023 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 1024 return -EINVAL; 1025 1026 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1027 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 1028 return -EOPNOTSUPP; 1029 } 1030 1031 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL); 1032 if (ret) { 1033 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 1034 return ret; 1035 } 1036 1037 smu->current_power_limit = limit; 1038 1039 return 0; 1040 } 1041 1042 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu) 1043 { 1044 return smu_cmn_send_smc_msg(smu, 1045 SMU_MSG_AllowIHHostInterrupt, 1046 NULL); 1047 } 1048 1049 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu) 1050 { 1051 int ret = 0; 1052 1053 if (smu->dc_controlled_by_gpio && 1054 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) 1055 ret = smu_v13_0_allow_ih_interrupt(smu); 1056 1057 return ret; 1058 } 1059 1060 int smu_v13_0_enable_thermal_alert(struct smu_context *smu) 1061 { 1062 int ret = 0; 1063 1064 if (!smu->irq_source.num_types) 1065 return 0; 1066 1067 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 1068 if (ret) 1069 return ret; 1070 1071 return smu_v13_0_process_pending_interrupt(smu); 1072 } 1073 1074 int smu_v13_0_disable_thermal_alert(struct smu_context *smu) 1075 { 1076 if (!smu->irq_source.num_types) 1077 return 0; 1078 1079 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1080 } 1081 1082 static uint16_t convert_to_vddc(uint8_t vid) 1083 { 1084 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE); 1085 } 1086 1087 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) 1088 { 1089 struct amdgpu_device *adev = smu->adev; 1090 uint32_t vdd = 0, val_vid = 0; 1091 1092 if (!value) 1093 return -EINVAL; 1094 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) & 1095 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 1096 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 1097 1098 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); 1099 1100 *value = vdd; 1101 1102 return 0; 1103 1104 } 1105 1106 int 1107 smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 1108 struct pp_display_clock_request 1109 *clock_req) 1110 { 1111 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1112 int ret = 0; 1113 enum smu_clk_type clk_select = 0; 1114 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1115 1116 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || 1117 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1118 switch (clk_type) { 1119 case amd_pp_dcef_clock: 1120 clk_select = SMU_DCEFCLK; 1121 break; 1122 case amd_pp_disp_clock: 1123 clk_select = SMU_DISPCLK; 1124 break; 1125 case amd_pp_pixel_clock: 1126 clk_select = SMU_PIXCLK; 1127 break; 1128 case amd_pp_phy_clock: 1129 clk_select = SMU_PHYCLK; 1130 break; 1131 case amd_pp_mem_clock: 1132 clk_select = SMU_UCLK; 1133 break; 1134 default: 1135 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); 1136 ret = -EINVAL; 1137 break; 1138 } 1139 1140 if (ret) 1141 goto failed; 1142 1143 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) 1144 return 0; 1145 1146 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); 1147 1148 if(clk_select == SMU_UCLK) 1149 smu->hard_min_uclk_req_from_dal = clk_freq; 1150 } 1151 1152 failed: 1153 return ret; 1154 } 1155 1156 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu) 1157 { 1158 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1159 return AMD_FAN_CTRL_MANUAL; 1160 else 1161 return AMD_FAN_CTRL_AUTO; 1162 } 1163 1164 static int 1165 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) 1166 { 1167 int ret = 0; 1168 1169 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1170 return 0; 1171 1172 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); 1173 if (ret) 1174 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!", 1175 __func__, (auto_fan_control ? "Start" : "Stop")); 1176 1177 return ret; 1178 } 1179 1180 static int 1181 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) 1182 { 1183 struct amdgpu_device *adev = smu->adev; 1184 1185 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, 1186 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), 1187 CG_FDO_CTRL2, TMIN, 0)); 1188 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, 1189 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), 1190 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1191 1192 return 0; 1193 } 1194 1195 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu, 1196 uint32_t speed) 1197 { 1198 struct amdgpu_device *adev = smu->adev; 1199 uint32_t duty100, duty; 1200 uint64_t tmp64; 1201 1202 speed = MIN(speed, 255); 1203 1204 if (smu_v13_0_auto_fan_control(smu, 0)) 1205 return -EINVAL; 1206 1207 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1), 1208 CG_FDO_CTRL1, FMAX_DUTY100); 1209 if (!duty100) 1210 return -EINVAL; 1211 1212 tmp64 = (uint64_t)speed * duty100; 1213 do_div(tmp64, 255); 1214 duty = (uint32_t)tmp64; 1215 1216 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0, 1217 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0), 1218 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1219 1220 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1221 } 1222 1223 int 1224 smu_v13_0_set_fan_control_mode(struct smu_context *smu, 1225 uint32_t mode) 1226 { 1227 int ret = 0; 1228 1229 switch (mode) { 1230 case AMD_FAN_CTRL_NONE: 1231 ret = smu_v13_0_set_fan_speed_pwm(smu, 255); 1232 break; 1233 case AMD_FAN_CTRL_MANUAL: 1234 ret = smu_v13_0_auto_fan_control(smu, 0); 1235 break; 1236 case AMD_FAN_CTRL_AUTO: 1237 ret = smu_v13_0_auto_fan_control(smu, 1); 1238 break; 1239 default: 1240 break; 1241 } 1242 1243 if (ret) { 1244 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__); 1245 return -EINVAL; 1246 } 1247 1248 return ret; 1249 } 1250 1251 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, 1252 uint32_t speed) 1253 { 1254 struct amdgpu_device *adev = smu->adev; 1255 uint32_t crystal_clock_freq = 2500; 1256 uint32_t tach_period; 1257 int ret; 1258 1259 if (!speed) 1260 return -EINVAL; 1261 1262 ret = smu_v13_0_auto_fan_control(smu, 0); 1263 if (ret) 1264 return ret; 1265 1266 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1267 WREG32_SOC15(THM, 0, regCG_TACH_CTRL, 1268 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL), 1269 CG_TACH_CTRL, TARGET_PERIOD, 1270 tach_period)); 1271 1272 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1273 } 1274 1275 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, 1276 uint32_t pstate) 1277 { 1278 int ret = 0; 1279 ret = smu_cmn_send_smc_msg_with_param(smu, 1280 SMU_MSG_SetXgmiMode, 1281 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 1282 NULL); 1283 return ret; 1284 } 1285 1286 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev, 1287 struct amdgpu_irq_src *source, 1288 unsigned tyep, 1289 enum amdgpu_interrupt_state state) 1290 { 1291 struct smu_context *smu = adev->powerplay.pp_handle; 1292 uint32_t low, high; 1293 uint32_t val = 0; 1294 1295 switch (state) { 1296 case AMDGPU_IRQ_STATE_DISABLE: 1297 /* For THM irqs */ 1298 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1299 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); 1300 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); 1301 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 1302 1303 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0); 1304 1305 /* For MP1 SW irqs */ 1306 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1307 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 1308 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 1309 1310 break; 1311 case AMDGPU_IRQ_STATE_ENABLE: 1312 /* For THM irqs */ 1313 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 1314 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 1315 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1316 smu->thermal_range.software_shutdown_temp); 1317 1318 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1319 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 1320 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 1321 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 1322 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 1323 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 1324 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 1325 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1326 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 1327 1328 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 1329 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 1330 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 1331 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val); 1332 1333 /* For MP1 SW irqs */ 1334 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); 1335 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 1336 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 1337 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); 1338 1339 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1340 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 1341 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 1342 1343 break; 1344 default: 1345 break; 1346 } 1347 1348 return 0; 1349 } 1350 1351 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu) 1352 { 1353 return smu_cmn_send_smc_msg(smu, 1354 SMU_MSG_ReenableAcDcInterrupt, 1355 NULL); 1356 } 1357 1358 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 1359 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 1360 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 1361 1362 static int smu_v13_0_irq_process(struct amdgpu_device *adev, 1363 struct amdgpu_irq_src *source, 1364 struct amdgpu_iv_entry *entry) 1365 { 1366 struct smu_context *smu = adev->powerplay.pp_handle; 1367 uint32_t client_id = entry->client_id; 1368 uint32_t src_id = entry->src_id; 1369 /* 1370 * ctxid is used to distinguish different 1371 * events for SMCToHost interrupt. 1372 */ 1373 uint32_t ctxid = entry->src_data[0]; 1374 uint32_t data; 1375 uint32_t high; 1376 1377 if (client_id == SOC15_IH_CLIENTID_THM) { 1378 switch (src_id) { 1379 case THM_11_0__SRCID__THM_DIG_THERM_L2H: 1380 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1381 /* 1382 * SW CTF just occurred. 1383 * Try to do a graceful shutdown to prevent further damage. 1384 */ 1385 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1386 orderly_poweroff(true); 1387 break; 1388 case THM_11_0__SRCID__THM_DIG_THERM_H2L: 1389 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 1390 break; 1391 default: 1392 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 1393 src_id); 1394 break; 1395 } 1396 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { 1397 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); 1398 /* 1399 * HW CTF just occurred. Shutdown to prevent further damage. 1400 */ 1401 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); 1402 orderly_poweroff(true); 1403 } else if (client_id == SOC15_IH_CLIENTID_MP1) { 1404 if (src_id == 0xfe) { 1405 /* ACK SMUToHost interrupt */ 1406 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1407 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); 1408 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); 1409 1410 switch (ctxid) { 1411 case 0x3: 1412 dev_dbg(adev->dev, "Switched to AC mode!\n"); 1413 smu_v13_0_ack_ac_dc_interrupt(smu); 1414 break; 1415 case 0x4: 1416 dev_dbg(adev->dev, "Switched to DC mode!\n"); 1417 smu_v13_0_ack_ac_dc_interrupt(smu); 1418 break; 1419 case 0x7: 1420 /* 1421 * Increment the throttle interrupt counter 1422 */ 1423 atomic64_inc(&smu->throttle_int_counter); 1424 1425 if (!atomic_read(&adev->throttling_logging_enabled)) 1426 return 0; 1427 1428 if (__ratelimit(&adev->throttling_logging_rs)) 1429 schedule_work(&smu->throttling_logging_work); 1430 1431 break; 1432 case 0x8: 1433 high = smu->thermal_range.software_shutdown_temp + 1434 smu->thermal_range.software_shutdown_temp_offset; 1435 high = min_t(typeof(high), 1436 SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1437 high); 1438 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n", 1439 high, 1440 smu->thermal_range.software_shutdown_temp_offset); 1441 1442 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1443 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL, 1444 DIG_THERM_INTH, 1445 (high & 0xff)); 1446 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1447 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data); 1448 break; 1449 case 0x9: 1450 high = min_t(typeof(high), 1451 SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1452 smu->thermal_range.software_shutdown_temp); 1453 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high); 1454 1455 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1456 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL, 1457 DIG_THERM_INTH, 1458 (high & 0xff)); 1459 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1460 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data); 1461 break; 1462 } 1463 } 1464 } 1465 1466 return 0; 1467 } 1468 1469 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = 1470 { 1471 .set = smu_v13_0_set_irq_state, 1472 .process = smu_v13_0_irq_process, 1473 }; 1474 1475 int smu_v13_0_register_irq_handler(struct smu_context *smu) 1476 { 1477 struct amdgpu_device *adev = smu->adev; 1478 struct amdgpu_irq_src *irq_src = &smu->irq_source; 1479 int ret = 0; 1480 1481 if (amdgpu_sriov_vf(adev)) 1482 return 0; 1483 1484 irq_src->num_types = 1; 1485 irq_src->funcs = &smu_v13_0_irq_funcs; 1486 1487 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1488 THM_11_0__SRCID__THM_DIG_THERM_L2H, 1489 irq_src); 1490 if (ret) 1491 return ret; 1492 1493 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1494 THM_11_0__SRCID__THM_DIG_THERM_H2L, 1495 irq_src); 1496 if (ret) 1497 return ret; 1498 1499 /* Register CTF(GPIO_19) interrupt */ 1500 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, 1501 SMUIO_11_0__SRCID__SMUIO_GPIO19, 1502 irq_src); 1503 if (ret) 1504 return ret; 1505 1506 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 1507 0xfe, 1508 irq_src); 1509 if (ret) 1510 return ret; 1511 1512 return ret; 1513 } 1514 1515 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 1516 struct pp_smu_nv_clock_table *max_clocks) 1517 { 1518 struct smu_table_context *table_context = &smu->smu_table; 1519 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL; 1520 1521 if (!max_clocks || !table_context->max_sustainable_clocks) 1522 return -EINVAL; 1523 1524 sustainable_clocks = table_context->max_sustainable_clocks; 1525 1526 max_clocks->dcfClockInKhz = 1527 (unsigned int) sustainable_clocks->dcef_clock * 1000; 1528 max_clocks->displayClockInKhz = 1529 (unsigned int) sustainable_clocks->display_clock * 1000; 1530 max_clocks->phyClockInKhz = 1531 (unsigned int) sustainable_clocks->phy_clock * 1000; 1532 max_clocks->pixelClockInKhz = 1533 (unsigned int) sustainable_clocks->pixel_clock * 1000; 1534 max_clocks->uClockInKhz = 1535 (unsigned int) sustainable_clocks->uclock * 1000; 1536 max_clocks->socClockInKhz = 1537 (unsigned int) sustainable_clocks->soc_clock * 1000; 1538 max_clocks->dscClockInKhz = 0; 1539 max_clocks->dppClockInKhz = 0; 1540 max_clocks->fabricClockInKhz = 0; 1541 1542 return 0; 1543 } 1544 1545 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu) 1546 { 1547 int ret = 0; 1548 1549 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); 1550 1551 return ret; 1552 } 1553 1554 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu, 1555 uint64_t event_arg) 1556 { 1557 int ret = 0; 1558 1559 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n"); 1560 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL); 1561 1562 return ret; 1563 } 1564 1565 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1566 uint64_t event_arg) 1567 { 1568 int ret = -EINVAL; 1569 1570 switch (event) { 1571 case SMU_EVENT_RESET_COMPLETE: 1572 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg); 1573 break; 1574 default: 1575 break; 1576 } 1577 1578 return ret; 1579 } 1580 1581 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1582 uint32_t *min, uint32_t *max) 1583 { 1584 int ret = 0, clk_id = 0; 1585 uint32_t param = 0; 1586 uint32_t clock_limit; 1587 1588 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 1589 switch (clk_type) { 1590 case SMU_MCLK: 1591 case SMU_UCLK: 1592 clock_limit = smu->smu_table.boot_values.uclk; 1593 break; 1594 case SMU_GFXCLK: 1595 case SMU_SCLK: 1596 clock_limit = smu->smu_table.boot_values.gfxclk; 1597 break; 1598 case SMU_SOCCLK: 1599 clock_limit = smu->smu_table.boot_values.socclk; 1600 break; 1601 default: 1602 clock_limit = 0; 1603 break; 1604 } 1605 1606 /* clock in Mhz unit */ 1607 if (min) 1608 *min = clock_limit / 100; 1609 if (max) 1610 *max = clock_limit / 100; 1611 1612 return 0; 1613 } 1614 1615 clk_id = smu_cmn_to_asic_specific_index(smu, 1616 CMN2ASIC_MAPPING_CLK, 1617 clk_type); 1618 if (clk_id < 0) { 1619 ret = -EINVAL; 1620 goto failed; 1621 } 1622 param = (clk_id & 0xffff) << 16; 1623 1624 if (max) { 1625 if (smu->adev->pm.ac_power) 1626 ret = smu_cmn_send_smc_msg_with_param(smu, 1627 SMU_MSG_GetMaxDpmFreq, 1628 param, 1629 max); 1630 else 1631 ret = smu_cmn_send_smc_msg_with_param(smu, 1632 SMU_MSG_GetDcModeMaxDpmFreq, 1633 param, 1634 max); 1635 if (ret) 1636 goto failed; 1637 } 1638 1639 if (min) { 1640 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 1641 if (ret) 1642 goto failed; 1643 } 1644 1645 failed: 1646 return ret; 1647 } 1648 1649 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, 1650 enum smu_clk_type clk_type, 1651 uint32_t min, 1652 uint32_t max) 1653 { 1654 int ret = 0, clk_id = 0; 1655 uint32_t param; 1656 1657 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1658 return 0; 1659 1660 clk_id = smu_cmn_to_asic_specific_index(smu, 1661 CMN2ASIC_MAPPING_CLK, 1662 clk_type); 1663 if (clk_id < 0) 1664 return clk_id; 1665 1666 if (max > 0) { 1667 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1668 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1669 param, NULL); 1670 if (ret) 1671 goto out; 1672 } 1673 1674 if (min > 0) { 1675 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1676 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1677 param, NULL); 1678 if (ret) 1679 goto out; 1680 } 1681 1682 out: 1683 return ret; 1684 } 1685 1686 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 1687 enum smu_clk_type clk_type, 1688 uint32_t min, 1689 uint32_t max) 1690 { 1691 int ret = 0, clk_id = 0; 1692 uint32_t param; 1693 1694 if (min <= 0 && max <= 0) 1695 return -EINVAL; 1696 1697 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1698 return 0; 1699 1700 clk_id = smu_cmn_to_asic_specific_index(smu, 1701 CMN2ASIC_MAPPING_CLK, 1702 clk_type); 1703 if (clk_id < 0) 1704 return clk_id; 1705 1706 if (max > 0) { 1707 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1708 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1709 param, NULL); 1710 if (ret) 1711 return ret; 1712 } 1713 1714 if (min > 0) { 1715 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1716 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1717 param, NULL); 1718 if (ret) 1719 return ret; 1720 } 1721 1722 return ret; 1723 } 1724 1725 int smu_v13_0_set_performance_level(struct smu_context *smu, 1726 enum amd_dpm_forced_level level) 1727 { 1728 struct smu_13_0_dpm_context *dpm_context = 1729 smu->smu_dpm.dpm_context; 1730 struct smu_13_0_dpm_table *gfx_table = 1731 &dpm_context->dpm_tables.gfx_table; 1732 struct smu_13_0_dpm_table *mem_table = 1733 &dpm_context->dpm_tables.uclk_table; 1734 struct smu_13_0_dpm_table *soc_table = 1735 &dpm_context->dpm_tables.soc_table; 1736 struct smu_13_0_dpm_table *vclk_table = 1737 &dpm_context->dpm_tables.vclk_table; 1738 struct smu_13_0_dpm_table *dclk_table = 1739 &dpm_context->dpm_tables.dclk_table; 1740 struct smu_13_0_dpm_table *fclk_table = 1741 &dpm_context->dpm_tables.fclk_table; 1742 struct smu_umd_pstate_table *pstate_table = 1743 &smu->pstate_table; 1744 struct amdgpu_device *adev = smu->adev; 1745 uint32_t sclk_min = 0, sclk_max = 0; 1746 uint32_t mclk_min = 0, mclk_max = 0; 1747 uint32_t socclk_min = 0, socclk_max = 0; 1748 uint32_t vclk_min = 0, vclk_max = 0; 1749 uint32_t dclk_min = 0, dclk_max = 0; 1750 uint32_t fclk_min = 0, fclk_max = 0; 1751 int ret = 0, i; 1752 1753 switch (level) { 1754 case AMD_DPM_FORCED_LEVEL_HIGH: 1755 sclk_min = sclk_max = gfx_table->max; 1756 mclk_min = mclk_max = mem_table->max; 1757 socclk_min = socclk_max = soc_table->max; 1758 vclk_min = vclk_max = vclk_table->max; 1759 dclk_min = dclk_max = dclk_table->max; 1760 fclk_min = fclk_max = fclk_table->max; 1761 break; 1762 case AMD_DPM_FORCED_LEVEL_LOW: 1763 sclk_min = sclk_max = gfx_table->min; 1764 mclk_min = mclk_max = mem_table->min; 1765 socclk_min = socclk_max = soc_table->min; 1766 vclk_min = vclk_max = vclk_table->min; 1767 dclk_min = dclk_max = dclk_table->min; 1768 fclk_min = fclk_max = fclk_table->min; 1769 break; 1770 case AMD_DPM_FORCED_LEVEL_AUTO: 1771 sclk_min = gfx_table->min; 1772 sclk_max = gfx_table->max; 1773 mclk_min = mem_table->min; 1774 mclk_max = mem_table->max; 1775 socclk_min = soc_table->min; 1776 socclk_max = soc_table->max; 1777 vclk_min = vclk_table->min; 1778 vclk_max = vclk_table->max; 1779 dclk_min = dclk_table->min; 1780 dclk_max = dclk_table->max; 1781 fclk_min = fclk_table->min; 1782 fclk_max = fclk_table->max; 1783 break; 1784 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1785 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1786 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1787 socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1788 vclk_min = vclk_max = pstate_table->vclk_pstate.standard; 1789 dclk_min = dclk_max = pstate_table->dclk_pstate.standard; 1790 fclk_min = fclk_max = pstate_table->fclk_pstate.standard; 1791 break; 1792 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1793 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1794 break; 1795 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1796 mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1797 break; 1798 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1799 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1800 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1801 socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1802 vclk_min = vclk_max = pstate_table->vclk_pstate.peak; 1803 dclk_min = dclk_max = pstate_table->dclk_pstate.peak; 1804 fclk_min = fclk_max = pstate_table->fclk_pstate.peak; 1805 break; 1806 case AMD_DPM_FORCED_LEVEL_MANUAL: 1807 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1808 return 0; 1809 default: 1810 dev_err(adev->dev, "Invalid performance level %d\n", level); 1811 return -EINVAL; 1812 } 1813 1814 /* 1815 * Unset those settings for SMU 13.0.2. As soft limits settings 1816 * for those clock domains are not supported. 1817 */ 1818 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) { 1819 mclk_min = mclk_max = 0; 1820 socclk_min = socclk_max = 0; 1821 vclk_min = vclk_max = 0; 1822 dclk_min = dclk_max = 0; 1823 fclk_min = fclk_max = 0; 1824 } 1825 1826 if (sclk_min && sclk_max) { 1827 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1828 SMU_GFXCLK, 1829 sclk_min, 1830 sclk_max); 1831 if (ret) 1832 return ret; 1833 1834 pstate_table->gfxclk_pstate.curr.min = sclk_min; 1835 pstate_table->gfxclk_pstate.curr.max = sclk_max; 1836 } 1837 1838 if (mclk_min && mclk_max) { 1839 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1840 SMU_MCLK, 1841 mclk_min, 1842 mclk_max); 1843 if (ret) 1844 return ret; 1845 1846 pstate_table->uclk_pstate.curr.min = mclk_min; 1847 pstate_table->uclk_pstate.curr.max = mclk_max; 1848 } 1849 1850 if (socclk_min && socclk_max) { 1851 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1852 SMU_SOCCLK, 1853 socclk_min, 1854 socclk_max); 1855 if (ret) 1856 return ret; 1857 1858 pstate_table->socclk_pstate.curr.min = socclk_min; 1859 pstate_table->socclk_pstate.curr.max = socclk_max; 1860 } 1861 1862 if (vclk_min && vclk_max) { 1863 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1864 if (adev->vcn.harvest_config & (1 << i)) 1865 continue; 1866 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1867 i ? SMU_VCLK1 : SMU_VCLK, 1868 vclk_min, 1869 vclk_max); 1870 if (ret) 1871 return ret; 1872 } 1873 pstate_table->vclk_pstate.curr.min = vclk_min; 1874 pstate_table->vclk_pstate.curr.max = vclk_max; 1875 } 1876 1877 if (dclk_min && dclk_max) { 1878 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1879 if (adev->vcn.harvest_config & (1 << i)) 1880 continue; 1881 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1882 i ? SMU_DCLK1 : SMU_DCLK, 1883 dclk_min, 1884 dclk_max); 1885 if (ret) 1886 return ret; 1887 } 1888 pstate_table->dclk_pstate.curr.min = dclk_min; 1889 pstate_table->dclk_pstate.curr.max = dclk_max; 1890 } 1891 1892 if (fclk_min && fclk_max) { 1893 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1894 SMU_FCLK, 1895 fclk_min, 1896 fclk_max); 1897 if (ret) 1898 return ret; 1899 1900 pstate_table->fclk_pstate.curr.min = fclk_min; 1901 pstate_table->fclk_pstate.curr.max = fclk_max; 1902 } 1903 1904 return ret; 1905 } 1906 1907 int smu_v13_0_set_power_source(struct smu_context *smu, 1908 enum smu_power_src_type power_src) 1909 { 1910 int pwr_source; 1911 1912 pwr_source = smu_cmn_to_asic_specific_index(smu, 1913 CMN2ASIC_MAPPING_PWR, 1914 (uint32_t)power_src); 1915 if (pwr_source < 0) 1916 return -EINVAL; 1917 1918 return smu_cmn_send_smc_msg_with_param(smu, 1919 SMU_MSG_NotifyPowerSource, 1920 pwr_source, 1921 NULL); 1922 } 1923 1924 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu, 1925 enum smu_clk_type clk_type, uint16_t level, 1926 uint32_t *value) 1927 { 1928 int ret = 0, clk_id = 0; 1929 uint32_t param; 1930 1931 if (!value) 1932 return -EINVAL; 1933 1934 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1935 return 0; 1936 1937 clk_id = smu_cmn_to_asic_specific_index(smu, 1938 CMN2ASIC_MAPPING_CLK, 1939 clk_type); 1940 if (clk_id < 0) 1941 return clk_id; 1942 1943 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1944 1945 ret = smu_cmn_send_smc_msg_with_param(smu, 1946 SMU_MSG_GetDpmFreqByIndex, 1947 param, 1948 value); 1949 if (ret) 1950 return ret; 1951 1952 *value = *value & 0x7fffffff; 1953 1954 return ret; 1955 } 1956 1957 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu, 1958 enum smu_clk_type clk_type, 1959 uint32_t *value) 1960 { 1961 int ret; 1962 1963 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value); 1964 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */ 1965 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value)) 1966 ++(*value); 1967 1968 return ret; 1969 } 1970 1971 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu, 1972 enum smu_clk_type clk_type, 1973 bool *is_fine_grained_dpm) 1974 { 1975 int ret = 0, clk_id = 0; 1976 uint32_t param; 1977 uint32_t value; 1978 1979 if (!is_fine_grained_dpm) 1980 return -EINVAL; 1981 1982 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1983 return 0; 1984 1985 clk_id = smu_cmn_to_asic_specific_index(smu, 1986 CMN2ASIC_MAPPING_CLK, 1987 clk_type); 1988 if (clk_id < 0) 1989 return clk_id; 1990 1991 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff); 1992 1993 ret = smu_cmn_send_smc_msg_with_param(smu, 1994 SMU_MSG_GetDpmFreqByIndex, 1995 param, 1996 &value); 1997 if (ret) 1998 return ret; 1999 2000 /* 2001 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM 2002 * now, we un-support it 2003 */ 2004 *is_fine_grained_dpm = value & 0x80000000; 2005 2006 return 0; 2007 } 2008 2009 int smu_v13_0_set_single_dpm_table(struct smu_context *smu, 2010 enum smu_clk_type clk_type, 2011 struct smu_13_0_dpm_table *single_dpm_table) 2012 { 2013 int ret = 0; 2014 uint32_t clk; 2015 int i; 2016 2017 ret = smu_v13_0_get_dpm_level_count(smu, 2018 clk_type, 2019 &single_dpm_table->count); 2020 if (ret) { 2021 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 2022 return ret; 2023 } 2024 2025 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) { 2026 ret = smu_v13_0_get_fine_grained_status(smu, 2027 clk_type, 2028 &single_dpm_table->is_fine_grained); 2029 if (ret) { 2030 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); 2031 return ret; 2032 } 2033 } 2034 2035 for (i = 0; i < single_dpm_table->count; i++) { 2036 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2037 clk_type, 2038 i, 2039 &clk); 2040 if (ret) { 2041 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 2042 return ret; 2043 } 2044 2045 single_dpm_table->dpm_levels[i].value = clk; 2046 single_dpm_table->dpm_levels[i].enabled = true; 2047 2048 if (i == 0) 2049 single_dpm_table->min = clk; 2050 else if (i == single_dpm_table->count - 1) 2051 single_dpm_table->max = clk; 2052 } 2053 2054 return 0; 2055 } 2056 2057 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu) 2058 { 2059 struct amdgpu_device *adev = smu->adev; 2060 2061 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2062 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2063 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2064 } 2065 2066 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu) 2067 { 2068 uint32_t width_level; 2069 2070 width_level = smu_v13_0_get_current_pcie_link_width_level(smu); 2071 if (width_level > LINK_WIDTH_MAX) 2072 width_level = 0; 2073 2074 return link_width[width_level]; 2075 } 2076 2077 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu) 2078 { 2079 struct amdgpu_device *adev = smu->adev; 2080 2081 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2082 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2083 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2084 } 2085 2086 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu) 2087 { 2088 uint32_t speed_level; 2089 2090 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu); 2091 if (speed_level > LINK_SPEED_MAX) 2092 speed_level = 0; 2093 2094 return link_speed[speed_level]; 2095 } 2096 2097 int smu_v13_0_set_vcn_enable(struct smu_context *smu, 2098 bool enable) 2099 { 2100 struct amdgpu_device *adev = smu->adev; 2101 int i, ret = 0; 2102 2103 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2104 if (adev->vcn.harvest_config & (1 << i)) 2105 continue; 2106 2107 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 2108 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 2109 i << 16U, NULL); 2110 if (ret) 2111 return ret; 2112 } 2113 2114 return ret; 2115 } 2116 2117 int smu_v13_0_set_jpeg_enable(struct smu_context *smu, 2118 bool enable) 2119 { 2120 return smu_cmn_send_smc_msg_with_param(smu, enable ? 2121 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, 2122 0, NULL); 2123 } 2124 2125 int smu_v13_0_run_btc(struct smu_context *smu) 2126 { 2127 int res; 2128 2129 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2130 if (res) 2131 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 2132 2133 return res; 2134 } 2135 2136 int smu_v13_0_gpo_control(struct smu_context *smu, 2137 bool enablement) 2138 { 2139 int res; 2140 2141 res = smu_cmn_send_smc_msg_with_param(smu, 2142 SMU_MSG_AllowGpo, 2143 enablement ? 1 : 0, 2144 NULL); 2145 if (res) 2146 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement); 2147 2148 return res; 2149 } 2150 2151 int smu_v13_0_deep_sleep_control(struct smu_context *smu, 2152 bool enablement) 2153 { 2154 struct amdgpu_device *adev = smu->adev; 2155 int ret = 0; 2156 2157 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 2158 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 2159 if (ret) { 2160 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 2161 return ret; 2162 } 2163 } 2164 2165 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 2166 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 2167 if (ret) { 2168 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 2169 return ret; 2170 } 2171 } 2172 2173 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 2174 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 2175 if (ret) { 2176 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 2177 return ret; 2178 } 2179 } 2180 2181 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 2182 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 2183 if (ret) { 2184 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 2185 return ret; 2186 } 2187 } 2188 2189 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 2190 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 2191 if (ret) { 2192 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 2193 return ret; 2194 } 2195 } 2196 2197 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) { 2198 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement); 2199 if (ret) { 2200 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable"); 2201 return ret; 2202 } 2203 } 2204 2205 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) { 2206 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement); 2207 if (ret) { 2208 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable"); 2209 return ret; 2210 } 2211 } 2212 2213 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) { 2214 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement); 2215 if (ret) { 2216 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable"); 2217 return ret; 2218 } 2219 } 2220 2221 return ret; 2222 } 2223 2224 int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 2225 bool enablement) 2226 { 2227 int ret = 0; 2228 2229 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 2230 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 2231 2232 return ret; 2233 } 2234 2235 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu, 2236 enum smu_baco_seq baco_seq) 2237 { 2238 struct smu_baco_context *smu_baco = &smu->smu_baco; 2239 int ret; 2240 2241 ret = smu_cmn_send_smc_msg_with_param(smu, 2242 SMU_MSG_ArmD3, 2243 baco_seq, 2244 NULL); 2245 if (ret) 2246 return ret; 2247 2248 if (baco_seq == BACO_SEQ_BAMACO || 2249 baco_seq == BACO_SEQ_BACO) 2250 smu_baco->state = SMU_BACO_STATE_ENTER; 2251 else 2252 smu_baco->state = SMU_BACO_STATE_EXIT; 2253 2254 return 0; 2255 } 2256 2257 bool smu_v13_0_baco_is_support(struct smu_context *smu) 2258 { 2259 struct smu_baco_context *smu_baco = &smu->smu_baco; 2260 2261 if (amdgpu_sriov_vf(smu->adev) || 2262 !smu_baco->platform_support) 2263 return false; 2264 2265 /* return true if ASIC is in BACO state already */ 2266 if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER) 2267 return true; 2268 2269 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 2270 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 2271 return false; 2272 2273 return true; 2274 } 2275 2276 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu) 2277 { 2278 struct smu_baco_context *smu_baco = &smu->smu_baco; 2279 2280 return smu_baco->state; 2281 } 2282 2283 int smu_v13_0_baco_set_state(struct smu_context *smu, 2284 enum smu_baco_state state) 2285 { 2286 struct smu_baco_context *smu_baco = &smu->smu_baco; 2287 struct amdgpu_device *adev = smu->adev; 2288 int ret = 0; 2289 2290 if (smu_v13_0_baco_get_state(smu) == state) 2291 return 0; 2292 2293 if (state == SMU_BACO_STATE_ENTER) { 2294 ret = smu_cmn_send_smc_msg_with_param(smu, 2295 SMU_MSG_EnterBaco, 2296 smu_baco->maco_support ? 2297 BACO_SEQ_BAMACO : BACO_SEQ_BACO, 2298 NULL); 2299 } else { 2300 ret = smu_cmn_send_smc_msg(smu, 2301 SMU_MSG_ExitBaco, 2302 NULL); 2303 if (ret) 2304 return ret; 2305 2306 /* clear vbios scratch 6 and 7 for coming asic reinit */ 2307 WREG32(adev->bios_scratch_reg_offset + 6, 0); 2308 WREG32(adev->bios_scratch_reg_offset + 7, 0); 2309 } 2310 2311 if (!ret) 2312 smu_baco->state = state; 2313 2314 return ret; 2315 } 2316 2317 int smu_v13_0_baco_enter(struct smu_context *smu) 2318 { 2319 int ret = 0; 2320 2321 ret = smu_v13_0_baco_set_state(smu, 2322 SMU_BACO_STATE_ENTER); 2323 if (ret) 2324 return ret; 2325 2326 msleep(10); 2327 2328 return ret; 2329 } 2330 2331 int smu_v13_0_baco_exit(struct smu_context *smu) 2332 { 2333 return smu_v13_0_baco_set_state(smu, 2334 SMU_BACO_STATE_EXIT); 2335 } 2336 2337 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu) 2338 { 2339 uint16_t index; 2340 2341 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2342 SMU_MSG_EnableGfxImu); 2343 /* Param 1 to tell PMFW to enable GFXOFF feature */ 2344 return smu_cmn_send_msg_without_waiting(smu, index, 1); 2345 } 2346 2347 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, 2348 enum PP_OD_DPM_TABLE_COMMAND type, 2349 long input[], uint32_t size) 2350 { 2351 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 2352 int ret = 0; 2353 2354 /* Only allowed in manual mode */ 2355 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 2356 return -EINVAL; 2357 2358 switch (type) { 2359 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2360 if (size != 2) { 2361 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2362 return -EINVAL; 2363 } 2364 2365 if (input[0] == 0) { 2366 if (input[1] < smu->gfx_default_hard_min_freq) { 2367 dev_warn(smu->adev->dev, 2368 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2369 input[1], smu->gfx_default_hard_min_freq); 2370 return -EINVAL; 2371 } 2372 smu->gfx_actual_hard_min_freq = input[1]; 2373 } else if (input[0] == 1) { 2374 if (input[1] > smu->gfx_default_soft_max_freq) { 2375 dev_warn(smu->adev->dev, 2376 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2377 input[1], smu->gfx_default_soft_max_freq); 2378 return -EINVAL; 2379 } 2380 smu->gfx_actual_soft_max_freq = input[1]; 2381 } else { 2382 return -EINVAL; 2383 } 2384 break; 2385 case PP_OD_RESTORE_DEFAULT_TABLE: 2386 if (size != 0) { 2387 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2388 return -EINVAL; 2389 } 2390 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 2391 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 2392 break; 2393 case PP_OD_COMMIT_DPM_TABLE: 2394 if (size != 0) { 2395 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2396 return -EINVAL; 2397 } 2398 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 2399 dev_err(smu->adev->dev, 2400 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 2401 smu->gfx_actual_hard_min_freq, 2402 smu->gfx_actual_soft_max_freq); 2403 return -EINVAL; 2404 } 2405 2406 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 2407 smu->gfx_actual_hard_min_freq, 2408 NULL); 2409 if (ret) { 2410 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 2411 return ret; 2412 } 2413 2414 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 2415 smu->gfx_actual_soft_max_freq, 2416 NULL); 2417 if (ret) { 2418 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 2419 return ret; 2420 } 2421 break; 2422 default: 2423 return -ENOSYS; 2424 } 2425 2426 return ret; 2427 } 2428 2429 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu) 2430 { 2431 struct smu_table_context *smu_table = &smu->smu_table; 2432 2433 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, 2434 smu_table->clocks_table, false); 2435 } 2436 2437 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu) 2438 { 2439 struct amdgpu_device *adev = smu->adev; 2440 2441 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2442 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2443 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2444 } 2445 2446 int smu_v13_0_mode1_reset(struct smu_context *smu) 2447 { 2448 int ret = 0; 2449 2450 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 2451 if (!ret) 2452 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 2453 2454 return ret; 2455 } 2456