1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/reboot.h> 27 28 #define SMU_13_0_PARTIAL_PPTABLE 29 #define SWSMU_CODE_LAYER_L3 30 31 #include "amdgpu.h" 32 #include "amdgpu_smu.h" 33 #include "atomfirmware.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_atombios.h" 36 #include "smu_v13_0.h" 37 #include "soc15_common.h" 38 #include "atom.h" 39 #include "amdgpu_ras.h" 40 #include "smu_cmn.h" 41 42 #include "asic_reg/thm/thm_13_0_2_offset.h" 43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h" 44 #include "asic_reg/mp/mp_13_0_2_offset.h" 45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h" 46 #include "asic_reg/smuio/smuio_13_0_2_offset.h" 47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h" 48 49 /* 50 * DO NOT use these for err/warn/info/debug messages. 51 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52 * They are more MGPU friendly. 53 */ 54 #undef pr_err 55 #undef pr_warn 56 #undef pr_info 57 #undef pr_debug 58 59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin"); 60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin"); 61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin"); 62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin"); 63 64 #define mmMP1_SMN_C2PMSG_66 0x0282 65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 66 67 #define mmMP1_SMN_C2PMSG_82 0x0292 68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 69 70 #define mmMP1_SMN_C2PMSG_90 0x029a 71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 72 73 #define SMU13_VOLTAGE_SCALE 4 74 75 #define LINK_WIDTH_MAX 6 76 #define LINK_SPEED_MAX 3 77 78 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L 80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 81 #define smnPCIE_LC_SPEED_CNTL 0x11140290 82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE 84 85 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 86 static const int link_speed[] = {25, 50, 80, 160}; 87 88 int smu_v13_0_init_microcode(struct smu_context *smu) 89 { 90 struct amdgpu_device *adev = smu->adev; 91 const char *chip_name; 92 char fw_name[30]; 93 char ucode_prefix[30]; 94 int err = 0; 95 const struct smc_firmware_header_v1_0 *hdr; 96 const struct common_firmware_header *header; 97 struct amdgpu_firmware_info *ucode = NULL; 98 99 /* doesn't need to load smu firmware in IOV mode */ 100 if (amdgpu_sriov_vf(adev)) 101 return 0; 102 103 switch (adev->ip_versions[MP1_HWIP][0]) { 104 case IP_VERSION(13, 0, 2): 105 chip_name = "aldebaran_smc"; 106 break; 107 default: 108 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); 109 chip_name = ucode_prefix; 110 } 111 112 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); 113 114 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 115 if (err) 116 goto out; 117 err = amdgpu_ucode_validate(adev->pm.fw); 118 if (err) 119 goto out; 120 121 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 122 amdgpu_ucode_print_smc_hdr(&hdr->header); 123 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 124 125 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 126 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 127 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 128 ucode->fw = adev->pm.fw; 129 header = (const struct common_firmware_header *)ucode->fw->data; 130 adev->firmware.fw_size += 131 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 132 } 133 134 out: 135 if (err) { 136 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n", 137 fw_name); 138 release_firmware(adev->pm.fw); 139 adev->pm.fw = NULL; 140 } 141 return err; 142 } 143 144 void smu_v13_0_fini_microcode(struct smu_context *smu) 145 { 146 struct amdgpu_device *adev = smu->adev; 147 148 release_firmware(adev->pm.fw); 149 adev->pm.fw = NULL; 150 adev->pm.fw_version = 0; 151 } 152 153 int smu_v13_0_load_microcode(struct smu_context *smu) 154 { 155 #if 0 156 struct amdgpu_device *adev = smu->adev; 157 const uint32_t *src; 158 const struct smc_firmware_header_v1_0 *hdr; 159 uint32_t addr_start = MP1_SRAM; 160 uint32_t i; 161 uint32_t smc_fw_size; 162 uint32_t mp1_fw_flags; 163 164 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 165 src = (const uint32_t *)(adev->pm.fw->data + 166 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 167 smc_fw_size = hdr->header.ucode_size_bytes; 168 169 for (i = 1; i < smc_fw_size/4 - 1; i++) { 170 WREG32_PCIE(addr_start, src[i]); 171 addr_start += 4; 172 } 173 174 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 175 1 & MP1_SMN_PUB_CTRL__RESET_MASK); 176 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 177 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); 178 179 for (i = 0; i < adev->usec_timeout; i++) { 180 mp1_fw_flags = RREG32_PCIE(MP1_Public | 181 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 182 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 183 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 184 break; 185 udelay(1); 186 } 187 188 if (i == adev->usec_timeout) 189 return -ETIME; 190 #endif 191 192 return 0; 193 } 194 195 int smu_v13_0_init_pptable_microcode(struct smu_context *smu) 196 { 197 struct amdgpu_device *adev = smu->adev; 198 struct amdgpu_firmware_info *ucode = NULL; 199 uint32_t size = 0, pptable_id = 0; 200 int ret = 0; 201 void *table; 202 203 /* doesn't need to load smu firmware in IOV mode */ 204 if (amdgpu_sriov_vf(adev)) 205 return 0; 206 207 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 208 return 0; 209 210 if (!adev->scpm_enabled) 211 return 0; 212 213 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) || 214 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) || 215 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))) 216 return 0; 217 218 /* override pptable_id from driver parameter */ 219 if (amdgpu_smu_pptable_id >= 0) { 220 pptable_id = amdgpu_smu_pptable_id; 221 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 222 } else { 223 pptable_id = smu->smu_table.boot_values.pp_table_id; 224 } 225 226 /* "pptable_id == 0" means vbios carries the pptable. */ 227 if (!pptable_id) 228 return 0; 229 230 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 231 if (ret) 232 return ret; 233 234 smu->pptable_firmware.data = table; 235 smu->pptable_firmware.size = size; 236 237 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE]; 238 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE; 239 ucode->fw = &smu->pptable_firmware; 240 adev->firmware.fw_size += 241 ALIGN(smu->pptable_firmware.size, PAGE_SIZE); 242 243 return 0; 244 } 245 246 int smu_v13_0_check_fw_status(struct smu_context *smu) 247 { 248 struct amdgpu_device *adev = smu->adev; 249 uint32_t mp1_fw_flags; 250 251 switch (adev->ip_versions[MP1_HWIP][0]) { 252 case IP_VERSION(13, 0, 4): 253 mp1_fw_flags = RREG32_PCIE(MP1_Public | 254 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff)); 255 break; 256 default: 257 mp1_fw_flags = RREG32_PCIE(MP1_Public | 258 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 259 break; 260 } 261 262 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 263 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 264 return 0; 265 266 return -EIO; 267 } 268 269 int smu_v13_0_check_fw_version(struct smu_context *smu) 270 { 271 struct amdgpu_device *adev = smu->adev; 272 uint32_t if_version = 0xff, smu_version = 0xff; 273 uint8_t smu_program, smu_major, smu_minor, smu_debug; 274 int ret = 0; 275 276 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 277 if (ret) 278 return ret; 279 280 smu_program = (smu_version >> 24) & 0xff; 281 smu_major = (smu_version >> 16) & 0xff; 282 smu_minor = (smu_version >> 8) & 0xff; 283 smu_debug = (smu_version >> 0) & 0xff; 284 if (smu->is_apu) 285 adev->pm.fw_version = smu_version; 286 287 switch (adev->ip_versions[MP1_HWIP][0]) { 288 case IP_VERSION(13, 0, 2): 289 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; 290 break; 291 case IP_VERSION(13, 0, 0): 292 case IP_VERSION(13, 0, 10): 293 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10; 294 break; 295 case IP_VERSION(13, 0, 7): 296 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7; 297 break; 298 case IP_VERSION(13, 0, 1): 299 case IP_VERSION(13, 0, 3): 300 case IP_VERSION(13, 0, 8): 301 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP; 302 break; 303 case IP_VERSION(13, 0, 4): 304 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4; 305 break; 306 case IP_VERSION(13, 0, 5): 307 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5; 308 break; 309 default: 310 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n", 311 adev->ip_versions[MP1_HWIP][0]); 312 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV; 313 break; 314 } 315 316 /* only for dGPU w/ SMU13*/ 317 if (adev->pm.fw) 318 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n", 319 smu_program, smu_version, smu_major, smu_minor, smu_debug); 320 321 /* 322 * 1. if_version mismatch is not critical as our fw is designed 323 * to be backward compatible. 324 * 2. New fw usually brings some optimizations. But that's visible 325 * only on the paired driver. 326 * Considering above, we just leave user a warning message instead 327 * of halt driver loading. 328 */ 329 if (if_version != smu->smc_driver_if_version) { 330 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " 331 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", 332 smu->smc_driver_if_version, if_version, 333 smu_program, smu_version, smu_major, smu_minor, smu_debug); 334 dev_warn(adev->dev, "SMU driver if version not matched\n"); 335 } 336 337 return ret; 338 } 339 340 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 341 { 342 struct amdgpu_device *adev = smu->adev; 343 uint32_t ppt_offset_bytes; 344 const struct smc_firmware_header_v2_0 *v2; 345 346 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 347 348 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 349 *size = le32_to_cpu(v2->ppt_size_bytes); 350 *table = (uint8_t *)v2 + ppt_offset_bytes; 351 352 return 0; 353 } 354 355 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table, 356 uint32_t *size, uint32_t pptable_id) 357 { 358 struct amdgpu_device *adev = smu->adev; 359 const struct smc_firmware_header_v2_1 *v2_1; 360 struct smc_soft_pptable_entry *entries; 361 uint32_t pptable_count = 0; 362 int i = 0; 363 364 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 365 entries = (struct smc_soft_pptable_entry *) 366 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 367 pptable_count = le32_to_cpu(v2_1->pptable_count); 368 for (i = 0; i < pptable_count; i++) { 369 if (le32_to_cpu(entries[i].id) == pptable_id) { 370 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 371 *size = le32_to_cpu(entries[i].ppt_size_bytes); 372 break; 373 } 374 } 375 376 if (i == pptable_count) 377 return -EINVAL; 378 379 return 0; 380 } 381 382 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size) 383 { 384 struct amdgpu_device *adev = smu->adev; 385 uint16_t atom_table_size; 386 uint8_t frev, crev; 387 int ret, index; 388 389 dev_info(adev->dev, "use vbios provided pptable\n"); 390 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 391 powerplayinfo); 392 393 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 394 (uint8_t **)table); 395 if (ret) 396 return ret; 397 398 if (size) 399 *size = atom_table_size; 400 401 return 0; 402 } 403 404 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, 405 void **table, 406 uint32_t *size, 407 uint32_t pptable_id) 408 { 409 const struct smc_firmware_header_v1_0 *hdr; 410 struct amdgpu_device *adev = smu->adev; 411 uint16_t version_major, version_minor; 412 int ret; 413 414 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 415 if (!hdr) 416 return -EINVAL; 417 418 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id); 419 420 version_major = le16_to_cpu(hdr->header.header_version_major); 421 version_minor = le16_to_cpu(hdr->header.header_version_minor); 422 if (version_major != 2) { 423 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n", 424 version_major, version_minor); 425 return -EINVAL; 426 } 427 428 switch (version_minor) { 429 case 0: 430 ret = smu_v13_0_set_pptable_v2_0(smu, table, size); 431 break; 432 case 1: 433 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id); 434 break; 435 default: 436 ret = -EINVAL; 437 break; 438 } 439 440 return ret; 441 } 442 443 int smu_v13_0_setup_pptable(struct smu_context *smu) 444 { 445 struct amdgpu_device *adev = smu->adev; 446 uint32_t size = 0, pptable_id = 0; 447 void *table; 448 int ret = 0; 449 450 /* override pptable_id from driver parameter */ 451 if (amdgpu_smu_pptable_id >= 0) { 452 pptable_id = amdgpu_smu_pptable_id; 453 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 454 } else { 455 pptable_id = smu->smu_table.boot_values.pp_table_id; 456 } 457 458 /* force using vbios pptable in sriov mode */ 459 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1)) 460 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size); 461 else 462 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 463 464 if (ret) 465 return ret; 466 467 if (!smu->smu_table.power_play_table) 468 smu->smu_table.power_play_table = table; 469 if (!smu->smu_table.power_play_table_size) 470 smu->smu_table.power_play_table_size = size; 471 472 return 0; 473 } 474 475 int smu_v13_0_init_smc_tables(struct smu_context *smu) 476 { 477 struct smu_table_context *smu_table = &smu->smu_table; 478 struct smu_table *tables = smu_table->tables; 479 int ret = 0; 480 481 smu_table->driver_pptable = 482 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 483 if (!smu_table->driver_pptable) { 484 ret = -ENOMEM; 485 goto err0_out; 486 } 487 488 smu_table->max_sustainable_clocks = 489 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL); 490 if (!smu_table->max_sustainable_clocks) { 491 ret = -ENOMEM; 492 goto err1_out; 493 } 494 495 /* Aldebaran does not support OVERDRIVE */ 496 if (tables[SMU_TABLE_OVERDRIVE].size) { 497 smu_table->overdrive_table = 498 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 499 if (!smu_table->overdrive_table) { 500 ret = -ENOMEM; 501 goto err2_out; 502 } 503 504 smu_table->boot_overdrive_table = 505 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 506 if (!smu_table->boot_overdrive_table) { 507 ret = -ENOMEM; 508 goto err3_out; 509 } 510 } 511 512 smu_table->combo_pptable = 513 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL); 514 if (!smu_table->combo_pptable) { 515 ret = -ENOMEM; 516 goto err4_out; 517 } 518 519 return 0; 520 521 err4_out: 522 kfree(smu_table->boot_overdrive_table); 523 err3_out: 524 kfree(smu_table->overdrive_table); 525 err2_out: 526 kfree(smu_table->max_sustainable_clocks); 527 err1_out: 528 kfree(smu_table->driver_pptable); 529 err0_out: 530 return ret; 531 } 532 533 int smu_v13_0_fini_smc_tables(struct smu_context *smu) 534 { 535 struct smu_table_context *smu_table = &smu->smu_table; 536 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 537 538 kfree(smu_table->gpu_metrics_table); 539 kfree(smu_table->combo_pptable); 540 kfree(smu_table->boot_overdrive_table); 541 kfree(smu_table->overdrive_table); 542 kfree(smu_table->max_sustainable_clocks); 543 kfree(smu_table->driver_pptable); 544 smu_table->gpu_metrics_table = NULL; 545 smu_table->combo_pptable = NULL; 546 smu_table->boot_overdrive_table = NULL; 547 smu_table->overdrive_table = NULL; 548 smu_table->max_sustainable_clocks = NULL; 549 smu_table->driver_pptable = NULL; 550 kfree(smu_table->hardcode_pptable); 551 smu_table->hardcode_pptable = NULL; 552 553 kfree(smu_table->ecc_table); 554 kfree(smu_table->metrics_table); 555 kfree(smu_table->watermarks_table); 556 smu_table->ecc_table = NULL; 557 smu_table->metrics_table = NULL; 558 smu_table->watermarks_table = NULL; 559 smu_table->metrics_time = 0; 560 561 kfree(smu_dpm->dpm_context); 562 kfree(smu_dpm->golden_dpm_context); 563 kfree(smu_dpm->dpm_current_power_state); 564 kfree(smu_dpm->dpm_request_power_state); 565 smu_dpm->dpm_context = NULL; 566 smu_dpm->golden_dpm_context = NULL; 567 smu_dpm->dpm_context_size = 0; 568 smu_dpm->dpm_current_power_state = NULL; 569 smu_dpm->dpm_request_power_state = NULL; 570 571 return 0; 572 } 573 574 int smu_v13_0_init_power(struct smu_context *smu) 575 { 576 struct smu_power_context *smu_power = &smu->smu_power; 577 578 if (smu_power->power_context || smu_power->power_context_size != 0) 579 return -EINVAL; 580 581 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 582 GFP_KERNEL); 583 if (!smu_power->power_context) 584 return -ENOMEM; 585 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context); 586 587 return 0; 588 } 589 590 int smu_v13_0_fini_power(struct smu_context *smu) 591 { 592 struct smu_power_context *smu_power = &smu->smu_power; 593 594 if (!smu_power->power_context || smu_power->power_context_size == 0) 595 return -EINVAL; 596 597 kfree(smu_power->power_context); 598 smu_power->power_context = NULL; 599 smu_power->power_context_size = 0; 600 601 return 0; 602 } 603 604 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu) 605 { 606 int ret, index; 607 uint16_t size; 608 uint8_t frev, crev; 609 struct atom_common_table_header *header; 610 struct atom_firmware_info_v3_4 *v_3_4; 611 struct atom_firmware_info_v3_3 *v_3_3; 612 struct atom_firmware_info_v3_1 *v_3_1; 613 struct atom_smu_info_v3_6 *smu_info_v3_6; 614 struct atom_smu_info_v4_0 *smu_info_v4_0; 615 616 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 617 firmwareinfo); 618 619 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 620 (uint8_t **)&header); 621 if (ret) 622 return ret; 623 624 if (header->format_revision != 3) { 625 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n"); 626 return -EINVAL; 627 } 628 629 switch (header->content_revision) { 630 case 0: 631 case 1: 632 case 2: 633 v_3_1 = (struct atom_firmware_info_v3_1 *)header; 634 smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 635 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 636 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 637 smu->smu_table.boot_values.socclk = 0; 638 smu->smu_table.boot_values.dcefclk = 0; 639 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 640 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 641 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 642 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 643 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 644 smu->smu_table.boot_values.pp_table_id = 0; 645 break; 646 case 3: 647 v_3_3 = (struct atom_firmware_info_v3_3 *)header; 648 smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 649 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 650 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 651 smu->smu_table.boot_values.socclk = 0; 652 smu->smu_table.boot_values.dcefclk = 0; 653 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 654 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 655 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 656 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 657 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 658 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 659 break; 660 case 4: 661 default: 662 v_3_4 = (struct atom_firmware_info_v3_4 *)header; 663 smu->smu_table.boot_values.revision = v_3_4->firmware_revision; 664 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; 665 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; 666 smu->smu_table.boot_values.socclk = 0; 667 smu->smu_table.boot_values.dcefclk = 0; 668 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; 669 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; 670 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; 671 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; 672 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; 673 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id; 674 break; 675 } 676 677 smu->smu_table.boot_values.format_revision = header->format_revision; 678 smu->smu_table.boot_values.content_revision = header->content_revision; 679 680 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 681 smu_info); 682 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 683 (uint8_t **)&header)) { 684 685 if ((frev == 3) && (crev == 6)) { 686 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header; 687 688 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; 689 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz; 690 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz; 691 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; 692 } else if ((frev == 3) && (crev == 1)) { 693 return 0; 694 } else if ((frev == 4) && (crev == 0)) { 695 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header; 696 697 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; 698 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; 699 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz; 700 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz; 701 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz; 702 } else { 703 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n", 704 (uint32_t)frev, (uint32_t)crev); 705 } 706 } 707 708 return 0; 709 } 710 711 712 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu) 713 { 714 struct smu_table_context *smu_table = &smu->smu_table; 715 struct smu_table *memory_pool = &smu_table->memory_pool; 716 int ret = 0; 717 uint64_t address; 718 uint32_t address_low, address_high; 719 720 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 721 return ret; 722 723 address = memory_pool->mc_address; 724 address_high = (uint32_t)upper_32_bits(address); 725 address_low = (uint32_t)lower_32_bits(address); 726 727 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 728 address_high, NULL); 729 if (ret) 730 return ret; 731 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 732 address_low, NULL); 733 if (ret) 734 return ret; 735 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 736 (uint32_t)memory_pool->size, NULL); 737 if (ret) 738 return ret; 739 740 return ret; 741 } 742 743 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 744 { 745 int ret; 746 747 ret = smu_cmn_send_smc_msg_with_param(smu, 748 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); 749 if (ret) 750 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!"); 751 752 return ret; 753 } 754 755 int smu_v13_0_set_driver_table_location(struct smu_context *smu) 756 { 757 struct smu_table *driver_table = &smu->smu_table.driver_table; 758 int ret = 0; 759 760 if (driver_table->mc_address) { 761 ret = smu_cmn_send_smc_msg_with_param(smu, 762 SMU_MSG_SetDriverDramAddrHigh, 763 upper_32_bits(driver_table->mc_address), 764 NULL); 765 if (!ret) 766 ret = smu_cmn_send_smc_msg_with_param(smu, 767 SMU_MSG_SetDriverDramAddrLow, 768 lower_32_bits(driver_table->mc_address), 769 NULL); 770 } 771 772 return ret; 773 } 774 775 int smu_v13_0_set_tool_table_location(struct smu_context *smu) 776 { 777 int ret = 0; 778 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 779 780 if (tool_table->mc_address) { 781 ret = smu_cmn_send_smc_msg_with_param(smu, 782 SMU_MSG_SetToolsDramAddrHigh, 783 upper_32_bits(tool_table->mc_address), 784 NULL); 785 if (!ret) 786 ret = smu_cmn_send_smc_msg_with_param(smu, 787 SMU_MSG_SetToolsDramAddrLow, 788 lower_32_bits(tool_table->mc_address), 789 NULL); 790 } 791 792 return ret; 793 } 794 795 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count) 796 { 797 int ret = 0; 798 799 if (!smu->pm_enabled) 800 return ret; 801 802 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL); 803 804 return ret; 805 } 806 807 int smu_v13_0_set_allowed_mask(struct smu_context *smu) 808 { 809 struct smu_feature *feature = &smu->smu_feature; 810 int ret = 0; 811 uint32_t feature_mask[2]; 812 813 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || 814 feature->feature_num < 64) 815 return -EINVAL; 816 817 bitmap_to_arr32(feature_mask, feature->allowed, 64); 818 819 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 820 feature_mask[1], NULL); 821 if (ret) 822 return ret; 823 824 return smu_cmn_send_smc_msg_with_param(smu, 825 SMU_MSG_SetAllowedFeaturesMaskLow, 826 feature_mask[0], 827 NULL); 828 } 829 830 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable) 831 { 832 int ret = 0; 833 struct amdgpu_device *adev = smu->adev; 834 835 switch (adev->ip_versions[MP1_HWIP][0]) { 836 case IP_VERSION(13, 0, 0): 837 case IP_VERSION(13, 0, 1): 838 case IP_VERSION(13, 0, 3): 839 case IP_VERSION(13, 0, 4): 840 case IP_VERSION(13, 0, 5): 841 case IP_VERSION(13, 0, 7): 842 case IP_VERSION(13, 0, 8): 843 case IP_VERSION(13, 0, 10): 844 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 845 return 0; 846 if (enable) 847 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 848 else 849 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 850 break; 851 default: 852 break; 853 } 854 855 return ret; 856 } 857 858 int smu_v13_0_system_features_control(struct smu_context *smu, 859 bool en) 860 { 861 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 862 SMU_MSG_DisableAllSmuFeatures), NULL); 863 } 864 865 int smu_v13_0_notify_display_change(struct smu_context *smu) 866 { 867 int ret = 0; 868 869 if (!smu->pm_enabled) 870 return ret; 871 872 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 873 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 874 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 875 876 return ret; 877 } 878 879 static int 880 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, 881 enum smu_clk_type clock_select) 882 { 883 int ret = 0; 884 int clk_id; 885 886 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || 887 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) 888 return 0; 889 890 clk_id = smu_cmn_to_asic_specific_index(smu, 891 CMN2ASIC_MAPPING_CLK, 892 clock_select); 893 if (clk_id < 0) 894 return -EINVAL; 895 896 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, 897 clk_id << 16, clock); 898 if (ret) { 899 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); 900 return ret; 901 } 902 903 if (*clock != 0) 904 return 0; 905 906 /* if DC limit is zero, return AC limit */ 907 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, 908 clk_id << 16, clock); 909 if (ret) { 910 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!"); 911 return ret; 912 } 913 914 return 0; 915 } 916 917 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu) 918 { 919 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks = 920 smu->smu_table.max_sustainable_clocks; 921 int ret = 0; 922 923 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; 924 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; 925 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; 926 max_sustainable_clocks->display_clock = 0xFFFFFFFF; 927 max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 928 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 929 930 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 931 ret = smu_v13_0_get_max_sustainable_clock(smu, 932 &(max_sustainable_clocks->uclock), 933 SMU_UCLK); 934 if (ret) { 935 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!", 936 __func__); 937 return ret; 938 } 939 } 940 941 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 942 ret = smu_v13_0_get_max_sustainable_clock(smu, 943 &(max_sustainable_clocks->soc_clock), 944 SMU_SOCCLK); 945 if (ret) { 946 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!", 947 __func__); 948 return ret; 949 } 950 } 951 952 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 953 ret = smu_v13_0_get_max_sustainable_clock(smu, 954 &(max_sustainable_clocks->dcef_clock), 955 SMU_DCEFCLK); 956 if (ret) { 957 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!", 958 __func__); 959 return ret; 960 } 961 962 ret = smu_v13_0_get_max_sustainable_clock(smu, 963 &(max_sustainable_clocks->display_clock), 964 SMU_DISPCLK); 965 if (ret) { 966 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!", 967 __func__); 968 return ret; 969 } 970 ret = smu_v13_0_get_max_sustainable_clock(smu, 971 &(max_sustainable_clocks->phy_clock), 972 SMU_PHYCLK); 973 if (ret) { 974 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!", 975 __func__); 976 return ret; 977 } 978 ret = smu_v13_0_get_max_sustainable_clock(smu, 979 &(max_sustainable_clocks->pixel_clock), 980 SMU_PIXCLK); 981 if (ret) { 982 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!", 983 __func__); 984 return ret; 985 } 986 } 987 988 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 989 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 990 991 return 0; 992 } 993 994 int smu_v13_0_get_current_power_limit(struct smu_context *smu, 995 uint32_t *power_limit) 996 { 997 int power_src; 998 int ret = 0; 999 1000 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 1001 return -EINVAL; 1002 1003 power_src = smu_cmn_to_asic_specific_index(smu, 1004 CMN2ASIC_MAPPING_PWR, 1005 smu->adev->pm.ac_power ? 1006 SMU_POWER_SOURCE_AC : 1007 SMU_POWER_SOURCE_DC); 1008 if (power_src < 0) 1009 return -EINVAL; 1010 1011 ret = smu_cmn_send_smc_msg_with_param(smu, 1012 SMU_MSG_GetPptLimit, 1013 power_src << 16, 1014 power_limit); 1015 if (ret) 1016 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 1017 1018 return ret; 1019 } 1020 1021 int smu_v13_0_set_power_limit(struct smu_context *smu, 1022 enum smu_ppt_limit_type limit_type, 1023 uint32_t limit) 1024 { 1025 int ret = 0; 1026 1027 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 1028 return -EINVAL; 1029 1030 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1031 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 1032 return -EOPNOTSUPP; 1033 } 1034 1035 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL); 1036 if (ret) { 1037 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 1038 return ret; 1039 } 1040 1041 smu->current_power_limit = limit; 1042 1043 return 0; 1044 } 1045 1046 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu) 1047 { 1048 return smu_cmn_send_smc_msg(smu, 1049 SMU_MSG_AllowIHHostInterrupt, 1050 NULL); 1051 } 1052 1053 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu) 1054 { 1055 int ret = 0; 1056 1057 if (smu->dc_controlled_by_gpio && 1058 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) 1059 ret = smu_v13_0_allow_ih_interrupt(smu); 1060 1061 return ret; 1062 } 1063 1064 int smu_v13_0_enable_thermal_alert(struct smu_context *smu) 1065 { 1066 int ret = 0; 1067 1068 if (!smu->irq_source.num_types) 1069 return 0; 1070 1071 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 1072 if (ret) 1073 return ret; 1074 1075 return smu_v13_0_process_pending_interrupt(smu); 1076 } 1077 1078 int smu_v13_0_disable_thermal_alert(struct smu_context *smu) 1079 { 1080 if (!smu->irq_source.num_types) 1081 return 0; 1082 1083 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1084 } 1085 1086 static uint16_t convert_to_vddc(uint8_t vid) 1087 { 1088 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE); 1089 } 1090 1091 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) 1092 { 1093 struct amdgpu_device *adev = smu->adev; 1094 uint32_t vdd = 0, val_vid = 0; 1095 1096 if (!value) 1097 return -EINVAL; 1098 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) & 1099 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 1100 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 1101 1102 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); 1103 1104 *value = vdd; 1105 1106 return 0; 1107 1108 } 1109 1110 int 1111 smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 1112 struct pp_display_clock_request 1113 *clock_req) 1114 { 1115 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1116 int ret = 0; 1117 enum smu_clk_type clk_select = 0; 1118 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1119 1120 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || 1121 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1122 switch (clk_type) { 1123 case amd_pp_dcef_clock: 1124 clk_select = SMU_DCEFCLK; 1125 break; 1126 case amd_pp_disp_clock: 1127 clk_select = SMU_DISPCLK; 1128 break; 1129 case amd_pp_pixel_clock: 1130 clk_select = SMU_PIXCLK; 1131 break; 1132 case amd_pp_phy_clock: 1133 clk_select = SMU_PHYCLK; 1134 break; 1135 case amd_pp_mem_clock: 1136 clk_select = SMU_UCLK; 1137 break; 1138 default: 1139 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); 1140 ret = -EINVAL; 1141 break; 1142 } 1143 1144 if (ret) 1145 goto failed; 1146 1147 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) 1148 return 0; 1149 1150 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); 1151 1152 if(clk_select == SMU_UCLK) 1153 smu->hard_min_uclk_req_from_dal = clk_freq; 1154 } 1155 1156 failed: 1157 return ret; 1158 } 1159 1160 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu) 1161 { 1162 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1163 return AMD_FAN_CTRL_MANUAL; 1164 else 1165 return AMD_FAN_CTRL_AUTO; 1166 } 1167 1168 static int 1169 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) 1170 { 1171 int ret = 0; 1172 1173 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1174 return 0; 1175 1176 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); 1177 if (ret) 1178 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!", 1179 __func__, (auto_fan_control ? "Start" : "Stop")); 1180 1181 return ret; 1182 } 1183 1184 static int 1185 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) 1186 { 1187 struct amdgpu_device *adev = smu->adev; 1188 1189 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, 1190 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), 1191 CG_FDO_CTRL2, TMIN, 0)); 1192 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, 1193 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), 1194 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1195 1196 return 0; 1197 } 1198 1199 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu, 1200 uint32_t speed) 1201 { 1202 struct amdgpu_device *adev = smu->adev; 1203 uint32_t duty100, duty; 1204 uint64_t tmp64; 1205 1206 speed = MIN(speed, 255); 1207 1208 if (smu_v13_0_auto_fan_control(smu, 0)) 1209 return -EINVAL; 1210 1211 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1), 1212 CG_FDO_CTRL1, FMAX_DUTY100); 1213 if (!duty100) 1214 return -EINVAL; 1215 1216 tmp64 = (uint64_t)speed * duty100; 1217 do_div(tmp64, 255); 1218 duty = (uint32_t)tmp64; 1219 1220 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0, 1221 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0), 1222 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1223 1224 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1225 } 1226 1227 int 1228 smu_v13_0_set_fan_control_mode(struct smu_context *smu, 1229 uint32_t mode) 1230 { 1231 int ret = 0; 1232 1233 switch (mode) { 1234 case AMD_FAN_CTRL_NONE: 1235 ret = smu_v13_0_set_fan_speed_pwm(smu, 255); 1236 break; 1237 case AMD_FAN_CTRL_MANUAL: 1238 ret = smu_v13_0_auto_fan_control(smu, 0); 1239 break; 1240 case AMD_FAN_CTRL_AUTO: 1241 ret = smu_v13_0_auto_fan_control(smu, 1); 1242 break; 1243 default: 1244 break; 1245 } 1246 1247 if (ret) { 1248 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__); 1249 return -EINVAL; 1250 } 1251 1252 return ret; 1253 } 1254 1255 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, 1256 uint32_t speed) 1257 { 1258 struct amdgpu_device *adev = smu->adev; 1259 uint32_t tach_period, crystal_clock_freq; 1260 int ret; 1261 1262 if (!speed) 1263 return -EINVAL; 1264 1265 ret = smu_v13_0_auto_fan_control(smu, 0); 1266 if (ret) 1267 return ret; 1268 1269 crystal_clock_freq = amdgpu_asic_get_xclk(adev); 1270 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1271 WREG32_SOC15(THM, 0, regCG_TACH_CTRL, 1272 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL), 1273 CG_TACH_CTRL, TARGET_PERIOD, 1274 tach_period)); 1275 1276 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1277 } 1278 1279 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, 1280 uint32_t pstate) 1281 { 1282 int ret = 0; 1283 ret = smu_cmn_send_smc_msg_with_param(smu, 1284 SMU_MSG_SetXgmiMode, 1285 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 1286 NULL); 1287 return ret; 1288 } 1289 1290 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev, 1291 struct amdgpu_irq_src *source, 1292 unsigned tyep, 1293 enum amdgpu_interrupt_state state) 1294 { 1295 struct smu_context *smu = adev->powerplay.pp_handle; 1296 uint32_t low, high; 1297 uint32_t val = 0; 1298 1299 switch (state) { 1300 case AMDGPU_IRQ_STATE_DISABLE: 1301 /* For THM irqs */ 1302 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1303 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); 1304 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); 1305 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 1306 1307 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0); 1308 1309 /* For MP1 SW irqs */ 1310 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1311 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 1312 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 1313 1314 break; 1315 case AMDGPU_IRQ_STATE_ENABLE: 1316 /* For THM irqs */ 1317 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 1318 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 1319 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1320 smu->thermal_range.software_shutdown_temp); 1321 1322 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1323 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 1324 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 1325 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 1326 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 1327 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 1328 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 1329 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1330 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 1331 1332 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 1333 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 1334 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 1335 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val); 1336 1337 /* For MP1 SW irqs */ 1338 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); 1339 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 1340 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 1341 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); 1342 1343 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1344 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 1345 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 1346 1347 break; 1348 default: 1349 break; 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu) 1356 { 1357 return smu_cmn_send_smc_msg(smu, 1358 SMU_MSG_ReenableAcDcInterrupt, 1359 NULL); 1360 } 1361 1362 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 1363 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 1364 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 1365 1366 static int smu_v13_0_irq_process(struct amdgpu_device *adev, 1367 struct amdgpu_irq_src *source, 1368 struct amdgpu_iv_entry *entry) 1369 { 1370 struct smu_context *smu = adev->powerplay.pp_handle; 1371 uint32_t client_id = entry->client_id; 1372 uint32_t src_id = entry->src_id; 1373 /* 1374 * ctxid is used to distinguish different 1375 * events for SMCToHost interrupt. 1376 */ 1377 uint32_t ctxid = entry->src_data[0]; 1378 uint32_t data; 1379 1380 if (client_id == SOC15_IH_CLIENTID_THM) { 1381 switch (src_id) { 1382 case THM_11_0__SRCID__THM_DIG_THERM_L2H: 1383 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1384 /* 1385 * SW CTF just occurred. 1386 * Try to do a graceful shutdown to prevent further damage. 1387 */ 1388 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1389 orderly_poweroff(true); 1390 break; 1391 case THM_11_0__SRCID__THM_DIG_THERM_H2L: 1392 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 1393 break; 1394 default: 1395 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 1396 src_id); 1397 break; 1398 } 1399 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { 1400 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); 1401 /* 1402 * HW CTF just occurred. Shutdown to prevent further damage. 1403 */ 1404 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); 1405 orderly_poweroff(true); 1406 } else if (client_id == SOC15_IH_CLIENTID_MP1) { 1407 if (src_id == 0xfe) { 1408 /* ACK SMUToHost interrupt */ 1409 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1410 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); 1411 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); 1412 1413 switch (ctxid) { 1414 case 0x3: 1415 dev_dbg(adev->dev, "Switched to AC mode!\n"); 1416 smu_v13_0_ack_ac_dc_interrupt(smu); 1417 break; 1418 case 0x4: 1419 dev_dbg(adev->dev, "Switched to DC mode!\n"); 1420 smu_v13_0_ack_ac_dc_interrupt(smu); 1421 break; 1422 case 0x7: 1423 /* 1424 * Increment the throttle interrupt counter 1425 */ 1426 atomic64_inc(&smu->throttle_int_counter); 1427 1428 if (!atomic_read(&adev->throttling_logging_enabled)) 1429 return 0; 1430 1431 if (__ratelimit(&adev->throttling_logging_rs)) 1432 schedule_work(&smu->throttling_logging_work); 1433 1434 break; 1435 } 1436 } 1437 } 1438 1439 return 0; 1440 } 1441 1442 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = 1443 { 1444 .set = smu_v13_0_set_irq_state, 1445 .process = smu_v13_0_irq_process, 1446 }; 1447 1448 int smu_v13_0_register_irq_handler(struct smu_context *smu) 1449 { 1450 struct amdgpu_device *adev = smu->adev; 1451 struct amdgpu_irq_src *irq_src = &smu->irq_source; 1452 int ret = 0; 1453 1454 if (amdgpu_sriov_vf(adev)) 1455 return 0; 1456 1457 irq_src->num_types = 1; 1458 irq_src->funcs = &smu_v13_0_irq_funcs; 1459 1460 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1461 THM_11_0__SRCID__THM_DIG_THERM_L2H, 1462 irq_src); 1463 if (ret) 1464 return ret; 1465 1466 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1467 THM_11_0__SRCID__THM_DIG_THERM_H2L, 1468 irq_src); 1469 if (ret) 1470 return ret; 1471 1472 /* Register CTF(GPIO_19) interrupt */ 1473 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, 1474 SMUIO_11_0__SRCID__SMUIO_GPIO19, 1475 irq_src); 1476 if (ret) 1477 return ret; 1478 1479 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 1480 0xfe, 1481 irq_src); 1482 if (ret) 1483 return ret; 1484 1485 return ret; 1486 } 1487 1488 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 1489 struct pp_smu_nv_clock_table *max_clocks) 1490 { 1491 struct smu_table_context *table_context = &smu->smu_table; 1492 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL; 1493 1494 if (!max_clocks || !table_context->max_sustainable_clocks) 1495 return -EINVAL; 1496 1497 sustainable_clocks = table_context->max_sustainable_clocks; 1498 1499 max_clocks->dcfClockInKhz = 1500 (unsigned int) sustainable_clocks->dcef_clock * 1000; 1501 max_clocks->displayClockInKhz = 1502 (unsigned int) sustainable_clocks->display_clock * 1000; 1503 max_clocks->phyClockInKhz = 1504 (unsigned int) sustainable_clocks->phy_clock * 1000; 1505 max_clocks->pixelClockInKhz = 1506 (unsigned int) sustainable_clocks->pixel_clock * 1000; 1507 max_clocks->uClockInKhz = 1508 (unsigned int) sustainable_clocks->uclock * 1000; 1509 max_clocks->socClockInKhz = 1510 (unsigned int) sustainable_clocks->soc_clock * 1000; 1511 max_clocks->dscClockInKhz = 0; 1512 max_clocks->dppClockInKhz = 0; 1513 max_clocks->fabricClockInKhz = 0; 1514 1515 return 0; 1516 } 1517 1518 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu) 1519 { 1520 int ret = 0; 1521 1522 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); 1523 1524 return ret; 1525 } 1526 1527 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu, 1528 uint64_t event_arg) 1529 { 1530 int ret = 0; 1531 1532 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n"); 1533 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL); 1534 1535 return ret; 1536 } 1537 1538 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1539 uint64_t event_arg) 1540 { 1541 int ret = -EINVAL; 1542 1543 switch (event) { 1544 case SMU_EVENT_RESET_COMPLETE: 1545 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg); 1546 break; 1547 default: 1548 break; 1549 } 1550 1551 return ret; 1552 } 1553 1554 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1555 uint32_t *min, uint32_t *max) 1556 { 1557 int ret = 0, clk_id = 0; 1558 uint32_t param = 0; 1559 uint32_t clock_limit; 1560 1561 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 1562 switch (clk_type) { 1563 case SMU_MCLK: 1564 case SMU_UCLK: 1565 clock_limit = smu->smu_table.boot_values.uclk; 1566 break; 1567 case SMU_GFXCLK: 1568 case SMU_SCLK: 1569 clock_limit = smu->smu_table.boot_values.gfxclk; 1570 break; 1571 case SMU_SOCCLK: 1572 clock_limit = smu->smu_table.boot_values.socclk; 1573 break; 1574 default: 1575 clock_limit = 0; 1576 break; 1577 } 1578 1579 /* clock in Mhz unit */ 1580 if (min) 1581 *min = clock_limit / 100; 1582 if (max) 1583 *max = clock_limit / 100; 1584 1585 return 0; 1586 } 1587 1588 clk_id = smu_cmn_to_asic_specific_index(smu, 1589 CMN2ASIC_MAPPING_CLK, 1590 clk_type); 1591 if (clk_id < 0) { 1592 ret = -EINVAL; 1593 goto failed; 1594 } 1595 param = (clk_id & 0xffff) << 16; 1596 1597 if (max) { 1598 if (smu->adev->pm.ac_power) 1599 ret = smu_cmn_send_smc_msg_with_param(smu, 1600 SMU_MSG_GetMaxDpmFreq, 1601 param, 1602 max); 1603 else 1604 ret = smu_cmn_send_smc_msg_with_param(smu, 1605 SMU_MSG_GetDcModeMaxDpmFreq, 1606 param, 1607 max); 1608 if (ret) 1609 goto failed; 1610 } 1611 1612 if (min) { 1613 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 1614 if (ret) 1615 goto failed; 1616 } 1617 1618 failed: 1619 return ret; 1620 } 1621 1622 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, 1623 enum smu_clk_type clk_type, 1624 uint32_t min, 1625 uint32_t max) 1626 { 1627 int ret = 0, clk_id = 0; 1628 uint32_t param; 1629 1630 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1631 return 0; 1632 1633 clk_id = smu_cmn_to_asic_specific_index(smu, 1634 CMN2ASIC_MAPPING_CLK, 1635 clk_type); 1636 if (clk_id < 0) 1637 return clk_id; 1638 1639 if (max > 0) { 1640 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1641 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1642 param, NULL); 1643 if (ret) 1644 goto out; 1645 } 1646 1647 if (min > 0) { 1648 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1649 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1650 param, NULL); 1651 if (ret) 1652 goto out; 1653 } 1654 1655 out: 1656 return ret; 1657 } 1658 1659 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 1660 enum smu_clk_type clk_type, 1661 uint32_t min, 1662 uint32_t max) 1663 { 1664 int ret = 0, clk_id = 0; 1665 uint32_t param; 1666 1667 if (min <= 0 && max <= 0) 1668 return -EINVAL; 1669 1670 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1671 return 0; 1672 1673 clk_id = smu_cmn_to_asic_specific_index(smu, 1674 CMN2ASIC_MAPPING_CLK, 1675 clk_type); 1676 if (clk_id < 0) 1677 return clk_id; 1678 1679 if (max > 0) { 1680 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1681 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1682 param, NULL); 1683 if (ret) 1684 return ret; 1685 } 1686 1687 if (min > 0) { 1688 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1689 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1690 param, NULL); 1691 if (ret) 1692 return ret; 1693 } 1694 1695 return ret; 1696 } 1697 1698 int smu_v13_0_set_performance_level(struct smu_context *smu, 1699 enum amd_dpm_forced_level level) 1700 { 1701 struct smu_13_0_dpm_context *dpm_context = 1702 smu->smu_dpm.dpm_context; 1703 struct smu_13_0_dpm_table *gfx_table = 1704 &dpm_context->dpm_tables.gfx_table; 1705 struct smu_13_0_dpm_table *mem_table = 1706 &dpm_context->dpm_tables.uclk_table; 1707 struct smu_13_0_dpm_table *soc_table = 1708 &dpm_context->dpm_tables.soc_table; 1709 struct smu_13_0_dpm_table *vclk_table = 1710 &dpm_context->dpm_tables.vclk_table; 1711 struct smu_13_0_dpm_table *dclk_table = 1712 &dpm_context->dpm_tables.dclk_table; 1713 struct smu_13_0_dpm_table *fclk_table = 1714 &dpm_context->dpm_tables.fclk_table; 1715 struct smu_umd_pstate_table *pstate_table = 1716 &smu->pstate_table; 1717 struct amdgpu_device *adev = smu->adev; 1718 uint32_t sclk_min = 0, sclk_max = 0; 1719 uint32_t mclk_min = 0, mclk_max = 0; 1720 uint32_t socclk_min = 0, socclk_max = 0; 1721 uint32_t vclk_min = 0, vclk_max = 0; 1722 uint32_t dclk_min = 0, dclk_max = 0; 1723 uint32_t fclk_min = 0, fclk_max = 0; 1724 int ret = 0, i; 1725 1726 switch (level) { 1727 case AMD_DPM_FORCED_LEVEL_HIGH: 1728 sclk_min = sclk_max = gfx_table->max; 1729 mclk_min = mclk_max = mem_table->max; 1730 socclk_min = socclk_max = soc_table->max; 1731 vclk_min = vclk_max = vclk_table->max; 1732 dclk_min = dclk_max = dclk_table->max; 1733 fclk_min = fclk_max = fclk_table->max; 1734 break; 1735 case AMD_DPM_FORCED_LEVEL_LOW: 1736 sclk_min = sclk_max = gfx_table->min; 1737 mclk_min = mclk_max = mem_table->min; 1738 socclk_min = socclk_max = soc_table->min; 1739 vclk_min = vclk_max = vclk_table->min; 1740 dclk_min = dclk_max = dclk_table->min; 1741 fclk_min = fclk_max = fclk_table->min; 1742 break; 1743 case AMD_DPM_FORCED_LEVEL_AUTO: 1744 sclk_min = gfx_table->min; 1745 sclk_max = gfx_table->max; 1746 mclk_min = mem_table->min; 1747 mclk_max = mem_table->max; 1748 socclk_min = soc_table->min; 1749 socclk_max = soc_table->max; 1750 vclk_min = vclk_table->min; 1751 vclk_max = vclk_table->max; 1752 dclk_min = dclk_table->min; 1753 dclk_max = dclk_table->max; 1754 fclk_min = fclk_table->min; 1755 fclk_max = fclk_table->max; 1756 break; 1757 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1758 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1759 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1760 socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1761 vclk_min = vclk_max = pstate_table->vclk_pstate.standard; 1762 dclk_min = dclk_max = pstate_table->dclk_pstate.standard; 1763 fclk_min = fclk_max = pstate_table->fclk_pstate.standard; 1764 break; 1765 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1766 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1767 break; 1768 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1769 mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1770 break; 1771 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1772 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1773 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1774 socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1775 vclk_min = vclk_max = pstate_table->vclk_pstate.peak; 1776 dclk_min = dclk_max = pstate_table->dclk_pstate.peak; 1777 fclk_min = fclk_max = pstate_table->fclk_pstate.peak; 1778 break; 1779 case AMD_DPM_FORCED_LEVEL_MANUAL: 1780 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1781 return 0; 1782 default: 1783 dev_err(adev->dev, "Invalid performance level %d\n", level); 1784 return -EINVAL; 1785 } 1786 1787 /* 1788 * Unset those settings for SMU 13.0.2. As soft limits settings 1789 * for those clock domains are not supported. 1790 */ 1791 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) { 1792 mclk_min = mclk_max = 0; 1793 socclk_min = socclk_max = 0; 1794 vclk_min = vclk_max = 0; 1795 dclk_min = dclk_max = 0; 1796 fclk_min = fclk_max = 0; 1797 } 1798 1799 if (sclk_min && sclk_max) { 1800 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1801 SMU_GFXCLK, 1802 sclk_min, 1803 sclk_max); 1804 if (ret) 1805 return ret; 1806 1807 pstate_table->gfxclk_pstate.curr.min = sclk_min; 1808 pstate_table->gfxclk_pstate.curr.max = sclk_max; 1809 } 1810 1811 if (mclk_min && mclk_max) { 1812 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1813 SMU_MCLK, 1814 mclk_min, 1815 mclk_max); 1816 if (ret) 1817 return ret; 1818 1819 pstate_table->uclk_pstate.curr.min = mclk_min; 1820 pstate_table->uclk_pstate.curr.max = mclk_max; 1821 } 1822 1823 if (socclk_min && socclk_max) { 1824 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1825 SMU_SOCCLK, 1826 socclk_min, 1827 socclk_max); 1828 if (ret) 1829 return ret; 1830 1831 pstate_table->socclk_pstate.curr.min = socclk_min; 1832 pstate_table->socclk_pstate.curr.max = socclk_max; 1833 } 1834 1835 if (vclk_min && vclk_max) { 1836 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1837 if (adev->vcn.harvest_config & (1 << i)) 1838 continue; 1839 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1840 i ? SMU_VCLK1 : SMU_VCLK, 1841 vclk_min, 1842 vclk_max); 1843 if (ret) 1844 return ret; 1845 } 1846 pstate_table->vclk_pstate.curr.min = vclk_min; 1847 pstate_table->vclk_pstate.curr.max = vclk_max; 1848 } 1849 1850 if (dclk_min && dclk_max) { 1851 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1852 if (adev->vcn.harvest_config & (1 << i)) 1853 continue; 1854 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1855 i ? SMU_DCLK1 : SMU_DCLK, 1856 dclk_min, 1857 dclk_max); 1858 if (ret) 1859 return ret; 1860 } 1861 pstate_table->dclk_pstate.curr.min = dclk_min; 1862 pstate_table->dclk_pstate.curr.max = dclk_max; 1863 } 1864 1865 if (fclk_min && fclk_max) { 1866 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1867 SMU_FCLK, 1868 fclk_min, 1869 fclk_max); 1870 if (ret) 1871 return ret; 1872 1873 pstate_table->fclk_pstate.curr.min = fclk_min; 1874 pstate_table->fclk_pstate.curr.max = fclk_max; 1875 } 1876 1877 return ret; 1878 } 1879 1880 int smu_v13_0_set_power_source(struct smu_context *smu, 1881 enum smu_power_src_type power_src) 1882 { 1883 int pwr_source; 1884 1885 pwr_source = smu_cmn_to_asic_specific_index(smu, 1886 CMN2ASIC_MAPPING_PWR, 1887 (uint32_t)power_src); 1888 if (pwr_source < 0) 1889 return -EINVAL; 1890 1891 return smu_cmn_send_smc_msg_with_param(smu, 1892 SMU_MSG_NotifyPowerSource, 1893 pwr_source, 1894 NULL); 1895 } 1896 1897 static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu, 1898 enum smu_clk_type clk_type, 1899 uint16_t level, 1900 uint32_t *value) 1901 { 1902 int ret = 0, clk_id = 0; 1903 uint32_t param; 1904 1905 if (!value) 1906 return -EINVAL; 1907 1908 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1909 return 0; 1910 1911 clk_id = smu_cmn_to_asic_specific_index(smu, 1912 CMN2ASIC_MAPPING_CLK, 1913 clk_type); 1914 if (clk_id < 0) 1915 return clk_id; 1916 1917 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1918 1919 ret = smu_cmn_send_smc_msg_with_param(smu, 1920 SMU_MSG_GetDpmFreqByIndex, 1921 param, 1922 value); 1923 if (ret) 1924 return ret; 1925 1926 *value = *value & 0x7fffffff; 1927 1928 return ret; 1929 } 1930 1931 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu, 1932 enum smu_clk_type clk_type, 1933 uint32_t *value) 1934 { 1935 int ret; 1936 1937 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value); 1938 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */ 1939 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value)) 1940 ++(*value); 1941 1942 return ret; 1943 } 1944 1945 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu, 1946 enum smu_clk_type clk_type, 1947 bool *is_fine_grained_dpm) 1948 { 1949 int ret = 0, clk_id = 0; 1950 uint32_t param; 1951 uint32_t value; 1952 1953 if (!is_fine_grained_dpm) 1954 return -EINVAL; 1955 1956 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1957 return 0; 1958 1959 clk_id = smu_cmn_to_asic_specific_index(smu, 1960 CMN2ASIC_MAPPING_CLK, 1961 clk_type); 1962 if (clk_id < 0) 1963 return clk_id; 1964 1965 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff); 1966 1967 ret = smu_cmn_send_smc_msg_with_param(smu, 1968 SMU_MSG_GetDpmFreqByIndex, 1969 param, 1970 &value); 1971 if (ret) 1972 return ret; 1973 1974 /* 1975 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM 1976 * now, we un-support it 1977 */ 1978 *is_fine_grained_dpm = value & 0x80000000; 1979 1980 return 0; 1981 } 1982 1983 int smu_v13_0_set_single_dpm_table(struct smu_context *smu, 1984 enum smu_clk_type clk_type, 1985 struct smu_13_0_dpm_table *single_dpm_table) 1986 { 1987 int ret = 0; 1988 uint32_t clk; 1989 int i; 1990 1991 ret = smu_v13_0_get_dpm_level_count(smu, 1992 clk_type, 1993 &single_dpm_table->count); 1994 if (ret) { 1995 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 1996 return ret; 1997 } 1998 1999 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) { 2000 ret = smu_v13_0_get_fine_grained_status(smu, 2001 clk_type, 2002 &single_dpm_table->is_fine_grained); 2003 if (ret) { 2004 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); 2005 return ret; 2006 } 2007 } 2008 2009 for (i = 0; i < single_dpm_table->count; i++) { 2010 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2011 clk_type, 2012 i, 2013 &clk); 2014 if (ret) { 2015 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 2016 return ret; 2017 } 2018 2019 single_dpm_table->dpm_levels[i].value = clk; 2020 single_dpm_table->dpm_levels[i].enabled = true; 2021 2022 if (i == 0) 2023 single_dpm_table->min = clk; 2024 else if (i == single_dpm_table->count - 1) 2025 single_dpm_table->max = clk; 2026 } 2027 2028 return 0; 2029 } 2030 2031 int smu_v13_0_get_dpm_level_range(struct smu_context *smu, 2032 enum smu_clk_type clk_type, 2033 uint32_t *min_value, 2034 uint32_t *max_value) 2035 { 2036 uint32_t level_count = 0; 2037 int ret = 0; 2038 2039 if (!min_value && !max_value) 2040 return -EINVAL; 2041 2042 if (min_value) { 2043 /* by default, level 0 clock value as min value */ 2044 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2045 clk_type, 2046 0, 2047 min_value); 2048 if (ret) 2049 return ret; 2050 } 2051 2052 if (max_value) { 2053 ret = smu_v13_0_get_dpm_level_count(smu, 2054 clk_type, 2055 &level_count); 2056 if (ret) 2057 return ret; 2058 2059 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2060 clk_type, 2061 level_count - 1, 2062 max_value); 2063 if (ret) 2064 return ret; 2065 } 2066 2067 return ret; 2068 } 2069 2070 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu) 2071 { 2072 struct amdgpu_device *adev = smu->adev; 2073 2074 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2075 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2076 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2077 } 2078 2079 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu) 2080 { 2081 uint32_t width_level; 2082 2083 width_level = smu_v13_0_get_current_pcie_link_width_level(smu); 2084 if (width_level > LINK_WIDTH_MAX) 2085 width_level = 0; 2086 2087 return link_width[width_level]; 2088 } 2089 2090 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu) 2091 { 2092 struct amdgpu_device *adev = smu->adev; 2093 2094 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2095 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2096 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2097 } 2098 2099 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu) 2100 { 2101 uint32_t speed_level; 2102 2103 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu); 2104 if (speed_level > LINK_SPEED_MAX) 2105 speed_level = 0; 2106 2107 return link_speed[speed_level]; 2108 } 2109 2110 int smu_v13_0_set_vcn_enable(struct smu_context *smu, 2111 bool enable) 2112 { 2113 struct amdgpu_device *adev = smu->adev; 2114 int i, ret = 0; 2115 2116 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2117 if (adev->vcn.harvest_config & (1 << i)) 2118 continue; 2119 2120 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 2121 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 2122 i << 16U, NULL); 2123 if (ret) 2124 return ret; 2125 } 2126 2127 return ret; 2128 } 2129 2130 int smu_v13_0_set_jpeg_enable(struct smu_context *smu, 2131 bool enable) 2132 { 2133 return smu_cmn_send_smc_msg_with_param(smu, enable ? 2134 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, 2135 0, NULL); 2136 } 2137 2138 int smu_v13_0_run_btc(struct smu_context *smu) 2139 { 2140 int res; 2141 2142 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2143 if (res) 2144 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 2145 2146 return res; 2147 } 2148 2149 int smu_v13_0_deep_sleep_control(struct smu_context *smu, 2150 bool enablement) 2151 { 2152 struct amdgpu_device *adev = smu->adev; 2153 int ret = 0; 2154 2155 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 2156 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 2157 if (ret) { 2158 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 2159 return ret; 2160 } 2161 } 2162 2163 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 2164 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 2165 if (ret) { 2166 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 2167 return ret; 2168 } 2169 } 2170 2171 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 2172 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 2173 if (ret) { 2174 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 2175 return ret; 2176 } 2177 } 2178 2179 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 2180 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 2181 if (ret) { 2182 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 2183 return ret; 2184 } 2185 } 2186 2187 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 2188 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 2189 if (ret) { 2190 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 2191 return ret; 2192 } 2193 } 2194 2195 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) { 2196 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement); 2197 if (ret) { 2198 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable"); 2199 return ret; 2200 } 2201 } 2202 2203 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) { 2204 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement); 2205 if (ret) { 2206 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable"); 2207 return ret; 2208 } 2209 } 2210 2211 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) { 2212 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement); 2213 if (ret) { 2214 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable"); 2215 return ret; 2216 } 2217 } 2218 2219 return ret; 2220 } 2221 2222 int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 2223 bool enablement) 2224 { 2225 int ret = 0; 2226 2227 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 2228 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 2229 2230 return ret; 2231 } 2232 2233 bool smu_v13_0_baco_is_support(struct smu_context *smu) 2234 { 2235 struct smu_baco_context *smu_baco = &smu->smu_baco; 2236 2237 if (amdgpu_sriov_vf(smu->adev) || 2238 !smu_baco->platform_support) 2239 return false; 2240 2241 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 2242 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 2243 return false; 2244 2245 return true; 2246 } 2247 2248 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu) 2249 { 2250 struct smu_baco_context *smu_baco = &smu->smu_baco; 2251 2252 return smu_baco->state; 2253 } 2254 2255 int smu_v13_0_baco_set_state(struct smu_context *smu, 2256 enum smu_baco_state state) 2257 { 2258 struct smu_baco_context *smu_baco = &smu->smu_baco; 2259 struct amdgpu_device *adev = smu->adev; 2260 int ret = 0; 2261 2262 if (smu_v13_0_baco_get_state(smu) == state) 2263 return 0; 2264 2265 if (state == SMU_BACO_STATE_ENTER) { 2266 ret = smu_cmn_send_smc_msg_with_param(smu, 2267 SMU_MSG_EnterBaco, 2268 smu_baco->maco_support ? 2269 BACO_SEQ_BAMACO : BACO_SEQ_BACO, 2270 NULL); 2271 } else { 2272 ret = smu_cmn_send_smc_msg(smu, 2273 SMU_MSG_ExitBaco, 2274 NULL); 2275 if (ret) 2276 return ret; 2277 2278 /* clear vbios scratch 6 and 7 for coming asic reinit */ 2279 WREG32(adev->bios_scratch_reg_offset + 6, 0); 2280 WREG32(adev->bios_scratch_reg_offset + 7, 0); 2281 } 2282 2283 if (!ret) 2284 smu_baco->state = state; 2285 2286 return ret; 2287 } 2288 2289 int smu_v13_0_baco_enter(struct smu_context *smu) 2290 { 2291 int ret = 0; 2292 2293 ret = smu_v13_0_baco_set_state(smu, 2294 SMU_BACO_STATE_ENTER); 2295 if (ret) 2296 return ret; 2297 2298 msleep(10); 2299 2300 return ret; 2301 } 2302 2303 int smu_v13_0_baco_exit(struct smu_context *smu) 2304 { 2305 return smu_v13_0_baco_set_state(smu, 2306 SMU_BACO_STATE_EXIT); 2307 } 2308 2309 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu) 2310 { 2311 uint16_t index; 2312 2313 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2314 SMU_MSG_EnableGfxImu); 2315 /* Param 1 to tell PMFW to enable GFXOFF feature */ 2316 return smu_cmn_send_msg_without_waiting(smu, index, 1); 2317 } 2318 2319 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, 2320 enum PP_OD_DPM_TABLE_COMMAND type, 2321 long input[], uint32_t size) 2322 { 2323 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 2324 int ret = 0; 2325 2326 /* Only allowed in manual mode */ 2327 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 2328 return -EINVAL; 2329 2330 switch (type) { 2331 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2332 if (size != 2) { 2333 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2334 return -EINVAL; 2335 } 2336 2337 if (input[0] == 0) { 2338 if (input[1] < smu->gfx_default_hard_min_freq) { 2339 dev_warn(smu->adev->dev, 2340 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2341 input[1], smu->gfx_default_hard_min_freq); 2342 return -EINVAL; 2343 } 2344 smu->gfx_actual_hard_min_freq = input[1]; 2345 } else if (input[0] == 1) { 2346 if (input[1] > smu->gfx_default_soft_max_freq) { 2347 dev_warn(smu->adev->dev, 2348 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2349 input[1], smu->gfx_default_soft_max_freq); 2350 return -EINVAL; 2351 } 2352 smu->gfx_actual_soft_max_freq = input[1]; 2353 } else { 2354 return -EINVAL; 2355 } 2356 break; 2357 case PP_OD_RESTORE_DEFAULT_TABLE: 2358 if (size != 0) { 2359 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2360 return -EINVAL; 2361 } 2362 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 2363 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 2364 break; 2365 case PP_OD_COMMIT_DPM_TABLE: 2366 if (size != 0) { 2367 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2368 return -EINVAL; 2369 } 2370 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 2371 dev_err(smu->adev->dev, 2372 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 2373 smu->gfx_actual_hard_min_freq, 2374 smu->gfx_actual_soft_max_freq); 2375 return -EINVAL; 2376 } 2377 2378 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 2379 smu->gfx_actual_hard_min_freq, 2380 NULL); 2381 if (ret) { 2382 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 2383 return ret; 2384 } 2385 2386 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 2387 smu->gfx_actual_soft_max_freq, 2388 NULL); 2389 if (ret) { 2390 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 2391 return ret; 2392 } 2393 break; 2394 default: 2395 return -ENOSYS; 2396 } 2397 2398 return ret; 2399 } 2400 2401 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu) 2402 { 2403 struct smu_table_context *smu_table = &smu->smu_table; 2404 2405 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, 2406 smu_table->clocks_table, false); 2407 } 2408 2409 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu) 2410 { 2411 struct amdgpu_device *adev = smu->adev; 2412 2413 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2414 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2415 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2416 } 2417 2418 int smu_v13_0_mode1_reset(struct smu_context *smu) 2419 { 2420 int ret = 0; 2421 2422 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 2423 if (!ret) 2424 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 2425 2426 return ret; 2427 } 2428