1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/reboot.h> 27 28 #define SMU_13_0_PARTIAL_PPTABLE 29 #define SWSMU_CODE_LAYER_L3 30 31 #include "amdgpu.h" 32 #include "amdgpu_smu.h" 33 #include "atomfirmware.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_atombios.h" 36 #include "smu_v13_0.h" 37 #include "soc15_common.h" 38 #include "atom.h" 39 #include "amdgpu_ras.h" 40 #include "smu_cmn.h" 41 42 #include "asic_reg/thm/thm_13_0_2_offset.h" 43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h" 44 #include "asic_reg/mp/mp_13_0_2_offset.h" 45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h" 46 #include "asic_reg/smuio/smuio_13_0_2_offset.h" 47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h" 48 49 /* 50 * DO NOT use these for err/warn/info/debug messages. 51 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52 * They are more MGPU friendly. 53 */ 54 #undef pr_err 55 #undef pr_warn 56 #undef pr_info 57 #undef pr_debug 58 59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin"); 60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin"); 61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin"); 62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin"); 63 64 #define mmMP1_SMN_C2PMSG_66 0x0282 65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 66 67 #define mmMP1_SMN_C2PMSG_82 0x0292 68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 69 70 #define mmMP1_SMN_C2PMSG_90 0x029a 71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 72 73 #define SMU13_VOLTAGE_SCALE 4 74 75 #define LINK_WIDTH_MAX 6 76 #define LINK_SPEED_MAX 3 77 78 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L 80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 81 #define smnPCIE_LC_SPEED_CNTL 0x11140290 82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE 84 85 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 86 static const int link_speed[] = {25, 50, 80, 160}; 87 88 int smu_v13_0_init_microcode(struct smu_context *smu) 89 { 90 struct amdgpu_device *adev = smu->adev; 91 const char *chip_name; 92 char fw_name[30]; 93 char ucode_prefix[30]; 94 int err = 0; 95 const struct smc_firmware_header_v1_0 *hdr; 96 const struct common_firmware_header *header; 97 struct amdgpu_firmware_info *ucode = NULL; 98 99 /* doesn't need to load smu firmware in IOV mode */ 100 if (amdgpu_sriov_vf(adev)) 101 return 0; 102 103 switch (adev->ip_versions[MP1_HWIP][0]) { 104 case IP_VERSION(13, 0, 2): 105 chip_name = "aldebaran_smc"; 106 break; 107 default: 108 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); 109 chip_name = ucode_prefix; 110 } 111 112 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); 113 114 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 115 if (err) 116 goto out; 117 err = amdgpu_ucode_validate(adev->pm.fw); 118 if (err) 119 goto out; 120 121 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 122 amdgpu_ucode_print_smc_hdr(&hdr->header); 123 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 124 125 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 126 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 127 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 128 ucode->fw = adev->pm.fw; 129 header = (const struct common_firmware_header *)ucode->fw->data; 130 adev->firmware.fw_size += 131 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 132 } 133 134 out: 135 if (err) { 136 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n", 137 fw_name); 138 release_firmware(adev->pm.fw); 139 adev->pm.fw = NULL; 140 } 141 return err; 142 } 143 144 void smu_v13_0_fini_microcode(struct smu_context *smu) 145 { 146 struct amdgpu_device *adev = smu->adev; 147 148 release_firmware(adev->pm.fw); 149 adev->pm.fw = NULL; 150 adev->pm.fw_version = 0; 151 } 152 153 int smu_v13_0_load_microcode(struct smu_context *smu) 154 { 155 #if 0 156 struct amdgpu_device *adev = smu->adev; 157 const uint32_t *src; 158 const struct smc_firmware_header_v1_0 *hdr; 159 uint32_t addr_start = MP1_SRAM; 160 uint32_t i; 161 uint32_t smc_fw_size; 162 uint32_t mp1_fw_flags; 163 164 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 165 src = (const uint32_t *)(adev->pm.fw->data + 166 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 167 smc_fw_size = hdr->header.ucode_size_bytes; 168 169 for (i = 1; i < smc_fw_size/4 - 1; i++) { 170 WREG32_PCIE(addr_start, src[i]); 171 addr_start += 4; 172 } 173 174 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 175 1 & MP1_SMN_PUB_CTRL__RESET_MASK); 176 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 177 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); 178 179 for (i = 0; i < adev->usec_timeout; i++) { 180 mp1_fw_flags = RREG32_PCIE(MP1_Public | 181 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 182 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 183 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 184 break; 185 udelay(1); 186 } 187 188 if (i == adev->usec_timeout) 189 return -ETIME; 190 #endif 191 192 return 0; 193 } 194 195 int smu_v13_0_init_pptable_microcode(struct smu_context *smu) 196 { 197 struct amdgpu_device *adev = smu->adev; 198 struct amdgpu_firmware_info *ucode = NULL; 199 uint32_t size = 0, pptable_id = 0; 200 int ret = 0; 201 void *table; 202 203 /* doesn't need to load smu firmware in IOV mode */ 204 if (amdgpu_sriov_vf(adev)) 205 return 0; 206 207 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 208 return 0; 209 210 if (!adev->scpm_enabled) 211 return 0; 212 213 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) || 214 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) || 215 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))) 216 return 0; 217 218 /* override pptable_id from driver parameter */ 219 if (amdgpu_smu_pptable_id >= 0) { 220 pptable_id = amdgpu_smu_pptable_id; 221 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 222 } else { 223 pptable_id = smu->smu_table.boot_values.pp_table_id; 224 } 225 226 /* "pptable_id == 0" means vbios carries the pptable. */ 227 if (!pptable_id) 228 return 0; 229 230 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 231 if (ret) 232 return ret; 233 234 smu->pptable_firmware.data = table; 235 smu->pptable_firmware.size = size; 236 237 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE]; 238 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE; 239 ucode->fw = &smu->pptable_firmware; 240 adev->firmware.fw_size += 241 ALIGN(smu->pptable_firmware.size, PAGE_SIZE); 242 243 return 0; 244 } 245 246 int smu_v13_0_check_fw_status(struct smu_context *smu) 247 { 248 struct amdgpu_device *adev = smu->adev; 249 uint32_t mp1_fw_flags; 250 251 switch (adev->ip_versions[MP1_HWIP][0]) { 252 case IP_VERSION(13, 0, 4): 253 case IP_VERSION(13, 0, 11): 254 mp1_fw_flags = RREG32_PCIE(MP1_Public | 255 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff)); 256 break; 257 default: 258 mp1_fw_flags = RREG32_PCIE(MP1_Public | 259 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 260 break; 261 } 262 263 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 264 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 265 return 0; 266 267 return -EIO; 268 } 269 270 int smu_v13_0_check_fw_version(struct smu_context *smu) 271 { 272 struct amdgpu_device *adev = smu->adev; 273 uint32_t if_version = 0xff, smu_version = 0xff; 274 uint8_t smu_program, smu_major, smu_minor, smu_debug; 275 int ret = 0; 276 277 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 278 if (ret) 279 return ret; 280 281 smu_program = (smu_version >> 24) & 0xff; 282 smu_major = (smu_version >> 16) & 0xff; 283 smu_minor = (smu_version >> 8) & 0xff; 284 smu_debug = (smu_version >> 0) & 0xff; 285 if (smu->is_apu) 286 adev->pm.fw_version = smu_version; 287 288 switch (adev->ip_versions[MP1_HWIP][0]) { 289 case IP_VERSION(13, 0, 2): 290 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; 291 break; 292 case IP_VERSION(13, 0, 0): 293 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0; 294 break; 295 case IP_VERSION(13, 0, 10): 296 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10; 297 break; 298 case IP_VERSION(13, 0, 7): 299 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7; 300 break; 301 case IP_VERSION(13, 0, 1): 302 case IP_VERSION(13, 0, 3): 303 case IP_VERSION(13, 0, 8): 304 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP; 305 break; 306 case IP_VERSION(13, 0, 4): 307 case IP_VERSION(13, 0, 11): 308 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4; 309 break; 310 case IP_VERSION(13, 0, 5): 311 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5; 312 break; 313 default: 314 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n", 315 adev->ip_versions[MP1_HWIP][0]); 316 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV; 317 break; 318 } 319 320 /* only for dGPU w/ SMU13*/ 321 if (adev->pm.fw) 322 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n", 323 smu_program, smu_version, smu_major, smu_minor, smu_debug); 324 325 /* 326 * 1. if_version mismatch is not critical as our fw is designed 327 * to be backward compatible. 328 * 2. New fw usually brings some optimizations. But that's visible 329 * only on the paired driver. 330 * Considering above, we just leave user a warning message instead 331 * of halt driver loading. 332 */ 333 if (if_version != smu->smc_driver_if_version) { 334 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " 335 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", 336 smu->smc_driver_if_version, if_version, 337 smu_program, smu_version, smu_major, smu_minor, smu_debug); 338 dev_warn(adev->dev, "SMU driver if version not matched\n"); 339 } 340 341 return ret; 342 } 343 344 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 345 { 346 struct amdgpu_device *adev = smu->adev; 347 uint32_t ppt_offset_bytes; 348 const struct smc_firmware_header_v2_0 *v2; 349 350 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 351 352 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 353 *size = le32_to_cpu(v2->ppt_size_bytes); 354 *table = (uint8_t *)v2 + ppt_offset_bytes; 355 356 return 0; 357 } 358 359 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table, 360 uint32_t *size, uint32_t pptable_id) 361 { 362 struct amdgpu_device *adev = smu->adev; 363 const struct smc_firmware_header_v2_1 *v2_1; 364 struct smc_soft_pptable_entry *entries; 365 uint32_t pptable_count = 0; 366 int i = 0; 367 368 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 369 entries = (struct smc_soft_pptable_entry *) 370 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 371 pptable_count = le32_to_cpu(v2_1->pptable_count); 372 for (i = 0; i < pptable_count; i++) { 373 if (le32_to_cpu(entries[i].id) == pptable_id) { 374 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 375 *size = le32_to_cpu(entries[i].ppt_size_bytes); 376 break; 377 } 378 } 379 380 if (i == pptable_count) 381 return -EINVAL; 382 383 return 0; 384 } 385 386 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size) 387 { 388 struct amdgpu_device *adev = smu->adev; 389 uint16_t atom_table_size; 390 uint8_t frev, crev; 391 int ret, index; 392 393 dev_info(adev->dev, "use vbios provided pptable\n"); 394 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 395 powerplayinfo); 396 397 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 398 (uint8_t **)table); 399 if (ret) 400 return ret; 401 402 if (size) 403 *size = atom_table_size; 404 405 return 0; 406 } 407 408 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, 409 void **table, 410 uint32_t *size, 411 uint32_t pptable_id) 412 { 413 const struct smc_firmware_header_v1_0 *hdr; 414 struct amdgpu_device *adev = smu->adev; 415 uint16_t version_major, version_minor; 416 int ret; 417 418 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 419 if (!hdr) 420 return -EINVAL; 421 422 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id); 423 424 version_major = le16_to_cpu(hdr->header.header_version_major); 425 version_minor = le16_to_cpu(hdr->header.header_version_minor); 426 if (version_major != 2) { 427 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n", 428 version_major, version_minor); 429 return -EINVAL; 430 } 431 432 switch (version_minor) { 433 case 0: 434 ret = smu_v13_0_set_pptable_v2_0(smu, table, size); 435 break; 436 case 1: 437 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id); 438 break; 439 default: 440 ret = -EINVAL; 441 break; 442 } 443 444 return ret; 445 } 446 447 int smu_v13_0_setup_pptable(struct smu_context *smu) 448 { 449 struct amdgpu_device *adev = smu->adev; 450 uint32_t size = 0, pptable_id = 0; 451 void *table; 452 int ret = 0; 453 454 /* override pptable_id from driver parameter */ 455 if (amdgpu_smu_pptable_id >= 0) { 456 pptable_id = amdgpu_smu_pptable_id; 457 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 458 } else { 459 pptable_id = smu->smu_table.boot_values.pp_table_id; 460 } 461 462 /* force using vbios pptable in sriov mode */ 463 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1)) 464 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size); 465 else 466 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 467 468 if (ret) 469 return ret; 470 471 if (!smu->smu_table.power_play_table) 472 smu->smu_table.power_play_table = table; 473 if (!smu->smu_table.power_play_table_size) 474 smu->smu_table.power_play_table_size = size; 475 476 return 0; 477 } 478 479 int smu_v13_0_init_smc_tables(struct smu_context *smu) 480 { 481 struct smu_table_context *smu_table = &smu->smu_table; 482 struct smu_table *tables = smu_table->tables; 483 int ret = 0; 484 485 smu_table->driver_pptable = 486 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 487 if (!smu_table->driver_pptable) { 488 ret = -ENOMEM; 489 goto err0_out; 490 } 491 492 smu_table->max_sustainable_clocks = 493 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL); 494 if (!smu_table->max_sustainable_clocks) { 495 ret = -ENOMEM; 496 goto err1_out; 497 } 498 499 /* Aldebaran does not support OVERDRIVE */ 500 if (tables[SMU_TABLE_OVERDRIVE].size) { 501 smu_table->overdrive_table = 502 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 503 if (!smu_table->overdrive_table) { 504 ret = -ENOMEM; 505 goto err2_out; 506 } 507 508 smu_table->boot_overdrive_table = 509 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 510 if (!smu_table->boot_overdrive_table) { 511 ret = -ENOMEM; 512 goto err3_out; 513 } 514 } 515 516 smu_table->combo_pptable = 517 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL); 518 if (!smu_table->combo_pptable) { 519 ret = -ENOMEM; 520 goto err4_out; 521 } 522 523 return 0; 524 525 err4_out: 526 kfree(smu_table->boot_overdrive_table); 527 err3_out: 528 kfree(smu_table->overdrive_table); 529 err2_out: 530 kfree(smu_table->max_sustainable_clocks); 531 err1_out: 532 kfree(smu_table->driver_pptable); 533 err0_out: 534 return ret; 535 } 536 537 int smu_v13_0_fini_smc_tables(struct smu_context *smu) 538 { 539 struct smu_table_context *smu_table = &smu->smu_table; 540 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 541 542 kfree(smu_table->gpu_metrics_table); 543 kfree(smu_table->combo_pptable); 544 kfree(smu_table->boot_overdrive_table); 545 kfree(smu_table->overdrive_table); 546 kfree(smu_table->max_sustainable_clocks); 547 kfree(smu_table->driver_pptable); 548 smu_table->gpu_metrics_table = NULL; 549 smu_table->combo_pptable = NULL; 550 smu_table->boot_overdrive_table = NULL; 551 smu_table->overdrive_table = NULL; 552 smu_table->max_sustainable_clocks = NULL; 553 smu_table->driver_pptable = NULL; 554 kfree(smu_table->hardcode_pptable); 555 smu_table->hardcode_pptable = NULL; 556 557 kfree(smu_table->ecc_table); 558 kfree(smu_table->metrics_table); 559 kfree(smu_table->watermarks_table); 560 smu_table->ecc_table = NULL; 561 smu_table->metrics_table = NULL; 562 smu_table->watermarks_table = NULL; 563 smu_table->metrics_time = 0; 564 565 kfree(smu_dpm->dpm_context); 566 kfree(smu_dpm->golden_dpm_context); 567 kfree(smu_dpm->dpm_current_power_state); 568 kfree(smu_dpm->dpm_request_power_state); 569 smu_dpm->dpm_context = NULL; 570 smu_dpm->golden_dpm_context = NULL; 571 smu_dpm->dpm_context_size = 0; 572 smu_dpm->dpm_current_power_state = NULL; 573 smu_dpm->dpm_request_power_state = NULL; 574 575 return 0; 576 } 577 578 int smu_v13_0_init_power(struct smu_context *smu) 579 { 580 struct smu_power_context *smu_power = &smu->smu_power; 581 582 if (smu_power->power_context || smu_power->power_context_size != 0) 583 return -EINVAL; 584 585 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 586 GFP_KERNEL); 587 if (!smu_power->power_context) 588 return -ENOMEM; 589 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context); 590 591 return 0; 592 } 593 594 int smu_v13_0_fini_power(struct smu_context *smu) 595 { 596 struct smu_power_context *smu_power = &smu->smu_power; 597 598 if (!smu_power->power_context || smu_power->power_context_size == 0) 599 return -EINVAL; 600 601 kfree(smu_power->power_context); 602 smu_power->power_context = NULL; 603 smu_power->power_context_size = 0; 604 605 return 0; 606 } 607 608 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu) 609 { 610 int ret, index; 611 uint16_t size; 612 uint8_t frev, crev; 613 struct atom_common_table_header *header; 614 struct atom_firmware_info_v3_4 *v_3_4; 615 struct atom_firmware_info_v3_3 *v_3_3; 616 struct atom_firmware_info_v3_1 *v_3_1; 617 struct atom_smu_info_v3_6 *smu_info_v3_6; 618 struct atom_smu_info_v4_0 *smu_info_v4_0; 619 620 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 621 firmwareinfo); 622 623 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 624 (uint8_t **)&header); 625 if (ret) 626 return ret; 627 628 if (header->format_revision != 3) { 629 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n"); 630 return -EINVAL; 631 } 632 633 switch (header->content_revision) { 634 case 0: 635 case 1: 636 case 2: 637 v_3_1 = (struct atom_firmware_info_v3_1 *)header; 638 smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 639 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 640 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 641 smu->smu_table.boot_values.socclk = 0; 642 smu->smu_table.boot_values.dcefclk = 0; 643 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 644 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 645 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 646 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 647 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 648 smu->smu_table.boot_values.pp_table_id = 0; 649 break; 650 case 3: 651 v_3_3 = (struct atom_firmware_info_v3_3 *)header; 652 smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 653 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 654 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 655 smu->smu_table.boot_values.socclk = 0; 656 smu->smu_table.boot_values.dcefclk = 0; 657 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 658 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 659 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 660 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 661 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 662 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 663 break; 664 case 4: 665 default: 666 v_3_4 = (struct atom_firmware_info_v3_4 *)header; 667 smu->smu_table.boot_values.revision = v_3_4->firmware_revision; 668 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; 669 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; 670 smu->smu_table.boot_values.socclk = 0; 671 smu->smu_table.boot_values.dcefclk = 0; 672 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; 673 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; 674 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; 675 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; 676 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; 677 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id; 678 break; 679 } 680 681 smu->smu_table.boot_values.format_revision = header->format_revision; 682 smu->smu_table.boot_values.content_revision = header->content_revision; 683 684 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 685 smu_info); 686 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 687 (uint8_t **)&header)) { 688 689 if ((frev == 3) && (crev == 6)) { 690 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header; 691 692 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; 693 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz; 694 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz; 695 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; 696 } else if ((frev == 3) && (crev == 1)) { 697 return 0; 698 } else if ((frev == 4) && (crev == 0)) { 699 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header; 700 701 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; 702 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; 703 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz; 704 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz; 705 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz; 706 } else { 707 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n", 708 (uint32_t)frev, (uint32_t)crev); 709 } 710 } 711 712 return 0; 713 } 714 715 716 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu) 717 { 718 struct smu_table_context *smu_table = &smu->smu_table; 719 struct smu_table *memory_pool = &smu_table->memory_pool; 720 int ret = 0; 721 uint64_t address; 722 uint32_t address_low, address_high; 723 724 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 725 return ret; 726 727 address = memory_pool->mc_address; 728 address_high = (uint32_t)upper_32_bits(address); 729 address_low = (uint32_t)lower_32_bits(address); 730 731 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 732 address_high, NULL); 733 if (ret) 734 return ret; 735 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 736 address_low, NULL); 737 if (ret) 738 return ret; 739 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 740 (uint32_t)memory_pool->size, NULL); 741 if (ret) 742 return ret; 743 744 return ret; 745 } 746 747 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 748 { 749 int ret; 750 751 ret = smu_cmn_send_smc_msg_with_param(smu, 752 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); 753 if (ret) 754 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!"); 755 756 return ret; 757 } 758 759 int smu_v13_0_set_driver_table_location(struct smu_context *smu) 760 { 761 struct smu_table *driver_table = &smu->smu_table.driver_table; 762 int ret = 0; 763 764 if (driver_table->mc_address) { 765 ret = smu_cmn_send_smc_msg_with_param(smu, 766 SMU_MSG_SetDriverDramAddrHigh, 767 upper_32_bits(driver_table->mc_address), 768 NULL); 769 if (!ret) 770 ret = smu_cmn_send_smc_msg_with_param(smu, 771 SMU_MSG_SetDriverDramAddrLow, 772 lower_32_bits(driver_table->mc_address), 773 NULL); 774 } 775 776 return ret; 777 } 778 779 int smu_v13_0_set_tool_table_location(struct smu_context *smu) 780 { 781 int ret = 0; 782 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 783 784 if (tool_table->mc_address) { 785 ret = smu_cmn_send_smc_msg_with_param(smu, 786 SMU_MSG_SetToolsDramAddrHigh, 787 upper_32_bits(tool_table->mc_address), 788 NULL); 789 if (!ret) 790 ret = smu_cmn_send_smc_msg_with_param(smu, 791 SMU_MSG_SetToolsDramAddrLow, 792 lower_32_bits(tool_table->mc_address), 793 NULL); 794 } 795 796 return ret; 797 } 798 799 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count) 800 { 801 int ret = 0; 802 803 if (!smu->pm_enabled) 804 return ret; 805 806 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL); 807 808 return ret; 809 } 810 811 int smu_v13_0_set_allowed_mask(struct smu_context *smu) 812 { 813 struct smu_feature *feature = &smu->smu_feature; 814 int ret = 0; 815 uint32_t feature_mask[2]; 816 817 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || 818 feature->feature_num < 64) 819 return -EINVAL; 820 821 bitmap_to_arr32(feature_mask, feature->allowed, 64); 822 823 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 824 feature_mask[1], NULL); 825 if (ret) 826 return ret; 827 828 return smu_cmn_send_smc_msg_with_param(smu, 829 SMU_MSG_SetAllowedFeaturesMaskLow, 830 feature_mask[0], 831 NULL); 832 } 833 834 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable) 835 { 836 int ret = 0; 837 struct amdgpu_device *adev = smu->adev; 838 839 switch (adev->ip_versions[MP1_HWIP][0]) { 840 case IP_VERSION(13, 0, 0): 841 case IP_VERSION(13, 0, 1): 842 case IP_VERSION(13, 0, 3): 843 case IP_VERSION(13, 0, 4): 844 case IP_VERSION(13, 0, 5): 845 case IP_VERSION(13, 0, 7): 846 case IP_VERSION(13, 0, 8): 847 case IP_VERSION(13, 0, 10): 848 case IP_VERSION(13, 0, 11): 849 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 850 return 0; 851 if (enable) 852 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 853 else 854 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 855 break; 856 default: 857 break; 858 } 859 860 return ret; 861 } 862 863 int smu_v13_0_system_features_control(struct smu_context *smu, 864 bool en) 865 { 866 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 867 SMU_MSG_DisableAllSmuFeatures), NULL); 868 } 869 870 int smu_v13_0_notify_display_change(struct smu_context *smu) 871 { 872 int ret = 0; 873 874 if (!smu->pm_enabled) 875 return ret; 876 877 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 878 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 879 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 880 881 return ret; 882 } 883 884 static int 885 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, 886 enum smu_clk_type clock_select) 887 { 888 int ret = 0; 889 int clk_id; 890 891 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || 892 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) 893 return 0; 894 895 clk_id = smu_cmn_to_asic_specific_index(smu, 896 CMN2ASIC_MAPPING_CLK, 897 clock_select); 898 if (clk_id < 0) 899 return -EINVAL; 900 901 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, 902 clk_id << 16, clock); 903 if (ret) { 904 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); 905 return ret; 906 } 907 908 if (*clock != 0) 909 return 0; 910 911 /* if DC limit is zero, return AC limit */ 912 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, 913 clk_id << 16, clock); 914 if (ret) { 915 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!"); 916 return ret; 917 } 918 919 return 0; 920 } 921 922 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu) 923 { 924 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks = 925 smu->smu_table.max_sustainable_clocks; 926 int ret = 0; 927 928 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; 929 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; 930 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; 931 max_sustainable_clocks->display_clock = 0xFFFFFFFF; 932 max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 933 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 934 935 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 936 ret = smu_v13_0_get_max_sustainable_clock(smu, 937 &(max_sustainable_clocks->uclock), 938 SMU_UCLK); 939 if (ret) { 940 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!", 941 __func__); 942 return ret; 943 } 944 } 945 946 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 947 ret = smu_v13_0_get_max_sustainable_clock(smu, 948 &(max_sustainable_clocks->soc_clock), 949 SMU_SOCCLK); 950 if (ret) { 951 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!", 952 __func__); 953 return ret; 954 } 955 } 956 957 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 958 ret = smu_v13_0_get_max_sustainable_clock(smu, 959 &(max_sustainable_clocks->dcef_clock), 960 SMU_DCEFCLK); 961 if (ret) { 962 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!", 963 __func__); 964 return ret; 965 } 966 967 ret = smu_v13_0_get_max_sustainable_clock(smu, 968 &(max_sustainable_clocks->display_clock), 969 SMU_DISPCLK); 970 if (ret) { 971 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!", 972 __func__); 973 return ret; 974 } 975 ret = smu_v13_0_get_max_sustainable_clock(smu, 976 &(max_sustainable_clocks->phy_clock), 977 SMU_PHYCLK); 978 if (ret) { 979 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!", 980 __func__); 981 return ret; 982 } 983 ret = smu_v13_0_get_max_sustainable_clock(smu, 984 &(max_sustainable_clocks->pixel_clock), 985 SMU_PIXCLK); 986 if (ret) { 987 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!", 988 __func__); 989 return ret; 990 } 991 } 992 993 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 994 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 995 996 return 0; 997 } 998 999 int smu_v13_0_get_current_power_limit(struct smu_context *smu, 1000 uint32_t *power_limit) 1001 { 1002 int power_src; 1003 int ret = 0; 1004 1005 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 1006 return -EINVAL; 1007 1008 power_src = smu_cmn_to_asic_specific_index(smu, 1009 CMN2ASIC_MAPPING_PWR, 1010 smu->adev->pm.ac_power ? 1011 SMU_POWER_SOURCE_AC : 1012 SMU_POWER_SOURCE_DC); 1013 if (power_src < 0) 1014 return -EINVAL; 1015 1016 ret = smu_cmn_send_smc_msg_with_param(smu, 1017 SMU_MSG_GetPptLimit, 1018 power_src << 16, 1019 power_limit); 1020 if (ret) 1021 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 1022 1023 return ret; 1024 } 1025 1026 int smu_v13_0_set_power_limit(struct smu_context *smu, 1027 enum smu_ppt_limit_type limit_type, 1028 uint32_t limit) 1029 { 1030 int ret = 0; 1031 1032 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 1033 return -EINVAL; 1034 1035 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1036 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 1037 return -EOPNOTSUPP; 1038 } 1039 1040 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL); 1041 if (ret) { 1042 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 1043 return ret; 1044 } 1045 1046 smu->current_power_limit = limit; 1047 1048 return 0; 1049 } 1050 1051 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu) 1052 { 1053 return smu_cmn_send_smc_msg(smu, 1054 SMU_MSG_AllowIHHostInterrupt, 1055 NULL); 1056 } 1057 1058 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu) 1059 { 1060 int ret = 0; 1061 1062 if (smu->dc_controlled_by_gpio && 1063 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) 1064 ret = smu_v13_0_allow_ih_interrupt(smu); 1065 1066 return ret; 1067 } 1068 1069 int smu_v13_0_enable_thermal_alert(struct smu_context *smu) 1070 { 1071 int ret = 0; 1072 1073 if (!smu->irq_source.num_types) 1074 return 0; 1075 1076 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 1077 if (ret) 1078 return ret; 1079 1080 return smu_v13_0_process_pending_interrupt(smu); 1081 } 1082 1083 int smu_v13_0_disable_thermal_alert(struct smu_context *smu) 1084 { 1085 if (!smu->irq_source.num_types) 1086 return 0; 1087 1088 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1089 } 1090 1091 static uint16_t convert_to_vddc(uint8_t vid) 1092 { 1093 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE); 1094 } 1095 1096 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) 1097 { 1098 struct amdgpu_device *adev = smu->adev; 1099 uint32_t vdd = 0, val_vid = 0; 1100 1101 if (!value) 1102 return -EINVAL; 1103 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) & 1104 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 1105 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 1106 1107 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); 1108 1109 *value = vdd; 1110 1111 return 0; 1112 1113 } 1114 1115 int 1116 smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 1117 struct pp_display_clock_request 1118 *clock_req) 1119 { 1120 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1121 int ret = 0; 1122 enum smu_clk_type clk_select = 0; 1123 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1124 1125 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || 1126 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1127 switch (clk_type) { 1128 case amd_pp_dcef_clock: 1129 clk_select = SMU_DCEFCLK; 1130 break; 1131 case amd_pp_disp_clock: 1132 clk_select = SMU_DISPCLK; 1133 break; 1134 case amd_pp_pixel_clock: 1135 clk_select = SMU_PIXCLK; 1136 break; 1137 case amd_pp_phy_clock: 1138 clk_select = SMU_PHYCLK; 1139 break; 1140 case amd_pp_mem_clock: 1141 clk_select = SMU_UCLK; 1142 break; 1143 default: 1144 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); 1145 ret = -EINVAL; 1146 break; 1147 } 1148 1149 if (ret) 1150 goto failed; 1151 1152 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) 1153 return 0; 1154 1155 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); 1156 1157 if(clk_select == SMU_UCLK) 1158 smu->hard_min_uclk_req_from_dal = clk_freq; 1159 } 1160 1161 failed: 1162 return ret; 1163 } 1164 1165 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu) 1166 { 1167 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1168 return AMD_FAN_CTRL_MANUAL; 1169 else 1170 return AMD_FAN_CTRL_AUTO; 1171 } 1172 1173 static int 1174 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) 1175 { 1176 int ret = 0; 1177 1178 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1179 return 0; 1180 1181 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); 1182 if (ret) 1183 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!", 1184 __func__, (auto_fan_control ? "Start" : "Stop")); 1185 1186 return ret; 1187 } 1188 1189 static int 1190 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) 1191 { 1192 struct amdgpu_device *adev = smu->adev; 1193 1194 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, 1195 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), 1196 CG_FDO_CTRL2, TMIN, 0)); 1197 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2, 1198 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2), 1199 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1200 1201 return 0; 1202 } 1203 1204 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu, 1205 uint32_t speed) 1206 { 1207 struct amdgpu_device *adev = smu->adev; 1208 uint32_t duty100, duty; 1209 uint64_t tmp64; 1210 1211 speed = MIN(speed, 255); 1212 1213 if (smu_v13_0_auto_fan_control(smu, 0)) 1214 return -EINVAL; 1215 1216 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1), 1217 CG_FDO_CTRL1, FMAX_DUTY100); 1218 if (!duty100) 1219 return -EINVAL; 1220 1221 tmp64 = (uint64_t)speed * duty100; 1222 do_div(tmp64, 255); 1223 duty = (uint32_t)tmp64; 1224 1225 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0, 1226 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0), 1227 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1228 1229 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1230 } 1231 1232 int 1233 smu_v13_0_set_fan_control_mode(struct smu_context *smu, 1234 uint32_t mode) 1235 { 1236 int ret = 0; 1237 1238 switch (mode) { 1239 case AMD_FAN_CTRL_NONE: 1240 ret = smu_v13_0_set_fan_speed_pwm(smu, 255); 1241 break; 1242 case AMD_FAN_CTRL_MANUAL: 1243 ret = smu_v13_0_auto_fan_control(smu, 0); 1244 break; 1245 case AMD_FAN_CTRL_AUTO: 1246 ret = smu_v13_0_auto_fan_control(smu, 1); 1247 break; 1248 default: 1249 break; 1250 } 1251 1252 if (ret) { 1253 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__); 1254 return -EINVAL; 1255 } 1256 1257 return ret; 1258 } 1259 1260 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, 1261 uint32_t speed) 1262 { 1263 struct amdgpu_device *adev = smu->adev; 1264 uint32_t tach_period, crystal_clock_freq; 1265 int ret; 1266 1267 if (!speed) 1268 return -EINVAL; 1269 1270 ret = smu_v13_0_auto_fan_control(smu, 0); 1271 if (ret) 1272 return ret; 1273 1274 crystal_clock_freq = amdgpu_asic_get_xclk(adev); 1275 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1276 WREG32_SOC15(THM, 0, regCG_TACH_CTRL, 1277 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL), 1278 CG_TACH_CTRL, TARGET_PERIOD, 1279 tach_period)); 1280 1281 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1282 } 1283 1284 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, 1285 uint32_t pstate) 1286 { 1287 int ret = 0; 1288 ret = smu_cmn_send_smc_msg_with_param(smu, 1289 SMU_MSG_SetXgmiMode, 1290 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 1291 NULL); 1292 return ret; 1293 } 1294 1295 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev, 1296 struct amdgpu_irq_src *source, 1297 unsigned tyep, 1298 enum amdgpu_interrupt_state state) 1299 { 1300 struct smu_context *smu = adev->powerplay.pp_handle; 1301 uint32_t low, high; 1302 uint32_t val = 0; 1303 1304 switch (state) { 1305 case AMDGPU_IRQ_STATE_DISABLE: 1306 /* For THM irqs */ 1307 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1308 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); 1309 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); 1310 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 1311 1312 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0); 1313 1314 /* For MP1 SW irqs */ 1315 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1316 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 1317 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 1318 1319 break; 1320 case AMDGPU_IRQ_STATE_ENABLE: 1321 /* For THM irqs */ 1322 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 1323 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 1324 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1325 smu->thermal_range.software_shutdown_temp); 1326 1327 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1328 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 1329 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 1330 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 1331 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 1332 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 1333 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 1334 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1335 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 1336 1337 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 1338 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 1339 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 1340 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val); 1341 1342 /* For MP1 SW irqs */ 1343 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); 1344 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 1345 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 1346 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); 1347 1348 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1349 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 1350 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 1351 1352 break; 1353 default: 1354 break; 1355 } 1356 1357 return 0; 1358 } 1359 1360 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu) 1361 { 1362 return smu_cmn_send_smc_msg(smu, 1363 SMU_MSG_ReenableAcDcInterrupt, 1364 NULL); 1365 } 1366 1367 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 1368 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 1369 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 1370 1371 static int smu_v13_0_irq_process(struct amdgpu_device *adev, 1372 struct amdgpu_irq_src *source, 1373 struct amdgpu_iv_entry *entry) 1374 { 1375 struct smu_context *smu = adev->powerplay.pp_handle; 1376 uint32_t client_id = entry->client_id; 1377 uint32_t src_id = entry->src_id; 1378 /* 1379 * ctxid is used to distinguish different 1380 * events for SMCToHost interrupt. 1381 */ 1382 uint32_t ctxid = entry->src_data[0]; 1383 uint32_t data; 1384 uint32_t high; 1385 1386 if (client_id == SOC15_IH_CLIENTID_THM) { 1387 switch (src_id) { 1388 case THM_11_0__SRCID__THM_DIG_THERM_L2H: 1389 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1390 /* 1391 * SW CTF just occurred. 1392 * Try to do a graceful shutdown to prevent further damage. 1393 */ 1394 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1395 orderly_poweroff(true); 1396 break; 1397 case THM_11_0__SRCID__THM_DIG_THERM_H2L: 1398 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 1399 break; 1400 default: 1401 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 1402 src_id); 1403 break; 1404 } 1405 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { 1406 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); 1407 /* 1408 * HW CTF just occurred. Shutdown to prevent further damage. 1409 */ 1410 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); 1411 orderly_poweroff(true); 1412 } else if (client_id == SOC15_IH_CLIENTID_MP1) { 1413 if (src_id == 0xfe) { 1414 /* ACK SMUToHost interrupt */ 1415 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 1416 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); 1417 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); 1418 1419 switch (ctxid) { 1420 case 0x3: 1421 dev_dbg(adev->dev, "Switched to AC mode!\n"); 1422 smu_v13_0_ack_ac_dc_interrupt(smu); 1423 break; 1424 case 0x4: 1425 dev_dbg(adev->dev, "Switched to DC mode!\n"); 1426 smu_v13_0_ack_ac_dc_interrupt(smu); 1427 break; 1428 case 0x7: 1429 /* 1430 * Increment the throttle interrupt counter 1431 */ 1432 atomic64_inc(&smu->throttle_int_counter); 1433 1434 if (!atomic_read(&adev->throttling_logging_enabled)) 1435 return 0; 1436 1437 if (__ratelimit(&adev->throttling_logging_rs)) 1438 schedule_work(&smu->throttling_logging_work); 1439 1440 break; 1441 case 0x8: 1442 high = smu->thermal_range.software_shutdown_temp + 1443 smu->thermal_range.software_shutdown_temp_offset; 1444 high = min_t(typeof(high), 1445 SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1446 high); 1447 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n", 1448 high, 1449 smu->thermal_range.software_shutdown_temp_offset); 1450 1451 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1452 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL, 1453 DIG_THERM_INTH, 1454 (high & 0xff)); 1455 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1456 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data); 1457 break; 1458 case 0x9: 1459 high = min_t(typeof(high), 1460 SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1461 smu->thermal_range.software_shutdown_temp); 1462 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high); 1463 1464 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 1465 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL, 1466 DIG_THERM_INTH, 1467 (high & 0xff)); 1468 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1469 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data); 1470 break; 1471 } 1472 } 1473 } 1474 1475 return 0; 1476 } 1477 1478 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = 1479 { 1480 .set = smu_v13_0_set_irq_state, 1481 .process = smu_v13_0_irq_process, 1482 }; 1483 1484 int smu_v13_0_register_irq_handler(struct smu_context *smu) 1485 { 1486 struct amdgpu_device *adev = smu->adev; 1487 struct amdgpu_irq_src *irq_src = &smu->irq_source; 1488 int ret = 0; 1489 1490 if (amdgpu_sriov_vf(adev)) 1491 return 0; 1492 1493 irq_src->num_types = 1; 1494 irq_src->funcs = &smu_v13_0_irq_funcs; 1495 1496 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1497 THM_11_0__SRCID__THM_DIG_THERM_L2H, 1498 irq_src); 1499 if (ret) 1500 return ret; 1501 1502 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1503 THM_11_0__SRCID__THM_DIG_THERM_H2L, 1504 irq_src); 1505 if (ret) 1506 return ret; 1507 1508 /* Register CTF(GPIO_19) interrupt */ 1509 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, 1510 SMUIO_11_0__SRCID__SMUIO_GPIO19, 1511 irq_src); 1512 if (ret) 1513 return ret; 1514 1515 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 1516 0xfe, 1517 irq_src); 1518 if (ret) 1519 return ret; 1520 1521 return ret; 1522 } 1523 1524 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 1525 struct pp_smu_nv_clock_table *max_clocks) 1526 { 1527 struct smu_table_context *table_context = &smu->smu_table; 1528 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL; 1529 1530 if (!max_clocks || !table_context->max_sustainable_clocks) 1531 return -EINVAL; 1532 1533 sustainable_clocks = table_context->max_sustainable_clocks; 1534 1535 max_clocks->dcfClockInKhz = 1536 (unsigned int) sustainable_clocks->dcef_clock * 1000; 1537 max_clocks->displayClockInKhz = 1538 (unsigned int) sustainable_clocks->display_clock * 1000; 1539 max_clocks->phyClockInKhz = 1540 (unsigned int) sustainable_clocks->phy_clock * 1000; 1541 max_clocks->pixelClockInKhz = 1542 (unsigned int) sustainable_clocks->pixel_clock * 1000; 1543 max_clocks->uClockInKhz = 1544 (unsigned int) sustainable_clocks->uclock * 1000; 1545 max_clocks->socClockInKhz = 1546 (unsigned int) sustainable_clocks->soc_clock * 1000; 1547 max_clocks->dscClockInKhz = 0; 1548 max_clocks->dppClockInKhz = 0; 1549 max_clocks->fabricClockInKhz = 0; 1550 1551 return 0; 1552 } 1553 1554 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu) 1555 { 1556 int ret = 0; 1557 1558 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); 1559 1560 return ret; 1561 } 1562 1563 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu, 1564 uint64_t event_arg) 1565 { 1566 int ret = 0; 1567 1568 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n"); 1569 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL); 1570 1571 return ret; 1572 } 1573 1574 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1575 uint64_t event_arg) 1576 { 1577 int ret = -EINVAL; 1578 1579 switch (event) { 1580 case SMU_EVENT_RESET_COMPLETE: 1581 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg); 1582 break; 1583 default: 1584 break; 1585 } 1586 1587 return ret; 1588 } 1589 1590 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1591 uint32_t *min, uint32_t *max) 1592 { 1593 int ret = 0, clk_id = 0; 1594 uint32_t param = 0; 1595 uint32_t clock_limit; 1596 1597 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 1598 switch (clk_type) { 1599 case SMU_MCLK: 1600 case SMU_UCLK: 1601 clock_limit = smu->smu_table.boot_values.uclk; 1602 break; 1603 case SMU_GFXCLK: 1604 case SMU_SCLK: 1605 clock_limit = smu->smu_table.boot_values.gfxclk; 1606 break; 1607 case SMU_SOCCLK: 1608 clock_limit = smu->smu_table.boot_values.socclk; 1609 break; 1610 default: 1611 clock_limit = 0; 1612 break; 1613 } 1614 1615 /* clock in Mhz unit */ 1616 if (min) 1617 *min = clock_limit / 100; 1618 if (max) 1619 *max = clock_limit / 100; 1620 1621 return 0; 1622 } 1623 1624 clk_id = smu_cmn_to_asic_specific_index(smu, 1625 CMN2ASIC_MAPPING_CLK, 1626 clk_type); 1627 if (clk_id < 0) { 1628 ret = -EINVAL; 1629 goto failed; 1630 } 1631 param = (clk_id & 0xffff) << 16; 1632 1633 if (max) { 1634 if (smu->adev->pm.ac_power) 1635 ret = smu_cmn_send_smc_msg_with_param(smu, 1636 SMU_MSG_GetMaxDpmFreq, 1637 param, 1638 max); 1639 else 1640 ret = smu_cmn_send_smc_msg_with_param(smu, 1641 SMU_MSG_GetDcModeMaxDpmFreq, 1642 param, 1643 max); 1644 if (ret) 1645 goto failed; 1646 } 1647 1648 if (min) { 1649 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 1650 if (ret) 1651 goto failed; 1652 } 1653 1654 failed: 1655 return ret; 1656 } 1657 1658 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, 1659 enum smu_clk_type clk_type, 1660 uint32_t min, 1661 uint32_t max) 1662 { 1663 int ret = 0, clk_id = 0; 1664 uint32_t param; 1665 1666 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1667 return 0; 1668 1669 clk_id = smu_cmn_to_asic_specific_index(smu, 1670 CMN2ASIC_MAPPING_CLK, 1671 clk_type); 1672 if (clk_id < 0) 1673 return clk_id; 1674 1675 if (max > 0) { 1676 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1677 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1678 param, NULL); 1679 if (ret) 1680 goto out; 1681 } 1682 1683 if (min > 0) { 1684 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1685 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1686 param, NULL); 1687 if (ret) 1688 goto out; 1689 } 1690 1691 out: 1692 return ret; 1693 } 1694 1695 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 1696 enum smu_clk_type clk_type, 1697 uint32_t min, 1698 uint32_t max) 1699 { 1700 int ret = 0, clk_id = 0; 1701 uint32_t param; 1702 1703 if (min <= 0 && max <= 0) 1704 return -EINVAL; 1705 1706 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1707 return 0; 1708 1709 clk_id = smu_cmn_to_asic_specific_index(smu, 1710 CMN2ASIC_MAPPING_CLK, 1711 clk_type); 1712 if (clk_id < 0) 1713 return clk_id; 1714 1715 if (max > 0) { 1716 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1717 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1718 param, NULL); 1719 if (ret) 1720 return ret; 1721 } 1722 1723 if (min > 0) { 1724 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1725 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1726 param, NULL); 1727 if (ret) 1728 return ret; 1729 } 1730 1731 return ret; 1732 } 1733 1734 int smu_v13_0_set_performance_level(struct smu_context *smu, 1735 enum amd_dpm_forced_level level) 1736 { 1737 struct smu_13_0_dpm_context *dpm_context = 1738 smu->smu_dpm.dpm_context; 1739 struct smu_13_0_dpm_table *gfx_table = 1740 &dpm_context->dpm_tables.gfx_table; 1741 struct smu_13_0_dpm_table *mem_table = 1742 &dpm_context->dpm_tables.uclk_table; 1743 struct smu_13_0_dpm_table *soc_table = 1744 &dpm_context->dpm_tables.soc_table; 1745 struct smu_13_0_dpm_table *vclk_table = 1746 &dpm_context->dpm_tables.vclk_table; 1747 struct smu_13_0_dpm_table *dclk_table = 1748 &dpm_context->dpm_tables.dclk_table; 1749 struct smu_13_0_dpm_table *fclk_table = 1750 &dpm_context->dpm_tables.fclk_table; 1751 struct smu_umd_pstate_table *pstate_table = 1752 &smu->pstate_table; 1753 struct amdgpu_device *adev = smu->adev; 1754 uint32_t sclk_min = 0, sclk_max = 0; 1755 uint32_t mclk_min = 0, mclk_max = 0; 1756 uint32_t socclk_min = 0, socclk_max = 0; 1757 uint32_t vclk_min = 0, vclk_max = 0; 1758 uint32_t dclk_min = 0, dclk_max = 0; 1759 uint32_t fclk_min = 0, fclk_max = 0; 1760 int ret = 0, i; 1761 1762 switch (level) { 1763 case AMD_DPM_FORCED_LEVEL_HIGH: 1764 sclk_min = sclk_max = gfx_table->max; 1765 mclk_min = mclk_max = mem_table->max; 1766 socclk_min = socclk_max = soc_table->max; 1767 vclk_min = vclk_max = vclk_table->max; 1768 dclk_min = dclk_max = dclk_table->max; 1769 fclk_min = fclk_max = fclk_table->max; 1770 break; 1771 case AMD_DPM_FORCED_LEVEL_LOW: 1772 sclk_min = sclk_max = gfx_table->min; 1773 mclk_min = mclk_max = mem_table->min; 1774 socclk_min = socclk_max = soc_table->min; 1775 vclk_min = vclk_max = vclk_table->min; 1776 dclk_min = dclk_max = dclk_table->min; 1777 fclk_min = fclk_max = fclk_table->min; 1778 break; 1779 case AMD_DPM_FORCED_LEVEL_AUTO: 1780 sclk_min = gfx_table->min; 1781 sclk_max = gfx_table->max; 1782 mclk_min = mem_table->min; 1783 mclk_max = mem_table->max; 1784 socclk_min = soc_table->min; 1785 socclk_max = soc_table->max; 1786 vclk_min = vclk_table->min; 1787 vclk_max = vclk_table->max; 1788 dclk_min = dclk_table->min; 1789 dclk_max = dclk_table->max; 1790 fclk_min = fclk_table->min; 1791 fclk_max = fclk_table->max; 1792 break; 1793 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1794 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1795 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1796 socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1797 vclk_min = vclk_max = pstate_table->vclk_pstate.standard; 1798 dclk_min = dclk_max = pstate_table->dclk_pstate.standard; 1799 fclk_min = fclk_max = pstate_table->fclk_pstate.standard; 1800 break; 1801 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1802 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1803 break; 1804 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1805 mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1806 break; 1807 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1808 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1809 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1810 socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1811 vclk_min = vclk_max = pstate_table->vclk_pstate.peak; 1812 dclk_min = dclk_max = pstate_table->dclk_pstate.peak; 1813 fclk_min = fclk_max = pstate_table->fclk_pstate.peak; 1814 break; 1815 case AMD_DPM_FORCED_LEVEL_MANUAL: 1816 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1817 return 0; 1818 default: 1819 dev_err(adev->dev, "Invalid performance level %d\n", level); 1820 return -EINVAL; 1821 } 1822 1823 /* 1824 * Unset those settings for SMU 13.0.2. As soft limits settings 1825 * for those clock domains are not supported. 1826 */ 1827 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) { 1828 mclk_min = mclk_max = 0; 1829 socclk_min = socclk_max = 0; 1830 vclk_min = vclk_max = 0; 1831 dclk_min = dclk_max = 0; 1832 fclk_min = fclk_max = 0; 1833 } 1834 1835 if (sclk_min && sclk_max) { 1836 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1837 SMU_GFXCLK, 1838 sclk_min, 1839 sclk_max); 1840 if (ret) 1841 return ret; 1842 1843 pstate_table->gfxclk_pstate.curr.min = sclk_min; 1844 pstate_table->gfxclk_pstate.curr.max = sclk_max; 1845 } 1846 1847 if (mclk_min && mclk_max) { 1848 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1849 SMU_MCLK, 1850 mclk_min, 1851 mclk_max); 1852 if (ret) 1853 return ret; 1854 1855 pstate_table->uclk_pstate.curr.min = mclk_min; 1856 pstate_table->uclk_pstate.curr.max = mclk_max; 1857 } 1858 1859 if (socclk_min && socclk_max) { 1860 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1861 SMU_SOCCLK, 1862 socclk_min, 1863 socclk_max); 1864 if (ret) 1865 return ret; 1866 1867 pstate_table->socclk_pstate.curr.min = socclk_min; 1868 pstate_table->socclk_pstate.curr.max = socclk_max; 1869 } 1870 1871 if (vclk_min && vclk_max) { 1872 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1873 if (adev->vcn.harvest_config & (1 << i)) 1874 continue; 1875 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1876 i ? SMU_VCLK1 : SMU_VCLK, 1877 vclk_min, 1878 vclk_max); 1879 if (ret) 1880 return ret; 1881 } 1882 pstate_table->vclk_pstate.curr.min = vclk_min; 1883 pstate_table->vclk_pstate.curr.max = vclk_max; 1884 } 1885 1886 if (dclk_min && dclk_max) { 1887 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1888 if (adev->vcn.harvest_config & (1 << i)) 1889 continue; 1890 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1891 i ? SMU_DCLK1 : SMU_DCLK, 1892 dclk_min, 1893 dclk_max); 1894 if (ret) 1895 return ret; 1896 } 1897 pstate_table->dclk_pstate.curr.min = dclk_min; 1898 pstate_table->dclk_pstate.curr.max = dclk_max; 1899 } 1900 1901 if (fclk_min && fclk_max) { 1902 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1903 SMU_FCLK, 1904 fclk_min, 1905 fclk_max); 1906 if (ret) 1907 return ret; 1908 1909 pstate_table->fclk_pstate.curr.min = fclk_min; 1910 pstate_table->fclk_pstate.curr.max = fclk_max; 1911 } 1912 1913 return ret; 1914 } 1915 1916 int smu_v13_0_set_power_source(struct smu_context *smu, 1917 enum smu_power_src_type power_src) 1918 { 1919 int pwr_source; 1920 1921 pwr_source = smu_cmn_to_asic_specific_index(smu, 1922 CMN2ASIC_MAPPING_PWR, 1923 (uint32_t)power_src); 1924 if (pwr_source < 0) 1925 return -EINVAL; 1926 1927 return smu_cmn_send_smc_msg_with_param(smu, 1928 SMU_MSG_NotifyPowerSource, 1929 pwr_source, 1930 NULL); 1931 } 1932 1933 static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu, 1934 enum smu_clk_type clk_type, 1935 uint16_t level, 1936 uint32_t *value) 1937 { 1938 int ret = 0, clk_id = 0; 1939 uint32_t param; 1940 1941 if (!value) 1942 return -EINVAL; 1943 1944 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1945 return 0; 1946 1947 clk_id = smu_cmn_to_asic_specific_index(smu, 1948 CMN2ASIC_MAPPING_CLK, 1949 clk_type); 1950 if (clk_id < 0) 1951 return clk_id; 1952 1953 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1954 1955 ret = smu_cmn_send_smc_msg_with_param(smu, 1956 SMU_MSG_GetDpmFreqByIndex, 1957 param, 1958 value); 1959 if (ret) 1960 return ret; 1961 1962 *value = *value & 0x7fffffff; 1963 1964 return ret; 1965 } 1966 1967 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu, 1968 enum smu_clk_type clk_type, 1969 uint32_t *value) 1970 { 1971 int ret; 1972 1973 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value); 1974 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */ 1975 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value)) 1976 ++(*value); 1977 1978 return ret; 1979 } 1980 1981 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu, 1982 enum smu_clk_type clk_type, 1983 bool *is_fine_grained_dpm) 1984 { 1985 int ret = 0, clk_id = 0; 1986 uint32_t param; 1987 uint32_t value; 1988 1989 if (!is_fine_grained_dpm) 1990 return -EINVAL; 1991 1992 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1993 return 0; 1994 1995 clk_id = smu_cmn_to_asic_specific_index(smu, 1996 CMN2ASIC_MAPPING_CLK, 1997 clk_type); 1998 if (clk_id < 0) 1999 return clk_id; 2000 2001 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff); 2002 2003 ret = smu_cmn_send_smc_msg_with_param(smu, 2004 SMU_MSG_GetDpmFreqByIndex, 2005 param, 2006 &value); 2007 if (ret) 2008 return ret; 2009 2010 /* 2011 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM 2012 * now, we un-support it 2013 */ 2014 *is_fine_grained_dpm = value & 0x80000000; 2015 2016 return 0; 2017 } 2018 2019 int smu_v13_0_set_single_dpm_table(struct smu_context *smu, 2020 enum smu_clk_type clk_type, 2021 struct smu_13_0_dpm_table *single_dpm_table) 2022 { 2023 int ret = 0; 2024 uint32_t clk; 2025 int i; 2026 2027 ret = smu_v13_0_get_dpm_level_count(smu, 2028 clk_type, 2029 &single_dpm_table->count); 2030 if (ret) { 2031 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 2032 return ret; 2033 } 2034 2035 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) { 2036 ret = smu_v13_0_get_fine_grained_status(smu, 2037 clk_type, 2038 &single_dpm_table->is_fine_grained); 2039 if (ret) { 2040 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); 2041 return ret; 2042 } 2043 } 2044 2045 for (i = 0; i < single_dpm_table->count; i++) { 2046 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2047 clk_type, 2048 i, 2049 &clk); 2050 if (ret) { 2051 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 2052 return ret; 2053 } 2054 2055 single_dpm_table->dpm_levels[i].value = clk; 2056 single_dpm_table->dpm_levels[i].enabled = true; 2057 2058 if (i == 0) 2059 single_dpm_table->min = clk; 2060 else if (i == single_dpm_table->count - 1) 2061 single_dpm_table->max = clk; 2062 } 2063 2064 return 0; 2065 } 2066 2067 int smu_v13_0_get_dpm_level_range(struct smu_context *smu, 2068 enum smu_clk_type clk_type, 2069 uint32_t *min_value, 2070 uint32_t *max_value) 2071 { 2072 uint32_t level_count = 0; 2073 int ret = 0; 2074 2075 if (!min_value && !max_value) 2076 return -EINVAL; 2077 2078 if (min_value) { 2079 /* by default, level 0 clock value as min value */ 2080 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2081 clk_type, 2082 0, 2083 min_value); 2084 if (ret) 2085 return ret; 2086 } 2087 2088 if (max_value) { 2089 ret = smu_v13_0_get_dpm_level_count(smu, 2090 clk_type, 2091 &level_count); 2092 if (ret) 2093 return ret; 2094 2095 ret = smu_v13_0_get_dpm_freq_by_index(smu, 2096 clk_type, 2097 level_count - 1, 2098 max_value); 2099 if (ret) 2100 return ret; 2101 } 2102 2103 return ret; 2104 } 2105 2106 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu) 2107 { 2108 struct amdgpu_device *adev = smu->adev; 2109 2110 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2111 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2112 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2113 } 2114 2115 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu) 2116 { 2117 uint32_t width_level; 2118 2119 width_level = smu_v13_0_get_current_pcie_link_width_level(smu); 2120 if (width_level > LINK_WIDTH_MAX) 2121 width_level = 0; 2122 2123 return link_width[width_level]; 2124 } 2125 2126 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu) 2127 { 2128 struct amdgpu_device *adev = smu->adev; 2129 2130 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2131 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2132 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2133 } 2134 2135 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu) 2136 { 2137 uint32_t speed_level; 2138 2139 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu); 2140 if (speed_level > LINK_SPEED_MAX) 2141 speed_level = 0; 2142 2143 return link_speed[speed_level]; 2144 } 2145 2146 int smu_v13_0_set_vcn_enable(struct smu_context *smu, 2147 bool enable) 2148 { 2149 struct amdgpu_device *adev = smu->adev; 2150 int i, ret = 0; 2151 2152 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2153 if (adev->vcn.harvest_config & (1 << i)) 2154 continue; 2155 2156 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 2157 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 2158 i << 16U, NULL); 2159 if (ret) 2160 return ret; 2161 } 2162 2163 return ret; 2164 } 2165 2166 int smu_v13_0_set_jpeg_enable(struct smu_context *smu, 2167 bool enable) 2168 { 2169 return smu_cmn_send_smc_msg_with_param(smu, enable ? 2170 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, 2171 0, NULL); 2172 } 2173 2174 int smu_v13_0_run_btc(struct smu_context *smu) 2175 { 2176 int res; 2177 2178 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2179 if (res) 2180 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 2181 2182 return res; 2183 } 2184 2185 int smu_v13_0_gpo_control(struct smu_context *smu, 2186 bool enablement) 2187 { 2188 int res; 2189 2190 res = smu_cmn_send_smc_msg_with_param(smu, 2191 SMU_MSG_AllowGpo, 2192 enablement ? 1 : 0, 2193 NULL); 2194 if (res) 2195 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement); 2196 2197 return res; 2198 } 2199 2200 int smu_v13_0_deep_sleep_control(struct smu_context *smu, 2201 bool enablement) 2202 { 2203 struct amdgpu_device *adev = smu->adev; 2204 int ret = 0; 2205 2206 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 2207 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 2208 if (ret) { 2209 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 2210 return ret; 2211 } 2212 } 2213 2214 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 2215 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 2216 if (ret) { 2217 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 2218 return ret; 2219 } 2220 } 2221 2222 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 2223 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 2224 if (ret) { 2225 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 2226 return ret; 2227 } 2228 } 2229 2230 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 2231 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 2232 if (ret) { 2233 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 2234 return ret; 2235 } 2236 } 2237 2238 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 2239 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 2240 if (ret) { 2241 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 2242 return ret; 2243 } 2244 } 2245 2246 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) { 2247 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement); 2248 if (ret) { 2249 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable"); 2250 return ret; 2251 } 2252 } 2253 2254 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) { 2255 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement); 2256 if (ret) { 2257 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable"); 2258 return ret; 2259 } 2260 } 2261 2262 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) { 2263 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement); 2264 if (ret) { 2265 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable"); 2266 return ret; 2267 } 2268 } 2269 2270 return ret; 2271 } 2272 2273 int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 2274 bool enablement) 2275 { 2276 int ret = 0; 2277 2278 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 2279 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 2280 2281 return ret; 2282 } 2283 2284 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu, 2285 enum smu_baco_seq baco_seq) 2286 { 2287 return smu_cmn_send_smc_msg_with_param(smu, 2288 SMU_MSG_ArmD3, 2289 baco_seq, 2290 NULL); 2291 } 2292 2293 bool smu_v13_0_baco_is_support(struct smu_context *smu) 2294 { 2295 struct smu_baco_context *smu_baco = &smu->smu_baco; 2296 2297 if (amdgpu_sriov_vf(smu->adev) || 2298 !smu_baco->platform_support) 2299 return false; 2300 2301 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 2302 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 2303 return false; 2304 2305 return true; 2306 } 2307 2308 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu) 2309 { 2310 struct smu_baco_context *smu_baco = &smu->smu_baco; 2311 2312 return smu_baco->state; 2313 } 2314 2315 int smu_v13_0_baco_set_state(struct smu_context *smu, 2316 enum smu_baco_state state) 2317 { 2318 struct smu_baco_context *smu_baco = &smu->smu_baco; 2319 struct amdgpu_device *adev = smu->adev; 2320 int ret = 0; 2321 2322 if (smu_v13_0_baco_get_state(smu) == state) 2323 return 0; 2324 2325 if (state == SMU_BACO_STATE_ENTER) { 2326 ret = smu_cmn_send_smc_msg_with_param(smu, 2327 SMU_MSG_EnterBaco, 2328 smu_baco->maco_support ? 2329 BACO_SEQ_BAMACO : BACO_SEQ_BACO, 2330 NULL); 2331 } else { 2332 ret = smu_cmn_send_smc_msg(smu, 2333 SMU_MSG_ExitBaco, 2334 NULL); 2335 if (ret) 2336 return ret; 2337 2338 /* clear vbios scratch 6 and 7 for coming asic reinit */ 2339 WREG32(adev->bios_scratch_reg_offset + 6, 0); 2340 WREG32(adev->bios_scratch_reg_offset + 7, 0); 2341 } 2342 2343 if (!ret) 2344 smu_baco->state = state; 2345 2346 return ret; 2347 } 2348 2349 int smu_v13_0_baco_enter(struct smu_context *smu) 2350 { 2351 int ret = 0; 2352 2353 ret = smu_v13_0_baco_set_state(smu, 2354 SMU_BACO_STATE_ENTER); 2355 if (ret) 2356 return ret; 2357 2358 msleep(10); 2359 2360 return ret; 2361 } 2362 2363 int smu_v13_0_baco_exit(struct smu_context *smu) 2364 { 2365 return smu_v13_0_baco_set_state(smu, 2366 SMU_BACO_STATE_EXIT); 2367 } 2368 2369 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu) 2370 { 2371 uint16_t index; 2372 2373 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2374 SMU_MSG_EnableGfxImu); 2375 /* Param 1 to tell PMFW to enable GFXOFF feature */ 2376 return smu_cmn_send_msg_without_waiting(smu, index, 1); 2377 } 2378 2379 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, 2380 enum PP_OD_DPM_TABLE_COMMAND type, 2381 long input[], uint32_t size) 2382 { 2383 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 2384 int ret = 0; 2385 2386 /* Only allowed in manual mode */ 2387 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 2388 return -EINVAL; 2389 2390 switch (type) { 2391 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2392 if (size != 2) { 2393 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2394 return -EINVAL; 2395 } 2396 2397 if (input[0] == 0) { 2398 if (input[1] < smu->gfx_default_hard_min_freq) { 2399 dev_warn(smu->adev->dev, 2400 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2401 input[1], smu->gfx_default_hard_min_freq); 2402 return -EINVAL; 2403 } 2404 smu->gfx_actual_hard_min_freq = input[1]; 2405 } else if (input[0] == 1) { 2406 if (input[1] > smu->gfx_default_soft_max_freq) { 2407 dev_warn(smu->adev->dev, 2408 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2409 input[1], smu->gfx_default_soft_max_freq); 2410 return -EINVAL; 2411 } 2412 smu->gfx_actual_soft_max_freq = input[1]; 2413 } else { 2414 return -EINVAL; 2415 } 2416 break; 2417 case PP_OD_RESTORE_DEFAULT_TABLE: 2418 if (size != 0) { 2419 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2420 return -EINVAL; 2421 } 2422 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 2423 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 2424 break; 2425 case PP_OD_COMMIT_DPM_TABLE: 2426 if (size != 0) { 2427 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2428 return -EINVAL; 2429 } 2430 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 2431 dev_err(smu->adev->dev, 2432 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 2433 smu->gfx_actual_hard_min_freq, 2434 smu->gfx_actual_soft_max_freq); 2435 return -EINVAL; 2436 } 2437 2438 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 2439 smu->gfx_actual_hard_min_freq, 2440 NULL); 2441 if (ret) { 2442 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 2443 return ret; 2444 } 2445 2446 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 2447 smu->gfx_actual_soft_max_freq, 2448 NULL); 2449 if (ret) { 2450 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 2451 return ret; 2452 } 2453 break; 2454 default: 2455 return -ENOSYS; 2456 } 2457 2458 return ret; 2459 } 2460 2461 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu) 2462 { 2463 struct smu_table_context *smu_table = &smu->smu_table; 2464 2465 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, 2466 smu_table->clocks_table, false); 2467 } 2468 2469 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu) 2470 { 2471 struct amdgpu_device *adev = smu->adev; 2472 2473 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2474 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2475 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2476 } 2477 2478 int smu_v13_0_mode1_reset(struct smu_context *smu) 2479 { 2480 int ret = 0; 2481 2482 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 2483 if (!ret) 2484 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 2485 2486 return ret; 2487 } 2488