1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_dpm.h" 29 #include "amdgpu_smu.h" 30 #include "atomfirmware.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_atombios.h" 33 #include "smu_v13_0.h" 34 #include "smu13_driver_if_aldebaran.h" 35 #include "soc15_common.h" 36 #include "atom.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 61 [smu_feature] = {1, (aldebaran_feature)} 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 73 74 /* possible frequency drift (1Mhz) */ 75 #define EPSILON 1 76 77 #define smnPCIE_ESM_CTRL 0x111003D0 78 79 /* 80 * SMU support ECCTABLE since version 68.42.0, 81 * use this to check ECCTALE feature whether support 82 */ 83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00 84 85 /* 86 * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0, 87 * use this to check mca_ceumc_addr record whether support 88 */ 89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700 90 91 /* 92 * SMU support BAD CHENNEL info MSG since version 68.51.00, 93 * use this to check ECCTALE feature whether support 94 */ 95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300 96 97 static const struct smu_temperature_range smu13_thermal_policy[] = 98 { 99 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 100 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 101 }; 102 103 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 104 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 105 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 106 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 107 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 108 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 109 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 110 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 111 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 112 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 113 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 114 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 115 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 116 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 117 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 118 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 119 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 120 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 121 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 122 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 123 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 124 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 125 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 126 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 127 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 128 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 129 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 130 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 131 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 132 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 133 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 134 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 135 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 136 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 137 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 138 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 139 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 140 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 141 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 142 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 143 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 144 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 145 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 146 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 147 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 148 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 149 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 150 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 151 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 152 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 153 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0), 154 MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0), 155 MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel, PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel, 0), 156 }; 157 158 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 159 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 160 CLK_MAP(SCLK, PPCLK_GFXCLK), 161 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 162 CLK_MAP(FCLK, PPCLK_FCLK), 163 CLK_MAP(UCLK, PPCLK_UCLK), 164 CLK_MAP(MCLK, PPCLK_UCLK), 165 CLK_MAP(DCLK, PPCLK_DCLK), 166 CLK_MAP(VCLK, PPCLK_VCLK), 167 CLK_MAP(LCLK, PPCLK_LCLK), 168 }; 169 170 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 175 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 176 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 177 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 178 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 179 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 180 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 181 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 182 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 183 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 184 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 185 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 186 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 187 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 188 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 189 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 190 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 191 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 192 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 193 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 194 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 195 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 196 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 197 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 198 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 199 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN), 200 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 201 }; 202 203 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 204 TAB_MAP(PPTABLE), 205 TAB_MAP(AVFS_PSM_DEBUG), 206 TAB_MAP(AVFS_FUSE_OVERRIDE), 207 TAB_MAP(PMSTATUSLOG), 208 TAB_MAP(SMU_METRICS), 209 TAB_MAP(DRIVER_SMU_CONFIG), 210 TAB_MAP(I2C_COMMANDS), 211 TAB_MAP(ECCINFO), 212 }; 213 214 static const uint8_t aldebaran_throttler_map[] = { 215 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 216 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 217 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 218 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 219 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT), 220 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), 221 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 222 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 223 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 224 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 225 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 226 }; 227 228 static int aldebaran_tables_init(struct smu_context *smu) 229 { 230 struct smu_table_context *smu_table = &smu->smu_table; 231 struct smu_table *tables = smu_table->tables; 232 233 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 235 236 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 237 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 238 239 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 240 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 241 242 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 243 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 244 245 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 246 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 247 248 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 249 if (!smu_table->metrics_table) 250 return -ENOMEM; 251 smu_table->metrics_time = 0; 252 253 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 254 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 255 if (!smu_table->gpu_metrics_table) { 256 kfree(smu_table->metrics_table); 257 return -ENOMEM; 258 } 259 260 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 261 if (!smu_table->ecc_table) 262 return -ENOMEM; 263 264 return 0; 265 } 266 267 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 268 { 269 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 270 271 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 272 GFP_KERNEL); 273 if (!smu_dpm->dpm_context) 274 return -ENOMEM; 275 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 276 277 return 0; 278 } 279 280 static int aldebaran_init_smc_tables(struct smu_context *smu) 281 { 282 int ret = 0; 283 284 ret = aldebaran_tables_init(smu); 285 if (ret) 286 return ret; 287 288 ret = aldebaran_allocate_dpm_context(smu); 289 if (ret) 290 return ret; 291 292 return smu_v13_0_init_smc_tables(smu); 293 } 294 295 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 296 uint32_t *feature_mask, uint32_t num) 297 { 298 if (num > 2) 299 return -EINVAL; 300 301 /* pptable will handle the features to enable */ 302 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 303 304 return 0; 305 } 306 307 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 308 { 309 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 310 struct smu_13_0_dpm_table *dpm_table = NULL; 311 PPTable_t *pptable = smu->smu_table.driver_pptable; 312 int ret = 0; 313 314 /* socclk dpm table setup */ 315 dpm_table = &dpm_context->dpm_tables.soc_table; 316 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 317 ret = smu_v13_0_set_single_dpm_table(smu, 318 SMU_SOCCLK, 319 dpm_table); 320 if (ret) 321 return ret; 322 } else { 323 dpm_table->count = 1; 324 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 325 dpm_table->dpm_levels[0].enabled = true; 326 dpm_table->min = dpm_table->dpm_levels[0].value; 327 dpm_table->max = dpm_table->dpm_levels[0].value; 328 } 329 330 /* gfxclk dpm table setup */ 331 dpm_table = &dpm_context->dpm_tables.gfx_table; 332 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 333 /* in the case of gfxclk, only fine-grained dpm is honored */ 334 dpm_table->count = 2; 335 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 336 dpm_table->dpm_levels[0].enabled = true; 337 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 338 dpm_table->dpm_levels[1].enabled = true; 339 dpm_table->min = dpm_table->dpm_levels[0].value; 340 dpm_table->max = dpm_table->dpm_levels[1].value; 341 } else { 342 dpm_table->count = 1; 343 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 344 dpm_table->dpm_levels[0].enabled = true; 345 dpm_table->min = dpm_table->dpm_levels[0].value; 346 dpm_table->max = dpm_table->dpm_levels[0].value; 347 } 348 349 /* memclk dpm table setup */ 350 dpm_table = &dpm_context->dpm_tables.uclk_table; 351 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 352 ret = smu_v13_0_set_single_dpm_table(smu, 353 SMU_UCLK, 354 dpm_table); 355 if (ret) 356 return ret; 357 } else { 358 dpm_table->count = 1; 359 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 360 dpm_table->dpm_levels[0].enabled = true; 361 dpm_table->min = dpm_table->dpm_levels[0].value; 362 dpm_table->max = dpm_table->dpm_levels[0].value; 363 } 364 365 /* fclk dpm table setup */ 366 dpm_table = &dpm_context->dpm_tables.fclk_table; 367 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 368 ret = smu_v13_0_set_single_dpm_table(smu, 369 SMU_FCLK, 370 dpm_table); 371 if (ret) 372 return ret; 373 } else { 374 dpm_table->count = 1; 375 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 376 dpm_table->dpm_levels[0].enabled = true; 377 dpm_table->min = dpm_table->dpm_levels[0].value; 378 dpm_table->max = dpm_table->dpm_levels[0].value; 379 } 380 381 return 0; 382 } 383 384 static int aldebaran_check_powerplay_table(struct smu_context *smu) 385 { 386 struct smu_table_context *table_context = &smu->smu_table; 387 struct smu_13_0_powerplay_table *powerplay_table = 388 table_context->power_play_table; 389 390 table_context->thermal_controller_type = 391 powerplay_table->thermal_controller_type; 392 393 return 0; 394 } 395 396 static int aldebaran_store_powerplay_table(struct smu_context *smu) 397 { 398 struct smu_table_context *table_context = &smu->smu_table; 399 struct smu_13_0_powerplay_table *powerplay_table = 400 table_context->power_play_table; 401 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 402 sizeof(PPTable_t)); 403 404 return 0; 405 } 406 407 static int aldebaran_append_powerplay_table(struct smu_context *smu) 408 { 409 struct smu_table_context *table_context = &smu->smu_table; 410 PPTable_t *smc_pptable = table_context->driver_pptable; 411 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 412 int index, ret; 413 414 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 415 smc_dpm_info); 416 417 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 418 (uint8_t **)&smc_dpm_table); 419 if (ret) 420 return ret; 421 422 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 423 smc_dpm_table->table_header.format_revision, 424 smc_dpm_table->table_header.content_revision); 425 426 if ((smc_dpm_table->table_header.format_revision == 4) && 427 (smc_dpm_table->table_header.content_revision == 10)) 428 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved, 429 smc_dpm_table, GfxMaxCurrent); 430 return 0; 431 } 432 433 static int aldebaran_setup_pptable(struct smu_context *smu) 434 { 435 int ret = 0; 436 437 /* VBIOS pptable is the first choice */ 438 smu->smu_table.boot_values.pp_table_id = 0; 439 440 ret = smu_v13_0_setup_pptable(smu); 441 if (ret) 442 return ret; 443 444 ret = aldebaran_store_powerplay_table(smu); 445 if (ret) 446 return ret; 447 448 ret = aldebaran_append_powerplay_table(smu); 449 if (ret) 450 return ret; 451 452 ret = aldebaran_check_powerplay_table(smu); 453 if (ret) 454 return ret; 455 456 return ret; 457 } 458 459 static bool aldebaran_is_primary(struct smu_context *smu) 460 { 461 struct amdgpu_device *adev = smu->adev; 462 463 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) 464 return adev->smuio.funcs->get_die_id(adev) == 0; 465 466 return true; 467 } 468 469 static int aldebaran_run_board_btc(struct smu_context *smu) 470 { 471 u32 smu_version; 472 int ret; 473 474 if (!aldebaran_is_primary(smu)) 475 return 0; 476 477 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 478 if (ret) { 479 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 480 return ret; 481 } 482 if (smu_version <= 0x00441d00) 483 return 0; 484 485 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL); 486 if (ret) 487 dev_err(smu->adev->dev, "Board power calibration failed!\n"); 488 489 return ret; 490 } 491 492 static int aldebaran_run_btc(struct smu_context *smu) 493 { 494 int ret; 495 496 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 497 if (ret) 498 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 499 else 500 ret = aldebaran_run_board_btc(smu); 501 502 return ret; 503 } 504 505 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 506 { 507 struct smu_13_0_dpm_context *dpm_context = 508 smu->smu_dpm.dpm_context; 509 struct smu_13_0_dpm_table *gfx_table = 510 &dpm_context->dpm_tables.gfx_table; 511 struct smu_13_0_dpm_table *mem_table = 512 &dpm_context->dpm_tables.uclk_table; 513 struct smu_13_0_dpm_table *soc_table = 514 &dpm_context->dpm_tables.soc_table; 515 struct smu_umd_pstate_table *pstate_table = 516 &smu->pstate_table; 517 518 pstate_table->gfxclk_pstate.min = gfx_table->min; 519 pstate_table->gfxclk_pstate.peak = gfx_table->max; 520 pstate_table->gfxclk_pstate.curr.min = gfx_table->min; 521 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 522 523 pstate_table->uclk_pstate.min = mem_table->min; 524 pstate_table->uclk_pstate.peak = mem_table->max; 525 pstate_table->uclk_pstate.curr.min = mem_table->min; 526 pstate_table->uclk_pstate.curr.max = mem_table->max; 527 528 pstate_table->socclk_pstate.min = soc_table->min; 529 pstate_table->socclk_pstate.peak = soc_table->max; 530 pstate_table->socclk_pstate.curr.min = soc_table->min; 531 pstate_table->socclk_pstate.curr.max = soc_table->max; 532 533 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 534 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 535 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 536 pstate_table->gfxclk_pstate.standard = 537 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 538 pstate_table->uclk_pstate.standard = 539 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 540 pstate_table->socclk_pstate.standard = 541 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 542 } else { 543 pstate_table->gfxclk_pstate.standard = 544 pstate_table->gfxclk_pstate.min; 545 pstate_table->uclk_pstate.standard = 546 pstate_table->uclk_pstate.min; 547 pstate_table->socclk_pstate.standard = 548 pstate_table->socclk_pstate.min; 549 } 550 551 return 0; 552 } 553 554 static int aldebaran_get_clk_table(struct smu_context *smu, 555 struct pp_clock_levels_with_latency *clocks, 556 struct smu_13_0_dpm_table *dpm_table) 557 { 558 int i, count; 559 560 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 561 clocks->num_levels = count; 562 563 for (i = 0; i < count; i++) { 564 clocks->data[i].clocks_in_khz = 565 dpm_table->dpm_levels[i].value * 1000; 566 clocks->data[i].latency_in_us = 0; 567 } 568 569 return 0; 570 } 571 572 static int aldebaran_freqs_in_same_level(int32_t frequency1, 573 int32_t frequency2) 574 { 575 return (abs(frequency1 - frequency2) <= EPSILON); 576 } 577 578 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 579 MetricsMember_t member, 580 uint32_t *value) 581 { 582 struct smu_table_context *smu_table= &smu->smu_table; 583 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 584 int ret = 0; 585 586 ret = smu_cmn_get_metrics_table(smu, 587 NULL, 588 false); 589 if (ret) 590 return ret; 591 592 switch (member) { 593 case METRICS_CURR_GFXCLK: 594 *value = metrics->CurrClock[PPCLK_GFXCLK]; 595 break; 596 case METRICS_CURR_SOCCLK: 597 *value = metrics->CurrClock[PPCLK_SOCCLK]; 598 break; 599 case METRICS_CURR_UCLK: 600 *value = metrics->CurrClock[PPCLK_UCLK]; 601 break; 602 case METRICS_CURR_VCLK: 603 *value = metrics->CurrClock[PPCLK_VCLK]; 604 break; 605 case METRICS_CURR_DCLK: 606 *value = metrics->CurrClock[PPCLK_DCLK]; 607 break; 608 case METRICS_CURR_FCLK: 609 *value = metrics->CurrClock[PPCLK_FCLK]; 610 break; 611 case METRICS_AVERAGE_GFXCLK: 612 *value = metrics->AverageGfxclkFrequency; 613 break; 614 case METRICS_AVERAGE_SOCCLK: 615 *value = metrics->AverageSocclkFrequency; 616 break; 617 case METRICS_AVERAGE_UCLK: 618 *value = metrics->AverageUclkFrequency; 619 break; 620 case METRICS_AVERAGE_GFXACTIVITY: 621 *value = metrics->AverageGfxActivity; 622 break; 623 case METRICS_AVERAGE_MEMACTIVITY: 624 *value = metrics->AverageUclkActivity; 625 break; 626 case METRICS_AVERAGE_SOCKETPOWER: 627 /* Valid power data is available only from primary die */ 628 *value = aldebaran_is_primary(smu) ? 629 metrics->AverageSocketPower << 8 : 630 0; 631 break; 632 case METRICS_TEMPERATURE_EDGE: 633 *value = metrics->TemperatureEdge * 634 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 635 break; 636 case METRICS_TEMPERATURE_HOTSPOT: 637 *value = metrics->TemperatureHotspot * 638 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 639 break; 640 case METRICS_TEMPERATURE_MEM: 641 *value = metrics->TemperatureHBM * 642 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 643 break; 644 case METRICS_TEMPERATURE_VRGFX: 645 *value = metrics->TemperatureVrGfx * 646 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 647 break; 648 case METRICS_TEMPERATURE_VRSOC: 649 *value = metrics->TemperatureVrSoc * 650 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 651 break; 652 case METRICS_TEMPERATURE_VRMEM: 653 *value = metrics->TemperatureVrMem * 654 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 655 break; 656 case METRICS_THROTTLER_STATUS: 657 *value = metrics->ThrottlerStatus; 658 break; 659 case METRICS_UNIQUE_ID_UPPER32: 660 *value = metrics->PublicSerialNumUpper32; 661 break; 662 case METRICS_UNIQUE_ID_LOWER32: 663 *value = metrics->PublicSerialNumLower32; 664 break; 665 default: 666 *value = UINT_MAX; 667 break; 668 } 669 670 return ret; 671 } 672 673 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 674 enum smu_clk_type clk_type, 675 uint32_t *value) 676 { 677 MetricsMember_t member_type; 678 int clk_id = 0; 679 680 if (!value) 681 return -EINVAL; 682 683 clk_id = smu_cmn_to_asic_specific_index(smu, 684 CMN2ASIC_MAPPING_CLK, 685 clk_type); 686 if (clk_id < 0) 687 return -EINVAL; 688 689 switch (clk_id) { 690 case PPCLK_GFXCLK: 691 /* 692 * CurrClock[clk_id] can provide accurate 693 * output only when the dpm feature is enabled. 694 * We can use Average_* for dpm disabled case. 695 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 696 */ 697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 698 member_type = METRICS_CURR_GFXCLK; 699 else 700 member_type = METRICS_AVERAGE_GFXCLK; 701 break; 702 case PPCLK_UCLK: 703 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 704 member_type = METRICS_CURR_UCLK; 705 else 706 member_type = METRICS_AVERAGE_UCLK; 707 break; 708 case PPCLK_SOCCLK: 709 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 710 member_type = METRICS_CURR_SOCCLK; 711 else 712 member_type = METRICS_AVERAGE_SOCCLK; 713 break; 714 case PPCLK_VCLK: 715 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 716 member_type = METRICS_CURR_VCLK; 717 else 718 member_type = METRICS_AVERAGE_VCLK; 719 break; 720 case PPCLK_DCLK: 721 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 722 member_type = METRICS_CURR_DCLK; 723 else 724 member_type = METRICS_AVERAGE_DCLK; 725 break; 726 case PPCLK_FCLK: 727 member_type = METRICS_CURR_FCLK; 728 break; 729 default: 730 return -EINVAL; 731 } 732 733 return aldebaran_get_smu_metrics_data(smu, 734 member_type, 735 value); 736 } 737 738 static int aldebaran_print_clk_levels(struct smu_context *smu, 739 enum smu_clk_type type, char *buf) 740 { 741 int i, now, size = 0; 742 int ret = 0; 743 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 744 struct pp_clock_levels_with_latency clocks; 745 struct smu_13_0_dpm_table *single_dpm_table; 746 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 747 struct smu_13_0_dpm_context *dpm_context = NULL; 748 uint32_t display_levels; 749 uint32_t freq_values[3] = {0}; 750 uint32_t min_clk, max_clk; 751 752 smu_cmn_get_sysfs_buf(&buf, &size); 753 754 if (amdgpu_ras_intr_triggered()) { 755 size += sysfs_emit_at(buf, size, "unavailable\n"); 756 return size; 757 } 758 759 dpm_context = smu_dpm->dpm_context; 760 761 switch (type) { 762 763 case SMU_OD_SCLK: 764 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK"); 765 fallthrough; 766 case SMU_SCLK: 767 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 768 if (ret) { 769 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 770 return ret; 771 } 772 773 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 774 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 775 if (ret) { 776 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 777 return ret; 778 } 779 780 display_levels = clocks.num_levels; 781 782 min_clk = pstate_table->gfxclk_pstate.curr.min; 783 max_clk = pstate_table->gfxclk_pstate.curr.max; 784 785 freq_values[0] = min_clk; 786 freq_values[1] = max_clk; 787 788 /* fine-grained dpm has only 2 levels */ 789 if (now > min_clk && now < max_clk) { 790 display_levels = clocks.num_levels + 1; 791 freq_values[2] = max_clk; 792 freq_values[1] = now; 793 } 794 795 /* 796 * For DPM disabled case, there will be only one clock level. 797 * And it's safe to assume that is always the current clock. 798 */ 799 if (display_levels == clocks.num_levels) { 800 for (i = 0; i < clocks.num_levels; i++) 801 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 802 freq_values[i], 803 (clocks.num_levels == 1) ? 804 "*" : 805 (aldebaran_freqs_in_same_level( 806 freq_values[i], now) ? 807 "*" : 808 "")); 809 } else { 810 for (i = 0; i < display_levels; i++) 811 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 812 freq_values[i], i == 1 ? "*" : ""); 813 } 814 815 break; 816 817 case SMU_OD_MCLK: 818 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK"); 819 fallthrough; 820 case SMU_MCLK: 821 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 822 if (ret) { 823 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 824 return ret; 825 } 826 827 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 828 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 829 if (ret) { 830 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 831 return ret; 832 } 833 834 for (i = 0; i < clocks.num_levels; i++) 835 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 836 i, clocks.data[i].clocks_in_khz / 1000, 837 (clocks.num_levels == 1) ? "*" : 838 (aldebaran_freqs_in_same_level( 839 clocks.data[i].clocks_in_khz / 1000, 840 now) ? "*" : "")); 841 break; 842 843 case SMU_SOCCLK: 844 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 845 if (ret) { 846 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 847 return ret; 848 } 849 850 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 851 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 852 if (ret) { 853 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 854 return ret; 855 } 856 857 for (i = 0; i < clocks.num_levels; i++) 858 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 859 i, clocks.data[i].clocks_in_khz / 1000, 860 (clocks.num_levels == 1) ? "*" : 861 (aldebaran_freqs_in_same_level( 862 clocks.data[i].clocks_in_khz / 1000, 863 now) ? "*" : "")); 864 break; 865 866 case SMU_FCLK: 867 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 868 if (ret) { 869 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 870 return ret; 871 } 872 873 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 874 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 875 if (ret) { 876 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 877 return ret; 878 } 879 880 for (i = 0; i < single_dpm_table->count; i++) 881 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 882 i, single_dpm_table->dpm_levels[i].value, 883 (clocks.num_levels == 1) ? "*" : 884 (aldebaran_freqs_in_same_level( 885 clocks.data[i].clocks_in_khz / 1000, 886 now) ? "*" : "")); 887 break; 888 889 case SMU_VCLK: 890 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); 891 if (ret) { 892 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); 893 return ret; 894 } 895 896 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 897 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 898 if (ret) { 899 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); 900 return ret; 901 } 902 903 for (i = 0; i < single_dpm_table->count; i++) 904 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 905 i, single_dpm_table->dpm_levels[i].value, 906 (clocks.num_levels == 1) ? "*" : 907 (aldebaran_freqs_in_same_level( 908 clocks.data[i].clocks_in_khz / 1000, 909 now) ? "*" : "")); 910 break; 911 912 case SMU_DCLK: 913 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); 914 if (ret) { 915 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); 916 return ret; 917 } 918 919 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 920 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 921 if (ret) { 922 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); 923 return ret; 924 } 925 926 for (i = 0; i < single_dpm_table->count; i++) 927 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 928 i, single_dpm_table->dpm_levels[i].value, 929 (clocks.num_levels == 1) ? "*" : 930 (aldebaran_freqs_in_same_level( 931 clocks.data[i].clocks_in_khz / 1000, 932 now) ? "*" : "")); 933 break; 934 935 default: 936 break; 937 } 938 939 return size; 940 } 941 942 static int aldebaran_upload_dpm_level(struct smu_context *smu, 943 bool max, 944 uint32_t feature_mask, 945 uint32_t level) 946 { 947 struct smu_13_0_dpm_context *dpm_context = 948 smu->smu_dpm.dpm_context; 949 uint32_t freq; 950 int ret = 0; 951 952 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 953 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 954 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 955 ret = smu_cmn_send_smc_msg_with_param(smu, 956 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 957 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 958 NULL); 959 if (ret) { 960 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 961 max ? "max" : "min"); 962 return ret; 963 } 964 } 965 966 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 967 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 968 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 969 ret = smu_cmn_send_smc_msg_with_param(smu, 970 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 971 (PPCLK_UCLK << 16) | (freq & 0xffff), 972 NULL); 973 if (ret) { 974 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 975 max ? "max" : "min"); 976 return ret; 977 } 978 } 979 980 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 981 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 982 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 983 ret = smu_cmn_send_smc_msg_with_param(smu, 984 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 985 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 986 NULL); 987 if (ret) { 988 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 989 max ? "max" : "min"); 990 return ret; 991 } 992 } 993 994 return ret; 995 } 996 997 static int aldebaran_force_clk_levels(struct smu_context *smu, 998 enum smu_clk_type type, uint32_t mask) 999 { 1000 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1001 struct smu_13_0_dpm_table *single_dpm_table = NULL; 1002 uint32_t soft_min_level, soft_max_level; 1003 int ret = 0; 1004 1005 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1006 soft_max_level = mask ? (fls(mask) - 1) : 0; 1007 1008 switch (type) { 1009 case SMU_SCLK: 1010 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1011 if (soft_max_level >= single_dpm_table->count) { 1012 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 1013 soft_max_level, single_dpm_table->count - 1); 1014 ret = -EINVAL; 1015 break; 1016 } 1017 1018 ret = aldebaran_upload_dpm_level(smu, 1019 false, 1020 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1021 soft_min_level); 1022 if (ret) { 1023 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1024 break; 1025 } 1026 1027 ret = aldebaran_upload_dpm_level(smu, 1028 true, 1029 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1030 soft_max_level); 1031 if (ret) 1032 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1033 1034 break; 1035 1036 case SMU_MCLK: 1037 case SMU_SOCCLK: 1038 case SMU_FCLK: 1039 /* 1040 * Should not arrive here since aldebaran does not 1041 * support mclk/socclk/fclk softmin/softmax settings 1042 */ 1043 ret = -EINVAL; 1044 break; 1045 1046 default: 1047 break; 1048 } 1049 1050 return ret; 1051 } 1052 1053 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 1054 struct smu_temperature_range *range) 1055 { 1056 struct smu_table_context *table_context = &smu->smu_table; 1057 struct smu_13_0_powerplay_table *powerplay_table = 1058 table_context->power_play_table; 1059 PPTable_t *pptable = smu->smu_table.driver_pptable; 1060 1061 if (!range) 1062 return -EINVAL; 1063 1064 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1065 1066 range->hotspot_crit_max = pptable->ThotspotLimit * 1067 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1068 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1069 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1070 range->mem_crit_max = pptable->TmemLimit * 1071 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1072 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1073 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1074 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1075 1076 return 0; 1077 } 1078 1079 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 1080 enum amd_pp_sensors sensor, 1081 uint32_t *value) 1082 { 1083 int ret = 0; 1084 1085 if (!value) 1086 return -EINVAL; 1087 1088 switch (sensor) { 1089 case AMDGPU_PP_SENSOR_GPU_LOAD: 1090 ret = aldebaran_get_smu_metrics_data(smu, 1091 METRICS_AVERAGE_GFXACTIVITY, 1092 value); 1093 break; 1094 case AMDGPU_PP_SENSOR_MEM_LOAD: 1095 ret = aldebaran_get_smu_metrics_data(smu, 1096 METRICS_AVERAGE_MEMACTIVITY, 1097 value); 1098 break; 1099 default: 1100 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 1101 return -EINVAL; 1102 } 1103 1104 return ret; 1105 } 1106 1107 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value) 1108 { 1109 if (!value) 1110 return -EINVAL; 1111 1112 return aldebaran_get_smu_metrics_data(smu, 1113 METRICS_AVERAGE_SOCKETPOWER, 1114 value); 1115 } 1116 1117 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 1118 enum amd_pp_sensors sensor, 1119 uint32_t *value) 1120 { 1121 int ret = 0; 1122 1123 if (!value) 1124 return -EINVAL; 1125 1126 switch (sensor) { 1127 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1128 ret = aldebaran_get_smu_metrics_data(smu, 1129 METRICS_TEMPERATURE_HOTSPOT, 1130 value); 1131 break; 1132 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1133 ret = aldebaran_get_smu_metrics_data(smu, 1134 METRICS_TEMPERATURE_EDGE, 1135 value); 1136 break; 1137 case AMDGPU_PP_SENSOR_MEM_TEMP: 1138 ret = aldebaran_get_smu_metrics_data(smu, 1139 METRICS_TEMPERATURE_MEM, 1140 value); 1141 break; 1142 default: 1143 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1144 return -EINVAL; 1145 } 1146 1147 return ret; 1148 } 1149 1150 static int aldebaran_read_sensor(struct smu_context *smu, 1151 enum amd_pp_sensors sensor, 1152 void *data, uint32_t *size) 1153 { 1154 int ret = 0; 1155 1156 if (amdgpu_ras_intr_triggered()) 1157 return 0; 1158 1159 if (!data || !size) 1160 return -EINVAL; 1161 1162 switch (sensor) { 1163 case AMDGPU_PP_SENSOR_MEM_LOAD: 1164 case AMDGPU_PP_SENSOR_GPU_LOAD: 1165 ret = aldebaran_get_current_activity_percent(smu, 1166 sensor, 1167 (uint32_t *)data); 1168 *size = 4; 1169 break; 1170 case AMDGPU_PP_SENSOR_GPU_POWER: 1171 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data); 1172 *size = 4; 1173 break; 1174 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1175 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1176 case AMDGPU_PP_SENSOR_MEM_TEMP: 1177 ret = aldebaran_thermal_get_temperature(smu, sensor, 1178 (uint32_t *)data); 1179 *size = 4; 1180 break; 1181 case AMDGPU_PP_SENSOR_GFX_MCLK: 1182 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1183 /* the output clock frequency in 10K unit */ 1184 *(uint32_t *)data *= 100; 1185 *size = 4; 1186 break; 1187 case AMDGPU_PP_SENSOR_GFX_SCLK: 1188 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1189 *(uint32_t *)data *= 100; 1190 *size = 4; 1191 break; 1192 case AMDGPU_PP_SENSOR_VDDGFX: 1193 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1194 *size = 4; 1195 break; 1196 default: 1197 ret = -EOPNOTSUPP; 1198 break; 1199 } 1200 1201 return ret; 1202 } 1203 1204 static int aldebaran_get_power_limit(struct smu_context *smu, 1205 uint32_t *current_power_limit, 1206 uint32_t *default_power_limit, 1207 uint32_t *max_power_limit) 1208 { 1209 PPTable_t *pptable = smu->smu_table.driver_pptable; 1210 uint32_t power_limit = 0; 1211 int ret; 1212 1213 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1214 if (current_power_limit) 1215 *current_power_limit = 0; 1216 if (default_power_limit) 1217 *default_power_limit = 0; 1218 if (max_power_limit) 1219 *max_power_limit = 0; 1220 1221 dev_warn(smu->adev->dev, 1222 "PPT feature is not enabled, power values can't be fetched."); 1223 1224 return 0; 1225 } 1226 1227 /* Valid power data is available only from primary die. 1228 * For secondary die show the value as 0. 1229 */ 1230 if (aldebaran_is_primary(smu)) { 1231 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, 1232 &power_limit); 1233 1234 if (ret) { 1235 /* the last hope to figure out the ppt limit */ 1236 if (!pptable) { 1237 dev_err(smu->adev->dev, 1238 "Cannot get PPT limit due to pptable missing!"); 1239 return -EINVAL; 1240 } 1241 power_limit = pptable->PptLimit; 1242 } 1243 } 1244 1245 if (current_power_limit) 1246 *current_power_limit = power_limit; 1247 if (default_power_limit) 1248 *default_power_limit = power_limit; 1249 1250 if (max_power_limit) { 1251 if (pptable) 1252 *max_power_limit = pptable->PptLimit; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static int aldebaran_set_power_limit(struct smu_context *smu, 1259 enum smu_ppt_limit_type limit_type, 1260 uint32_t limit) 1261 { 1262 /* Power limit can be set only through primary die */ 1263 if (aldebaran_is_primary(smu)) 1264 return smu_v13_0_set_power_limit(smu, limit_type, limit); 1265 1266 return -EINVAL; 1267 } 1268 1269 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1270 { 1271 int ret; 1272 1273 ret = smu_v13_0_system_features_control(smu, enable); 1274 if (!ret && enable) 1275 ret = aldebaran_run_btc(smu); 1276 1277 return ret; 1278 } 1279 1280 static int aldebaran_set_performance_level(struct smu_context *smu, 1281 enum amd_dpm_forced_level level) 1282 { 1283 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1284 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1285 struct smu_13_0_dpm_table *gfx_table = 1286 &dpm_context->dpm_tables.gfx_table; 1287 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1288 1289 /* Disable determinism if switching to another mode */ 1290 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && 1291 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { 1292 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1293 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 1294 } 1295 1296 switch (level) { 1297 1298 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1299 return 0; 1300 1301 case AMD_DPM_FORCED_LEVEL_HIGH: 1302 case AMD_DPM_FORCED_LEVEL_LOW: 1303 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1304 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1305 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1306 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1307 default: 1308 break; 1309 } 1310 1311 return smu_v13_0_set_performance_level(smu, level); 1312 } 1313 1314 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1315 enum smu_clk_type clk_type, 1316 uint32_t min, 1317 uint32_t max) 1318 { 1319 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1320 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1321 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1322 struct amdgpu_device *adev = smu->adev; 1323 uint32_t min_clk; 1324 uint32_t max_clk; 1325 int ret = 0; 1326 1327 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1328 return -EINVAL; 1329 1330 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1331 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1332 return -EINVAL; 1333 1334 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1335 if (min >= max) { 1336 dev_err(smu->adev->dev, 1337 "Minimum GFX clk should be less than the maximum allowed clock\n"); 1338 return -EINVAL; 1339 } 1340 1341 if ((min == pstate_table->gfxclk_pstate.curr.min) && 1342 (max == pstate_table->gfxclk_pstate.curr.max)) 1343 return 0; 1344 1345 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, 1346 min, max); 1347 if (!ret) { 1348 pstate_table->gfxclk_pstate.curr.min = min; 1349 pstate_table->gfxclk_pstate.curr.max = max; 1350 } 1351 1352 return ret; 1353 } 1354 1355 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1356 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1357 (max > dpm_context->dpm_tables.gfx_table.max)) { 1358 dev_warn(adev->dev, 1359 "Invalid max frequency %d MHz specified for determinism\n", max); 1360 return -EINVAL; 1361 } 1362 1363 /* Restore default min/max clocks and enable determinism */ 1364 min_clk = dpm_context->dpm_tables.gfx_table.min; 1365 max_clk = dpm_context->dpm_tables.gfx_table.max; 1366 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1367 if (!ret) { 1368 usleep_range(500, 1000); 1369 ret = smu_cmn_send_smc_msg_with_param(smu, 1370 SMU_MSG_EnableDeterminism, 1371 max, NULL); 1372 if (ret) { 1373 dev_err(adev->dev, 1374 "Failed to enable determinism at GFX clock %d MHz\n", max); 1375 } else { 1376 pstate_table->gfxclk_pstate.curr.min = min_clk; 1377 pstate_table->gfxclk_pstate.curr.max = max; 1378 } 1379 } 1380 } 1381 1382 return ret; 1383 } 1384 1385 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1386 long input[], uint32_t size) 1387 { 1388 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1389 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1390 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1391 uint32_t min_clk; 1392 uint32_t max_clk; 1393 int ret = 0; 1394 1395 /* Only allowed in manual or determinism mode */ 1396 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1397 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1398 return -EINVAL; 1399 1400 switch (type) { 1401 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1402 if (size != 2) { 1403 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1404 return -EINVAL; 1405 } 1406 1407 if (input[0] == 0) { 1408 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1409 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1410 input[1], dpm_context->dpm_tables.gfx_table.min); 1411 pstate_table->gfxclk_pstate.custom.min = 1412 pstate_table->gfxclk_pstate.curr.min; 1413 return -EINVAL; 1414 } 1415 1416 pstate_table->gfxclk_pstate.custom.min = input[1]; 1417 } else if (input[0] == 1) { 1418 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1419 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1420 input[1], dpm_context->dpm_tables.gfx_table.max); 1421 pstate_table->gfxclk_pstate.custom.max = 1422 pstate_table->gfxclk_pstate.curr.max; 1423 return -EINVAL; 1424 } 1425 1426 pstate_table->gfxclk_pstate.custom.max = input[1]; 1427 } else { 1428 return -EINVAL; 1429 } 1430 break; 1431 case PP_OD_RESTORE_DEFAULT_TABLE: 1432 if (size != 0) { 1433 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1434 return -EINVAL; 1435 } else { 1436 /* Use the default frequencies for manual and determinism mode */ 1437 min_clk = dpm_context->dpm_tables.gfx_table.min; 1438 max_clk = dpm_context->dpm_tables.gfx_table.max; 1439 1440 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1441 } 1442 break; 1443 case PP_OD_COMMIT_DPM_TABLE: 1444 if (size != 0) { 1445 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1446 return -EINVAL; 1447 } else { 1448 if (!pstate_table->gfxclk_pstate.custom.min) 1449 pstate_table->gfxclk_pstate.custom.min = 1450 pstate_table->gfxclk_pstate.curr.min; 1451 1452 if (!pstate_table->gfxclk_pstate.custom.max) 1453 pstate_table->gfxclk_pstate.custom.max = 1454 pstate_table->gfxclk_pstate.curr.max; 1455 1456 min_clk = pstate_table->gfxclk_pstate.custom.min; 1457 max_clk = pstate_table->gfxclk_pstate.custom.max; 1458 1459 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1460 } 1461 break; 1462 default: 1463 return -ENOSYS; 1464 } 1465 1466 return ret; 1467 } 1468 1469 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1470 { 1471 int ret; 1472 uint64_t feature_enabled; 1473 1474 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1475 if (ret) 1476 return false; 1477 return !!(feature_enabled & SMC_DPM_FEATURE); 1478 } 1479 1480 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1481 struct i2c_msg *msg, int num_msgs) 1482 { 1483 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 1484 struct amdgpu_device *adev = smu_i2c->adev; 1485 struct smu_context *smu = adev->powerplay.pp_handle; 1486 struct smu_table_context *smu_table = &smu->smu_table; 1487 struct smu_table *table = &smu_table->driver_table; 1488 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1489 int i, j, r, c; 1490 u16 dir; 1491 1492 if (!adev->pm.dpm_enabled) 1493 return -EBUSY; 1494 1495 req = kzalloc(sizeof(*req), GFP_KERNEL); 1496 if (!req) 1497 return -ENOMEM; 1498 1499 req->I2CcontrollerPort = smu_i2c->port; 1500 req->I2CSpeed = I2C_SPEED_FAST_400K; 1501 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1502 dir = msg[0].flags & I2C_M_RD; 1503 1504 for (c = i = 0; i < num_msgs; i++) { 1505 for (j = 0; j < msg[i].len; j++, c++) { 1506 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1507 1508 if (!(msg[i].flags & I2C_M_RD)) { 1509 /* write */ 1510 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1511 cmd->ReadWriteData = msg[i].buf[j]; 1512 } 1513 1514 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1515 /* The direction changes. 1516 */ 1517 dir = msg[i].flags & I2C_M_RD; 1518 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1519 } 1520 1521 req->NumCmds++; 1522 1523 /* 1524 * Insert STOP if we are at the last byte of either last 1525 * message for the transaction or the client explicitly 1526 * requires a STOP at this particular message. 1527 */ 1528 if ((j == msg[i].len - 1) && 1529 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1530 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1531 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1532 } 1533 } 1534 } 1535 mutex_lock(&adev->pm.mutex); 1536 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1537 mutex_unlock(&adev->pm.mutex); 1538 if (r) 1539 goto fail; 1540 1541 for (c = i = 0; i < num_msgs; i++) { 1542 if (!(msg[i].flags & I2C_M_RD)) { 1543 c += msg[i].len; 1544 continue; 1545 } 1546 for (j = 0; j < msg[i].len; j++, c++) { 1547 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1548 1549 msg[i].buf[j] = cmd->ReadWriteData; 1550 } 1551 } 1552 r = num_msgs; 1553 fail: 1554 kfree(req); 1555 return r; 1556 } 1557 1558 static u32 aldebaran_i2c_func(struct i2c_adapter *adap) 1559 { 1560 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1561 } 1562 1563 1564 static const struct i2c_algorithm aldebaran_i2c_algo = { 1565 .master_xfer = aldebaran_i2c_xfer, 1566 .functionality = aldebaran_i2c_func, 1567 }; 1568 1569 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = { 1570 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1571 .max_read_len = MAX_SW_I2C_COMMANDS, 1572 .max_write_len = MAX_SW_I2C_COMMANDS, 1573 .max_comb_1st_msg_len = 2, 1574 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1575 }; 1576 1577 static int aldebaran_i2c_control_init(struct smu_context *smu) 1578 { 1579 struct amdgpu_device *adev = smu->adev; 1580 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0]; 1581 struct i2c_adapter *control = &smu_i2c->adapter; 1582 int res; 1583 1584 smu_i2c->adev = adev; 1585 smu_i2c->port = 0; 1586 mutex_init(&smu_i2c->mutex); 1587 control->owner = THIS_MODULE; 1588 control->class = I2C_CLASS_SPD; 1589 control->dev.parent = &adev->pdev->dev; 1590 control->algo = &aldebaran_i2c_algo; 1591 snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); 1592 control->quirks = &aldebaran_i2c_control_quirks; 1593 i2c_set_adapdata(control, smu_i2c); 1594 1595 res = i2c_add_adapter(control); 1596 if (res) { 1597 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1598 goto Out_err; 1599 } 1600 1601 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1602 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1603 1604 return 0; 1605 Out_err: 1606 i2c_del_adapter(control); 1607 1608 return res; 1609 } 1610 1611 static void aldebaran_i2c_control_fini(struct smu_context *smu) 1612 { 1613 struct amdgpu_device *adev = smu->adev; 1614 int i; 1615 1616 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1617 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1618 struct i2c_adapter *control = &smu_i2c->adapter; 1619 1620 i2c_del_adapter(control); 1621 } 1622 adev->pm.ras_eeprom_i2c_bus = NULL; 1623 adev->pm.fru_eeprom_i2c_bus = NULL; 1624 } 1625 1626 static void aldebaran_get_unique_id(struct smu_context *smu) 1627 { 1628 struct amdgpu_device *adev = smu->adev; 1629 uint32_t upper32 = 0, lower32 = 0; 1630 1631 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32)) 1632 goto out; 1633 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32)) 1634 goto out; 1635 1636 out: 1637 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1638 if (adev->serial[0] == '\0') 1639 sprintf(adev->serial, "%016llx", adev->unique_id); 1640 } 1641 1642 static bool aldebaran_is_baco_supported(struct smu_context *smu) 1643 { 1644 /* aldebaran is not support baco */ 1645 1646 return false; 1647 } 1648 1649 static int aldebaran_set_df_cstate(struct smu_context *smu, 1650 enum pp_df_cstate state) 1651 { 1652 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1653 } 1654 1655 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) 1656 { 1657 struct amdgpu_device *adev = smu->adev; 1658 1659 /* The message only works on master die and NACK will be sent 1660 back for other dies, only send it on master die */ 1661 if (!adev->smuio.funcs->get_socket_id(adev) && 1662 !adev->smuio.funcs->get_die_id(adev)) 1663 return smu_cmn_send_smc_msg_with_param(smu, 1664 SMU_MSG_GmiPwrDnControl, 1665 en ? 0 : 1, 1666 NULL); 1667 else 1668 return 0; 1669 } 1670 1671 static const struct throttling_logging_label { 1672 uint32_t feature_mask; 1673 const char *label; 1674 } logging_label[] = { 1675 {(1U << THROTTLER_TEMP_GPU_BIT), "GPU"}, 1676 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1677 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1678 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1679 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1680 }; 1681 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1682 { 1683 int ret; 1684 int throttler_idx, throtting_events = 0, buf_idx = 0; 1685 struct amdgpu_device *adev = smu->adev; 1686 uint32_t throttler_status; 1687 char log_buf[256]; 1688 1689 ret = aldebaran_get_smu_metrics_data(smu, 1690 METRICS_THROTTLER_STATUS, 1691 &throttler_status); 1692 if (ret) 1693 return; 1694 1695 memset(log_buf, 0, sizeof(log_buf)); 1696 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1697 throttler_idx++) { 1698 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1699 throtting_events++; 1700 buf_idx += snprintf(log_buf + buf_idx, 1701 sizeof(log_buf) - buf_idx, 1702 "%s%s", 1703 throtting_events > 1 ? " and " : "", 1704 logging_label[throttler_idx].label); 1705 if (buf_idx >= sizeof(log_buf)) { 1706 dev_err(adev->dev, "buffer overflow!\n"); 1707 log_buf[sizeof(log_buf) - 1] = '\0'; 1708 break; 1709 } 1710 } 1711 } 1712 1713 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1714 log_buf); 1715 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 1716 smu_cmn_get_indep_throttler_status(throttler_status, 1717 aldebaran_throttler_map)); 1718 } 1719 1720 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1721 { 1722 struct amdgpu_device *adev = smu->adev; 1723 uint32_t esm_ctrl; 1724 1725 /* TODO: confirm this on real target */ 1726 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1727 if ((esm_ctrl >> 15) & 0x1FFFF) 1728 return (((esm_ctrl >> 8) & 0x3F) + 128); 1729 1730 return smu_v13_0_get_current_pcie_link_speed(smu); 1731 } 1732 1733 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1734 void **table) 1735 { 1736 struct smu_table_context *smu_table = &smu->smu_table; 1737 struct gpu_metrics_v1_3 *gpu_metrics = 1738 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1739 SmuMetrics_t metrics; 1740 int i, ret = 0; 1741 1742 ret = smu_cmn_get_metrics_table(smu, 1743 &metrics, 1744 true); 1745 if (ret) 1746 return ret; 1747 1748 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1749 1750 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1751 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1752 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1753 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1754 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1755 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1756 1757 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1758 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1759 gpu_metrics->average_mm_activity = 0; 1760 1761 /* Valid power data is available only from primary die */ 1762 if (aldebaran_is_primary(smu)) { 1763 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1764 gpu_metrics->energy_accumulator = 1765 (uint64_t)metrics.EnergyAcc64bitHigh << 32 | 1766 metrics.EnergyAcc64bitLow; 1767 } else { 1768 gpu_metrics->average_socket_power = 0; 1769 gpu_metrics->energy_accumulator = 0; 1770 } 1771 1772 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1773 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1774 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1775 gpu_metrics->average_vclk0_frequency = 0; 1776 gpu_metrics->average_dclk0_frequency = 0; 1777 1778 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1779 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1780 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1781 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1782 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1783 1784 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1785 gpu_metrics->indep_throttle_status = 1786 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1787 aldebaran_throttler_map); 1788 1789 gpu_metrics->current_fan_speed = 0; 1790 1791 gpu_metrics->pcie_link_width = 1792 smu_v13_0_get_current_pcie_link_width(smu); 1793 gpu_metrics->pcie_link_speed = 1794 aldebaran_get_current_pcie_link_speed(smu); 1795 1796 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1797 1798 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1799 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1800 1801 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1802 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1803 1804 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) | 1805 metrics.TimeStampLow; 1806 1807 *table = (void *)gpu_metrics; 1808 1809 return sizeof(struct gpu_metrics_v1_3); 1810 } 1811 1812 static int aldebaran_check_ecc_table_support(struct smu_context *smu, 1813 int *ecctable_version) 1814 { 1815 uint32_t if_version = 0xff, smu_version = 0xff; 1816 int ret = 0; 1817 1818 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 1819 if (ret) { 1820 /* return not support if failed get smu_version */ 1821 ret = -EOPNOTSUPP; 1822 } 1823 1824 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) 1825 ret = -EOPNOTSUPP; 1826 else if (smu_version >= SUPPORT_ECCTABLE_SMU_VERSION && 1827 smu_version < SUPPORT_ECCTABLE_V2_SMU_VERSION) 1828 *ecctable_version = 1; 1829 else 1830 *ecctable_version = 2; 1831 1832 return ret; 1833 } 1834 1835 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, 1836 void *table) 1837 { 1838 struct smu_table_context *smu_table = &smu->smu_table; 1839 EccInfoTable_t *ecc_table = NULL; 1840 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 1841 int i, ret = 0; 1842 int table_version = 0; 1843 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 1844 1845 ret = aldebaran_check_ecc_table_support(smu, &table_version); 1846 if (ret) 1847 return ret; 1848 1849 ret = smu_cmn_update_table(smu, 1850 SMU_TABLE_ECCINFO, 1851 0, 1852 smu_table->ecc_table, 1853 false); 1854 if (ret) { 1855 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 1856 return ret; 1857 } 1858 1859 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 1860 1861 if (table_version == 1) { 1862 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1863 ecc_info_per_channel = &(eccinfo->ecc[i]); 1864 ecc_info_per_channel->ce_count_lo_chip = 1865 ecc_table->EccInfo[i].ce_count_lo_chip; 1866 ecc_info_per_channel->ce_count_hi_chip = 1867 ecc_table->EccInfo[i].ce_count_hi_chip; 1868 ecc_info_per_channel->mca_umc_status = 1869 ecc_table->EccInfo[i].mca_umc_status; 1870 ecc_info_per_channel->mca_umc_addr = 1871 ecc_table->EccInfo[i].mca_umc_addr; 1872 } 1873 } else if (table_version == 2) { 1874 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1875 ecc_info_per_channel = &(eccinfo->ecc[i]); 1876 ecc_info_per_channel->ce_count_lo_chip = 1877 ecc_table->EccInfo_V2[i].ce_count_lo_chip; 1878 ecc_info_per_channel->ce_count_hi_chip = 1879 ecc_table->EccInfo_V2[i].ce_count_hi_chip; 1880 ecc_info_per_channel->mca_umc_status = 1881 ecc_table->EccInfo_V2[i].mca_umc_status; 1882 ecc_info_per_channel->mca_umc_addr = 1883 ecc_table->EccInfo_V2[i].mca_umc_addr; 1884 ecc_info_per_channel->mca_ceumc_addr = 1885 ecc_table->EccInfo_V2[i].mca_ceumc_addr; 1886 } 1887 eccinfo->record_ce_addr_supported = 1; 1888 } 1889 1890 return ret; 1891 } 1892 1893 static int aldebaran_mode1_reset(struct smu_context *smu) 1894 { 1895 u32 smu_version, fatal_err, param; 1896 int ret = 0; 1897 struct amdgpu_device *adev = smu->adev; 1898 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1899 1900 fatal_err = 0; 1901 param = SMU_RESET_MODE_1; 1902 1903 /* 1904 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 1905 */ 1906 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1907 if (smu_version < 0x00440700) { 1908 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1909 } 1910 else { 1911 /* fatal error triggered by ras, PMFW supports the flag 1912 from 68.44.0 */ 1913 if ((smu_version >= 0x00442c00) && ras && 1914 atomic_read(&ras->in_recovery)) 1915 fatal_err = 1; 1916 1917 param |= (fatal_err << 16); 1918 ret = smu_cmn_send_smc_msg_with_param(smu, 1919 SMU_MSG_GfxDeviceDriverReset, param, NULL); 1920 } 1921 1922 if (!ret) 1923 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 1924 1925 return ret; 1926 } 1927 1928 static int aldebaran_mode2_reset(struct smu_context *smu) 1929 { 1930 u32 smu_version; 1931 int ret = 0, index; 1932 struct amdgpu_device *adev = smu->adev; 1933 int timeout = 10; 1934 1935 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1936 1937 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1938 SMU_MSG_GfxDeviceDriverReset); 1939 1940 mutex_lock(&smu->message_lock); 1941 if (smu_version >= 0x00441400) { 1942 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1943 /* This is similar to FLR, wait till max FLR timeout */ 1944 msleep(100); 1945 dev_dbg(smu->adev->dev, "restore config space...\n"); 1946 /* Restore the config space saved during init */ 1947 amdgpu_device_load_pci_state(adev->pdev); 1948 1949 dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1950 while (ret == -ETIME && timeout) { 1951 ret = smu_cmn_wait_for_response(smu); 1952 /* Wait a bit more time for getting ACK */ 1953 if (ret == -ETIME) { 1954 --timeout; 1955 usleep_range(500, 1000); 1956 continue; 1957 } 1958 1959 if (ret != 1) { 1960 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n", 1961 SMU_RESET_MODE_2, ret); 1962 goto out; 1963 } 1964 } 1965 1966 } else { 1967 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", 1968 smu_version); 1969 } 1970 1971 if (ret == 1) 1972 ret = 0; 1973 out: 1974 mutex_unlock(&smu->message_lock); 1975 1976 return ret; 1977 } 1978 1979 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 1980 { 1981 int ret = 0; 1982 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL); 1983 1984 return ret; 1985 } 1986 1987 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1988 { 1989 #if 0 1990 struct amdgpu_device *adev = smu->adev; 1991 u32 smu_version; 1992 uint32_t val; 1993 /** 1994 * PM FW version support mode1 reset from 68.07 1995 */ 1996 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1997 if ((smu_version < 0x00440700)) 1998 return false; 1999 /** 2000 * mode1 reset relies on PSP, so we should check if 2001 * PSP is alive. 2002 */ 2003 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 2004 2005 return val != 0x0; 2006 #endif 2007 return true; 2008 } 2009 2010 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 2011 { 2012 return true; 2013 } 2014 2015 static int aldebaran_set_mp1_state(struct smu_context *smu, 2016 enum pp_mp1_state mp1_state) 2017 { 2018 switch (mp1_state) { 2019 case PP_MP1_STATE_UNLOAD: 2020 return smu_cmn_set_mp1_state(smu, mp1_state); 2021 default: 2022 return 0; 2023 } 2024 } 2025 2026 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, 2027 uint32_t size) 2028 { 2029 int ret = 0; 2030 2031 /* message SMU to update the bad page number on SMUBUS */ 2032 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL); 2033 if (ret) 2034 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n", 2035 __func__); 2036 2037 return ret; 2038 } 2039 2040 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu) 2041 { 2042 uint32_t if_version = 0xff, smu_version = 0xff; 2043 int ret = 0; 2044 2045 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 2046 if (ret) { 2047 /* return not support if failed get smu_version */ 2048 ret = -EOPNOTSUPP; 2049 } 2050 2051 if (smu_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION) 2052 ret = -EOPNOTSUPP; 2053 2054 return ret; 2055 } 2056 2057 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu, 2058 uint32_t size) 2059 { 2060 int ret = 0; 2061 2062 ret = aldebaran_check_bad_channel_info_support(smu); 2063 if (ret) 2064 return ret; 2065 2066 /* message SMU to update the bad channel info on SMUBUS */ 2067 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL); 2068 if (ret) 2069 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n", 2070 __func__); 2071 2072 return ret; 2073 } 2074 2075 static const struct pptable_funcs aldebaran_ppt_funcs = { 2076 /* init dpm */ 2077 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 2078 /* dpm/clk tables */ 2079 .set_default_dpm_table = aldebaran_set_default_dpm_table, 2080 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 2081 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 2082 .print_clk_levels = aldebaran_print_clk_levels, 2083 .force_clk_levels = aldebaran_force_clk_levels, 2084 .read_sensor = aldebaran_read_sensor, 2085 .set_performance_level = aldebaran_set_performance_level, 2086 .get_power_limit = aldebaran_get_power_limit, 2087 .is_dpm_running = aldebaran_is_dpm_running, 2088 .get_unique_id = aldebaran_get_unique_id, 2089 .init_microcode = smu_v13_0_init_microcode, 2090 .load_microcode = smu_v13_0_load_microcode, 2091 .fini_microcode = smu_v13_0_fini_microcode, 2092 .init_smc_tables = aldebaran_init_smc_tables, 2093 .fini_smc_tables = smu_v13_0_fini_smc_tables, 2094 .init_power = smu_v13_0_init_power, 2095 .fini_power = smu_v13_0_fini_power, 2096 .check_fw_status = smu_v13_0_check_fw_status, 2097 /* pptable related */ 2098 .setup_pptable = aldebaran_setup_pptable, 2099 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 2100 .check_fw_version = smu_v13_0_check_fw_version, 2101 .write_pptable = smu_cmn_write_pptable, 2102 .set_driver_table_location = smu_v13_0_set_driver_table_location, 2103 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2104 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2105 .system_features_control = aldebaran_system_features_control, 2106 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2107 .send_smc_msg = smu_cmn_send_smc_msg, 2108 .get_enabled_mask = smu_cmn_get_enabled_mask, 2109 .feature_is_enabled = smu_cmn_feature_is_enabled, 2110 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2111 .set_power_limit = aldebaran_set_power_limit, 2112 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 2113 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2114 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2115 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 2116 .register_irq_handler = smu_v13_0_register_irq_handler, 2117 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 2118 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 2119 .baco_is_support= aldebaran_is_baco_supported, 2120 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 2121 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 2122 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 2123 .set_df_cstate = aldebaran_set_df_cstate, 2124 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down, 2125 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 2126 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2127 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2128 .get_gpu_metrics = aldebaran_get_gpu_metrics, 2129 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 2130 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 2131 .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr, 2132 .mode1_reset = aldebaran_mode1_reset, 2133 .set_mp1_state = aldebaran_set_mp1_state, 2134 .mode2_reset = aldebaran_mode2_reset, 2135 .wait_for_event = smu_v13_0_wait_for_event, 2136 .i2c_init = aldebaran_i2c_control_init, 2137 .i2c_fini = aldebaran_i2c_control_fini, 2138 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num, 2139 .get_ecc_info = aldebaran_get_ecc_info, 2140 .send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag, 2141 }; 2142 2143 void aldebaran_set_ppt_funcs(struct smu_context *smu) 2144 { 2145 smu->ppt_funcs = &aldebaran_ppt_funcs; 2146 smu->message_map = aldebaran_message_map; 2147 smu->clock_map = aldebaran_clk_map; 2148 smu->feature_map = aldebaran_feature_mask_map; 2149 smu->table_map = aldebaran_table_map; 2150 smu_v13_0_set_smu_mailbox_registers(smu); 2151 } 2152