1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_dpm.h" 29 #include "amdgpu_smu.h" 30 #include "atomfirmware.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_atombios.h" 33 #include "smu_v13_0.h" 34 #include "smu13_driver_if_aldebaran.h" 35 #include "soc15_common.h" 36 #include "atom.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 61 [smu_feature] = {1, (aldebaran_feature)} 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 73 74 /* possible frequency drift (1Mhz) */ 75 #define EPSILON 1 76 77 #define smnPCIE_ESM_CTRL 0x111003D0 78 79 /* 80 * SMU support ECCTABLE since version 68.42.0, 81 * use this to check ECCTALE feature whether support 82 */ 83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00 84 85 /* 86 * SMU support BAD CHENNEL info MSG since version 68.51.00, 87 * use this to check ECCTALE feature whether support 88 */ 89 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300 90 91 static const struct smu_temperature_range smu13_thermal_policy[] = 92 { 93 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 94 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 95 }; 96 97 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 98 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 99 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 100 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 101 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 102 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 103 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 104 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 105 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 106 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 107 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 108 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 109 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 110 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 111 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 112 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 113 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 114 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 115 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 116 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 117 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 118 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 119 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 120 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 121 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 122 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 123 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 124 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 125 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 126 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 127 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 128 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 129 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 130 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 131 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 132 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 133 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 134 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 135 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 136 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 137 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 138 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 139 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 140 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 141 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 142 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 143 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 144 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 145 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 146 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 147 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0), 148 MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0), 149 MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel, PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel, 0), 150 }; 151 152 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 153 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 154 CLK_MAP(SCLK, PPCLK_GFXCLK), 155 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 156 CLK_MAP(FCLK, PPCLK_FCLK), 157 CLK_MAP(UCLK, PPCLK_UCLK), 158 CLK_MAP(MCLK, PPCLK_UCLK), 159 CLK_MAP(DCLK, PPCLK_DCLK), 160 CLK_MAP(VCLK, PPCLK_VCLK), 161 CLK_MAP(LCLK, PPCLK_LCLK), 162 }; 163 164 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 165 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS), 166 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 167 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 168 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 169 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 170 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 175 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 176 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 177 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 178 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 179 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 180 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 181 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 182 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 183 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 184 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 185 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 186 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 187 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 188 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 189 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 190 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 191 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 192 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 193 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN), 194 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 195 }; 196 197 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 198 TAB_MAP(PPTABLE), 199 TAB_MAP(AVFS_PSM_DEBUG), 200 TAB_MAP(AVFS_FUSE_OVERRIDE), 201 TAB_MAP(PMSTATUSLOG), 202 TAB_MAP(SMU_METRICS), 203 TAB_MAP(DRIVER_SMU_CONFIG), 204 TAB_MAP(I2C_COMMANDS), 205 TAB_MAP(ECCINFO), 206 }; 207 208 static const uint8_t aldebaran_throttler_map[] = { 209 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 210 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 211 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 212 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 213 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT), 214 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), 215 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 216 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 217 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 218 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 219 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 220 }; 221 222 static int aldebaran_tables_init(struct smu_context *smu) 223 { 224 struct smu_table_context *smu_table = &smu->smu_table; 225 struct smu_table *tables = smu_table->tables; 226 227 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 229 230 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 231 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 232 233 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 235 236 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 237 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 238 239 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 240 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 241 242 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 243 if (!smu_table->metrics_table) 244 return -ENOMEM; 245 smu_table->metrics_time = 0; 246 247 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 248 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 249 if (!smu_table->gpu_metrics_table) { 250 kfree(smu_table->metrics_table); 251 return -ENOMEM; 252 } 253 254 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 255 if (!smu_table->ecc_table) 256 return -ENOMEM; 257 258 return 0; 259 } 260 261 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 262 { 263 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 264 265 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 266 GFP_KERNEL); 267 if (!smu_dpm->dpm_context) 268 return -ENOMEM; 269 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 270 271 return 0; 272 } 273 274 static int aldebaran_init_smc_tables(struct smu_context *smu) 275 { 276 int ret = 0; 277 278 ret = aldebaran_tables_init(smu); 279 if (ret) 280 return ret; 281 282 ret = aldebaran_allocate_dpm_context(smu); 283 if (ret) 284 return ret; 285 286 return smu_v13_0_init_smc_tables(smu); 287 } 288 289 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 290 uint32_t *feature_mask, uint32_t num) 291 { 292 if (num > 2) 293 return -EINVAL; 294 295 /* pptable will handle the features to enable */ 296 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 297 298 return 0; 299 } 300 301 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 302 { 303 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 304 struct smu_13_0_dpm_table *dpm_table = NULL; 305 PPTable_t *pptable = smu->smu_table.driver_pptable; 306 int ret = 0; 307 308 /* socclk dpm table setup */ 309 dpm_table = &dpm_context->dpm_tables.soc_table; 310 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 311 ret = smu_v13_0_set_single_dpm_table(smu, 312 SMU_SOCCLK, 313 dpm_table); 314 if (ret) 315 return ret; 316 } else { 317 dpm_table->count = 1; 318 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 319 dpm_table->dpm_levels[0].enabled = true; 320 dpm_table->min = dpm_table->dpm_levels[0].value; 321 dpm_table->max = dpm_table->dpm_levels[0].value; 322 } 323 324 /* gfxclk dpm table setup */ 325 dpm_table = &dpm_context->dpm_tables.gfx_table; 326 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 327 /* in the case of gfxclk, only fine-grained dpm is honored */ 328 dpm_table->count = 2; 329 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 330 dpm_table->dpm_levels[0].enabled = true; 331 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 332 dpm_table->dpm_levels[1].enabled = true; 333 dpm_table->min = dpm_table->dpm_levels[0].value; 334 dpm_table->max = dpm_table->dpm_levels[1].value; 335 } else { 336 dpm_table->count = 1; 337 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 338 dpm_table->dpm_levels[0].enabled = true; 339 dpm_table->min = dpm_table->dpm_levels[0].value; 340 dpm_table->max = dpm_table->dpm_levels[0].value; 341 } 342 343 /* memclk dpm table setup */ 344 dpm_table = &dpm_context->dpm_tables.uclk_table; 345 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 346 ret = smu_v13_0_set_single_dpm_table(smu, 347 SMU_UCLK, 348 dpm_table); 349 if (ret) 350 return ret; 351 } else { 352 dpm_table->count = 1; 353 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 354 dpm_table->dpm_levels[0].enabled = true; 355 dpm_table->min = dpm_table->dpm_levels[0].value; 356 dpm_table->max = dpm_table->dpm_levels[0].value; 357 } 358 359 /* fclk dpm table setup */ 360 dpm_table = &dpm_context->dpm_tables.fclk_table; 361 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 362 ret = smu_v13_0_set_single_dpm_table(smu, 363 SMU_FCLK, 364 dpm_table); 365 if (ret) 366 return ret; 367 } else { 368 dpm_table->count = 1; 369 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 370 dpm_table->dpm_levels[0].enabled = true; 371 dpm_table->min = dpm_table->dpm_levels[0].value; 372 dpm_table->max = dpm_table->dpm_levels[0].value; 373 } 374 375 return 0; 376 } 377 378 static int aldebaran_check_powerplay_table(struct smu_context *smu) 379 { 380 struct smu_table_context *table_context = &smu->smu_table; 381 struct smu_13_0_powerplay_table *powerplay_table = 382 table_context->power_play_table; 383 384 table_context->thermal_controller_type = 385 powerplay_table->thermal_controller_type; 386 387 return 0; 388 } 389 390 static int aldebaran_store_powerplay_table(struct smu_context *smu) 391 { 392 struct smu_table_context *table_context = &smu->smu_table; 393 struct smu_13_0_powerplay_table *powerplay_table = 394 table_context->power_play_table; 395 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 396 sizeof(PPTable_t)); 397 398 return 0; 399 } 400 401 static int aldebaran_append_powerplay_table(struct smu_context *smu) 402 { 403 struct smu_table_context *table_context = &smu->smu_table; 404 PPTable_t *smc_pptable = table_context->driver_pptable; 405 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 406 int index, ret; 407 408 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 409 smc_dpm_info); 410 411 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 412 (uint8_t **)&smc_dpm_table); 413 if (ret) 414 return ret; 415 416 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 417 smc_dpm_table->table_header.format_revision, 418 smc_dpm_table->table_header.content_revision); 419 420 if ((smc_dpm_table->table_header.format_revision == 4) && 421 (smc_dpm_table->table_header.content_revision == 10)) 422 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved, 423 smc_dpm_table, GfxMaxCurrent); 424 return 0; 425 } 426 427 static int aldebaran_setup_pptable(struct smu_context *smu) 428 { 429 int ret = 0; 430 431 /* VBIOS pptable is the first choice */ 432 smu->smu_table.boot_values.pp_table_id = 0; 433 434 ret = smu_v13_0_setup_pptable(smu); 435 if (ret) 436 return ret; 437 438 ret = aldebaran_store_powerplay_table(smu); 439 if (ret) 440 return ret; 441 442 ret = aldebaran_append_powerplay_table(smu); 443 if (ret) 444 return ret; 445 446 ret = aldebaran_check_powerplay_table(smu); 447 if (ret) 448 return ret; 449 450 return ret; 451 } 452 453 static bool aldebaran_is_primary(struct smu_context *smu) 454 { 455 struct amdgpu_device *adev = smu->adev; 456 457 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) 458 return adev->smuio.funcs->get_die_id(adev) == 0; 459 460 return true; 461 } 462 463 static int aldebaran_run_board_btc(struct smu_context *smu) 464 { 465 u32 smu_version; 466 int ret; 467 468 if (!aldebaran_is_primary(smu)) 469 return 0; 470 471 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 472 if (ret) { 473 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 474 return ret; 475 } 476 if (smu_version <= 0x00441d00) 477 return 0; 478 479 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL); 480 if (ret) 481 dev_err(smu->adev->dev, "Board power calibration failed!\n"); 482 483 return ret; 484 } 485 486 static int aldebaran_run_btc(struct smu_context *smu) 487 { 488 int ret; 489 490 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 491 if (ret) 492 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 493 else 494 ret = aldebaran_run_board_btc(smu); 495 496 return ret; 497 } 498 499 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 500 { 501 struct smu_13_0_dpm_context *dpm_context = 502 smu->smu_dpm.dpm_context; 503 struct smu_13_0_dpm_table *gfx_table = 504 &dpm_context->dpm_tables.gfx_table; 505 struct smu_13_0_dpm_table *mem_table = 506 &dpm_context->dpm_tables.uclk_table; 507 struct smu_13_0_dpm_table *soc_table = 508 &dpm_context->dpm_tables.soc_table; 509 struct smu_umd_pstate_table *pstate_table = 510 &smu->pstate_table; 511 512 pstate_table->gfxclk_pstate.min = gfx_table->min; 513 pstate_table->gfxclk_pstate.peak = gfx_table->max; 514 pstate_table->gfxclk_pstate.curr.min = gfx_table->min; 515 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 516 517 pstate_table->uclk_pstate.min = mem_table->min; 518 pstate_table->uclk_pstate.peak = mem_table->max; 519 pstate_table->uclk_pstate.curr.min = mem_table->min; 520 pstate_table->uclk_pstate.curr.max = mem_table->max; 521 522 pstate_table->socclk_pstate.min = soc_table->min; 523 pstate_table->socclk_pstate.peak = soc_table->max; 524 pstate_table->socclk_pstate.curr.min = soc_table->min; 525 pstate_table->socclk_pstate.curr.max = soc_table->max; 526 527 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 528 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 529 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 530 pstate_table->gfxclk_pstate.standard = 531 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 532 pstate_table->uclk_pstate.standard = 533 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 534 pstate_table->socclk_pstate.standard = 535 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 536 } else { 537 pstate_table->gfxclk_pstate.standard = 538 pstate_table->gfxclk_pstate.min; 539 pstate_table->uclk_pstate.standard = 540 pstate_table->uclk_pstate.min; 541 pstate_table->socclk_pstate.standard = 542 pstate_table->socclk_pstate.min; 543 } 544 545 return 0; 546 } 547 548 static int aldebaran_get_clk_table(struct smu_context *smu, 549 struct pp_clock_levels_with_latency *clocks, 550 struct smu_13_0_dpm_table *dpm_table) 551 { 552 int i, count; 553 554 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 555 clocks->num_levels = count; 556 557 for (i = 0; i < count; i++) { 558 clocks->data[i].clocks_in_khz = 559 dpm_table->dpm_levels[i].value * 1000; 560 clocks->data[i].latency_in_us = 0; 561 } 562 563 return 0; 564 } 565 566 static int aldebaran_freqs_in_same_level(int32_t frequency1, 567 int32_t frequency2) 568 { 569 return (abs(frequency1 - frequency2) <= EPSILON); 570 } 571 572 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 573 MetricsMember_t member, 574 uint32_t *value) 575 { 576 struct smu_table_context *smu_table= &smu->smu_table; 577 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 578 int ret = 0; 579 580 ret = smu_cmn_get_metrics_table(smu, 581 NULL, 582 false); 583 if (ret) 584 return ret; 585 586 switch (member) { 587 case METRICS_CURR_GFXCLK: 588 *value = metrics->CurrClock[PPCLK_GFXCLK]; 589 break; 590 case METRICS_CURR_SOCCLK: 591 *value = metrics->CurrClock[PPCLK_SOCCLK]; 592 break; 593 case METRICS_CURR_UCLK: 594 *value = metrics->CurrClock[PPCLK_UCLK]; 595 break; 596 case METRICS_CURR_VCLK: 597 *value = metrics->CurrClock[PPCLK_VCLK]; 598 break; 599 case METRICS_CURR_DCLK: 600 *value = metrics->CurrClock[PPCLK_DCLK]; 601 break; 602 case METRICS_CURR_FCLK: 603 *value = metrics->CurrClock[PPCLK_FCLK]; 604 break; 605 case METRICS_AVERAGE_GFXCLK: 606 *value = metrics->AverageGfxclkFrequency; 607 break; 608 case METRICS_AVERAGE_SOCCLK: 609 *value = metrics->AverageSocclkFrequency; 610 break; 611 case METRICS_AVERAGE_UCLK: 612 *value = metrics->AverageUclkFrequency; 613 break; 614 case METRICS_AVERAGE_GFXACTIVITY: 615 *value = metrics->AverageGfxActivity; 616 break; 617 case METRICS_AVERAGE_MEMACTIVITY: 618 *value = metrics->AverageUclkActivity; 619 break; 620 case METRICS_AVERAGE_SOCKETPOWER: 621 /* Valid power data is available only from primary die */ 622 *value = aldebaran_is_primary(smu) ? 623 metrics->AverageSocketPower << 8 : 624 0; 625 break; 626 case METRICS_TEMPERATURE_EDGE: 627 *value = metrics->TemperatureEdge * 628 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 629 break; 630 case METRICS_TEMPERATURE_HOTSPOT: 631 *value = metrics->TemperatureHotspot * 632 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 633 break; 634 case METRICS_TEMPERATURE_MEM: 635 *value = metrics->TemperatureHBM * 636 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 637 break; 638 case METRICS_TEMPERATURE_VRGFX: 639 *value = metrics->TemperatureVrGfx * 640 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 641 break; 642 case METRICS_TEMPERATURE_VRSOC: 643 *value = metrics->TemperatureVrSoc * 644 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 645 break; 646 case METRICS_TEMPERATURE_VRMEM: 647 *value = metrics->TemperatureVrMem * 648 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 649 break; 650 case METRICS_THROTTLER_STATUS: 651 *value = metrics->ThrottlerStatus; 652 break; 653 default: 654 *value = UINT_MAX; 655 break; 656 } 657 658 return ret; 659 } 660 661 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 662 enum smu_clk_type clk_type, 663 uint32_t *value) 664 { 665 MetricsMember_t member_type; 666 int clk_id = 0; 667 668 if (!value) 669 return -EINVAL; 670 671 clk_id = smu_cmn_to_asic_specific_index(smu, 672 CMN2ASIC_MAPPING_CLK, 673 clk_type); 674 if (clk_id < 0) 675 return -EINVAL; 676 677 switch (clk_id) { 678 case PPCLK_GFXCLK: 679 /* 680 * CurrClock[clk_id] can provide accurate 681 * output only when the dpm feature is enabled. 682 * We can use Average_* for dpm disabled case. 683 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 684 */ 685 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 686 member_type = METRICS_CURR_GFXCLK; 687 else 688 member_type = METRICS_AVERAGE_GFXCLK; 689 break; 690 case PPCLK_UCLK: 691 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 692 member_type = METRICS_CURR_UCLK; 693 else 694 member_type = METRICS_AVERAGE_UCLK; 695 break; 696 case PPCLK_SOCCLK: 697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 698 member_type = METRICS_CURR_SOCCLK; 699 else 700 member_type = METRICS_AVERAGE_SOCCLK; 701 break; 702 case PPCLK_VCLK: 703 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 704 member_type = METRICS_CURR_VCLK; 705 else 706 member_type = METRICS_AVERAGE_VCLK; 707 break; 708 case PPCLK_DCLK: 709 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 710 member_type = METRICS_CURR_DCLK; 711 else 712 member_type = METRICS_AVERAGE_DCLK; 713 break; 714 case PPCLK_FCLK: 715 member_type = METRICS_CURR_FCLK; 716 break; 717 default: 718 return -EINVAL; 719 } 720 721 return aldebaran_get_smu_metrics_data(smu, 722 member_type, 723 value); 724 } 725 726 static int aldebaran_print_clk_levels(struct smu_context *smu, 727 enum smu_clk_type type, char *buf) 728 { 729 int i, now, size = 0; 730 int ret = 0; 731 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 732 struct pp_clock_levels_with_latency clocks; 733 struct smu_13_0_dpm_table *single_dpm_table; 734 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 735 struct smu_13_0_dpm_context *dpm_context = NULL; 736 uint32_t display_levels; 737 uint32_t freq_values[3] = {0}; 738 uint32_t min_clk, max_clk; 739 740 smu_cmn_get_sysfs_buf(&buf, &size); 741 742 if (amdgpu_ras_intr_triggered()) { 743 size += sysfs_emit_at(buf, size, "unavailable\n"); 744 return size; 745 } 746 747 dpm_context = smu_dpm->dpm_context; 748 749 switch (type) { 750 751 case SMU_OD_SCLK: 752 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK"); 753 fallthrough; 754 case SMU_SCLK: 755 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 756 if (ret) { 757 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 758 return ret; 759 } 760 761 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 762 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 763 if (ret) { 764 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 765 return ret; 766 } 767 768 display_levels = clocks.num_levels; 769 770 min_clk = pstate_table->gfxclk_pstate.curr.min; 771 max_clk = pstate_table->gfxclk_pstate.curr.max; 772 773 freq_values[0] = min_clk; 774 freq_values[1] = max_clk; 775 776 /* fine-grained dpm has only 2 levels */ 777 if (now > min_clk && now < max_clk) { 778 display_levels = clocks.num_levels + 1; 779 freq_values[2] = max_clk; 780 freq_values[1] = now; 781 } 782 783 /* 784 * For DPM disabled case, there will be only one clock level. 785 * And it's safe to assume that is always the current clock. 786 */ 787 if (display_levels == clocks.num_levels) { 788 for (i = 0; i < clocks.num_levels; i++) 789 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 790 freq_values[i], 791 (clocks.num_levels == 1) ? 792 "*" : 793 (aldebaran_freqs_in_same_level( 794 freq_values[i], now) ? 795 "*" : 796 "")); 797 } else { 798 for (i = 0; i < display_levels; i++) 799 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 800 freq_values[i], i == 1 ? "*" : ""); 801 } 802 803 break; 804 805 case SMU_OD_MCLK: 806 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK"); 807 fallthrough; 808 case SMU_MCLK: 809 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 810 if (ret) { 811 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 812 return ret; 813 } 814 815 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 816 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 817 if (ret) { 818 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 819 return ret; 820 } 821 822 for (i = 0; i < clocks.num_levels; i++) 823 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 824 i, clocks.data[i].clocks_in_khz / 1000, 825 (clocks.num_levels == 1) ? "*" : 826 (aldebaran_freqs_in_same_level( 827 clocks.data[i].clocks_in_khz / 1000, 828 now) ? "*" : "")); 829 break; 830 831 case SMU_SOCCLK: 832 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 833 if (ret) { 834 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 835 return ret; 836 } 837 838 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 839 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 840 if (ret) { 841 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 842 return ret; 843 } 844 845 for (i = 0; i < clocks.num_levels; i++) 846 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 847 i, clocks.data[i].clocks_in_khz / 1000, 848 (clocks.num_levels == 1) ? "*" : 849 (aldebaran_freqs_in_same_level( 850 clocks.data[i].clocks_in_khz / 1000, 851 now) ? "*" : "")); 852 break; 853 854 case SMU_FCLK: 855 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 856 if (ret) { 857 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 858 return ret; 859 } 860 861 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 862 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 863 if (ret) { 864 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 865 return ret; 866 } 867 868 for (i = 0; i < single_dpm_table->count; i++) 869 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 870 i, single_dpm_table->dpm_levels[i].value, 871 (clocks.num_levels == 1) ? "*" : 872 (aldebaran_freqs_in_same_level( 873 clocks.data[i].clocks_in_khz / 1000, 874 now) ? "*" : "")); 875 break; 876 877 case SMU_VCLK: 878 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); 879 if (ret) { 880 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); 881 return ret; 882 } 883 884 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 885 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 886 if (ret) { 887 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); 888 return ret; 889 } 890 891 for (i = 0; i < single_dpm_table->count; i++) 892 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 893 i, single_dpm_table->dpm_levels[i].value, 894 (clocks.num_levels == 1) ? "*" : 895 (aldebaran_freqs_in_same_level( 896 clocks.data[i].clocks_in_khz / 1000, 897 now) ? "*" : "")); 898 break; 899 900 case SMU_DCLK: 901 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); 902 if (ret) { 903 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); 904 return ret; 905 } 906 907 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 908 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 909 if (ret) { 910 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); 911 return ret; 912 } 913 914 for (i = 0; i < single_dpm_table->count; i++) 915 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 916 i, single_dpm_table->dpm_levels[i].value, 917 (clocks.num_levels == 1) ? "*" : 918 (aldebaran_freqs_in_same_level( 919 clocks.data[i].clocks_in_khz / 1000, 920 now) ? "*" : "")); 921 break; 922 923 default: 924 break; 925 } 926 927 return size; 928 } 929 930 static int aldebaran_upload_dpm_level(struct smu_context *smu, 931 bool max, 932 uint32_t feature_mask, 933 uint32_t level) 934 { 935 struct smu_13_0_dpm_context *dpm_context = 936 smu->smu_dpm.dpm_context; 937 uint32_t freq; 938 int ret = 0; 939 940 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 941 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 942 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 943 ret = smu_cmn_send_smc_msg_with_param(smu, 944 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 945 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 946 NULL); 947 if (ret) { 948 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 949 max ? "max" : "min"); 950 return ret; 951 } 952 } 953 954 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 955 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 956 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 957 ret = smu_cmn_send_smc_msg_with_param(smu, 958 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 959 (PPCLK_UCLK << 16) | (freq & 0xffff), 960 NULL); 961 if (ret) { 962 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 963 max ? "max" : "min"); 964 return ret; 965 } 966 } 967 968 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 969 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 970 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 971 ret = smu_cmn_send_smc_msg_with_param(smu, 972 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 973 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 974 NULL); 975 if (ret) { 976 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 977 max ? "max" : "min"); 978 return ret; 979 } 980 } 981 982 return ret; 983 } 984 985 static int aldebaran_force_clk_levels(struct smu_context *smu, 986 enum smu_clk_type type, uint32_t mask) 987 { 988 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 989 struct smu_13_0_dpm_table *single_dpm_table = NULL; 990 uint32_t soft_min_level, soft_max_level; 991 int ret = 0; 992 993 soft_min_level = mask ? (ffs(mask) - 1) : 0; 994 soft_max_level = mask ? (fls(mask) - 1) : 0; 995 996 switch (type) { 997 case SMU_SCLK: 998 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 999 if (soft_max_level >= single_dpm_table->count) { 1000 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 1001 soft_max_level, single_dpm_table->count - 1); 1002 ret = -EINVAL; 1003 break; 1004 } 1005 1006 ret = aldebaran_upload_dpm_level(smu, 1007 false, 1008 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1009 soft_min_level); 1010 if (ret) { 1011 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1012 break; 1013 } 1014 1015 ret = aldebaran_upload_dpm_level(smu, 1016 true, 1017 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1018 soft_max_level); 1019 if (ret) 1020 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1021 1022 break; 1023 1024 case SMU_MCLK: 1025 case SMU_SOCCLK: 1026 case SMU_FCLK: 1027 /* 1028 * Should not arrive here since aldebaran does not 1029 * support mclk/socclk/fclk softmin/softmax settings 1030 */ 1031 ret = -EINVAL; 1032 break; 1033 1034 default: 1035 break; 1036 } 1037 1038 return ret; 1039 } 1040 1041 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 1042 struct smu_temperature_range *range) 1043 { 1044 struct smu_table_context *table_context = &smu->smu_table; 1045 struct smu_13_0_powerplay_table *powerplay_table = 1046 table_context->power_play_table; 1047 PPTable_t *pptable = smu->smu_table.driver_pptable; 1048 1049 if (!range) 1050 return -EINVAL; 1051 1052 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1053 1054 range->hotspot_crit_max = pptable->ThotspotLimit * 1055 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1056 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1057 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1058 range->mem_crit_max = pptable->TmemLimit * 1059 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1060 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1061 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1062 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1063 1064 return 0; 1065 } 1066 1067 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 1068 enum amd_pp_sensors sensor, 1069 uint32_t *value) 1070 { 1071 int ret = 0; 1072 1073 if (!value) 1074 return -EINVAL; 1075 1076 switch (sensor) { 1077 case AMDGPU_PP_SENSOR_GPU_LOAD: 1078 ret = aldebaran_get_smu_metrics_data(smu, 1079 METRICS_AVERAGE_GFXACTIVITY, 1080 value); 1081 break; 1082 case AMDGPU_PP_SENSOR_MEM_LOAD: 1083 ret = aldebaran_get_smu_metrics_data(smu, 1084 METRICS_AVERAGE_MEMACTIVITY, 1085 value); 1086 break; 1087 default: 1088 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 1089 return -EINVAL; 1090 } 1091 1092 return ret; 1093 } 1094 1095 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value) 1096 { 1097 if (!value) 1098 return -EINVAL; 1099 1100 return aldebaran_get_smu_metrics_data(smu, 1101 METRICS_AVERAGE_SOCKETPOWER, 1102 value); 1103 } 1104 1105 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 1106 enum amd_pp_sensors sensor, 1107 uint32_t *value) 1108 { 1109 int ret = 0; 1110 1111 if (!value) 1112 return -EINVAL; 1113 1114 switch (sensor) { 1115 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1116 ret = aldebaran_get_smu_metrics_data(smu, 1117 METRICS_TEMPERATURE_HOTSPOT, 1118 value); 1119 break; 1120 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1121 ret = aldebaran_get_smu_metrics_data(smu, 1122 METRICS_TEMPERATURE_EDGE, 1123 value); 1124 break; 1125 case AMDGPU_PP_SENSOR_MEM_TEMP: 1126 ret = aldebaran_get_smu_metrics_data(smu, 1127 METRICS_TEMPERATURE_MEM, 1128 value); 1129 break; 1130 default: 1131 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1132 return -EINVAL; 1133 } 1134 1135 return ret; 1136 } 1137 1138 static int aldebaran_read_sensor(struct smu_context *smu, 1139 enum amd_pp_sensors sensor, 1140 void *data, uint32_t *size) 1141 { 1142 int ret = 0; 1143 1144 if (amdgpu_ras_intr_triggered()) 1145 return 0; 1146 1147 if (!data || !size) 1148 return -EINVAL; 1149 1150 switch (sensor) { 1151 case AMDGPU_PP_SENSOR_MEM_LOAD: 1152 case AMDGPU_PP_SENSOR_GPU_LOAD: 1153 ret = aldebaran_get_current_activity_percent(smu, 1154 sensor, 1155 (uint32_t *)data); 1156 *size = 4; 1157 break; 1158 case AMDGPU_PP_SENSOR_GPU_POWER: 1159 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data); 1160 *size = 4; 1161 break; 1162 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1163 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1164 case AMDGPU_PP_SENSOR_MEM_TEMP: 1165 ret = aldebaran_thermal_get_temperature(smu, sensor, 1166 (uint32_t *)data); 1167 *size = 4; 1168 break; 1169 case AMDGPU_PP_SENSOR_GFX_MCLK: 1170 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1171 /* the output clock frequency in 10K unit */ 1172 *(uint32_t *)data *= 100; 1173 *size = 4; 1174 break; 1175 case AMDGPU_PP_SENSOR_GFX_SCLK: 1176 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1177 *(uint32_t *)data *= 100; 1178 *size = 4; 1179 break; 1180 case AMDGPU_PP_SENSOR_VDDGFX: 1181 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1182 *size = 4; 1183 break; 1184 default: 1185 ret = -EOPNOTSUPP; 1186 break; 1187 } 1188 1189 return ret; 1190 } 1191 1192 static int aldebaran_get_power_limit(struct smu_context *smu, 1193 uint32_t *current_power_limit, 1194 uint32_t *default_power_limit, 1195 uint32_t *max_power_limit) 1196 { 1197 PPTable_t *pptable = smu->smu_table.driver_pptable; 1198 uint32_t power_limit = 0; 1199 int ret; 1200 1201 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1202 if (current_power_limit) 1203 *current_power_limit = 0; 1204 if (default_power_limit) 1205 *default_power_limit = 0; 1206 if (max_power_limit) 1207 *max_power_limit = 0; 1208 1209 dev_warn(smu->adev->dev, 1210 "PPT feature is not enabled, power values can't be fetched."); 1211 1212 return 0; 1213 } 1214 1215 /* Valid power data is available only from primary die. 1216 * For secondary die show the value as 0. 1217 */ 1218 if (aldebaran_is_primary(smu)) { 1219 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, 1220 &power_limit); 1221 1222 if (ret) { 1223 /* the last hope to figure out the ppt limit */ 1224 if (!pptable) { 1225 dev_err(smu->adev->dev, 1226 "Cannot get PPT limit due to pptable missing!"); 1227 return -EINVAL; 1228 } 1229 power_limit = pptable->PptLimit; 1230 } 1231 } 1232 1233 if (current_power_limit) 1234 *current_power_limit = power_limit; 1235 if (default_power_limit) 1236 *default_power_limit = power_limit; 1237 1238 if (max_power_limit) { 1239 if (pptable) 1240 *max_power_limit = pptable->PptLimit; 1241 } 1242 1243 return 0; 1244 } 1245 1246 static int aldebaran_set_power_limit(struct smu_context *smu, 1247 enum smu_ppt_limit_type limit_type, 1248 uint32_t limit) 1249 { 1250 /* Power limit can be set only through primary die */ 1251 if (aldebaran_is_primary(smu)) 1252 return smu_v13_0_set_power_limit(smu, limit_type, limit); 1253 1254 return -EINVAL; 1255 } 1256 1257 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1258 { 1259 int ret; 1260 1261 ret = smu_v13_0_system_features_control(smu, enable); 1262 if (!ret && enable) 1263 ret = aldebaran_run_btc(smu); 1264 1265 return ret; 1266 } 1267 1268 static int aldebaran_set_performance_level(struct smu_context *smu, 1269 enum amd_dpm_forced_level level) 1270 { 1271 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1272 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1273 struct smu_13_0_dpm_table *gfx_table = 1274 &dpm_context->dpm_tables.gfx_table; 1275 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1276 1277 /* Disable determinism if switching to another mode */ 1278 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && 1279 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { 1280 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1281 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 1282 } 1283 1284 switch (level) { 1285 1286 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1287 return 0; 1288 1289 case AMD_DPM_FORCED_LEVEL_HIGH: 1290 case AMD_DPM_FORCED_LEVEL_LOW: 1291 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1292 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1293 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1294 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1295 default: 1296 break; 1297 } 1298 1299 return smu_v13_0_set_performance_level(smu, level); 1300 } 1301 1302 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1303 enum smu_clk_type clk_type, 1304 uint32_t min, 1305 uint32_t max) 1306 { 1307 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1308 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1309 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1310 struct amdgpu_device *adev = smu->adev; 1311 uint32_t min_clk; 1312 uint32_t max_clk; 1313 int ret = 0; 1314 1315 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1316 return -EINVAL; 1317 1318 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1319 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1320 return -EINVAL; 1321 1322 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1323 if (min >= max) { 1324 dev_err(smu->adev->dev, 1325 "Minimum GFX clk should be less than the maximum allowed clock\n"); 1326 return -EINVAL; 1327 } 1328 1329 if ((min == pstate_table->gfxclk_pstate.curr.min) && 1330 (max == pstate_table->gfxclk_pstate.curr.max)) 1331 return 0; 1332 1333 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, 1334 min, max); 1335 if (!ret) { 1336 pstate_table->gfxclk_pstate.curr.min = min; 1337 pstate_table->gfxclk_pstate.curr.max = max; 1338 } 1339 1340 return ret; 1341 } 1342 1343 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1344 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1345 (max > dpm_context->dpm_tables.gfx_table.max)) { 1346 dev_warn(adev->dev, 1347 "Invalid max frequency %d MHz specified for determinism\n", max); 1348 return -EINVAL; 1349 } 1350 1351 /* Restore default min/max clocks and enable determinism */ 1352 min_clk = dpm_context->dpm_tables.gfx_table.min; 1353 max_clk = dpm_context->dpm_tables.gfx_table.max; 1354 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1355 if (!ret) { 1356 usleep_range(500, 1000); 1357 ret = smu_cmn_send_smc_msg_with_param(smu, 1358 SMU_MSG_EnableDeterminism, 1359 max, NULL); 1360 if (ret) { 1361 dev_err(adev->dev, 1362 "Failed to enable determinism at GFX clock %d MHz\n", max); 1363 } else { 1364 pstate_table->gfxclk_pstate.curr.min = min_clk; 1365 pstate_table->gfxclk_pstate.curr.max = max; 1366 } 1367 } 1368 } 1369 1370 return ret; 1371 } 1372 1373 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1374 long input[], uint32_t size) 1375 { 1376 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1377 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1378 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1379 uint32_t min_clk; 1380 uint32_t max_clk; 1381 int ret = 0; 1382 1383 /* Only allowed in manual or determinism mode */ 1384 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1385 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1386 return -EINVAL; 1387 1388 switch (type) { 1389 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1390 if (size != 2) { 1391 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1392 return -EINVAL; 1393 } 1394 1395 if (input[0] == 0) { 1396 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1397 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1398 input[1], dpm_context->dpm_tables.gfx_table.min); 1399 pstate_table->gfxclk_pstate.custom.min = 1400 pstate_table->gfxclk_pstate.curr.min; 1401 return -EINVAL; 1402 } 1403 1404 pstate_table->gfxclk_pstate.custom.min = input[1]; 1405 } else if (input[0] == 1) { 1406 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1407 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1408 input[1], dpm_context->dpm_tables.gfx_table.max); 1409 pstate_table->gfxclk_pstate.custom.max = 1410 pstate_table->gfxclk_pstate.curr.max; 1411 return -EINVAL; 1412 } 1413 1414 pstate_table->gfxclk_pstate.custom.max = input[1]; 1415 } else { 1416 return -EINVAL; 1417 } 1418 break; 1419 case PP_OD_RESTORE_DEFAULT_TABLE: 1420 if (size != 0) { 1421 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1422 return -EINVAL; 1423 } else { 1424 /* Use the default frequencies for manual and determinism mode */ 1425 min_clk = dpm_context->dpm_tables.gfx_table.min; 1426 max_clk = dpm_context->dpm_tables.gfx_table.max; 1427 1428 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1429 } 1430 break; 1431 case PP_OD_COMMIT_DPM_TABLE: 1432 if (size != 0) { 1433 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1434 return -EINVAL; 1435 } else { 1436 if (!pstate_table->gfxclk_pstate.custom.min) 1437 pstate_table->gfxclk_pstate.custom.min = 1438 pstate_table->gfxclk_pstate.curr.min; 1439 1440 if (!pstate_table->gfxclk_pstate.custom.max) 1441 pstate_table->gfxclk_pstate.custom.max = 1442 pstate_table->gfxclk_pstate.curr.max; 1443 1444 min_clk = pstate_table->gfxclk_pstate.custom.min; 1445 max_clk = pstate_table->gfxclk_pstate.custom.max; 1446 1447 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1448 } 1449 break; 1450 default: 1451 return -ENOSYS; 1452 } 1453 1454 return ret; 1455 } 1456 1457 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1458 { 1459 int ret; 1460 uint64_t feature_enabled; 1461 1462 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1463 if (ret) 1464 return false; 1465 return !!(feature_enabled & SMC_DPM_FEATURE); 1466 } 1467 1468 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1469 struct i2c_msg *msg, int num_msgs) 1470 { 1471 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 1472 struct amdgpu_device *adev = smu_i2c->adev; 1473 struct smu_context *smu = adev->powerplay.pp_handle; 1474 struct smu_table_context *smu_table = &smu->smu_table; 1475 struct smu_table *table = &smu_table->driver_table; 1476 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1477 int i, j, r, c; 1478 u16 dir; 1479 1480 if (!adev->pm.dpm_enabled) 1481 return -EBUSY; 1482 1483 req = kzalloc(sizeof(*req), GFP_KERNEL); 1484 if (!req) 1485 return -ENOMEM; 1486 1487 req->I2CcontrollerPort = smu_i2c->port; 1488 req->I2CSpeed = I2C_SPEED_FAST_400K; 1489 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1490 dir = msg[0].flags & I2C_M_RD; 1491 1492 for (c = i = 0; i < num_msgs; i++) { 1493 for (j = 0; j < msg[i].len; j++, c++) { 1494 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1495 1496 if (!(msg[i].flags & I2C_M_RD)) { 1497 /* write */ 1498 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1499 cmd->ReadWriteData = msg[i].buf[j]; 1500 } 1501 1502 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1503 /* The direction changes. 1504 */ 1505 dir = msg[i].flags & I2C_M_RD; 1506 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1507 } 1508 1509 req->NumCmds++; 1510 1511 /* 1512 * Insert STOP if we are at the last byte of either last 1513 * message for the transaction or the client explicitly 1514 * requires a STOP at this particular message. 1515 */ 1516 if ((j == msg[i].len - 1) && 1517 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1518 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1519 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1520 } 1521 } 1522 } 1523 mutex_lock(&adev->pm.mutex); 1524 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1525 mutex_unlock(&adev->pm.mutex); 1526 if (r) 1527 goto fail; 1528 1529 for (c = i = 0; i < num_msgs; i++) { 1530 if (!(msg[i].flags & I2C_M_RD)) { 1531 c += msg[i].len; 1532 continue; 1533 } 1534 for (j = 0; j < msg[i].len; j++, c++) { 1535 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1536 1537 msg[i].buf[j] = cmd->ReadWriteData; 1538 } 1539 } 1540 r = num_msgs; 1541 fail: 1542 kfree(req); 1543 return r; 1544 } 1545 1546 static u32 aldebaran_i2c_func(struct i2c_adapter *adap) 1547 { 1548 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1549 } 1550 1551 1552 static const struct i2c_algorithm aldebaran_i2c_algo = { 1553 .master_xfer = aldebaran_i2c_xfer, 1554 .functionality = aldebaran_i2c_func, 1555 }; 1556 1557 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = { 1558 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1559 .max_read_len = MAX_SW_I2C_COMMANDS, 1560 .max_write_len = MAX_SW_I2C_COMMANDS, 1561 .max_comb_1st_msg_len = 2, 1562 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1563 }; 1564 1565 static int aldebaran_i2c_control_init(struct smu_context *smu) 1566 { 1567 struct amdgpu_device *adev = smu->adev; 1568 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0]; 1569 struct i2c_adapter *control = &smu_i2c->adapter; 1570 int res; 1571 1572 smu_i2c->adev = adev; 1573 smu_i2c->port = 0; 1574 mutex_init(&smu_i2c->mutex); 1575 control->owner = THIS_MODULE; 1576 control->class = I2C_CLASS_SPD; 1577 control->dev.parent = &adev->pdev->dev; 1578 control->algo = &aldebaran_i2c_algo; 1579 snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); 1580 control->quirks = &aldebaran_i2c_control_quirks; 1581 i2c_set_adapdata(control, smu_i2c); 1582 1583 res = i2c_add_adapter(control); 1584 if (res) { 1585 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1586 goto Out_err; 1587 } 1588 1589 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1590 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1591 1592 return 0; 1593 Out_err: 1594 i2c_del_adapter(control); 1595 1596 return res; 1597 } 1598 1599 static void aldebaran_i2c_control_fini(struct smu_context *smu) 1600 { 1601 struct amdgpu_device *adev = smu->adev; 1602 int i; 1603 1604 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1605 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1606 struct i2c_adapter *control = &smu_i2c->adapter; 1607 1608 i2c_del_adapter(control); 1609 } 1610 adev->pm.ras_eeprom_i2c_bus = NULL; 1611 adev->pm.fru_eeprom_i2c_bus = NULL; 1612 } 1613 1614 static void aldebaran_get_unique_id(struct smu_context *smu) 1615 { 1616 struct amdgpu_device *adev = smu->adev; 1617 SmuMetrics_t *metrics = smu->smu_table.metrics_table; 1618 uint32_t upper32 = 0, lower32 = 0; 1619 int ret; 1620 1621 ret = smu_cmn_get_metrics_table(smu, NULL, false); 1622 if (ret) 1623 goto out; 1624 1625 upper32 = metrics->PublicSerialNumUpper32; 1626 lower32 = metrics->PublicSerialNumLower32; 1627 1628 out: 1629 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1630 if (adev->serial[0] == '\0') 1631 sprintf(adev->serial, "%016llx", adev->unique_id); 1632 } 1633 1634 static bool aldebaran_is_baco_supported(struct smu_context *smu) 1635 { 1636 /* aldebaran is not support baco */ 1637 1638 return false; 1639 } 1640 1641 static int aldebaran_set_df_cstate(struct smu_context *smu, 1642 enum pp_df_cstate state) 1643 { 1644 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1645 } 1646 1647 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) 1648 { 1649 struct amdgpu_device *adev = smu->adev; 1650 1651 /* The message only works on master die and NACK will be sent 1652 back for other dies, only send it on master die */ 1653 if (!adev->smuio.funcs->get_socket_id(adev) && 1654 !adev->smuio.funcs->get_die_id(adev)) 1655 return smu_cmn_send_smc_msg_with_param(smu, 1656 SMU_MSG_GmiPwrDnControl, 1657 en ? 0 : 1, 1658 NULL); 1659 else 1660 return 0; 1661 } 1662 1663 static const struct throttling_logging_label { 1664 uint32_t feature_mask; 1665 const char *label; 1666 } logging_label[] = { 1667 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1668 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1669 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1670 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1671 }; 1672 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1673 { 1674 int ret; 1675 int throttler_idx, throtting_events = 0, buf_idx = 0; 1676 struct amdgpu_device *adev = smu->adev; 1677 uint32_t throttler_status; 1678 char log_buf[256]; 1679 1680 ret = aldebaran_get_smu_metrics_data(smu, 1681 METRICS_THROTTLER_STATUS, 1682 &throttler_status); 1683 if (ret) 1684 return; 1685 1686 memset(log_buf, 0, sizeof(log_buf)); 1687 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1688 throttler_idx++) { 1689 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1690 throtting_events++; 1691 buf_idx += snprintf(log_buf + buf_idx, 1692 sizeof(log_buf) - buf_idx, 1693 "%s%s", 1694 throtting_events > 1 ? " and " : "", 1695 logging_label[throttler_idx].label); 1696 if (buf_idx >= sizeof(log_buf)) { 1697 dev_err(adev->dev, "buffer overflow!\n"); 1698 log_buf[sizeof(log_buf) - 1] = '\0'; 1699 break; 1700 } 1701 } 1702 } 1703 1704 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1705 log_buf); 1706 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 1707 smu_cmn_get_indep_throttler_status(throttler_status, 1708 aldebaran_throttler_map)); 1709 } 1710 1711 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1712 { 1713 struct amdgpu_device *adev = smu->adev; 1714 uint32_t esm_ctrl; 1715 1716 /* TODO: confirm this on real target */ 1717 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1718 if ((esm_ctrl >> 15) & 0x1FFFF) 1719 return (((esm_ctrl >> 8) & 0x3F) + 128); 1720 1721 return smu_v13_0_get_current_pcie_link_speed(smu); 1722 } 1723 1724 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1725 void **table) 1726 { 1727 struct smu_table_context *smu_table = &smu->smu_table; 1728 struct gpu_metrics_v1_3 *gpu_metrics = 1729 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1730 SmuMetrics_t metrics; 1731 int i, ret = 0; 1732 1733 ret = smu_cmn_get_metrics_table(smu, 1734 &metrics, 1735 true); 1736 if (ret) 1737 return ret; 1738 1739 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1740 1741 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1742 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1743 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1744 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1745 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1746 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1747 1748 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1749 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1750 gpu_metrics->average_mm_activity = 0; 1751 1752 /* Valid power data is available only from primary die */ 1753 if (aldebaran_is_primary(smu)) { 1754 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1755 gpu_metrics->energy_accumulator = 1756 (uint64_t)metrics.EnergyAcc64bitHigh << 32 | 1757 metrics.EnergyAcc64bitLow; 1758 } else { 1759 gpu_metrics->average_socket_power = 0; 1760 gpu_metrics->energy_accumulator = 0; 1761 } 1762 1763 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1764 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1765 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1766 gpu_metrics->average_vclk0_frequency = 0; 1767 gpu_metrics->average_dclk0_frequency = 0; 1768 1769 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1770 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1771 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1772 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1773 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1774 1775 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1776 gpu_metrics->indep_throttle_status = 1777 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1778 aldebaran_throttler_map); 1779 1780 gpu_metrics->current_fan_speed = 0; 1781 1782 gpu_metrics->pcie_link_width = 1783 smu_v13_0_get_current_pcie_link_width(smu); 1784 gpu_metrics->pcie_link_speed = 1785 aldebaran_get_current_pcie_link_speed(smu); 1786 1787 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1788 1789 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1790 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1791 1792 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1793 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1794 1795 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) | 1796 metrics.TimeStampLow; 1797 1798 *table = (void *)gpu_metrics; 1799 1800 return sizeof(struct gpu_metrics_v1_3); 1801 } 1802 1803 static int aldebaran_check_ecc_table_support(struct smu_context *smu) 1804 { 1805 uint32_t if_version = 0xff, smu_version = 0xff; 1806 int ret = 0; 1807 1808 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 1809 if (ret) { 1810 /* return not support if failed get smu_version */ 1811 ret = -EOPNOTSUPP; 1812 } 1813 1814 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) 1815 ret = -EOPNOTSUPP; 1816 1817 return ret; 1818 } 1819 1820 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, 1821 void *table) 1822 { 1823 struct smu_table_context *smu_table = &smu->smu_table; 1824 EccInfoTable_t *ecc_table = NULL; 1825 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 1826 int i, ret = 0; 1827 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 1828 1829 ret = aldebaran_check_ecc_table_support(smu); 1830 if (ret) 1831 return ret; 1832 1833 ret = smu_cmn_update_table(smu, 1834 SMU_TABLE_ECCINFO, 1835 0, 1836 smu_table->ecc_table, 1837 false); 1838 if (ret) { 1839 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 1840 return ret; 1841 } 1842 1843 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 1844 1845 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1846 ecc_info_per_channel = &(eccinfo->ecc[i]); 1847 ecc_info_per_channel->ce_count_lo_chip = 1848 ecc_table->EccInfo[i].ce_count_lo_chip; 1849 ecc_info_per_channel->ce_count_hi_chip = 1850 ecc_table->EccInfo[i].ce_count_hi_chip; 1851 ecc_info_per_channel->mca_umc_status = 1852 ecc_table->EccInfo[i].mca_umc_status; 1853 ecc_info_per_channel->mca_umc_addr = 1854 ecc_table->EccInfo[i].mca_umc_addr; 1855 } 1856 1857 return ret; 1858 } 1859 1860 static int aldebaran_mode1_reset(struct smu_context *smu) 1861 { 1862 u32 smu_version, fatal_err, param; 1863 int ret = 0; 1864 struct amdgpu_device *adev = smu->adev; 1865 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1866 1867 fatal_err = 0; 1868 param = SMU_RESET_MODE_1; 1869 1870 /* 1871 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 1872 */ 1873 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1874 if (smu_version < 0x00440700) { 1875 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1876 } 1877 else { 1878 /* fatal error triggered by ras, PMFW supports the flag 1879 from 68.44.0 */ 1880 if ((smu_version >= 0x00442c00) && ras && 1881 atomic_read(&ras->in_recovery)) 1882 fatal_err = 1; 1883 1884 param |= (fatal_err << 16); 1885 ret = smu_cmn_send_smc_msg_with_param(smu, 1886 SMU_MSG_GfxDeviceDriverReset, param, NULL); 1887 } 1888 1889 if (!ret) 1890 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 1891 1892 return ret; 1893 } 1894 1895 static int aldebaran_mode2_reset(struct smu_context *smu) 1896 { 1897 u32 smu_version; 1898 int ret = 0, index; 1899 struct amdgpu_device *adev = smu->adev; 1900 int timeout = 10; 1901 1902 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1903 1904 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1905 SMU_MSG_GfxDeviceDriverReset); 1906 1907 mutex_lock(&smu->message_lock); 1908 if (smu_version >= 0x00441400) { 1909 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1910 /* This is similar to FLR, wait till max FLR timeout */ 1911 msleep(100); 1912 dev_dbg(smu->adev->dev, "restore config space...\n"); 1913 /* Restore the config space saved during init */ 1914 amdgpu_device_load_pci_state(adev->pdev); 1915 1916 dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1917 while (ret == -ETIME && timeout) { 1918 ret = smu_cmn_wait_for_response(smu); 1919 /* Wait a bit more time for getting ACK */ 1920 if (ret == -ETIME) { 1921 --timeout; 1922 usleep_range(500, 1000); 1923 continue; 1924 } 1925 1926 if (ret != 1) { 1927 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n", 1928 SMU_RESET_MODE_2, ret); 1929 goto out; 1930 } 1931 } 1932 1933 } else { 1934 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", 1935 smu_version); 1936 } 1937 1938 if (ret == 1) 1939 ret = 0; 1940 out: 1941 mutex_unlock(&smu->message_lock); 1942 1943 return ret; 1944 } 1945 1946 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 1947 { 1948 int ret = 0; 1949 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL); 1950 1951 return ret; 1952 } 1953 1954 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1955 { 1956 #if 0 1957 struct amdgpu_device *adev = smu->adev; 1958 u32 smu_version; 1959 uint32_t val; 1960 /** 1961 * PM FW version support mode1 reset from 68.07 1962 */ 1963 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1964 if ((smu_version < 0x00440700)) 1965 return false; 1966 /** 1967 * mode1 reset relies on PSP, so we should check if 1968 * PSP is alive. 1969 */ 1970 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1971 1972 return val != 0x0; 1973 #endif 1974 return true; 1975 } 1976 1977 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 1978 { 1979 return true; 1980 } 1981 1982 static int aldebaran_set_mp1_state(struct smu_context *smu, 1983 enum pp_mp1_state mp1_state) 1984 { 1985 switch (mp1_state) { 1986 case PP_MP1_STATE_UNLOAD: 1987 return smu_cmn_set_mp1_state(smu, mp1_state); 1988 default: 1989 return 0; 1990 } 1991 } 1992 1993 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, 1994 uint32_t size) 1995 { 1996 int ret = 0; 1997 1998 /* message SMU to update the bad page number on SMUBUS */ 1999 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL); 2000 if (ret) 2001 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n", 2002 __func__); 2003 2004 return ret; 2005 } 2006 2007 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu) 2008 { 2009 uint32_t if_version = 0xff, smu_version = 0xff; 2010 int ret = 0; 2011 2012 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 2013 if (ret) { 2014 /* return not support if failed get smu_version */ 2015 ret = -EOPNOTSUPP; 2016 } 2017 2018 if (smu_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION) 2019 ret = -EOPNOTSUPP; 2020 2021 return ret; 2022 } 2023 2024 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu, 2025 uint32_t size) 2026 { 2027 int ret = 0; 2028 2029 ret = aldebaran_check_bad_channel_info_support(smu); 2030 if (ret) 2031 return ret; 2032 2033 /* message SMU to update the bad channel info on SMUBUS */ 2034 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL); 2035 if (ret) 2036 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n", 2037 __func__); 2038 2039 return ret; 2040 } 2041 2042 static const struct pptable_funcs aldebaran_ppt_funcs = { 2043 /* init dpm */ 2044 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 2045 /* dpm/clk tables */ 2046 .set_default_dpm_table = aldebaran_set_default_dpm_table, 2047 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 2048 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 2049 .print_clk_levels = aldebaran_print_clk_levels, 2050 .force_clk_levels = aldebaran_force_clk_levels, 2051 .read_sensor = aldebaran_read_sensor, 2052 .set_performance_level = aldebaran_set_performance_level, 2053 .get_power_limit = aldebaran_get_power_limit, 2054 .is_dpm_running = aldebaran_is_dpm_running, 2055 .get_unique_id = aldebaran_get_unique_id, 2056 .init_microcode = smu_v13_0_init_microcode, 2057 .load_microcode = smu_v13_0_load_microcode, 2058 .fini_microcode = smu_v13_0_fini_microcode, 2059 .init_smc_tables = aldebaran_init_smc_tables, 2060 .fini_smc_tables = smu_v13_0_fini_smc_tables, 2061 .init_power = smu_v13_0_init_power, 2062 .fini_power = smu_v13_0_fini_power, 2063 .check_fw_status = smu_v13_0_check_fw_status, 2064 /* pptable related */ 2065 .setup_pptable = aldebaran_setup_pptable, 2066 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 2067 .check_fw_version = smu_v13_0_check_fw_version, 2068 .write_pptable = smu_cmn_write_pptable, 2069 .set_driver_table_location = smu_v13_0_set_driver_table_location, 2070 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2071 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2072 .system_features_control = aldebaran_system_features_control, 2073 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2074 .send_smc_msg = smu_cmn_send_smc_msg, 2075 .get_enabled_mask = smu_cmn_get_enabled_mask, 2076 .feature_is_enabled = smu_cmn_feature_is_enabled, 2077 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2078 .set_power_limit = aldebaran_set_power_limit, 2079 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 2080 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2081 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2082 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 2083 .register_irq_handler = smu_v13_0_register_irq_handler, 2084 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 2085 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 2086 .baco_is_support= aldebaran_is_baco_supported, 2087 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 2088 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 2089 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 2090 .set_df_cstate = aldebaran_set_df_cstate, 2091 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down, 2092 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 2093 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2094 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2095 .get_gpu_metrics = aldebaran_get_gpu_metrics, 2096 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 2097 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 2098 .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr, 2099 .mode1_reset = aldebaran_mode1_reset, 2100 .set_mp1_state = aldebaran_set_mp1_state, 2101 .mode2_reset = aldebaran_mode2_reset, 2102 .wait_for_event = smu_v13_0_wait_for_event, 2103 .i2c_init = aldebaran_i2c_control_init, 2104 .i2c_fini = aldebaran_i2c_control_fini, 2105 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num, 2106 .get_ecc_info = aldebaran_get_ecc_info, 2107 .send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag, 2108 }; 2109 2110 void aldebaran_set_ppt_funcs(struct smu_context *smu) 2111 { 2112 smu->ppt_funcs = &aldebaran_ppt_funcs; 2113 smu->message_map = aldebaran_message_map; 2114 smu->clock_map = aldebaran_clk_map; 2115 smu->feature_map = aldebaran_feature_mask_map; 2116 smu->table_map = aldebaran_table_map; 2117 } 2118