1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_dpm.h" 29 #include "amdgpu_smu.h" 30 #include "atomfirmware.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_atombios.h" 33 #include "smu_v13_0.h" 34 #include "smu13_driver_if_aldebaran.h" 35 #include "soc15_common.h" 36 #include "atom.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 61 [smu_feature] = {1, (aldebaran_feature)} 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 73 74 /* possible frequency drift (1Mhz) */ 75 #define EPSILON 1 76 77 #define smnPCIE_ESM_CTRL 0x111003D0 78 79 /* 80 * SMU support ECCTABLE since version 68.42.0, 81 * use this to check ECCTALE feature whether support 82 */ 83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00 84 85 /* 86 * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0, 87 * use this to check mca_ceumc_addr record whether support 88 */ 89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700 90 91 /* 92 * SMU support BAD CHENNEL info MSG since version 68.51.00, 93 * use this to check ECCTALE feature whether support 94 */ 95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300 96 97 static const struct smu_temperature_range smu13_thermal_policy[] = { 98 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 99 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 100 }; 101 102 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 103 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 104 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 105 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 108 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 109 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 110 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 111 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 112 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 113 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 114 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 115 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 116 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 117 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 118 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 119 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 120 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 121 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 122 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 123 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 124 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 125 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 126 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 127 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 128 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 129 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 130 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 132 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 133 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 134 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 135 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 136 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 137 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 138 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 139 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 140 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 141 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 142 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 143 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 144 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 145 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 146 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 147 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 148 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 149 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 150 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 151 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 152 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0), 153 MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0), 154 MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel, PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel, 0), 155 }; 156 157 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 158 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 159 CLK_MAP(SCLK, PPCLK_GFXCLK), 160 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 161 CLK_MAP(FCLK, PPCLK_FCLK), 162 CLK_MAP(UCLK, PPCLK_UCLK), 163 CLK_MAP(MCLK, PPCLK_UCLK), 164 CLK_MAP(DCLK, PPCLK_DCLK), 165 CLK_MAP(VCLK, PPCLK_VCLK), 166 CLK_MAP(LCLK, PPCLK_LCLK), 167 }; 168 169 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 170 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS), 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 175 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 176 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 177 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 178 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 179 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 180 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 181 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 182 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 183 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 184 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 185 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 186 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 187 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 188 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 189 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 190 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 191 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 192 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 193 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 194 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 195 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 196 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 197 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 198 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DWN), 199 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 200 }; 201 202 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 203 TAB_MAP(PPTABLE), 204 TAB_MAP(AVFS_PSM_DEBUG), 205 TAB_MAP(AVFS_FUSE_OVERRIDE), 206 TAB_MAP(PMSTATUSLOG), 207 TAB_MAP(SMU_METRICS), 208 TAB_MAP(DRIVER_SMU_CONFIG), 209 TAB_MAP(I2C_COMMANDS), 210 TAB_MAP(ECCINFO), 211 }; 212 213 static const uint8_t aldebaran_throttler_map[] = { 214 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 215 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 216 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 217 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 218 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT), 219 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), 220 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 221 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 222 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 223 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 224 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 225 }; 226 227 static int aldebaran_tables_init(struct smu_context *smu) 228 { 229 struct smu_table_context *smu_table = &smu->smu_table; 230 struct smu_table *tables = smu_table->tables; 231 232 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 233 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 234 235 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 237 238 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 239 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 240 241 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 242 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 243 244 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 245 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 246 247 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 248 if (!smu_table->metrics_table) 249 return -ENOMEM; 250 smu_table->metrics_time = 0; 251 252 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 253 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 254 if (!smu_table->gpu_metrics_table) { 255 kfree(smu_table->metrics_table); 256 return -ENOMEM; 257 } 258 259 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 260 if (!smu_table->ecc_table) 261 return -ENOMEM; 262 263 return 0; 264 } 265 266 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 267 { 268 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 269 270 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 271 GFP_KERNEL); 272 if (!smu_dpm->dpm_context) 273 return -ENOMEM; 274 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 275 276 return 0; 277 } 278 279 static int aldebaran_init_smc_tables(struct smu_context *smu) 280 { 281 int ret = 0; 282 283 ret = aldebaran_tables_init(smu); 284 if (ret) 285 return ret; 286 287 ret = aldebaran_allocate_dpm_context(smu); 288 if (ret) 289 return ret; 290 291 return smu_v13_0_init_smc_tables(smu); 292 } 293 294 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 295 uint32_t *feature_mask, uint32_t num) 296 { 297 if (num > 2) 298 return -EINVAL; 299 300 /* pptable will handle the features to enable */ 301 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 302 303 return 0; 304 } 305 306 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 307 { 308 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 309 struct smu_13_0_dpm_table *dpm_table = NULL; 310 PPTable_t *pptable = smu->smu_table.driver_pptable; 311 int ret = 0; 312 313 /* socclk dpm table setup */ 314 dpm_table = &dpm_context->dpm_tables.soc_table; 315 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 316 ret = smu_v13_0_set_single_dpm_table(smu, 317 SMU_SOCCLK, 318 dpm_table); 319 if (ret) 320 return ret; 321 } else { 322 dpm_table->count = 1; 323 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 324 dpm_table->dpm_levels[0].enabled = true; 325 dpm_table->min = dpm_table->dpm_levels[0].value; 326 dpm_table->max = dpm_table->dpm_levels[0].value; 327 } 328 329 /* gfxclk dpm table setup */ 330 dpm_table = &dpm_context->dpm_tables.gfx_table; 331 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 332 /* in the case of gfxclk, only fine-grained dpm is honored */ 333 dpm_table->count = 2; 334 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 335 dpm_table->dpm_levels[0].enabled = true; 336 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 337 dpm_table->dpm_levels[1].enabled = true; 338 dpm_table->min = dpm_table->dpm_levels[0].value; 339 dpm_table->max = dpm_table->dpm_levels[1].value; 340 } else { 341 dpm_table->count = 1; 342 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 343 dpm_table->dpm_levels[0].enabled = true; 344 dpm_table->min = dpm_table->dpm_levels[0].value; 345 dpm_table->max = dpm_table->dpm_levels[0].value; 346 } 347 348 /* memclk dpm table setup */ 349 dpm_table = &dpm_context->dpm_tables.uclk_table; 350 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 351 ret = smu_v13_0_set_single_dpm_table(smu, 352 SMU_UCLK, 353 dpm_table); 354 if (ret) 355 return ret; 356 } else { 357 dpm_table->count = 1; 358 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 359 dpm_table->dpm_levels[0].enabled = true; 360 dpm_table->min = dpm_table->dpm_levels[0].value; 361 dpm_table->max = dpm_table->dpm_levels[0].value; 362 } 363 364 /* fclk dpm table setup */ 365 dpm_table = &dpm_context->dpm_tables.fclk_table; 366 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 367 ret = smu_v13_0_set_single_dpm_table(smu, 368 SMU_FCLK, 369 dpm_table); 370 if (ret) 371 return ret; 372 } else { 373 dpm_table->count = 1; 374 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 375 dpm_table->dpm_levels[0].enabled = true; 376 dpm_table->min = dpm_table->dpm_levels[0].value; 377 dpm_table->max = dpm_table->dpm_levels[0].value; 378 } 379 380 return 0; 381 } 382 383 static int aldebaran_check_powerplay_table(struct smu_context *smu) 384 { 385 struct smu_table_context *table_context = &smu->smu_table; 386 struct smu_13_0_powerplay_table *powerplay_table = 387 table_context->power_play_table; 388 389 table_context->thermal_controller_type = 390 powerplay_table->thermal_controller_type; 391 392 return 0; 393 } 394 395 static int aldebaran_store_powerplay_table(struct smu_context *smu) 396 { 397 struct smu_table_context *table_context = &smu->smu_table; 398 struct smu_13_0_powerplay_table *powerplay_table = 399 table_context->power_play_table; 400 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 401 sizeof(PPTable_t)); 402 403 return 0; 404 } 405 406 static int aldebaran_append_powerplay_table(struct smu_context *smu) 407 { 408 struct smu_table_context *table_context = &smu->smu_table; 409 PPTable_t *smc_pptable = table_context->driver_pptable; 410 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 411 int index, ret; 412 413 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 414 smc_dpm_info); 415 416 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 417 (uint8_t **)&smc_dpm_table); 418 if (ret) 419 return ret; 420 421 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 422 smc_dpm_table->table_header.format_revision, 423 smc_dpm_table->table_header.content_revision); 424 425 if ((smc_dpm_table->table_header.format_revision == 4) && 426 (smc_dpm_table->table_header.content_revision == 10)) 427 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved, 428 smc_dpm_table, GfxMaxCurrent); 429 return 0; 430 } 431 432 static int aldebaran_setup_pptable(struct smu_context *smu) 433 { 434 int ret = 0; 435 436 /* VBIOS pptable is the first choice */ 437 smu->smu_table.boot_values.pp_table_id = 0; 438 439 ret = smu_v13_0_setup_pptable(smu); 440 if (ret) 441 return ret; 442 443 ret = aldebaran_store_powerplay_table(smu); 444 if (ret) 445 return ret; 446 447 ret = aldebaran_append_powerplay_table(smu); 448 if (ret) 449 return ret; 450 451 ret = aldebaran_check_powerplay_table(smu); 452 if (ret) 453 return ret; 454 455 return ret; 456 } 457 458 static bool aldebaran_is_primary(struct smu_context *smu) 459 { 460 struct amdgpu_device *adev = smu->adev; 461 462 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) 463 return adev->smuio.funcs->get_die_id(adev) == 0; 464 465 return true; 466 } 467 468 static int aldebaran_run_board_btc(struct smu_context *smu) 469 { 470 u32 smu_version; 471 int ret; 472 473 if (!aldebaran_is_primary(smu)) 474 return 0; 475 476 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 477 if (ret) { 478 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 479 return ret; 480 } 481 if (smu_version <= 0x00441d00) 482 return 0; 483 484 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL); 485 if (ret) 486 dev_err(smu->adev->dev, "Board power calibration failed!\n"); 487 488 return ret; 489 } 490 491 static int aldebaran_run_btc(struct smu_context *smu) 492 { 493 int ret; 494 495 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 496 if (ret) 497 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 498 else 499 ret = aldebaran_run_board_btc(smu); 500 501 return ret; 502 } 503 504 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 505 { 506 struct smu_13_0_dpm_context *dpm_context = 507 smu->smu_dpm.dpm_context; 508 struct smu_13_0_dpm_table *gfx_table = 509 &dpm_context->dpm_tables.gfx_table; 510 struct smu_13_0_dpm_table *mem_table = 511 &dpm_context->dpm_tables.uclk_table; 512 struct smu_13_0_dpm_table *soc_table = 513 &dpm_context->dpm_tables.soc_table; 514 struct smu_umd_pstate_table *pstate_table = 515 &smu->pstate_table; 516 517 pstate_table->gfxclk_pstate.min = gfx_table->min; 518 pstate_table->gfxclk_pstate.peak = gfx_table->max; 519 pstate_table->gfxclk_pstate.curr.min = gfx_table->min; 520 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 521 522 pstate_table->uclk_pstate.min = mem_table->min; 523 pstate_table->uclk_pstate.peak = mem_table->max; 524 pstate_table->uclk_pstate.curr.min = mem_table->min; 525 pstate_table->uclk_pstate.curr.max = mem_table->max; 526 527 pstate_table->socclk_pstate.min = soc_table->min; 528 pstate_table->socclk_pstate.peak = soc_table->max; 529 pstate_table->socclk_pstate.curr.min = soc_table->min; 530 pstate_table->socclk_pstate.curr.max = soc_table->max; 531 532 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 533 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 534 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 535 pstate_table->gfxclk_pstate.standard = 536 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 537 pstate_table->uclk_pstate.standard = 538 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 539 pstate_table->socclk_pstate.standard = 540 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 541 } else { 542 pstate_table->gfxclk_pstate.standard = 543 pstate_table->gfxclk_pstate.min; 544 pstate_table->uclk_pstate.standard = 545 pstate_table->uclk_pstate.min; 546 pstate_table->socclk_pstate.standard = 547 pstate_table->socclk_pstate.min; 548 } 549 550 return 0; 551 } 552 553 static int aldebaran_get_clk_table(struct smu_context *smu, 554 struct pp_clock_levels_with_latency *clocks, 555 struct smu_13_0_dpm_table *dpm_table) 556 { 557 uint32_t i; 558 559 clocks->num_levels = min_t(uint32_t, 560 dpm_table->count, 561 (uint32_t)PP_MAX_CLOCK_LEVELS); 562 563 for (i = 0; i < clocks->num_levels; i++) { 564 clocks->data[i].clocks_in_khz = 565 dpm_table->dpm_levels[i].value * 1000; 566 clocks->data[i].latency_in_us = 0; 567 } 568 569 return 0; 570 } 571 572 static int aldebaran_freqs_in_same_level(int32_t frequency1, 573 int32_t frequency2) 574 { 575 return (abs(frequency1 - frequency2) <= EPSILON); 576 } 577 578 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 579 MetricsMember_t member, 580 uint32_t *value) 581 { 582 struct smu_table_context *smu_table = &smu->smu_table; 583 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 584 int ret = 0; 585 586 ret = smu_cmn_get_metrics_table(smu, 587 NULL, 588 false); 589 if (ret) 590 return ret; 591 592 switch (member) { 593 case METRICS_CURR_GFXCLK: 594 *value = metrics->CurrClock[PPCLK_GFXCLK]; 595 break; 596 case METRICS_CURR_SOCCLK: 597 *value = metrics->CurrClock[PPCLK_SOCCLK]; 598 break; 599 case METRICS_CURR_UCLK: 600 *value = metrics->CurrClock[PPCLK_UCLK]; 601 break; 602 case METRICS_CURR_VCLK: 603 *value = metrics->CurrClock[PPCLK_VCLK]; 604 break; 605 case METRICS_CURR_DCLK: 606 *value = metrics->CurrClock[PPCLK_DCLK]; 607 break; 608 case METRICS_CURR_FCLK: 609 *value = metrics->CurrClock[PPCLK_FCLK]; 610 break; 611 case METRICS_AVERAGE_GFXCLK: 612 *value = metrics->AverageGfxclkFrequency; 613 break; 614 case METRICS_AVERAGE_SOCCLK: 615 *value = metrics->AverageSocclkFrequency; 616 break; 617 case METRICS_AVERAGE_UCLK: 618 *value = metrics->AverageUclkFrequency; 619 break; 620 case METRICS_AVERAGE_GFXACTIVITY: 621 *value = metrics->AverageGfxActivity; 622 break; 623 case METRICS_AVERAGE_MEMACTIVITY: 624 *value = metrics->AverageUclkActivity; 625 break; 626 case METRICS_AVERAGE_SOCKETPOWER: 627 /* Valid power data is available only from primary die */ 628 *value = aldebaran_is_primary(smu) ? 629 metrics->AverageSocketPower << 8 : 630 0; 631 break; 632 case METRICS_TEMPERATURE_EDGE: 633 *value = metrics->TemperatureEdge * 634 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 635 break; 636 case METRICS_TEMPERATURE_HOTSPOT: 637 *value = metrics->TemperatureHotspot * 638 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 639 break; 640 case METRICS_TEMPERATURE_MEM: 641 *value = metrics->TemperatureHBM * 642 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 643 break; 644 case METRICS_TEMPERATURE_VRGFX: 645 *value = metrics->TemperatureVrGfx * 646 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 647 break; 648 case METRICS_TEMPERATURE_VRSOC: 649 *value = metrics->TemperatureVrSoc * 650 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 651 break; 652 case METRICS_TEMPERATURE_VRMEM: 653 *value = metrics->TemperatureVrMem * 654 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 655 break; 656 case METRICS_THROTTLER_STATUS: 657 *value = metrics->ThrottlerStatus; 658 break; 659 case METRICS_UNIQUE_ID_UPPER32: 660 *value = metrics->PublicSerialNumUpper32; 661 break; 662 case METRICS_UNIQUE_ID_LOWER32: 663 *value = metrics->PublicSerialNumLower32; 664 break; 665 default: 666 *value = UINT_MAX; 667 break; 668 } 669 670 return ret; 671 } 672 673 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 674 enum smu_clk_type clk_type, 675 uint32_t *value) 676 { 677 MetricsMember_t member_type; 678 int clk_id = 0; 679 680 if (!value) 681 return -EINVAL; 682 683 clk_id = smu_cmn_to_asic_specific_index(smu, 684 CMN2ASIC_MAPPING_CLK, 685 clk_type); 686 if (clk_id < 0) 687 return -EINVAL; 688 689 switch (clk_id) { 690 case PPCLK_GFXCLK: 691 /* 692 * CurrClock[clk_id] can provide accurate 693 * output only when the dpm feature is enabled. 694 * We can use Average_* for dpm disabled case. 695 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 696 */ 697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 698 member_type = METRICS_CURR_GFXCLK; 699 else 700 member_type = METRICS_AVERAGE_GFXCLK; 701 break; 702 case PPCLK_UCLK: 703 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 704 member_type = METRICS_CURR_UCLK; 705 else 706 member_type = METRICS_AVERAGE_UCLK; 707 break; 708 case PPCLK_SOCCLK: 709 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 710 member_type = METRICS_CURR_SOCCLK; 711 else 712 member_type = METRICS_AVERAGE_SOCCLK; 713 break; 714 case PPCLK_VCLK: 715 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 716 member_type = METRICS_CURR_VCLK; 717 else 718 member_type = METRICS_AVERAGE_VCLK; 719 break; 720 case PPCLK_DCLK: 721 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 722 member_type = METRICS_CURR_DCLK; 723 else 724 member_type = METRICS_AVERAGE_DCLK; 725 break; 726 case PPCLK_FCLK: 727 member_type = METRICS_CURR_FCLK; 728 break; 729 default: 730 return -EINVAL; 731 } 732 733 return aldebaran_get_smu_metrics_data(smu, 734 member_type, 735 value); 736 } 737 738 static int aldebaran_print_clk_levels(struct smu_context *smu, 739 enum smu_clk_type type, char *buf) 740 { 741 int i, now, size = 0; 742 int ret = 0; 743 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 744 struct pp_clock_levels_with_latency clocks; 745 struct smu_13_0_dpm_table *single_dpm_table; 746 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 747 struct smu_13_0_dpm_context *dpm_context = NULL; 748 int display_levels; 749 uint32_t freq_values[3] = {0}; 750 uint32_t min_clk, max_clk; 751 752 smu_cmn_get_sysfs_buf(&buf, &size); 753 754 if (amdgpu_ras_intr_triggered()) { 755 size += sysfs_emit_at(buf, size, "unavailable\n"); 756 return size; 757 } 758 759 dpm_context = smu_dpm->dpm_context; 760 761 switch (type) { 762 763 case SMU_OD_SCLK: 764 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK"); 765 fallthrough; 766 case SMU_SCLK: 767 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 768 if (ret) { 769 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 770 return ret; 771 } 772 773 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 774 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 775 if (ret) { 776 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 777 return ret; 778 } 779 780 display_levels = (clocks.num_levels == 1) ? 1 : 2; 781 782 min_clk = pstate_table->gfxclk_pstate.curr.min; 783 max_clk = pstate_table->gfxclk_pstate.curr.max; 784 785 freq_values[0] = min_clk; 786 freq_values[1] = max_clk; 787 788 /* fine-grained dpm has only 2 levels */ 789 if (now > min_clk && now < max_clk) { 790 display_levels++; 791 freq_values[2] = max_clk; 792 freq_values[1] = now; 793 } 794 795 for (i = 0; i < display_levels; i++) 796 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 797 freq_values[i], 798 (display_levels == 1) ? 799 "*" : 800 (aldebaran_freqs_in_same_level( 801 freq_values[i], now) ? 802 "*" : 803 "")); 804 805 break; 806 807 case SMU_OD_MCLK: 808 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK"); 809 fallthrough; 810 case SMU_MCLK: 811 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 812 if (ret) { 813 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 814 return ret; 815 } 816 817 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 818 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 819 if (ret) { 820 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 821 return ret; 822 } 823 824 for (i = 0; i < clocks.num_levels; i++) 825 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 826 i, clocks.data[i].clocks_in_khz / 1000, 827 (clocks.num_levels == 1) ? "*" : 828 (aldebaran_freqs_in_same_level( 829 clocks.data[i].clocks_in_khz / 1000, 830 now) ? "*" : "")); 831 break; 832 833 case SMU_SOCCLK: 834 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 835 if (ret) { 836 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 837 return ret; 838 } 839 840 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 841 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 842 if (ret) { 843 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 844 return ret; 845 } 846 847 for (i = 0; i < clocks.num_levels; i++) 848 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 849 i, clocks.data[i].clocks_in_khz / 1000, 850 (clocks.num_levels == 1) ? "*" : 851 (aldebaran_freqs_in_same_level( 852 clocks.data[i].clocks_in_khz / 1000, 853 now) ? "*" : "")); 854 break; 855 856 case SMU_FCLK: 857 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 858 if (ret) { 859 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 860 return ret; 861 } 862 863 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 864 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 865 if (ret) { 866 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 867 return ret; 868 } 869 870 for (i = 0; i < single_dpm_table->count; i++) 871 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 872 i, single_dpm_table->dpm_levels[i].value, 873 (clocks.num_levels == 1) ? "*" : 874 (aldebaran_freqs_in_same_level( 875 clocks.data[i].clocks_in_khz / 1000, 876 now) ? "*" : "")); 877 break; 878 879 case SMU_VCLK: 880 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); 881 if (ret) { 882 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); 883 return ret; 884 } 885 886 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 887 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 888 if (ret) { 889 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); 890 return ret; 891 } 892 893 for (i = 0; i < single_dpm_table->count; i++) 894 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 895 i, single_dpm_table->dpm_levels[i].value, 896 (clocks.num_levels == 1) ? "*" : 897 (aldebaran_freqs_in_same_level( 898 clocks.data[i].clocks_in_khz / 1000, 899 now) ? "*" : "")); 900 break; 901 902 case SMU_DCLK: 903 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); 904 if (ret) { 905 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); 906 return ret; 907 } 908 909 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 910 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 911 if (ret) { 912 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); 913 return ret; 914 } 915 916 for (i = 0; i < single_dpm_table->count; i++) 917 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 918 i, single_dpm_table->dpm_levels[i].value, 919 (clocks.num_levels == 1) ? "*" : 920 (aldebaran_freqs_in_same_level( 921 clocks.data[i].clocks_in_khz / 1000, 922 now) ? "*" : "")); 923 break; 924 925 default: 926 break; 927 } 928 929 return size; 930 } 931 932 static int aldebaran_upload_dpm_level(struct smu_context *smu, 933 bool max, 934 uint32_t feature_mask, 935 uint32_t level) 936 { 937 struct smu_13_0_dpm_context *dpm_context = 938 smu->smu_dpm.dpm_context; 939 uint32_t freq; 940 int ret = 0; 941 942 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 943 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 944 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 945 ret = smu_cmn_send_smc_msg_with_param(smu, 946 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 947 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 948 NULL); 949 if (ret) { 950 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 951 max ? "max" : "min"); 952 return ret; 953 } 954 } 955 956 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 957 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 958 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 959 ret = smu_cmn_send_smc_msg_with_param(smu, 960 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 961 (PPCLK_UCLK << 16) | (freq & 0xffff), 962 NULL); 963 if (ret) { 964 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 965 max ? "max" : "min"); 966 return ret; 967 } 968 } 969 970 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 971 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 972 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 973 ret = smu_cmn_send_smc_msg_with_param(smu, 974 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 975 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 976 NULL); 977 if (ret) { 978 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 979 max ? "max" : "min"); 980 return ret; 981 } 982 } 983 984 return ret; 985 } 986 987 static int aldebaran_force_clk_levels(struct smu_context *smu, 988 enum smu_clk_type type, uint32_t mask) 989 { 990 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 991 struct smu_13_0_dpm_table *single_dpm_table = NULL; 992 uint32_t soft_min_level, soft_max_level; 993 int ret = 0; 994 995 soft_min_level = mask ? (ffs(mask) - 1) : 0; 996 soft_max_level = mask ? (fls(mask) - 1) : 0; 997 998 switch (type) { 999 case SMU_SCLK: 1000 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1001 if (soft_max_level >= single_dpm_table->count) { 1002 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 1003 soft_max_level, single_dpm_table->count - 1); 1004 ret = -EINVAL; 1005 break; 1006 } 1007 1008 ret = aldebaran_upload_dpm_level(smu, 1009 false, 1010 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1011 soft_min_level); 1012 if (ret) { 1013 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1014 break; 1015 } 1016 1017 ret = aldebaran_upload_dpm_level(smu, 1018 true, 1019 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1020 soft_max_level); 1021 if (ret) 1022 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1023 1024 break; 1025 1026 case SMU_MCLK: 1027 case SMU_SOCCLK: 1028 case SMU_FCLK: 1029 /* 1030 * Should not arrive here since aldebaran does not 1031 * support mclk/socclk/fclk softmin/softmax settings 1032 */ 1033 ret = -EINVAL; 1034 break; 1035 1036 default: 1037 break; 1038 } 1039 1040 return ret; 1041 } 1042 1043 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 1044 struct smu_temperature_range *range) 1045 { 1046 struct smu_table_context *table_context = &smu->smu_table; 1047 struct smu_13_0_powerplay_table *powerplay_table = 1048 table_context->power_play_table; 1049 PPTable_t *pptable = smu->smu_table.driver_pptable; 1050 1051 if (!range) 1052 return -EINVAL; 1053 1054 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1055 1056 range->hotspot_crit_max = pptable->ThotspotLimit * 1057 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1058 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1059 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1060 range->mem_crit_max = pptable->TmemLimit * 1061 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1062 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1063 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1064 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1065 1066 return 0; 1067 } 1068 1069 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 1070 enum amd_pp_sensors sensor, 1071 uint32_t *value) 1072 { 1073 int ret = 0; 1074 1075 if (!value) 1076 return -EINVAL; 1077 1078 switch (sensor) { 1079 case AMDGPU_PP_SENSOR_GPU_LOAD: 1080 ret = aldebaran_get_smu_metrics_data(smu, 1081 METRICS_AVERAGE_GFXACTIVITY, 1082 value); 1083 break; 1084 case AMDGPU_PP_SENSOR_MEM_LOAD: 1085 ret = aldebaran_get_smu_metrics_data(smu, 1086 METRICS_AVERAGE_MEMACTIVITY, 1087 value); 1088 break; 1089 default: 1090 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 1091 return -EINVAL; 1092 } 1093 1094 return ret; 1095 } 1096 1097 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value) 1098 { 1099 if (!value) 1100 return -EINVAL; 1101 1102 return aldebaran_get_smu_metrics_data(smu, 1103 METRICS_AVERAGE_SOCKETPOWER, 1104 value); 1105 } 1106 1107 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 1108 enum amd_pp_sensors sensor, 1109 uint32_t *value) 1110 { 1111 int ret = 0; 1112 1113 if (!value) 1114 return -EINVAL; 1115 1116 switch (sensor) { 1117 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1118 ret = aldebaran_get_smu_metrics_data(smu, 1119 METRICS_TEMPERATURE_HOTSPOT, 1120 value); 1121 break; 1122 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1123 ret = aldebaran_get_smu_metrics_data(smu, 1124 METRICS_TEMPERATURE_EDGE, 1125 value); 1126 break; 1127 case AMDGPU_PP_SENSOR_MEM_TEMP: 1128 ret = aldebaran_get_smu_metrics_data(smu, 1129 METRICS_TEMPERATURE_MEM, 1130 value); 1131 break; 1132 default: 1133 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1134 return -EINVAL; 1135 } 1136 1137 return ret; 1138 } 1139 1140 static int aldebaran_read_sensor(struct smu_context *smu, 1141 enum amd_pp_sensors sensor, 1142 void *data, uint32_t *size) 1143 { 1144 int ret = 0; 1145 1146 if (amdgpu_ras_intr_triggered()) 1147 return 0; 1148 1149 if (!data || !size) 1150 return -EINVAL; 1151 1152 switch (sensor) { 1153 case AMDGPU_PP_SENSOR_MEM_LOAD: 1154 case AMDGPU_PP_SENSOR_GPU_LOAD: 1155 ret = aldebaran_get_current_activity_percent(smu, 1156 sensor, 1157 (uint32_t *)data); 1158 *size = 4; 1159 break; 1160 case AMDGPU_PP_SENSOR_GPU_POWER: 1161 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data); 1162 *size = 4; 1163 break; 1164 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1165 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1166 case AMDGPU_PP_SENSOR_MEM_TEMP: 1167 ret = aldebaran_thermal_get_temperature(smu, sensor, 1168 (uint32_t *)data); 1169 *size = 4; 1170 break; 1171 case AMDGPU_PP_SENSOR_GFX_MCLK: 1172 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1173 /* the output clock frequency in 10K unit */ 1174 *(uint32_t *)data *= 100; 1175 *size = 4; 1176 break; 1177 case AMDGPU_PP_SENSOR_GFX_SCLK: 1178 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1179 *(uint32_t *)data *= 100; 1180 *size = 4; 1181 break; 1182 case AMDGPU_PP_SENSOR_VDDGFX: 1183 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1184 *size = 4; 1185 break; 1186 default: 1187 ret = -EOPNOTSUPP; 1188 break; 1189 } 1190 1191 return ret; 1192 } 1193 1194 static int aldebaran_get_power_limit(struct smu_context *smu, 1195 uint32_t *current_power_limit, 1196 uint32_t *default_power_limit, 1197 uint32_t *max_power_limit) 1198 { 1199 PPTable_t *pptable = smu->smu_table.driver_pptable; 1200 uint32_t power_limit = 0; 1201 int ret; 1202 1203 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1204 if (current_power_limit) 1205 *current_power_limit = 0; 1206 if (default_power_limit) 1207 *default_power_limit = 0; 1208 if (max_power_limit) 1209 *max_power_limit = 0; 1210 1211 dev_warn(smu->adev->dev, 1212 "PPT feature is not enabled, power values can't be fetched."); 1213 1214 return 0; 1215 } 1216 1217 /* Valid power data is available only from primary die. 1218 * For secondary die show the value as 0. 1219 */ 1220 if (aldebaran_is_primary(smu)) { 1221 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, 1222 &power_limit); 1223 1224 if (ret) { 1225 /* the last hope to figure out the ppt limit */ 1226 if (!pptable) { 1227 dev_err(smu->adev->dev, 1228 "Cannot get PPT limit due to pptable missing!"); 1229 return -EINVAL; 1230 } 1231 power_limit = pptable->PptLimit; 1232 } 1233 } 1234 1235 if (current_power_limit) 1236 *current_power_limit = power_limit; 1237 if (default_power_limit) 1238 *default_power_limit = power_limit; 1239 1240 if (max_power_limit) { 1241 if (pptable) 1242 *max_power_limit = pptable->PptLimit; 1243 } 1244 1245 return 0; 1246 } 1247 1248 static int aldebaran_set_power_limit(struct smu_context *smu, 1249 enum smu_ppt_limit_type limit_type, 1250 uint32_t limit) 1251 { 1252 /* Power limit can be set only through primary die */ 1253 if (aldebaran_is_primary(smu)) 1254 return smu_v13_0_set_power_limit(smu, limit_type, limit); 1255 1256 return -EINVAL; 1257 } 1258 1259 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1260 { 1261 int ret; 1262 1263 ret = smu_v13_0_system_features_control(smu, enable); 1264 if (!ret && enable) 1265 ret = aldebaran_run_btc(smu); 1266 1267 return ret; 1268 } 1269 1270 static int aldebaran_set_performance_level(struct smu_context *smu, 1271 enum amd_dpm_forced_level level) 1272 { 1273 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1274 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1275 struct smu_13_0_dpm_table *gfx_table = 1276 &dpm_context->dpm_tables.gfx_table; 1277 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1278 1279 /* Disable determinism if switching to another mode */ 1280 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && 1281 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { 1282 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1283 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 1284 } 1285 1286 switch (level) { 1287 1288 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1289 return 0; 1290 1291 case AMD_DPM_FORCED_LEVEL_HIGH: 1292 case AMD_DPM_FORCED_LEVEL_LOW: 1293 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1294 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1295 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1296 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1297 default: 1298 break; 1299 } 1300 1301 return smu_v13_0_set_performance_level(smu, level); 1302 } 1303 1304 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1305 enum smu_clk_type clk_type, 1306 uint32_t min, 1307 uint32_t max) 1308 { 1309 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1310 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1311 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1312 struct amdgpu_device *adev = smu->adev; 1313 uint32_t min_clk; 1314 uint32_t max_clk; 1315 int ret = 0; 1316 1317 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1318 return -EINVAL; 1319 1320 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1321 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1322 return -EINVAL; 1323 1324 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1325 if (min >= max) { 1326 dev_err(smu->adev->dev, 1327 "Minimum GFX clk should be less than the maximum allowed clock\n"); 1328 return -EINVAL; 1329 } 1330 1331 if ((min == pstate_table->gfxclk_pstate.curr.min) && 1332 (max == pstate_table->gfxclk_pstate.curr.max)) 1333 return 0; 1334 1335 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, 1336 min, max); 1337 if (!ret) { 1338 pstate_table->gfxclk_pstate.curr.min = min; 1339 pstate_table->gfxclk_pstate.curr.max = max; 1340 } 1341 1342 return ret; 1343 } 1344 1345 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1346 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1347 (max > dpm_context->dpm_tables.gfx_table.max)) { 1348 dev_warn(adev->dev, 1349 "Invalid max frequency %d MHz specified for determinism\n", max); 1350 return -EINVAL; 1351 } 1352 1353 /* Restore default min/max clocks and enable determinism */ 1354 min_clk = dpm_context->dpm_tables.gfx_table.min; 1355 max_clk = dpm_context->dpm_tables.gfx_table.max; 1356 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1357 if (!ret) { 1358 usleep_range(500, 1000); 1359 ret = smu_cmn_send_smc_msg_with_param(smu, 1360 SMU_MSG_EnableDeterminism, 1361 max, NULL); 1362 if (ret) { 1363 dev_err(adev->dev, 1364 "Failed to enable determinism at GFX clock %d MHz\n", max); 1365 } else { 1366 pstate_table->gfxclk_pstate.curr.min = min_clk; 1367 pstate_table->gfxclk_pstate.curr.max = max; 1368 } 1369 } 1370 } 1371 1372 return ret; 1373 } 1374 1375 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1376 long input[], uint32_t size) 1377 { 1378 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1379 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1380 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1381 uint32_t min_clk; 1382 uint32_t max_clk; 1383 int ret = 0; 1384 1385 /* Only allowed in manual or determinism mode */ 1386 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1387 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1388 return -EINVAL; 1389 1390 switch (type) { 1391 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1392 if (size != 2) { 1393 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1394 return -EINVAL; 1395 } 1396 1397 if (input[0] == 0) { 1398 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1399 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1400 input[1], dpm_context->dpm_tables.gfx_table.min); 1401 pstate_table->gfxclk_pstate.custom.min = 1402 pstate_table->gfxclk_pstate.curr.min; 1403 return -EINVAL; 1404 } 1405 1406 pstate_table->gfxclk_pstate.custom.min = input[1]; 1407 } else if (input[0] == 1) { 1408 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1409 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1410 input[1], dpm_context->dpm_tables.gfx_table.max); 1411 pstate_table->gfxclk_pstate.custom.max = 1412 pstate_table->gfxclk_pstate.curr.max; 1413 return -EINVAL; 1414 } 1415 1416 pstate_table->gfxclk_pstate.custom.max = input[1]; 1417 } else { 1418 return -EINVAL; 1419 } 1420 break; 1421 case PP_OD_RESTORE_DEFAULT_TABLE: 1422 if (size != 0) { 1423 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1424 return -EINVAL; 1425 } else { 1426 /* Use the default frequencies for manual and determinism mode */ 1427 min_clk = dpm_context->dpm_tables.gfx_table.min; 1428 max_clk = dpm_context->dpm_tables.gfx_table.max; 1429 1430 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1431 } 1432 break; 1433 case PP_OD_COMMIT_DPM_TABLE: 1434 if (size != 0) { 1435 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1436 return -EINVAL; 1437 } else { 1438 if (!pstate_table->gfxclk_pstate.custom.min) 1439 pstate_table->gfxclk_pstate.custom.min = 1440 pstate_table->gfxclk_pstate.curr.min; 1441 1442 if (!pstate_table->gfxclk_pstate.custom.max) 1443 pstate_table->gfxclk_pstate.custom.max = 1444 pstate_table->gfxclk_pstate.curr.max; 1445 1446 min_clk = pstate_table->gfxclk_pstate.custom.min; 1447 max_clk = pstate_table->gfxclk_pstate.custom.max; 1448 1449 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1450 } 1451 break; 1452 default: 1453 return -ENOSYS; 1454 } 1455 1456 return ret; 1457 } 1458 1459 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1460 { 1461 int ret; 1462 uint64_t feature_enabled; 1463 1464 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1465 if (ret) 1466 return false; 1467 return !!(feature_enabled & SMC_DPM_FEATURE); 1468 } 1469 1470 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1471 struct i2c_msg *msg, int num_msgs) 1472 { 1473 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 1474 struct amdgpu_device *adev = smu_i2c->adev; 1475 struct smu_context *smu = adev->powerplay.pp_handle; 1476 struct smu_table_context *smu_table = &smu->smu_table; 1477 struct smu_table *table = &smu_table->driver_table; 1478 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1479 int i, j, r, c; 1480 u16 dir; 1481 1482 if (!adev->pm.dpm_enabled) 1483 return -EBUSY; 1484 1485 req = kzalloc(sizeof(*req), GFP_KERNEL); 1486 if (!req) 1487 return -ENOMEM; 1488 1489 req->I2CcontrollerPort = smu_i2c->port; 1490 req->I2CSpeed = I2C_SPEED_FAST_400K; 1491 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1492 dir = msg[0].flags & I2C_M_RD; 1493 1494 for (c = i = 0; i < num_msgs; i++) { 1495 for (j = 0; j < msg[i].len; j++, c++) { 1496 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1497 1498 if (!(msg[i].flags & I2C_M_RD)) { 1499 /* write */ 1500 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1501 cmd->ReadWriteData = msg[i].buf[j]; 1502 } 1503 1504 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1505 /* The direction changes. 1506 */ 1507 dir = msg[i].flags & I2C_M_RD; 1508 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1509 } 1510 1511 req->NumCmds++; 1512 1513 /* 1514 * Insert STOP if we are at the last byte of either last 1515 * message for the transaction or the client explicitly 1516 * requires a STOP at this particular message. 1517 */ 1518 if ((j == msg[i].len - 1) && 1519 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1520 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1521 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1522 } 1523 } 1524 } 1525 mutex_lock(&adev->pm.mutex); 1526 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1527 if (r) 1528 goto fail; 1529 1530 for (c = i = 0; i < num_msgs; i++) { 1531 if (!(msg[i].flags & I2C_M_RD)) { 1532 c += msg[i].len; 1533 continue; 1534 } 1535 for (j = 0; j < msg[i].len; j++, c++) { 1536 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1537 1538 msg[i].buf[j] = cmd->ReadWriteData; 1539 } 1540 } 1541 r = num_msgs; 1542 fail: 1543 mutex_unlock(&adev->pm.mutex); 1544 kfree(req); 1545 return r; 1546 } 1547 1548 static u32 aldebaran_i2c_func(struct i2c_adapter *adap) 1549 { 1550 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1551 } 1552 1553 1554 static const struct i2c_algorithm aldebaran_i2c_algo = { 1555 .master_xfer = aldebaran_i2c_xfer, 1556 .functionality = aldebaran_i2c_func, 1557 }; 1558 1559 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = { 1560 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1561 .max_read_len = MAX_SW_I2C_COMMANDS, 1562 .max_write_len = MAX_SW_I2C_COMMANDS, 1563 .max_comb_1st_msg_len = 2, 1564 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1565 }; 1566 1567 static int aldebaran_i2c_control_init(struct smu_context *smu) 1568 { 1569 struct amdgpu_device *adev = smu->adev; 1570 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0]; 1571 struct i2c_adapter *control = &smu_i2c->adapter; 1572 int res; 1573 1574 smu_i2c->adev = adev; 1575 smu_i2c->port = 0; 1576 mutex_init(&smu_i2c->mutex); 1577 control->owner = THIS_MODULE; 1578 control->class = I2C_CLASS_SPD; 1579 control->dev.parent = &adev->pdev->dev; 1580 control->algo = &aldebaran_i2c_algo; 1581 snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); 1582 control->quirks = &aldebaran_i2c_control_quirks; 1583 i2c_set_adapdata(control, smu_i2c); 1584 1585 res = i2c_add_adapter(control); 1586 if (res) { 1587 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1588 goto Out_err; 1589 } 1590 1591 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1592 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1593 1594 return 0; 1595 Out_err: 1596 i2c_del_adapter(control); 1597 1598 return res; 1599 } 1600 1601 static void aldebaran_i2c_control_fini(struct smu_context *smu) 1602 { 1603 struct amdgpu_device *adev = smu->adev; 1604 int i; 1605 1606 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1607 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1608 struct i2c_adapter *control = &smu_i2c->adapter; 1609 1610 i2c_del_adapter(control); 1611 } 1612 adev->pm.ras_eeprom_i2c_bus = NULL; 1613 adev->pm.fru_eeprom_i2c_bus = NULL; 1614 } 1615 1616 static void aldebaran_get_unique_id(struct smu_context *smu) 1617 { 1618 struct amdgpu_device *adev = smu->adev; 1619 uint32_t upper32 = 0, lower32 = 0; 1620 1621 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32)) 1622 goto out; 1623 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32)) 1624 goto out; 1625 1626 out: 1627 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1628 if (adev->serial[0] == '\0') 1629 sprintf(adev->serial, "%016llx", adev->unique_id); 1630 } 1631 1632 static bool aldebaran_is_baco_supported(struct smu_context *smu) 1633 { 1634 /* aldebaran is not support baco */ 1635 1636 return false; 1637 } 1638 1639 static int aldebaran_set_df_cstate(struct smu_context *smu, 1640 enum pp_df_cstate state) 1641 { 1642 struct amdgpu_device *adev = smu->adev; 1643 1644 /* 1645 * Aldebaran does not need the cstate disablement 1646 * prerequisite for gpu reset. 1647 */ 1648 if (amdgpu_in_reset(adev) || adev->in_suspend) 1649 return 0; 1650 1651 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1652 } 1653 1654 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) 1655 { 1656 struct amdgpu_device *adev = smu->adev; 1657 1658 /* The message only works on master die and NACK will be sent 1659 back for other dies, only send it on master die */ 1660 if (!adev->smuio.funcs->get_socket_id(adev) && 1661 !adev->smuio.funcs->get_die_id(adev)) 1662 return smu_cmn_send_smc_msg_with_param(smu, 1663 SMU_MSG_GmiPwrDnControl, 1664 en ? 0 : 1, 1665 NULL); 1666 else 1667 return 0; 1668 } 1669 1670 static const struct throttling_logging_label { 1671 uint32_t feature_mask; 1672 const char *label; 1673 } logging_label[] = { 1674 {(1U << THROTTLER_TEMP_GPU_BIT), "GPU"}, 1675 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1676 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1677 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1678 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1679 }; 1680 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1681 { 1682 int ret; 1683 int throttler_idx, throtting_events = 0, buf_idx = 0; 1684 struct amdgpu_device *adev = smu->adev; 1685 uint32_t throttler_status; 1686 char log_buf[256]; 1687 1688 ret = aldebaran_get_smu_metrics_data(smu, 1689 METRICS_THROTTLER_STATUS, 1690 &throttler_status); 1691 if (ret) 1692 return; 1693 1694 memset(log_buf, 0, sizeof(log_buf)); 1695 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1696 throttler_idx++) { 1697 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1698 throtting_events++; 1699 buf_idx += snprintf(log_buf + buf_idx, 1700 sizeof(log_buf) - buf_idx, 1701 "%s%s", 1702 throtting_events > 1 ? " and " : "", 1703 logging_label[throttler_idx].label); 1704 if (buf_idx >= sizeof(log_buf)) { 1705 dev_err(adev->dev, "buffer overflow!\n"); 1706 log_buf[sizeof(log_buf) - 1] = '\0'; 1707 break; 1708 } 1709 } 1710 } 1711 1712 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1713 log_buf); 1714 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 1715 smu_cmn_get_indep_throttler_status(throttler_status, 1716 aldebaran_throttler_map)); 1717 } 1718 1719 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1720 { 1721 struct amdgpu_device *adev = smu->adev; 1722 uint32_t esm_ctrl; 1723 1724 /* TODO: confirm this on real target */ 1725 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1726 if ((esm_ctrl >> 15) & 0x1FFFF) 1727 return (((esm_ctrl >> 8) & 0x3F) + 128); 1728 1729 return smu_v13_0_get_current_pcie_link_speed(smu); 1730 } 1731 1732 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1733 void **table) 1734 { 1735 struct smu_table_context *smu_table = &smu->smu_table; 1736 struct gpu_metrics_v1_3 *gpu_metrics = 1737 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1738 SmuMetrics_t metrics; 1739 int i, ret = 0; 1740 1741 ret = smu_cmn_get_metrics_table(smu, 1742 &metrics, 1743 true); 1744 if (ret) 1745 return ret; 1746 1747 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1748 1749 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1750 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1751 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1752 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1753 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1754 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1755 1756 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1757 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1758 gpu_metrics->average_mm_activity = 0; 1759 1760 /* Valid power data is available only from primary die */ 1761 if (aldebaran_is_primary(smu)) { 1762 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1763 gpu_metrics->energy_accumulator = 1764 (uint64_t)metrics.EnergyAcc64bitHigh << 32 | 1765 metrics.EnergyAcc64bitLow; 1766 } else { 1767 gpu_metrics->average_socket_power = 0; 1768 gpu_metrics->energy_accumulator = 0; 1769 } 1770 1771 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1772 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1773 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1774 gpu_metrics->average_vclk0_frequency = 0; 1775 gpu_metrics->average_dclk0_frequency = 0; 1776 1777 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1778 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1779 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1780 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1781 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1782 1783 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1784 gpu_metrics->indep_throttle_status = 1785 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1786 aldebaran_throttler_map); 1787 1788 gpu_metrics->current_fan_speed = 0; 1789 1790 gpu_metrics->pcie_link_width = 1791 smu_v13_0_get_current_pcie_link_width(smu); 1792 gpu_metrics->pcie_link_speed = 1793 aldebaran_get_current_pcie_link_speed(smu); 1794 1795 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1796 1797 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1798 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1799 1800 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1801 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1802 1803 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) | 1804 metrics.TimeStampLow; 1805 1806 *table = (void *)gpu_metrics; 1807 1808 return sizeof(struct gpu_metrics_v1_3); 1809 } 1810 1811 static int aldebaran_check_ecc_table_support(struct smu_context *smu, 1812 int *ecctable_version) 1813 { 1814 uint32_t if_version = 0xff, smu_version = 0xff; 1815 int ret = 0; 1816 1817 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 1818 if (ret) { 1819 /* return not support if failed get smu_version */ 1820 ret = -EOPNOTSUPP; 1821 } 1822 1823 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) 1824 ret = -EOPNOTSUPP; 1825 else if (smu_version >= SUPPORT_ECCTABLE_SMU_VERSION && 1826 smu_version < SUPPORT_ECCTABLE_V2_SMU_VERSION) 1827 *ecctable_version = 1; 1828 else 1829 *ecctable_version = 2; 1830 1831 return ret; 1832 } 1833 1834 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, 1835 void *table) 1836 { 1837 struct smu_table_context *smu_table = &smu->smu_table; 1838 EccInfoTable_t *ecc_table = NULL; 1839 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 1840 int i, ret = 0; 1841 int table_version = 0; 1842 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 1843 1844 ret = aldebaran_check_ecc_table_support(smu, &table_version); 1845 if (ret) 1846 return ret; 1847 1848 ret = smu_cmn_update_table(smu, 1849 SMU_TABLE_ECCINFO, 1850 0, 1851 smu_table->ecc_table, 1852 false); 1853 if (ret) { 1854 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 1855 return ret; 1856 } 1857 1858 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 1859 1860 if (table_version == 1) { 1861 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1862 ecc_info_per_channel = &(eccinfo->ecc[i]); 1863 ecc_info_per_channel->ce_count_lo_chip = 1864 ecc_table->EccInfo[i].ce_count_lo_chip; 1865 ecc_info_per_channel->ce_count_hi_chip = 1866 ecc_table->EccInfo[i].ce_count_hi_chip; 1867 ecc_info_per_channel->mca_umc_status = 1868 ecc_table->EccInfo[i].mca_umc_status; 1869 ecc_info_per_channel->mca_umc_addr = 1870 ecc_table->EccInfo[i].mca_umc_addr; 1871 } 1872 } else if (table_version == 2) { 1873 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1874 ecc_info_per_channel = &(eccinfo->ecc[i]); 1875 ecc_info_per_channel->ce_count_lo_chip = 1876 ecc_table->EccInfo_V2[i].ce_count_lo_chip; 1877 ecc_info_per_channel->ce_count_hi_chip = 1878 ecc_table->EccInfo_V2[i].ce_count_hi_chip; 1879 ecc_info_per_channel->mca_umc_status = 1880 ecc_table->EccInfo_V2[i].mca_umc_status; 1881 ecc_info_per_channel->mca_umc_addr = 1882 ecc_table->EccInfo_V2[i].mca_umc_addr; 1883 ecc_info_per_channel->mca_ceumc_addr = 1884 ecc_table->EccInfo_V2[i].mca_ceumc_addr; 1885 } 1886 eccinfo->record_ce_addr_supported = 1; 1887 } 1888 1889 return ret; 1890 } 1891 1892 static int aldebaran_mode1_reset(struct smu_context *smu) 1893 { 1894 u32 smu_version, fatal_err, param; 1895 int ret = 0; 1896 struct amdgpu_device *adev = smu->adev; 1897 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1898 1899 fatal_err = 0; 1900 param = SMU_RESET_MODE_1; 1901 1902 /* 1903 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 1904 */ 1905 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1906 if (smu_version < 0x00440700) { 1907 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1908 } else { 1909 /* fatal error triggered by ras, PMFW supports the flag 1910 from 68.44.0 */ 1911 if ((smu_version >= 0x00442c00) && ras && 1912 atomic_read(&ras->in_recovery)) 1913 fatal_err = 1; 1914 1915 param |= (fatal_err << 16); 1916 ret = smu_cmn_send_smc_msg_with_param(smu, 1917 SMU_MSG_GfxDeviceDriverReset, param, NULL); 1918 } 1919 1920 if (!ret) 1921 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 1922 1923 return ret; 1924 } 1925 1926 static int aldebaran_mode2_reset(struct smu_context *smu) 1927 { 1928 u32 smu_version; 1929 int ret = 0, index; 1930 struct amdgpu_device *adev = smu->adev; 1931 int timeout = 10; 1932 1933 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1934 1935 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1936 SMU_MSG_GfxDeviceDriverReset); 1937 1938 mutex_lock(&smu->message_lock); 1939 if (smu_version >= 0x00441400) { 1940 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1941 /* This is similar to FLR, wait till max FLR timeout */ 1942 msleep(100); 1943 dev_dbg(smu->adev->dev, "restore config space...\n"); 1944 /* Restore the config space saved during init */ 1945 amdgpu_device_load_pci_state(adev->pdev); 1946 1947 dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1948 while (ret == -ETIME && timeout) { 1949 ret = smu_cmn_wait_for_response(smu); 1950 /* Wait a bit more time for getting ACK */ 1951 if (ret == -ETIME) { 1952 --timeout; 1953 usleep_range(500, 1000); 1954 continue; 1955 } 1956 1957 if (ret != 1) { 1958 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n", 1959 SMU_RESET_MODE_2, ret); 1960 goto out; 1961 } 1962 } 1963 1964 } else { 1965 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", 1966 smu_version); 1967 } 1968 1969 if (ret == 1) 1970 ret = 0; 1971 out: 1972 mutex_unlock(&smu->message_lock); 1973 1974 return ret; 1975 } 1976 1977 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 1978 { 1979 int ret = 0; 1980 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL); 1981 1982 return ret; 1983 } 1984 1985 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1986 { 1987 #if 0 1988 struct amdgpu_device *adev = smu->adev; 1989 u32 smu_version; 1990 uint32_t val; 1991 /** 1992 * PM FW version support mode1 reset from 68.07 1993 */ 1994 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1995 if ((smu_version < 0x00440700)) 1996 return false; 1997 /** 1998 * mode1 reset relies on PSP, so we should check if 1999 * PSP is alive. 2000 */ 2001 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 2002 2003 return val != 0x0; 2004 #endif 2005 return true; 2006 } 2007 2008 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 2009 { 2010 return true; 2011 } 2012 2013 static int aldebaran_set_mp1_state(struct smu_context *smu, 2014 enum pp_mp1_state mp1_state) 2015 { 2016 switch (mp1_state) { 2017 case PP_MP1_STATE_UNLOAD: 2018 return smu_cmn_set_mp1_state(smu, mp1_state); 2019 default: 2020 return 0; 2021 } 2022 } 2023 2024 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, 2025 uint32_t size) 2026 { 2027 int ret = 0; 2028 2029 /* message SMU to update the bad page number on SMUBUS */ 2030 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL); 2031 if (ret) 2032 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n", 2033 __func__); 2034 2035 return ret; 2036 } 2037 2038 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu) 2039 { 2040 uint32_t if_version = 0xff, smu_version = 0xff; 2041 int ret = 0; 2042 2043 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 2044 if (ret) { 2045 /* return not support if failed get smu_version */ 2046 ret = -EOPNOTSUPP; 2047 } 2048 2049 if (smu_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION) 2050 ret = -EOPNOTSUPP; 2051 2052 return ret; 2053 } 2054 2055 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu, 2056 uint32_t size) 2057 { 2058 int ret = 0; 2059 2060 ret = aldebaran_check_bad_channel_info_support(smu); 2061 if (ret) 2062 return ret; 2063 2064 /* message SMU to update the bad channel info on SMUBUS */ 2065 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL); 2066 if (ret) 2067 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n", 2068 __func__); 2069 2070 return ret; 2071 } 2072 2073 static const struct pptable_funcs aldebaran_ppt_funcs = { 2074 /* init dpm */ 2075 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 2076 /* dpm/clk tables */ 2077 .set_default_dpm_table = aldebaran_set_default_dpm_table, 2078 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 2079 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 2080 .print_clk_levels = aldebaran_print_clk_levels, 2081 .force_clk_levels = aldebaran_force_clk_levels, 2082 .read_sensor = aldebaran_read_sensor, 2083 .set_performance_level = aldebaran_set_performance_level, 2084 .get_power_limit = aldebaran_get_power_limit, 2085 .is_dpm_running = aldebaran_is_dpm_running, 2086 .get_unique_id = aldebaran_get_unique_id, 2087 .init_microcode = smu_v13_0_init_microcode, 2088 .load_microcode = smu_v13_0_load_microcode, 2089 .fini_microcode = smu_v13_0_fini_microcode, 2090 .init_smc_tables = aldebaran_init_smc_tables, 2091 .fini_smc_tables = smu_v13_0_fini_smc_tables, 2092 .init_power = smu_v13_0_init_power, 2093 .fini_power = smu_v13_0_fini_power, 2094 .check_fw_status = smu_v13_0_check_fw_status, 2095 /* pptable related */ 2096 .setup_pptable = aldebaran_setup_pptable, 2097 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 2098 .check_fw_version = smu_v13_0_check_fw_version, 2099 .write_pptable = smu_cmn_write_pptable, 2100 .set_driver_table_location = smu_v13_0_set_driver_table_location, 2101 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2102 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2103 .system_features_control = aldebaran_system_features_control, 2104 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2105 .send_smc_msg = smu_cmn_send_smc_msg, 2106 .get_enabled_mask = smu_cmn_get_enabled_mask, 2107 .feature_is_enabled = smu_cmn_feature_is_enabled, 2108 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2109 .set_power_limit = aldebaran_set_power_limit, 2110 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 2111 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2112 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2113 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 2114 .register_irq_handler = smu_v13_0_register_irq_handler, 2115 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 2116 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 2117 .baco_is_support = aldebaran_is_baco_supported, 2118 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 2119 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 2120 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 2121 .set_df_cstate = aldebaran_set_df_cstate, 2122 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down, 2123 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 2124 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2125 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2126 .get_gpu_metrics = aldebaran_get_gpu_metrics, 2127 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 2128 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 2129 .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr, 2130 .mode1_reset = aldebaran_mode1_reset, 2131 .set_mp1_state = aldebaran_set_mp1_state, 2132 .mode2_reset = aldebaran_mode2_reset, 2133 .wait_for_event = smu_v13_0_wait_for_event, 2134 .i2c_init = aldebaran_i2c_control_init, 2135 .i2c_fini = aldebaran_i2c_control_fini, 2136 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num, 2137 .get_ecc_info = aldebaran_get_ecc_info, 2138 .send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag, 2139 }; 2140 2141 void aldebaran_set_ppt_funcs(struct smu_context *smu) 2142 { 2143 smu->ppt_funcs = &aldebaran_ppt_funcs; 2144 smu->message_map = aldebaran_message_map; 2145 smu->clock_map = aldebaran_clk_map; 2146 smu->feature_map = aldebaran_feature_mask_map; 2147 smu->table_map = aldebaran_table_map; 2148 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; 2149 smu_v13_0_set_smu_mailbox_registers(smu); 2150 } 2151