1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_smu.h" 29 #include "atomfirmware.h" 30 #include "amdgpu_atomfirmware.h" 31 #include "amdgpu_atombios.h" 32 #include "smu_v13_0.h" 33 #include "smu13_driver_if_aldebaran.h" 34 #include "soc15_common.h" 35 #include "atom.h" 36 #include "power_state.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 63 [smu_feature] = {1, (aldebaran_feature)} 64 65 #define FEATURE_MASK(feature) (1ULL << feature) 66 #define SMC_DPM_FEATURE ( \ 67 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 68 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 73 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 74 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 75 76 /* possible frequency drift (1Mhz) */ 77 #define EPSILON 1 78 79 #define smnPCIE_ESM_CTRL 0x111003D0 80 81 /* 82 * SMU support ECCTABLE since version 68.42.0, 83 * use this to check ECCTALE feature whether support 84 */ 85 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00 86 87 static const struct smu_temperature_range smu13_thermal_policy[] = 88 { 89 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 90 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 91 }; 92 93 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 94 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 95 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 96 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 99 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 100 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 101 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 102 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 103 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 104 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 105 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 106 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 107 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 108 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 109 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 110 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 111 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 112 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 113 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 114 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 115 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 116 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 117 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 118 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 119 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 120 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 121 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 122 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 123 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 124 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 125 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 126 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 127 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 128 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 129 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 130 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 131 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 132 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 133 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 134 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 135 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 136 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 137 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 138 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 139 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 140 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 141 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 142 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 143 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0), 144 }; 145 146 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 147 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 148 CLK_MAP(SCLK, PPCLK_GFXCLK), 149 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 150 CLK_MAP(FCLK, PPCLK_FCLK), 151 CLK_MAP(UCLK, PPCLK_UCLK), 152 CLK_MAP(MCLK, PPCLK_UCLK), 153 CLK_MAP(DCLK, PPCLK_DCLK), 154 CLK_MAP(VCLK, PPCLK_VCLK), 155 CLK_MAP(LCLK, PPCLK_LCLK), 156 }; 157 158 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 159 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS), 160 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 161 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 162 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 163 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 164 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 165 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 166 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 167 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 168 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 169 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 170 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 175 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 176 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 177 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 178 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 179 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 180 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 181 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 182 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 183 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 184 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 185 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 186 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 187 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN), 188 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 189 }; 190 191 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 192 TAB_MAP(PPTABLE), 193 TAB_MAP(AVFS_PSM_DEBUG), 194 TAB_MAP(AVFS_FUSE_OVERRIDE), 195 TAB_MAP(PMSTATUSLOG), 196 TAB_MAP(SMU_METRICS), 197 TAB_MAP(DRIVER_SMU_CONFIG), 198 TAB_MAP(I2C_COMMANDS), 199 TAB_MAP(ECCINFO), 200 }; 201 202 static const uint8_t aldebaran_throttler_map[] = { 203 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 204 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 205 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 206 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 207 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT), 208 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), 209 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 210 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 211 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 212 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 213 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 214 }; 215 216 static int aldebaran_tables_init(struct smu_context *smu) 217 { 218 struct smu_table_context *smu_table = &smu->smu_table; 219 struct smu_table *tables = smu_table->tables; 220 221 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 222 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 223 224 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 225 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 226 227 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 229 230 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 231 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 232 233 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 235 236 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 237 if (!smu_table->metrics_table) 238 return -ENOMEM; 239 smu_table->metrics_time = 0; 240 241 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 242 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 243 if (!smu_table->gpu_metrics_table) { 244 kfree(smu_table->metrics_table); 245 return -ENOMEM; 246 } 247 248 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 249 if (!smu_table->ecc_table) 250 return -ENOMEM; 251 252 return 0; 253 } 254 255 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 256 { 257 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 258 259 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 260 GFP_KERNEL); 261 if (!smu_dpm->dpm_context) 262 return -ENOMEM; 263 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 264 265 return 0; 266 } 267 268 static int aldebaran_init_smc_tables(struct smu_context *smu) 269 { 270 int ret = 0; 271 272 ret = aldebaran_tables_init(smu); 273 if (ret) 274 return ret; 275 276 ret = aldebaran_allocate_dpm_context(smu); 277 if (ret) 278 return ret; 279 280 return smu_v13_0_init_smc_tables(smu); 281 } 282 283 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 284 uint32_t *feature_mask, uint32_t num) 285 { 286 if (num > 2) 287 return -EINVAL; 288 289 /* pptable will handle the features to enable */ 290 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 291 292 return 0; 293 } 294 295 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 296 { 297 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 298 struct smu_13_0_dpm_table *dpm_table = NULL; 299 PPTable_t *pptable = smu->smu_table.driver_pptable; 300 int ret = 0; 301 302 /* socclk dpm table setup */ 303 dpm_table = &dpm_context->dpm_tables.soc_table; 304 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 305 ret = smu_v13_0_set_single_dpm_table(smu, 306 SMU_SOCCLK, 307 dpm_table); 308 if (ret) 309 return ret; 310 } else { 311 dpm_table->count = 1; 312 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 313 dpm_table->dpm_levels[0].enabled = true; 314 dpm_table->min = dpm_table->dpm_levels[0].value; 315 dpm_table->max = dpm_table->dpm_levels[0].value; 316 } 317 318 /* gfxclk dpm table setup */ 319 dpm_table = &dpm_context->dpm_tables.gfx_table; 320 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 321 /* in the case of gfxclk, only fine-grained dpm is honored */ 322 dpm_table->count = 2; 323 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 324 dpm_table->dpm_levels[0].enabled = true; 325 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 326 dpm_table->dpm_levels[1].enabled = true; 327 dpm_table->min = dpm_table->dpm_levels[0].value; 328 dpm_table->max = dpm_table->dpm_levels[1].value; 329 } else { 330 dpm_table->count = 1; 331 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 332 dpm_table->dpm_levels[0].enabled = true; 333 dpm_table->min = dpm_table->dpm_levels[0].value; 334 dpm_table->max = dpm_table->dpm_levels[0].value; 335 } 336 337 /* memclk dpm table setup */ 338 dpm_table = &dpm_context->dpm_tables.uclk_table; 339 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 340 ret = smu_v13_0_set_single_dpm_table(smu, 341 SMU_UCLK, 342 dpm_table); 343 if (ret) 344 return ret; 345 } else { 346 dpm_table->count = 1; 347 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 348 dpm_table->dpm_levels[0].enabled = true; 349 dpm_table->min = dpm_table->dpm_levels[0].value; 350 dpm_table->max = dpm_table->dpm_levels[0].value; 351 } 352 353 /* fclk dpm table setup */ 354 dpm_table = &dpm_context->dpm_tables.fclk_table; 355 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 356 ret = smu_v13_0_set_single_dpm_table(smu, 357 SMU_FCLK, 358 dpm_table); 359 if (ret) 360 return ret; 361 } else { 362 dpm_table->count = 1; 363 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 364 dpm_table->dpm_levels[0].enabled = true; 365 dpm_table->min = dpm_table->dpm_levels[0].value; 366 dpm_table->max = dpm_table->dpm_levels[0].value; 367 } 368 369 return 0; 370 } 371 372 static int aldebaran_check_powerplay_table(struct smu_context *smu) 373 { 374 struct smu_table_context *table_context = &smu->smu_table; 375 struct smu_13_0_powerplay_table *powerplay_table = 376 table_context->power_play_table; 377 378 table_context->thermal_controller_type = 379 powerplay_table->thermal_controller_type; 380 381 return 0; 382 } 383 384 static int aldebaran_store_powerplay_table(struct smu_context *smu) 385 { 386 struct smu_table_context *table_context = &smu->smu_table; 387 struct smu_13_0_powerplay_table *powerplay_table = 388 table_context->power_play_table; 389 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 390 sizeof(PPTable_t)); 391 392 return 0; 393 } 394 395 static int aldebaran_append_powerplay_table(struct smu_context *smu) 396 { 397 struct smu_table_context *table_context = &smu->smu_table; 398 PPTable_t *smc_pptable = table_context->driver_pptable; 399 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 400 int index, ret; 401 402 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 403 smc_dpm_info); 404 405 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 406 (uint8_t **)&smc_dpm_table); 407 if (ret) 408 return ret; 409 410 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 411 smc_dpm_table->table_header.format_revision, 412 smc_dpm_table->table_header.content_revision); 413 414 if ((smc_dpm_table->table_header.format_revision == 4) && 415 (smc_dpm_table->table_header.content_revision == 10)) 416 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved, 417 smc_dpm_table, GfxMaxCurrent); 418 return 0; 419 } 420 421 static int aldebaran_setup_pptable(struct smu_context *smu) 422 { 423 int ret = 0; 424 425 /* VBIOS pptable is the first choice */ 426 smu->smu_table.boot_values.pp_table_id = 0; 427 428 ret = smu_v13_0_setup_pptable(smu); 429 if (ret) 430 return ret; 431 432 ret = aldebaran_store_powerplay_table(smu); 433 if (ret) 434 return ret; 435 436 ret = aldebaran_append_powerplay_table(smu); 437 if (ret) 438 return ret; 439 440 ret = aldebaran_check_powerplay_table(smu); 441 if (ret) 442 return ret; 443 444 return ret; 445 } 446 447 static bool aldebaran_is_primary(struct smu_context *smu) 448 { 449 struct amdgpu_device *adev = smu->adev; 450 451 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) 452 return adev->smuio.funcs->get_die_id(adev) == 0; 453 454 return true; 455 } 456 457 static int aldebaran_run_board_btc(struct smu_context *smu) 458 { 459 u32 smu_version; 460 int ret; 461 462 if (!aldebaran_is_primary(smu)) 463 return 0; 464 465 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 466 if (ret) { 467 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 468 return ret; 469 } 470 if (smu_version <= 0x00441d00) 471 return 0; 472 473 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL); 474 if (ret) 475 dev_err(smu->adev->dev, "Board power calibration failed!\n"); 476 477 return ret; 478 } 479 480 static int aldebaran_run_btc(struct smu_context *smu) 481 { 482 int ret; 483 484 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 485 if (ret) 486 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 487 else 488 ret = aldebaran_run_board_btc(smu); 489 490 return ret; 491 } 492 493 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 494 { 495 struct smu_13_0_dpm_context *dpm_context = 496 smu->smu_dpm.dpm_context; 497 struct smu_13_0_dpm_table *gfx_table = 498 &dpm_context->dpm_tables.gfx_table; 499 struct smu_13_0_dpm_table *mem_table = 500 &dpm_context->dpm_tables.uclk_table; 501 struct smu_13_0_dpm_table *soc_table = 502 &dpm_context->dpm_tables.soc_table; 503 struct smu_umd_pstate_table *pstate_table = 504 &smu->pstate_table; 505 506 pstate_table->gfxclk_pstate.min = gfx_table->min; 507 pstate_table->gfxclk_pstate.peak = gfx_table->max; 508 pstate_table->gfxclk_pstate.curr.min = gfx_table->min; 509 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 510 511 pstate_table->uclk_pstate.min = mem_table->min; 512 pstate_table->uclk_pstate.peak = mem_table->max; 513 pstate_table->uclk_pstate.curr.min = mem_table->min; 514 pstate_table->uclk_pstate.curr.max = mem_table->max; 515 516 pstate_table->socclk_pstate.min = soc_table->min; 517 pstate_table->socclk_pstate.peak = soc_table->max; 518 pstate_table->socclk_pstate.curr.min = soc_table->min; 519 pstate_table->socclk_pstate.curr.max = soc_table->max; 520 521 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 522 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 523 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 524 pstate_table->gfxclk_pstate.standard = 525 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 526 pstate_table->uclk_pstate.standard = 527 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 528 pstate_table->socclk_pstate.standard = 529 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 530 } else { 531 pstate_table->gfxclk_pstate.standard = 532 pstate_table->gfxclk_pstate.min; 533 pstate_table->uclk_pstate.standard = 534 pstate_table->uclk_pstate.min; 535 pstate_table->socclk_pstate.standard = 536 pstate_table->socclk_pstate.min; 537 } 538 539 return 0; 540 } 541 542 static int aldebaran_get_clk_table(struct smu_context *smu, 543 struct pp_clock_levels_with_latency *clocks, 544 struct smu_13_0_dpm_table *dpm_table) 545 { 546 int i, count; 547 548 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 549 clocks->num_levels = count; 550 551 for (i = 0; i < count; i++) { 552 clocks->data[i].clocks_in_khz = 553 dpm_table->dpm_levels[i].value * 1000; 554 clocks->data[i].latency_in_us = 0; 555 } 556 557 return 0; 558 } 559 560 static int aldebaran_freqs_in_same_level(int32_t frequency1, 561 int32_t frequency2) 562 { 563 return (abs(frequency1 - frequency2) <= EPSILON); 564 } 565 566 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 567 MetricsMember_t member, 568 uint32_t *value) 569 { 570 struct smu_table_context *smu_table= &smu->smu_table; 571 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 572 int ret = 0; 573 574 mutex_lock(&smu->metrics_lock); 575 576 ret = smu_cmn_get_metrics_table_locked(smu, 577 NULL, 578 false); 579 if (ret) { 580 mutex_unlock(&smu->metrics_lock); 581 return ret; 582 } 583 584 switch (member) { 585 case METRICS_CURR_GFXCLK: 586 *value = metrics->CurrClock[PPCLK_GFXCLK]; 587 break; 588 case METRICS_CURR_SOCCLK: 589 *value = metrics->CurrClock[PPCLK_SOCCLK]; 590 break; 591 case METRICS_CURR_UCLK: 592 *value = metrics->CurrClock[PPCLK_UCLK]; 593 break; 594 case METRICS_CURR_VCLK: 595 *value = metrics->CurrClock[PPCLK_VCLK]; 596 break; 597 case METRICS_CURR_DCLK: 598 *value = metrics->CurrClock[PPCLK_DCLK]; 599 break; 600 case METRICS_CURR_FCLK: 601 *value = metrics->CurrClock[PPCLK_FCLK]; 602 break; 603 case METRICS_AVERAGE_GFXCLK: 604 *value = metrics->AverageGfxclkFrequency; 605 break; 606 case METRICS_AVERAGE_SOCCLK: 607 *value = metrics->AverageSocclkFrequency; 608 break; 609 case METRICS_AVERAGE_UCLK: 610 *value = metrics->AverageUclkFrequency; 611 break; 612 case METRICS_AVERAGE_GFXACTIVITY: 613 *value = metrics->AverageGfxActivity; 614 break; 615 case METRICS_AVERAGE_MEMACTIVITY: 616 *value = metrics->AverageUclkActivity; 617 break; 618 case METRICS_AVERAGE_SOCKETPOWER: 619 /* Valid power data is available only from primary die */ 620 *value = aldebaran_is_primary(smu) ? 621 metrics->AverageSocketPower << 8 : 622 0; 623 break; 624 case METRICS_TEMPERATURE_EDGE: 625 *value = metrics->TemperatureEdge * 626 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 627 break; 628 case METRICS_TEMPERATURE_HOTSPOT: 629 *value = metrics->TemperatureHotspot * 630 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 631 break; 632 case METRICS_TEMPERATURE_MEM: 633 *value = metrics->TemperatureHBM * 634 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 635 break; 636 case METRICS_TEMPERATURE_VRGFX: 637 *value = metrics->TemperatureVrGfx * 638 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 639 break; 640 case METRICS_TEMPERATURE_VRSOC: 641 *value = metrics->TemperatureVrSoc * 642 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 643 break; 644 case METRICS_TEMPERATURE_VRMEM: 645 *value = metrics->TemperatureVrMem * 646 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 647 break; 648 case METRICS_THROTTLER_STATUS: 649 *value = metrics->ThrottlerStatus; 650 break; 651 default: 652 *value = UINT_MAX; 653 break; 654 } 655 656 mutex_unlock(&smu->metrics_lock); 657 658 return ret; 659 } 660 661 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 662 enum smu_clk_type clk_type, 663 uint32_t *value) 664 { 665 MetricsMember_t member_type; 666 int clk_id = 0; 667 668 if (!value) 669 return -EINVAL; 670 671 clk_id = smu_cmn_to_asic_specific_index(smu, 672 CMN2ASIC_MAPPING_CLK, 673 clk_type); 674 if (clk_id < 0) 675 return -EINVAL; 676 677 switch (clk_id) { 678 case PPCLK_GFXCLK: 679 /* 680 * CurrClock[clk_id] can provide accurate 681 * output only when the dpm feature is enabled. 682 * We can use Average_* for dpm disabled case. 683 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 684 */ 685 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 686 member_type = METRICS_CURR_GFXCLK; 687 else 688 member_type = METRICS_AVERAGE_GFXCLK; 689 break; 690 case PPCLK_UCLK: 691 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 692 member_type = METRICS_CURR_UCLK; 693 else 694 member_type = METRICS_AVERAGE_UCLK; 695 break; 696 case PPCLK_SOCCLK: 697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 698 member_type = METRICS_CURR_SOCCLK; 699 else 700 member_type = METRICS_AVERAGE_SOCCLK; 701 break; 702 case PPCLK_VCLK: 703 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 704 member_type = METRICS_CURR_VCLK; 705 else 706 member_type = METRICS_AVERAGE_VCLK; 707 break; 708 case PPCLK_DCLK: 709 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 710 member_type = METRICS_CURR_DCLK; 711 else 712 member_type = METRICS_AVERAGE_DCLK; 713 break; 714 case PPCLK_FCLK: 715 member_type = METRICS_CURR_FCLK; 716 break; 717 default: 718 return -EINVAL; 719 } 720 721 return aldebaran_get_smu_metrics_data(smu, 722 member_type, 723 value); 724 } 725 726 static int aldebaran_print_clk_levels(struct smu_context *smu, 727 enum smu_clk_type type, char *buf) 728 { 729 int i, now, size = 0; 730 int ret = 0; 731 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 732 struct pp_clock_levels_with_latency clocks; 733 struct smu_13_0_dpm_table *single_dpm_table; 734 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 735 struct smu_13_0_dpm_context *dpm_context = NULL; 736 uint32_t display_levels; 737 uint32_t freq_values[3] = {0}; 738 uint32_t min_clk, max_clk; 739 740 smu_cmn_get_sysfs_buf(&buf, &size); 741 742 if (amdgpu_ras_intr_triggered()) { 743 size += sysfs_emit_at(buf, size, "unavailable\n"); 744 return size; 745 } 746 747 dpm_context = smu_dpm->dpm_context; 748 749 switch (type) { 750 751 case SMU_OD_SCLK: 752 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK"); 753 fallthrough; 754 case SMU_SCLK: 755 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 756 if (ret) { 757 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 758 return ret; 759 } 760 761 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 762 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 763 if (ret) { 764 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 765 return ret; 766 } 767 768 display_levels = clocks.num_levels; 769 770 min_clk = pstate_table->gfxclk_pstate.curr.min; 771 max_clk = pstate_table->gfxclk_pstate.curr.max; 772 773 freq_values[0] = min_clk; 774 freq_values[1] = max_clk; 775 776 /* fine-grained dpm has only 2 levels */ 777 if (now > min_clk && now < max_clk) { 778 display_levels = clocks.num_levels + 1; 779 freq_values[2] = max_clk; 780 freq_values[1] = now; 781 } 782 783 /* 784 * For DPM disabled case, there will be only one clock level. 785 * And it's safe to assume that is always the current clock. 786 */ 787 if (display_levels == clocks.num_levels) { 788 for (i = 0; i < clocks.num_levels; i++) 789 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 790 freq_values[i], 791 (clocks.num_levels == 1) ? 792 "*" : 793 (aldebaran_freqs_in_same_level( 794 freq_values[i], now) ? 795 "*" : 796 "")); 797 } else { 798 for (i = 0; i < display_levels; i++) 799 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 800 freq_values[i], i == 1 ? "*" : ""); 801 } 802 803 break; 804 805 case SMU_OD_MCLK: 806 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK"); 807 fallthrough; 808 case SMU_MCLK: 809 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 810 if (ret) { 811 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 812 return ret; 813 } 814 815 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 816 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 817 if (ret) { 818 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 819 return ret; 820 } 821 822 for (i = 0; i < clocks.num_levels; i++) 823 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 824 i, clocks.data[i].clocks_in_khz / 1000, 825 (clocks.num_levels == 1) ? "*" : 826 (aldebaran_freqs_in_same_level( 827 clocks.data[i].clocks_in_khz / 1000, 828 now) ? "*" : "")); 829 break; 830 831 case SMU_SOCCLK: 832 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 833 if (ret) { 834 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 835 return ret; 836 } 837 838 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 839 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 840 if (ret) { 841 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 842 return ret; 843 } 844 845 for (i = 0; i < clocks.num_levels; i++) 846 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 847 i, clocks.data[i].clocks_in_khz / 1000, 848 (clocks.num_levels == 1) ? "*" : 849 (aldebaran_freqs_in_same_level( 850 clocks.data[i].clocks_in_khz / 1000, 851 now) ? "*" : "")); 852 break; 853 854 case SMU_FCLK: 855 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 856 if (ret) { 857 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 858 return ret; 859 } 860 861 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 862 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 863 if (ret) { 864 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 865 return ret; 866 } 867 868 for (i = 0; i < single_dpm_table->count; i++) 869 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 870 i, single_dpm_table->dpm_levels[i].value, 871 (clocks.num_levels == 1) ? "*" : 872 (aldebaran_freqs_in_same_level( 873 clocks.data[i].clocks_in_khz / 1000, 874 now) ? "*" : "")); 875 break; 876 877 case SMU_VCLK: 878 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); 879 if (ret) { 880 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); 881 return ret; 882 } 883 884 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 885 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 886 if (ret) { 887 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); 888 return ret; 889 } 890 891 for (i = 0; i < single_dpm_table->count; i++) 892 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 893 i, single_dpm_table->dpm_levels[i].value, 894 (clocks.num_levels == 1) ? "*" : 895 (aldebaran_freqs_in_same_level( 896 clocks.data[i].clocks_in_khz / 1000, 897 now) ? "*" : "")); 898 break; 899 900 case SMU_DCLK: 901 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); 902 if (ret) { 903 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); 904 return ret; 905 } 906 907 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 908 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 909 if (ret) { 910 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); 911 return ret; 912 } 913 914 for (i = 0; i < single_dpm_table->count; i++) 915 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 916 i, single_dpm_table->dpm_levels[i].value, 917 (clocks.num_levels == 1) ? "*" : 918 (aldebaran_freqs_in_same_level( 919 clocks.data[i].clocks_in_khz / 1000, 920 now) ? "*" : "")); 921 break; 922 923 default: 924 break; 925 } 926 927 return size; 928 } 929 930 static int aldebaran_upload_dpm_level(struct smu_context *smu, 931 bool max, 932 uint32_t feature_mask, 933 uint32_t level) 934 { 935 struct smu_13_0_dpm_context *dpm_context = 936 smu->smu_dpm.dpm_context; 937 uint32_t freq; 938 int ret = 0; 939 940 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 941 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 942 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 943 ret = smu_cmn_send_smc_msg_with_param(smu, 944 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 945 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 946 NULL); 947 if (ret) { 948 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 949 max ? "max" : "min"); 950 return ret; 951 } 952 } 953 954 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 955 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 956 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 957 ret = smu_cmn_send_smc_msg_with_param(smu, 958 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 959 (PPCLK_UCLK << 16) | (freq & 0xffff), 960 NULL); 961 if (ret) { 962 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 963 max ? "max" : "min"); 964 return ret; 965 } 966 } 967 968 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 969 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 970 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 971 ret = smu_cmn_send_smc_msg_with_param(smu, 972 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 973 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 974 NULL); 975 if (ret) { 976 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 977 max ? "max" : "min"); 978 return ret; 979 } 980 } 981 982 return ret; 983 } 984 985 static int aldebaran_force_clk_levels(struct smu_context *smu, 986 enum smu_clk_type type, uint32_t mask) 987 { 988 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 989 struct smu_13_0_dpm_table *single_dpm_table = NULL; 990 uint32_t soft_min_level, soft_max_level; 991 int ret = 0; 992 993 soft_min_level = mask ? (ffs(mask) - 1) : 0; 994 soft_max_level = mask ? (fls(mask) - 1) : 0; 995 996 switch (type) { 997 case SMU_SCLK: 998 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 999 if (soft_max_level >= single_dpm_table->count) { 1000 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 1001 soft_max_level, single_dpm_table->count - 1); 1002 ret = -EINVAL; 1003 break; 1004 } 1005 1006 ret = aldebaran_upload_dpm_level(smu, 1007 false, 1008 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1009 soft_min_level); 1010 if (ret) { 1011 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1012 break; 1013 } 1014 1015 ret = aldebaran_upload_dpm_level(smu, 1016 true, 1017 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1018 soft_max_level); 1019 if (ret) 1020 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1021 1022 break; 1023 1024 case SMU_MCLK: 1025 case SMU_SOCCLK: 1026 case SMU_FCLK: 1027 /* 1028 * Should not arrive here since aldebaran does not 1029 * support mclk/socclk/fclk softmin/softmax settings 1030 */ 1031 ret = -EINVAL; 1032 break; 1033 1034 default: 1035 break; 1036 } 1037 1038 return ret; 1039 } 1040 1041 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 1042 struct smu_temperature_range *range) 1043 { 1044 struct smu_table_context *table_context = &smu->smu_table; 1045 struct smu_13_0_powerplay_table *powerplay_table = 1046 table_context->power_play_table; 1047 PPTable_t *pptable = smu->smu_table.driver_pptable; 1048 1049 if (!range) 1050 return -EINVAL; 1051 1052 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1053 1054 range->hotspot_crit_max = pptable->ThotspotLimit * 1055 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1056 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1057 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1058 range->mem_crit_max = pptable->TmemLimit * 1059 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1060 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1061 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1062 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1063 1064 return 0; 1065 } 1066 1067 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 1068 enum amd_pp_sensors sensor, 1069 uint32_t *value) 1070 { 1071 int ret = 0; 1072 1073 if (!value) 1074 return -EINVAL; 1075 1076 switch (sensor) { 1077 case AMDGPU_PP_SENSOR_GPU_LOAD: 1078 ret = aldebaran_get_smu_metrics_data(smu, 1079 METRICS_AVERAGE_GFXACTIVITY, 1080 value); 1081 break; 1082 case AMDGPU_PP_SENSOR_MEM_LOAD: 1083 ret = aldebaran_get_smu_metrics_data(smu, 1084 METRICS_AVERAGE_MEMACTIVITY, 1085 value); 1086 break; 1087 default: 1088 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 1089 return -EINVAL; 1090 } 1091 1092 return ret; 1093 } 1094 1095 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value) 1096 { 1097 if (!value) 1098 return -EINVAL; 1099 1100 return aldebaran_get_smu_metrics_data(smu, 1101 METRICS_AVERAGE_SOCKETPOWER, 1102 value); 1103 } 1104 1105 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 1106 enum amd_pp_sensors sensor, 1107 uint32_t *value) 1108 { 1109 int ret = 0; 1110 1111 if (!value) 1112 return -EINVAL; 1113 1114 switch (sensor) { 1115 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1116 ret = aldebaran_get_smu_metrics_data(smu, 1117 METRICS_TEMPERATURE_HOTSPOT, 1118 value); 1119 break; 1120 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1121 ret = aldebaran_get_smu_metrics_data(smu, 1122 METRICS_TEMPERATURE_EDGE, 1123 value); 1124 break; 1125 case AMDGPU_PP_SENSOR_MEM_TEMP: 1126 ret = aldebaran_get_smu_metrics_data(smu, 1127 METRICS_TEMPERATURE_MEM, 1128 value); 1129 break; 1130 default: 1131 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1132 return -EINVAL; 1133 } 1134 1135 return ret; 1136 } 1137 1138 static int aldebaran_read_sensor(struct smu_context *smu, 1139 enum amd_pp_sensors sensor, 1140 void *data, uint32_t *size) 1141 { 1142 int ret = 0; 1143 1144 if (amdgpu_ras_intr_triggered()) 1145 return 0; 1146 1147 if (!data || !size) 1148 return -EINVAL; 1149 1150 mutex_lock(&smu->sensor_lock); 1151 switch (sensor) { 1152 case AMDGPU_PP_SENSOR_MEM_LOAD: 1153 case AMDGPU_PP_SENSOR_GPU_LOAD: 1154 ret = aldebaran_get_current_activity_percent(smu, 1155 sensor, 1156 (uint32_t *)data); 1157 *size = 4; 1158 break; 1159 case AMDGPU_PP_SENSOR_GPU_POWER: 1160 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data); 1161 *size = 4; 1162 break; 1163 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1164 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1165 case AMDGPU_PP_SENSOR_MEM_TEMP: 1166 ret = aldebaran_thermal_get_temperature(smu, sensor, 1167 (uint32_t *)data); 1168 *size = 4; 1169 break; 1170 case AMDGPU_PP_SENSOR_GFX_MCLK: 1171 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1172 /* the output clock frequency in 10K unit */ 1173 *(uint32_t *)data *= 100; 1174 *size = 4; 1175 break; 1176 case AMDGPU_PP_SENSOR_GFX_SCLK: 1177 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1178 *(uint32_t *)data *= 100; 1179 *size = 4; 1180 break; 1181 case AMDGPU_PP_SENSOR_VDDGFX: 1182 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1183 *size = 4; 1184 break; 1185 default: 1186 ret = -EOPNOTSUPP; 1187 break; 1188 } 1189 mutex_unlock(&smu->sensor_lock); 1190 1191 return ret; 1192 } 1193 1194 static int aldebaran_get_power_limit(struct smu_context *smu, 1195 uint32_t *current_power_limit, 1196 uint32_t *default_power_limit, 1197 uint32_t *max_power_limit) 1198 { 1199 PPTable_t *pptable = smu->smu_table.driver_pptable; 1200 uint32_t power_limit = 0; 1201 int ret; 1202 1203 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1204 if (current_power_limit) 1205 *current_power_limit = 0; 1206 if (default_power_limit) 1207 *default_power_limit = 0; 1208 if (max_power_limit) 1209 *max_power_limit = 0; 1210 1211 dev_warn(smu->adev->dev, 1212 "PPT feature is not enabled, power values can't be fetched."); 1213 1214 return 0; 1215 } 1216 1217 /* Valid power data is available only from primary die. 1218 * For secondary die show the value as 0. 1219 */ 1220 if (aldebaran_is_primary(smu)) { 1221 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, 1222 &power_limit); 1223 1224 if (ret) { 1225 /* the last hope to figure out the ppt limit */ 1226 if (!pptable) { 1227 dev_err(smu->adev->dev, 1228 "Cannot get PPT limit due to pptable missing!"); 1229 return -EINVAL; 1230 } 1231 power_limit = pptable->PptLimit; 1232 } 1233 } 1234 1235 if (current_power_limit) 1236 *current_power_limit = power_limit; 1237 if (default_power_limit) 1238 *default_power_limit = power_limit; 1239 1240 if (max_power_limit) { 1241 if (pptable) 1242 *max_power_limit = pptable->PptLimit; 1243 } 1244 1245 return 0; 1246 } 1247 1248 static int aldebaran_set_power_limit(struct smu_context *smu, 1249 enum smu_ppt_limit_type limit_type, 1250 uint32_t limit) 1251 { 1252 /* Power limit can be set only through primary die */ 1253 if (aldebaran_is_primary(smu)) 1254 return smu_v13_0_set_power_limit(smu, limit_type, limit); 1255 1256 return -EINVAL; 1257 } 1258 1259 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1260 { 1261 int ret; 1262 1263 ret = smu_v13_0_system_features_control(smu, enable); 1264 if (!ret && enable) 1265 ret = aldebaran_run_btc(smu); 1266 1267 return ret; 1268 } 1269 1270 static int aldebaran_set_performance_level(struct smu_context *smu, 1271 enum amd_dpm_forced_level level) 1272 { 1273 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1274 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1275 struct smu_13_0_dpm_table *gfx_table = 1276 &dpm_context->dpm_tables.gfx_table; 1277 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1278 1279 /* Disable determinism if switching to another mode */ 1280 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && 1281 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { 1282 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1283 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 1284 } 1285 1286 switch (level) { 1287 1288 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1289 return 0; 1290 1291 case AMD_DPM_FORCED_LEVEL_HIGH: 1292 case AMD_DPM_FORCED_LEVEL_LOW: 1293 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1294 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1295 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1296 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1297 default: 1298 break; 1299 } 1300 1301 return smu_v13_0_set_performance_level(smu, level); 1302 } 1303 1304 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1305 enum smu_clk_type clk_type, 1306 uint32_t min, 1307 uint32_t max) 1308 { 1309 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1310 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1311 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1312 struct amdgpu_device *adev = smu->adev; 1313 uint32_t min_clk; 1314 uint32_t max_clk; 1315 int ret = 0; 1316 1317 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1318 return -EINVAL; 1319 1320 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1321 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1322 return -EINVAL; 1323 1324 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1325 if (min >= max) { 1326 dev_err(smu->adev->dev, 1327 "Minimum GFX clk should be less than the maximum allowed clock\n"); 1328 return -EINVAL; 1329 } 1330 1331 if ((min == pstate_table->gfxclk_pstate.curr.min) && 1332 (max == pstate_table->gfxclk_pstate.curr.max)) 1333 return 0; 1334 1335 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, 1336 min, max); 1337 if (!ret) { 1338 pstate_table->gfxclk_pstate.curr.min = min; 1339 pstate_table->gfxclk_pstate.curr.max = max; 1340 } 1341 1342 return ret; 1343 } 1344 1345 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1346 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1347 (max > dpm_context->dpm_tables.gfx_table.max)) { 1348 dev_warn(adev->dev, 1349 "Invalid max frequency %d MHz specified for determinism\n", max); 1350 return -EINVAL; 1351 } 1352 1353 /* Restore default min/max clocks and enable determinism */ 1354 min_clk = dpm_context->dpm_tables.gfx_table.min; 1355 max_clk = dpm_context->dpm_tables.gfx_table.max; 1356 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1357 if (!ret) { 1358 usleep_range(500, 1000); 1359 ret = smu_cmn_send_smc_msg_with_param(smu, 1360 SMU_MSG_EnableDeterminism, 1361 max, NULL); 1362 if (ret) { 1363 dev_err(adev->dev, 1364 "Failed to enable determinism at GFX clock %d MHz\n", max); 1365 } else { 1366 pstate_table->gfxclk_pstate.curr.min = min_clk; 1367 pstate_table->gfxclk_pstate.curr.max = max; 1368 } 1369 } 1370 } 1371 1372 return ret; 1373 } 1374 1375 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1376 long input[], uint32_t size) 1377 { 1378 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1379 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1380 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1381 uint32_t min_clk; 1382 uint32_t max_clk; 1383 int ret = 0; 1384 1385 /* Only allowed in manual or determinism mode */ 1386 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1387 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1388 return -EINVAL; 1389 1390 switch (type) { 1391 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1392 if (size != 2) { 1393 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1394 return -EINVAL; 1395 } 1396 1397 if (input[0] == 0) { 1398 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1399 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1400 input[1], dpm_context->dpm_tables.gfx_table.min); 1401 pstate_table->gfxclk_pstate.custom.min = 1402 pstate_table->gfxclk_pstate.curr.min; 1403 return -EINVAL; 1404 } 1405 1406 pstate_table->gfxclk_pstate.custom.min = input[1]; 1407 } else if (input[0] == 1) { 1408 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1409 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1410 input[1], dpm_context->dpm_tables.gfx_table.max); 1411 pstate_table->gfxclk_pstate.custom.max = 1412 pstate_table->gfxclk_pstate.curr.max; 1413 return -EINVAL; 1414 } 1415 1416 pstate_table->gfxclk_pstate.custom.max = input[1]; 1417 } else { 1418 return -EINVAL; 1419 } 1420 break; 1421 case PP_OD_RESTORE_DEFAULT_TABLE: 1422 if (size != 0) { 1423 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1424 return -EINVAL; 1425 } else { 1426 /* Use the default frequencies for manual and determinism mode */ 1427 min_clk = dpm_context->dpm_tables.gfx_table.min; 1428 max_clk = dpm_context->dpm_tables.gfx_table.max; 1429 1430 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1431 } 1432 break; 1433 case PP_OD_COMMIT_DPM_TABLE: 1434 if (size != 0) { 1435 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1436 return -EINVAL; 1437 } else { 1438 if (!pstate_table->gfxclk_pstate.custom.min) 1439 pstate_table->gfxclk_pstate.custom.min = 1440 pstate_table->gfxclk_pstate.curr.min; 1441 1442 if (!pstate_table->gfxclk_pstate.custom.max) 1443 pstate_table->gfxclk_pstate.custom.max = 1444 pstate_table->gfxclk_pstate.curr.max; 1445 1446 min_clk = pstate_table->gfxclk_pstate.custom.min; 1447 max_clk = pstate_table->gfxclk_pstate.custom.max; 1448 1449 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1450 } 1451 break; 1452 default: 1453 return -ENOSYS; 1454 } 1455 1456 return ret; 1457 } 1458 1459 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1460 { 1461 int ret; 1462 uint32_t feature_mask[2]; 1463 unsigned long feature_enabled; 1464 1465 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1466 if (ret) 1467 return false; 1468 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 1469 ((uint64_t)feature_mask[1] << 32)); 1470 return !!(feature_enabled & SMC_DPM_FEATURE); 1471 } 1472 1473 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1474 struct i2c_msg *msg, int num_msgs) 1475 { 1476 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 1477 struct smu_table_context *smu_table = &adev->smu.smu_table; 1478 struct smu_table *table = &smu_table->driver_table; 1479 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1480 int i, j, r, c; 1481 u16 dir; 1482 1483 req = kzalloc(sizeof(*req), GFP_KERNEL); 1484 if (!req) 1485 return -ENOMEM; 1486 1487 req->I2CcontrollerPort = 0; 1488 req->I2CSpeed = I2C_SPEED_FAST_400K; 1489 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1490 dir = msg[0].flags & I2C_M_RD; 1491 1492 for (c = i = 0; i < num_msgs; i++) { 1493 for (j = 0; j < msg[i].len; j++, c++) { 1494 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1495 1496 if (!(msg[i].flags & I2C_M_RD)) { 1497 /* write */ 1498 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1499 cmd->ReadWriteData = msg[i].buf[j]; 1500 } 1501 1502 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1503 /* The direction changes. 1504 */ 1505 dir = msg[i].flags & I2C_M_RD; 1506 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1507 } 1508 1509 req->NumCmds++; 1510 1511 /* 1512 * Insert STOP if we are at the last byte of either last 1513 * message for the transaction or the client explicitly 1514 * requires a STOP at this particular message. 1515 */ 1516 if ((j == msg[i].len - 1) && 1517 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1518 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1519 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1520 } 1521 } 1522 } 1523 mutex_lock(&adev->smu.mutex); 1524 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1525 mutex_unlock(&adev->smu.mutex); 1526 if (r) 1527 goto fail; 1528 1529 for (c = i = 0; i < num_msgs; i++) { 1530 if (!(msg[i].flags & I2C_M_RD)) { 1531 c += msg[i].len; 1532 continue; 1533 } 1534 for (j = 0; j < msg[i].len; j++, c++) { 1535 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1536 1537 msg[i].buf[j] = cmd->ReadWriteData; 1538 } 1539 } 1540 r = num_msgs; 1541 fail: 1542 kfree(req); 1543 return r; 1544 } 1545 1546 static u32 aldebaran_i2c_func(struct i2c_adapter *adap) 1547 { 1548 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1549 } 1550 1551 1552 static const struct i2c_algorithm aldebaran_i2c_algo = { 1553 .master_xfer = aldebaran_i2c_xfer, 1554 .functionality = aldebaran_i2c_func, 1555 }; 1556 1557 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = { 1558 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1559 .max_read_len = MAX_SW_I2C_COMMANDS, 1560 .max_write_len = MAX_SW_I2C_COMMANDS, 1561 .max_comb_1st_msg_len = 2, 1562 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1563 }; 1564 1565 static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 1566 { 1567 struct amdgpu_device *adev = to_amdgpu_device(control); 1568 int res; 1569 1570 control->owner = THIS_MODULE; 1571 control->class = I2C_CLASS_SPD; 1572 control->dev.parent = &adev->pdev->dev; 1573 control->algo = &aldebaran_i2c_algo; 1574 snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 1575 control->quirks = &aldebaran_i2c_control_quirks; 1576 1577 res = i2c_add_adapter(control); 1578 if (res) 1579 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1580 1581 return res; 1582 } 1583 1584 static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 1585 { 1586 i2c_del_adapter(control); 1587 } 1588 1589 static void aldebaran_get_unique_id(struct smu_context *smu) 1590 { 1591 struct amdgpu_device *adev = smu->adev; 1592 SmuMetrics_t *metrics = smu->smu_table.metrics_table; 1593 uint32_t upper32 = 0, lower32 = 0; 1594 int ret; 1595 1596 mutex_lock(&smu->metrics_lock); 1597 ret = smu_cmn_get_metrics_table_locked(smu, NULL, false); 1598 if (ret) 1599 goto out_unlock; 1600 1601 upper32 = metrics->PublicSerialNumUpper32; 1602 lower32 = metrics->PublicSerialNumLower32; 1603 1604 out_unlock: 1605 mutex_unlock(&smu->metrics_lock); 1606 1607 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1608 sprintf(adev->serial, "%016llx", adev->unique_id); 1609 } 1610 1611 static bool aldebaran_is_baco_supported(struct smu_context *smu) 1612 { 1613 /* aldebaran is not support baco */ 1614 1615 return false; 1616 } 1617 1618 static int aldebaran_set_df_cstate(struct smu_context *smu, 1619 enum pp_df_cstate state) 1620 { 1621 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1622 } 1623 1624 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) 1625 { 1626 return smu_cmn_send_smc_msg_with_param(smu, 1627 SMU_MSG_GmiPwrDnControl, 1628 en ? 0 : 1, 1629 NULL); 1630 } 1631 1632 static const struct throttling_logging_label { 1633 uint32_t feature_mask; 1634 const char *label; 1635 } logging_label[] = { 1636 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1637 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1638 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1639 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1640 }; 1641 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1642 { 1643 int ret; 1644 int throttler_idx, throtting_events = 0, buf_idx = 0; 1645 struct amdgpu_device *adev = smu->adev; 1646 uint32_t throttler_status; 1647 char log_buf[256]; 1648 1649 ret = aldebaran_get_smu_metrics_data(smu, 1650 METRICS_THROTTLER_STATUS, 1651 &throttler_status); 1652 if (ret) 1653 return; 1654 1655 memset(log_buf, 0, sizeof(log_buf)); 1656 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1657 throttler_idx++) { 1658 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1659 throtting_events++; 1660 buf_idx += snprintf(log_buf + buf_idx, 1661 sizeof(log_buf) - buf_idx, 1662 "%s%s", 1663 throtting_events > 1 ? " and " : "", 1664 logging_label[throttler_idx].label); 1665 if (buf_idx >= sizeof(log_buf)) { 1666 dev_err(adev->dev, "buffer overflow!\n"); 1667 log_buf[sizeof(log_buf) - 1] = '\0'; 1668 break; 1669 } 1670 } 1671 } 1672 1673 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1674 log_buf); 1675 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 1676 smu_cmn_get_indep_throttler_status(throttler_status, 1677 aldebaran_throttler_map)); 1678 } 1679 1680 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1681 { 1682 struct amdgpu_device *adev = smu->adev; 1683 uint32_t esm_ctrl; 1684 1685 /* TODO: confirm this on real target */ 1686 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1687 if ((esm_ctrl >> 15) & 0x1FFFF) 1688 return (((esm_ctrl >> 8) & 0x3F) + 128); 1689 1690 return smu_v13_0_get_current_pcie_link_speed(smu); 1691 } 1692 1693 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1694 void **table) 1695 { 1696 struct smu_table_context *smu_table = &smu->smu_table; 1697 struct gpu_metrics_v1_3 *gpu_metrics = 1698 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1699 SmuMetrics_t metrics; 1700 int i, ret = 0; 1701 1702 ret = smu_cmn_get_metrics_table(smu, 1703 &metrics, 1704 true); 1705 if (ret) 1706 return ret; 1707 1708 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1709 1710 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1711 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1712 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1713 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1714 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1715 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1716 1717 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1718 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1719 gpu_metrics->average_mm_activity = 0; 1720 1721 /* Valid power data is available only from primary die */ 1722 if (aldebaran_is_primary(smu)) { 1723 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1724 gpu_metrics->energy_accumulator = 1725 (uint64_t)metrics.EnergyAcc64bitHigh << 32 | 1726 metrics.EnergyAcc64bitLow; 1727 } else { 1728 gpu_metrics->average_socket_power = 0; 1729 gpu_metrics->energy_accumulator = 0; 1730 } 1731 1732 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1733 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1734 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1735 gpu_metrics->average_vclk0_frequency = 0; 1736 gpu_metrics->average_dclk0_frequency = 0; 1737 1738 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1739 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1740 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1741 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1742 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1743 1744 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1745 gpu_metrics->indep_throttle_status = 1746 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1747 aldebaran_throttler_map); 1748 1749 gpu_metrics->current_fan_speed = 0; 1750 1751 gpu_metrics->pcie_link_width = 1752 smu_v13_0_get_current_pcie_link_width(smu); 1753 gpu_metrics->pcie_link_speed = 1754 aldebaran_get_current_pcie_link_speed(smu); 1755 1756 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1757 1758 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1759 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1760 1761 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1762 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1763 1764 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) | 1765 metrics.TimeStampLow; 1766 1767 *table = (void *)gpu_metrics; 1768 1769 return sizeof(struct gpu_metrics_v1_3); 1770 } 1771 1772 static int aldebaran_check_ecc_table_support(struct smu_context *smu) 1773 { 1774 uint32_t if_version = 0xff, smu_version = 0xff; 1775 int ret = 0; 1776 1777 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 1778 if (ret) { 1779 /* return not support if failed get smu_version */ 1780 ret = -EOPNOTSUPP; 1781 } 1782 1783 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) 1784 ret = -EOPNOTSUPP; 1785 1786 return ret; 1787 } 1788 1789 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, 1790 void *table) 1791 { 1792 struct smu_table_context *smu_table = &smu->smu_table; 1793 EccInfoTable_t *ecc_table = NULL; 1794 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 1795 int i, ret = 0; 1796 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 1797 1798 ret = aldebaran_check_ecc_table_support(smu); 1799 if (ret) 1800 return ret; 1801 1802 ret = smu_cmn_update_table(smu, 1803 SMU_TABLE_ECCINFO, 1804 0, 1805 smu_table->ecc_table, 1806 false); 1807 if (ret) { 1808 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 1809 return ret; 1810 } 1811 1812 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 1813 1814 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1815 ecc_info_per_channel = &(eccinfo->ecc[i]); 1816 ecc_info_per_channel->ce_count_lo_chip = 1817 ecc_table->EccInfo[i].ce_count_lo_chip; 1818 ecc_info_per_channel->ce_count_hi_chip = 1819 ecc_table->EccInfo[i].ce_count_hi_chip; 1820 ecc_info_per_channel->mca_umc_status = 1821 ecc_table->EccInfo[i].mca_umc_status; 1822 ecc_info_per_channel->mca_umc_addr = 1823 ecc_table->EccInfo[i].mca_umc_addr; 1824 } 1825 1826 return ret; 1827 } 1828 1829 static int aldebaran_mode1_reset(struct smu_context *smu) 1830 { 1831 u32 smu_version, fatal_err, param; 1832 int ret = 0; 1833 struct amdgpu_device *adev = smu->adev; 1834 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1835 1836 fatal_err = 0; 1837 param = SMU_RESET_MODE_1; 1838 1839 /* 1840 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 1841 */ 1842 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1843 if (smu_version < 0x00440700) { 1844 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1845 } 1846 else { 1847 /* fatal error triggered by ras, PMFW supports the flag 1848 from 68.44.0 */ 1849 if ((smu_version >= 0x00442c00) && ras && 1850 atomic_read(&ras->in_recovery)) 1851 fatal_err = 1; 1852 1853 param |= (fatal_err << 16); 1854 ret = smu_cmn_send_smc_msg_with_param(smu, 1855 SMU_MSG_GfxDeviceDriverReset, param, NULL); 1856 } 1857 1858 if (!ret) 1859 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 1860 1861 return ret; 1862 } 1863 1864 static int aldebaran_mode2_reset(struct smu_context *smu) 1865 { 1866 u32 smu_version; 1867 int ret = 0, index; 1868 struct amdgpu_device *adev = smu->adev; 1869 int timeout = 10; 1870 1871 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1872 1873 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1874 SMU_MSG_GfxDeviceDriverReset); 1875 1876 mutex_lock(&smu->message_lock); 1877 if (smu_version >= 0x00441400) { 1878 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1879 /* This is similar to FLR, wait till max FLR timeout */ 1880 msleep(100); 1881 dev_dbg(smu->adev->dev, "restore config space...\n"); 1882 /* Restore the config space saved during init */ 1883 amdgpu_device_load_pci_state(adev->pdev); 1884 1885 dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1886 while (ret == -ETIME && timeout) { 1887 ret = smu_cmn_wait_for_response(smu); 1888 /* Wait a bit more time for getting ACK */ 1889 if (ret == -ETIME) { 1890 --timeout; 1891 usleep_range(500, 1000); 1892 continue; 1893 } 1894 1895 if (ret != 1) { 1896 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n", 1897 SMU_RESET_MODE_2, ret); 1898 goto out; 1899 } 1900 } 1901 1902 } else { 1903 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", 1904 smu_version); 1905 } 1906 1907 if (ret == 1) 1908 ret = 0; 1909 out: 1910 mutex_unlock(&smu->message_lock); 1911 1912 return ret; 1913 } 1914 1915 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1916 { 1917 #if 0 1918 struct amdgpu_device *adev = smu->adev; 1919 u32 smu_version; 1920 uint32_t val; 1921 /** 1922 * PM FW version support mode1 reset from 68.07 1923 */ 1924 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1925 if ((smu_version < 0x00440700)) 1926 return false; 1927 /** 1928 * mode1 reset relies on PSP, so we should check if 1929 * PSP is alive. 1930 */ 1931 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1932 1933 return val != 0x0; 1934 #endif 1935 return true; 1936 } 1937 1938 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 1939 { 1940 return true; 1941 } 1942 1943 static int aldebaran_set_mp1_state(struct smu_context *smu, 1944 enum pp_mp1_state mp1_state) 1945 { 1946 switch (mp1_state) { 1947 case PP_MP1_STATE_UNLOAD: 1948 return smu_cmn_set_mp1_state(smu, mp1_state); 1949 default: 1950 return 0; 1951 } 1952 } 1953 1954 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, 1955 uint32_t size) 1956 { 1957 int ret = 0; 1958 1959 /* message SMU to update the bad page number on SMUBUS */ 1960 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL); 1961 if (ret) 1962 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n", 1963 __func__); 1964 1965 return ret; 1966 } 1967 1968 static const struct pptable_funcs aldebaran_ppt_funcs = { 1969 /* init dpm */ 1970 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 1971 /* dpm/clk tables */ 1972 .set_default_dpm_table = aldebaran_set_default_dpm_table, 1973 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 1974 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 1975 .print_clk_levels = aldebaran_print_clk_levels, 1976 .force_clk_levels = aldebaran_force_clk_levels, 1977 .read_sensor = aldebaran_read_sensor, 1978 .set_performance_level = aldebaran_set_performance_level, 1979 .get_power_limit = aldebaran_get_power_limit, 1980 .is_dpm_running = aldebaran_is_dpm_running, 1981 .get_unique_id = aldebaran_get_unique_id, 1982 .init_microcode = smu_v13_0_init_microcode, 1983 .load_microcode = smu_v13_0_load_microcode, 1984 .fini_microcode = smu_v13_0_fini_microcode, 1985 .init_smc_tables = aldebaran_init_smc_tables, 1986 .fini_smc_tables = smu_v13_0_fini_smc_tables, 1987 .init_power = smu_v13_0_init_power, 1988 .fini_power = smu_v13_0_fini_power, 1989 .check_fw_status = smu_v13_0_check_fw_status, 1990 /* pptable related */ 1991 .setup_pptable = aldebaran_setup_pptable, 1992 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1993 .check_fw_version = smu_v13_0_check_fw_version, 1994 .write_pptable = smu_cmn_write_pptable, 1995 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1996 .set_tool_table_location = smu_v13_0_set_tool_table_location, 1997 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 1998 .system_features_control = aldebaran_system_features_control, 1999 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2000 .send_smc_msg = smu_cmn_send_smc_msg, 2001 .get_enabled_mask = smu_cmn_get_enabled_mask, 2002 .feature_is_enabled = smu_cmn_feature_is_enabled, 2003 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2004 .set_power_limit = aldebaran_set_power_limit, 2005 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 2006 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2007 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2008 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 2009 .register_irq_handler = smu_v13_0_register_irq_handler, 2010 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 2011 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 2012 .baco_is_support= aldebaran_is_baco_supported, 2013 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 2014 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 2015 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 2016 .set_df_cstate = aldebaran_set_df_cstate, 2017 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down, 2018 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 2019 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2020 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2021 .get_gpu_metrics = aldebaran_get_gpu_metrics, 2022 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 2023 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 2024 .mode1_reset = aldebaran_mode1_reset, 2025 .set_mp1_state = aldebaran_set_mp1_state, 2026 .mode2_reset = aldebaran_mode2_reset, 2027 .wait_for_event = smu_v13_0_wait_for_event, 2028 .i2c_init = aldebaran_i2c_control_init, 2029 .i2c_fini = aldebaran_i2c_control_fini, 2030 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num, 2031 .get_ecc_info = aldebaran_get_ecc_info, 2032 }; 2033 2034 void aldebaran_set_ppt_funcs(struct smu_context *smu) 2035 { 2036 smu->ppt_funcs = &aldebaran_ppt_funcs; 2037 smu->message_map = aldebaran_message_map; 2038 smu->clock_map = aldebaran_clk_map; 2039 smu->feature_map = aldebaran_feature_mask_map; 2040 smu->table_map = aldebaran_table_map; 2041 } 2042