1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_smu.h" 29 #include "atomfirmware.h" 30 #include "amdgpu_atomfirmware.h" 31 #include "amdgpu_atombios.h" 32 #include "smu_v13_0.h" 33 #include "smu13_driver_if_aldebaran.h" 34 #include "soc15_common.h" 35 #include "atom.h" 36 #include "power_state.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 63 [smu_feature] = {1, (aldebaran_feature)} 64 65 #define FEATURE_MASK(feature) (1ULL << feature) 66 #define SMC_DPM_FEATURE ( \ 67 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 68 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 73 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 74 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 75 76 /* possible frequency drift (1Mhz) */ 77 #define EPSILON 1 78 79 #define smnPCIE_ESM_CTRL 0x111003D0 80 81 /* 82 * SMU support ECCTABLE since version 68.42.0, 83 * use this to check ECCTALE feature whether support 84 */ 85 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00 86 87 static const struct smu_temperature_range smu13_thermal_policy[] = 88 { 89 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 90 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 91 }; 92 93 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 94 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 95 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 96 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 99 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 100 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 101 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 102 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 103 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 104 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 105 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 106 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 107 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 108 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 109 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 110 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 111 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 112 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 113 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 114 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 115 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 116 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 117 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 118 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 119 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 120 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 121 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 122 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 123 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 124 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 125 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 126 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 127 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 128 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 129 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 130 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 131 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 132 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 133 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 134 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 135 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 136 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 137 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 138 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 139 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 140 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 141 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 142 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 143 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0), 144 }; 145 146 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 147 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 148 CLK_MAP(SCLK, PPCLK_GFXCLK), 149 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 150 CLK_MAP(FCLK, PPCLK_FCLK), 151 CLK_MAP(UCLK, PPCLK_UCLK), 152 CLK_MAP(MCLK, PPCLK_UCLK), 153 CLK_MAP(DCLK, PPCLK_DCLK), 154 CLK_MAP(VCLK, PPCLK_VCLK), 155 CLK_MAP(LCLK, PPCLK_LCLK), 156 }; 157 158 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 159 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS), 160 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 161 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 162 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 163 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 164 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 165 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 166 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 167 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 168 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 169 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 170 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 175 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 176 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 177 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 178 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 179 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 180 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 181 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 182 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 183 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 184 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 185 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 186 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 187 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN), 188 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 189 }; 190 191 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 192 TAB_MAP(PPTABLE), 193 TAB_MAP(AVFS_PSM_DEBUG), 194 TAB_MAP(AVFS_FUSE_OVERRIDE), 195 TAB_MAP(PMSTATUSLOG), 196 TAB_MAP(SMU_METRICS), 197 TAB_MAP(DRIVER_SMU_CONFIG), 198 TAB_MAP(I2C_COMMANDS), 199 TAB_MAP(ECCINFO), 200 }; 201 202 static const uint8_t aldebaran_throttler_map[] = { 203 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 204 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 205 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 206 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 207 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT), 208 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), 209 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 210 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 211 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 212 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 213 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 214 }; 215 216 static int aldebaran_tables_init(struct smu_context *smu) 217 { 218 struct smu_table_context *smu_table = &smu->smu_table; 219 struct smu_table *tables = smu_table->tables; 220 221 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 222 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 223 224 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 225 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 226 227 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 229 230 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 231 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 232 233 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 235 236 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 237 if (!smu_table->metrics_table) 238 return -ENOMEM; 239 smu_table->metrics_time = 0; 240 241 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 242 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 243 if (!smu_table->gpu_metrics_table) { 244 kfree(smu_table->metrics_table); 245 return -ENOMEM; 246 } 247 248 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 249 if (!smu_table->ecc_table) 250 return -ENOMEM; 251 252 return 0; 253 } 254 255 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 256 { 257 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 258 259 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 260 GFP_KERNEL); 261 if (!smu_dpm->dpm_context) 262 return -ENOMEM; 263 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 264 265 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state), 266 GFP_KERNEL); 267 if (!smu_dpm->dpm_current_power_state) 268 return -ENOMEM; 269 270 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state), 271 GFP_KERNEL); 272 if (!smu_dpm->dpm_request_power_state) 273 return -ENOMEM; 274 275 return 0; 276 } 277 278 static int aldebaran_init_smc_tables(struct smu_context *smu) 279 { 280 int ret = 0; 281 282 ret = aldebaran_tables_init(smu); 283 if (ret) 284 return ret; 285 286 ret = aldebaran_allocate_dpm_context(smu); 287 if (ret) 288 return ret; 289 290 return smu_v13_0_init_smc_tables(smu); 291 } 292 293 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 294 uint32_t *feature_mask, uint32_t num) 295 { 296 if (num > 2) 297 return -EINVAL; 298 299 /* pptable will handle the features to enable */ 300 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 301 302 return 0; 303 } 304 305 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 306 { 307 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 308 struct smu_13_0_dpm_table *dpm_table = NULL; 309 PPTable_t *pptable = smu->smu_table.driver_pptable; 310 int ret = 0; 311 312 /* socclk dpm table setup */ 313 dpm_table = &dpm_context->dpm_tables.soc_table; 314 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 315 ret = smu_v13_0_set_single_dpm_table(smu, 316 SMU_SOCCLK, 317 dpm_table); 318 if (ret) 319 return ret; 320 } else { 321 dpm_table->count = 1; 322 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 323 dpm_table->dpm_levels[0].enabled = true; 324 dpm_table->min = dpm_table->dpm_levels[0].value; 325 dpm_table->max = dpm_table->dpm_levels[0].value; 326 } 327 328 /* gfxclk dpm table setup */ 329 dpm_table = &dpm_context->dpm_tables.gfx_table; 330 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 331 /* in the case of gfxclk, only fine-grained dpm is honored */ 332 dpm_table->count = 2; 333 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 334 dpm_table->dpm_levels[0].enabled = true; 335 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 336 dpm_table->dpm_levels[1].enabled = true; 337 dpm_table->min = dpm_table->dpm_levels[0].value; 338 dpm_table->max = dpm_table->dpm_levels[1].value; 339 } else { 340 dpm_table->count = 1; 341 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 342 dpm_table->dpm_levels[0].enabled = true; 343 dpm_table->min = dpm_table->dpm_levels[0].value; 344 dpm_table->max = dpm_table->dpm_levels[0].value; 345 } 346 347 /* memclk dpm table setup */ 348 dpm_table = &dpm_context->dpm_tables.uclk_table; 349 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 350 ret = smu_v13_0_set_single_dpm_table(smu, 351 SMU_UCLK, 352 dpm_table); 353 if (ret) 354 return ret; 355 } else { 356 dpm_table->count = 1; 357 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 358 dpm_table->dpm_levels[0].enabled = true; 359 dpm_table->min = dpm_table->dpm_levels[0].value; 360 dpm_table->max = dpm_table->dpm_levels[0].value; 361 } 362 363 /* fclk dpm table setup */ 364 dpm_table = &dpm_context->dpm_tables.fclk_table; 365 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 366 ret = smu_v13_0_set_single_dpm_table(smu, 367 SMU_FCLK, 368 dpm_table); 369 if (ret) 370 return ret; 371 } else { 372 dpm_table->count = 1; 373 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 374 dpm_table->dpm_levels[0].enabled = true; 375 dpm_table->min = dpm_table->dpm_levels[0].value; 376 dpm_table->max = dpm_table->dpm_levels[0].value; 377 } 378 379 return 0; 380 } 381 382 static int aldebaran_check_powerplay_table(struct smu_context *smu) 383 { 384 struct smu_table_context *table_context = &smu->smu_table; 385 struct smu_13_0_powerplay_table *powerplay_table = 386 table_context->power_play_table; 387 388 table_context->thermal_controller_type = 389 powerplay_table->thermal_controller_type; 390 391 return 0; 392 } 393 394 static int aldebaran_store_powerplay_table(struct smu_context *smu) 395 { 396 struct smu_table_context *table_context = &smu->smu_table; 397 struct smu_13_0_powerplay_table *powerplay_table = 398 table_context->power_play_table; 399 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 400 sizeof(PPTable_t)); 401 402 return 0; 403 } 404 405 static int aldebaran_append_powerplay_table(struct smu_context *smu) 406 { 407 struct smu_table_context *table_context = &smu->smu_table; 408 PPTable_t *smc_pptable = table_context->driver_pptable; 409 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 410 int index, ret; 411 412 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 413 smc_dpm_info); 414 415 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 416 (uint8_t **)&smc_dpm_table); 417 if (ret) 418 return ret; 419 420 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 421 smc_dpm_table->table_header.format_revision, 422 smc_dpm_table->table_header.content_revision); 423 424 if ((smc_dpm_table->table_header.format_revision == 4) && 425 (smc_dpm_table->table_header.content_revision == 10)) 426 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved, 427 smc_dpm_table, GfxMaxCurrent); 428 return 0; 429 } 430 431 static int aldebaran_setup_pptable(struct smu_context *smu) 432 { 433 int ret = 0; 434 435 /* VBIOS pptable is the first choice */ 436 smu->smu_table.boot_values.pp_table_id = 0; 437 438 ret = smu_v13_0_setup_pptable(smu); 439 if (ret) 440 return ret; 441 442 ret = aldebaran_store_powerplay_table(smu); 443 if (ret) 444 return ret; 445 446 ret = aldebaran_append_powerplay_table(smu); 447 if (ret) 448 return ret; 449 450 ret = aldebaran_check_powerplay_table(smu); 451 if (ret) 452 return ret; 453 454 return ret; 455 } 456 457 static bool aldebaran_is_primary(struct smu_context *smu) 458 { 459 struct amdgpu_device *adev = smu->adev; 460 461 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) 462 return adev->smuio.funcs->get_die_id(adev) == 0; 463 464 return true; 465 } 466 467 static int aldebaran_run_board_btc(struct smu_context *smu) 468 { 469 u32 smu_version; 470 int ret; 471 472 if (!aldebaran_is_primary(smu)) 473 return 0; 474 475 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 476 if (ret) { 477 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 478 return ret; 479 } 480 if (smu_version <= 0x00441d00) 481 return 0; 482 483 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL); 484 if (ret) 485 dev_err(smu->adev->dev, "Board power calibration failed!\n"); 486 487 return ret; 488 } 489 490 static int aldebaran_run_btc(struct smu_context *smu) 491 { 492 int ret; 493 494 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 495 if (ret) 496 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 497 else 498 ret = aldebaran_run_board_btc(smu); 499 500 return ret; 501 } 502 503 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 504 { 505 struct smu_13_0_dpm_context *dpm_context = 506 smu->smu_dpm.dpm_context; 507 struct smu_13_0_dpm_table *gfx_table = 508 &dpm_context->dpm_tables.gfx_table; 509 struct smu_13_0_dpm_table *mem_table = 510 &dpm_context->dpm_tables.uclk_table; 511 struct smu_13_0_dpm_table *soc_table = 512 &dpm_context->dpm_tables.soc_table; 513 struct smu_umd_pstate_table *pstate_table = 514 &smu->pstate_table; 515 516 pstate_table->gfxclk_pstate.min = gfx_table->min; 517 pstate_table->gfxclk_pstate.peak = gfx_table->max; 518 pstate_table->gfxclk_pstate.curr.min = gfx_table->min; 519 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 520 521 pstate_table->uclk_pstate.min = mem_table->min; 522 pstate_table->uclk_pstate.peak = mem_table->max; 523 pstate_table->uclk_pstate.curr.min = mem_table->min; 524 pstate_table->uclk_pstate.curr.max = mem_table->max; 525 526 pstate_table->socclk_pstate.min = soc_table->min; 527 pstate_table->socclk_pstate.peak = soc_table->max; 528 pstate_table->socclk_pstate.curr.min = soc_table->min; 529 pstate_table->socclk_pstate.curr.max = soc_table->max; 530 531 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 532 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 533 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 534 pstate_table->gfxclk_pstate.standard = 535 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 536 pstate_table->uclk_pstate.standard = 537 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 538 pstate_table->socclk_pstate.standard = 539 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 540 } else { 541 pstate_table->gfxclk_pstate.standard = 542 pstate_table->gfxclk_pstate.min; 543 pstate_table->uclk_pstate.standard = 544 pstate_table->uclk_pstate.min; 545 pstate_table->socclk_pstate.standard = 546 pstate_table->socclk_pstate.min; 547 } 548 549 return 0; 550 } 551 552 static int aldebaran_get_clk_table(struct smu_context *smu, 553 struct pp_clock_levels_with_latency *clocks, 554 struct smu_13_0_dpm_table *dpm_table) 555 { 556 int i, count; 557 558 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 559 clocks->num_levels = count; 560 561 for (i = 0; i < count; i++) { 562 clocks->data[i].clocks_in_khz = 563 dpm_table->dpm_levels[i].value * 1000; 564 clocks->data[i].latency_in_us = 0; 565 } 566 567 return 0; 568 } 569 570 static int aldebaran_freqs_in_same_level(int32_t frequency1, 571 int32_t frequency2) 572 { 573 return (abs(frequency1 - frequency2) <= EPSILON); 574 } 575 576 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 577 MetricsMember_t member, 578 uint32_t *value) 579 { 580 struct smu_table_context *smu_table= &smu->smu_table; 581 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 582 int ret = 0; 583 584 mutex_lock(&smu->metrics_lock); 585 586 ret = smu_cmn_get_metrics_table_locked(smu, 587 NULL, 588 false); 589 if (ret) { 590 mutex_unlock(&smu->metrics_lock); 591 return ret; 592 } 593 594 switch (member) { 595 case METRICS_CURR_GFXCLK: 596 *value = metrics->CurrClock[PPCLK_GFXCLK]; 597 break; 598 case METRICS_CURR_SOCCLK: 599 *value = metrics->CurrClock[PPCLK_SOCCLK]; 600 break; 601 case METRICS_CURR_UCLK: 602 *value = metrics->CurrClock[PPCLK_UCLK]; 603 break; 604 case METRICS_CURR_VCLK: 605 *value = metrics->CurrClock[PPCLK_VCLK]; 606 break; 607 case METRICS_CURR_DCLK: 608 *value = metrics->CurrClock[PPCLK_DCLK]; 609 break; 610 case METRICS_CURR_FCLK: 611 *value = metrics->CurrClock[PPCLK_FCLK]; 612 break; 613 case METRICS_AVERAGE_GFXCLK: 614 *value = metrics->AverageGfxclkFrequency; 615 break; 616 case METRICS_AVERAGE_SOCCLK: 617 *value = metrics->AverageSocclkFrequency; 618 break; 619 case METRICS_AVERAGE_UCLK: 620 *value = metrics->AverageUclkFrequency; 621 break; 622 case METRICS_AVERAGE_GFXACTIVITY: 623 *value = metrics->AverageGfxActivity; 624 break; 625 case METRICS_AVERAGE_MEMACTIVITY: 626 *value = metrics->AverageUclkActivity; 627 break; 628 case METRICS_AVERAGE_SOCKETPOWER: 629 /* Valid power data is available only from primary die */ 630 *value = aldebaran_is_primary(smu) ? 631 metrics->AverageSocketPower << 8 : 632 0; 633 break; 634 case METRICS_TEMPERATURE_EDGE: 635 *value = metrics->TemperatureEdge * 636 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 637 break; 638 case METRICS_TEMPERATURE_HOTSPOT: 639 *value = metrics->TemperatureHotspot * 640 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 641 break; 642 case METRICS_TEMPERATURE_MEM: 643 *value = metrics->TemperatureHBM * 644 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 645 break; 646 case METRICS_TEMPERATURE_VRGFX: 647 *value = metrics->TemperatureVrGfx * 648 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 649 break; 650 case METRICS_TEMPERATURE_VRSOC: 651 *value = metrics->TemperatureVrSoc * 652 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 653 break; 654 case METRICS_TEMPERATURE_VRMEM: 655 *value = metrics->TemperatureVrMem * 656 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 657 break; 658 case METRICS_THROTTLER_STATUS: 659 *value = metrics->ThrottlerStatus; 660 break; 661 default: 662 *value = UINT_MAX; 663 break; 664 } 665 666 mutex_unlock(&smu->metrics_lock); 667 668 return ret; 669 } 670 671 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 672 enum smu_clk_type clk_type, 673 uint32_t *value) 674 { 675 MetricsMember_t member_type; 676 int clk_id = 0; 677 678 if (!value) 679 return -EINVAL; 680 681 clk_id = smu_cmn_to_asic_specific_index(smu, 682 CMN2ASIC_MAPPING_CLK, 683 clk_type); 684 if (clk_id < 0) 685 return -EINVAL; 686 687 switch (clk_id) { 688 case PPCLK_GFXCLK: 689 /* 690 * CurrClock[clk_id] can provide accurate 691 * output only when the dpm feature is enabled. 692 * We can use Average_* for dpm disabled case. 693 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 694 */ 695 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 696 member_type = METRICS_CURR_GFXCLK; 697 else 698 member_type = METRICS_AVERAGE_GFXCLK; 699 break; 700 case PPCLK_UCLK: 701 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 702 member_type = METRICS_CURR_UCLK; 703 else 704 member_type = METRICS_AVERAGE_UCLK; 705 break; 706 case PPCLK_SOCCLK: 707 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 708 member_type = METRICS_CURR_SOCCLK; 709 else 710 member_type = METRICS_AVERAGE_SOCCLK; 711 break; 712 case PPCLK_VCLK: 713 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 714 member_type = METRICS_CURR_VCLK; 715 else 716 member_type = METRICS_AVERAGE_VCLK; 717 break; 718 case PPCLK_DCLK: 719 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 720 member_type = METRICS_CURR_DCLK; 721 else 722 member_type = METRICS_AVERAGE_DCLK; 723 break; 724 case PPCLK_FCLK: 725 member_type = METRICS_CURR_FCLK; 726 break; 727 default: 728 return -EINVAL; 729 } 730 731 return aldebaran_get_smu_metrics_data(smu, 732 member_type, 733 value); 734 } 735 736 static int aldebaran_print_clk_levels(struct smu_context *smu, 737 enum smu_clk_type type, char *buf) 738 { 739 int i, now, size = 0; 740 int ret = 0; 741 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 742 struct pp_clock_levels_with_latency clocks; 743 struct smu_13_0_dpm_table *single_dpm_table; 744 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 745 struct smu_13_0_dpm_context *dpm_context = NULL; 746 uint32_t display_levels; 747 uint32_t freq_values[3] = {0}; 748 uint32_t min_clk, max_clk; 749 750 smu_cmn_get_sysfs_buf(&buf, &size); 751 752 if (amdgpu_ras_intr_triggered()) { 753 size += sysfs_emit_at(buf, size, "unavailable\n"); 754 return size; 755 } 756 757 dpm_context = smu_dpm->dpm_context; 758 759 switch (type) { 760 761 case SMU_OD_SCLK: 762 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK"); 763 fallthrough; 764 case SMU_SCLK: 765 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 766 if (ret) { 767 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 768 return ret; 769 } 770 771 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 772 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 773 if (ret) { 774 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 775 return ret; 776 } 777 778 display_levels = clocks.num_levels; 779 780 min_clk = pstate_table->gfxclk_pstate.curr.min; 781 max_clk = pstate_table->gfxclk_pstate.curr.max; 782 783 freq_values[0] = min_clk; 784 freq_values[1] = max_clk; 785 786 /* fine-grained dpm has only 2 levels */ 787 if (now > min_clk && now < max_clk) { 788 display_levels = clocks.num_levels + 1; 789 freq_values[2] = max_clk; 790 freq_values[1] = now; 791 } 792 793 /* 794 * For DPM disabled case, there will be only one clock level. 795 * And it's safe to assume that is always the current clock. 796 */ 797 if (display_levels == clocks.num_levels) { 798 for (i = 0; i < clocks.num_levels; i++) 799 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 800 freq_values[i], 801 (clocks.num_levels == 1) ? 802 "*" : 803 (aldebaran_freqs_in_same_level( 804 freq_values[i], now) ? 805 "*" : 806 "")); 807 } else { 808 for (i = 0; i < display_levels; i++) 809 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 810 freq_values[i], i == 1 ? "*" : ""); 811 } 812 813 break; 814 815 case SMU_OD_MCLK: 816 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK"); 817 fallthrough; 818 case SMU_MCLK: 819 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 820 if (ret) { 821 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 822 return ret; 823 } 824 825 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 826 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 827 if (ret) { 828 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 829 return ret; 830 } 831 832 for (i = 0; i < clocks.num_levels; i++) 833 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 834 i, clocks.data[i].clocks_in_khz / 1000, 835 (clocks.num_levels == 1) ? "*" : 836 (aldebaran_freqs_in_same_level( 837 clocks.data[i].clocks_in_khz / 1000, 838 now) ? "*" : "")); 839 break; 840 841 case SMU_SOCCLK: 842 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 843 if (ret) { 844 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 845 return ret; 846 } 847 848 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 849 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 850 if (ret) { 851 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 852 return ret; 853 } 854 855 for (i = 0; i < clocks.num_levels; i++) 856 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 857 i, clocks.data[i].clocks_in_khz / 1000, 858 (clocks.num_levels == 1) ? "*" : 859 (aldebaran_freqs_in_same_level( 860 clocks.data[i].clocks_in_khz / 1000, 861 now) ? "*" : "")); 862 break; 863 864 case SMU_FCLK: 865 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 866 if (ret) { 867 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 868 return ret; 869 } 870 871 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 872 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 873 if (ret) { 874 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 875 return ret; 876 } 877 878 for (i = 0; i < single_dpm_table->count; i++) 879 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 880 i, single_dpm_table->dpm_levels[i].value, 881 (clocks.num_levels == 1) ? "*" : 882 (aldebaran_freqs_in_same_level( 883 clocks.data[i].clocks_in_khz / 1000, 884 now) ? "*" : "")); 885 break; 886 887 case SMU_VCLK: 888 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); 889 if (ret) { 890 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); 891 return ret; 892 } 893 894 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 895 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 896 if (ret) { 897 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); 898 return ret; 899 } 900 901 for (i = 0; i < single_dpm_table->count; i++) 902 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 903 i, single_dpm_table->dpm_levels[i].value, 904 (clocks.num_levels == 1) ? "*" : 905 (aldebaran_freqs_in_same_level( 906 clocks.data[i].clocks_in_khz / 1000, 907 now) ? "*" : "")); 908 break; 909 910 case SMU_DCLK: 911 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); 912 if (ret) { 913 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); 914 return ret; 915 } 916 917 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 918 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 919 if (ret) { 920 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); 921 return ret; 922 } 923 924 for (i = 0; i < single_dpm_table->count; i++) 925 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 926 i, single_dpm_table->dpm_levels[i].value, 927 (clocks.num_levels == 1) ? "*" : 928 (aldebaran_freqs_in_same_level( 929 clocks.data[i].clocks_in_khz / 1000, 930 now) ? "*" : "")); 931 break; 932 933 default: 934 break; 935 } 936 937 return size; 938 } 939 940 static int aldebaran_upload_dpm_level(struct smu_context *smu, 941 bool max, 942 uint32_t feature_mask, 943 uint32_t level) 944 { 945 struct smu_13_0_dpm_context *dpm_context = 946 smu->smu_dpm.dpm_context; 947 uint32_t freq; 948 int ret = 0; 949 950 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 951 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 952 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 953 ret = smu_cmn_send_smc_msg_with_param(smu, 954 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 955 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 956 NULL); 957 if (ret) { 958 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 959 max ? "max" : "min"); 960 return ret; 961 } 962 } 963 964 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 965 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 966 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 967 ret = smu_cmn_send_smc_msg_with_param(smu, 968 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 969 (PPCLK_UCLK << 16) | (freq & 0xffff), 970 NULL); 971 if (ret) { 972 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 973 max ? "max" : "min"); 974 return ret; 975 } 976 } 977 978 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 979 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 980 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 981 ret = smu_cmn_send_smc_msg_with_param(smu, 982 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 983 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 984 NULL); 985 if (ret) { 986 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 987 max ? "max" : "min"); 988 return ret; 989 } 990 } 991 992 return ret; 993 } 994 995 static int aldebaran_force_clk_levels(struct smu_context *smu, 996 enum smu_clk_type type, uint32_t mask) 997 { 998 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 999 struct smu_13_0_dpm_table *single_dpm_table = NULL; 1000 uint32_t soft_min_level, soft_max_level; 1001 int ret = 0; 1002 1003 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1004 soft_max_level = mask ? (fls(mask) - 1) : 0; 1005 1006 switch (type) { 1007 case SMU_SCLK: 1008 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1009 if (soft_max_level >= single_dpm_table->count) { 1010 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 1011 soft_max_level, single_dpm_table->count - 1); 1012 ret = -EINVAL; 1013 break; 1014 } 1015 1016 ret = aldebaran_upload_dpm_level(smu, 1017 false, 1018 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1019 soft_min_level); 1020 if (ret) { 1021 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1022 break; 1023 } 1024 1025 ret = aldebaran_upload_dpm_level(smu, 1026 true, 1027 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1028 soft_max_level); 1029 if (ret) 1030 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1031 1032 break; 1033 1034 case SMU_MCLK: 1035 case SMU_SOCCLK: 1036 case SMU_FCLK: 1037 /* 1038 * Should not arrive here since aldebaran does not 1039 * support mclk/socclk/fclk softmin/softmax settings 1040 */ 1041 ret = -EINVAL; 1042 break; 1043 1044 default: 1045 break; 1046 } 1047 1048 return ret; 1049 } 1050 1051 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 1052 struct smu_temperature_range *range) 1053 { 1054 struct smu_table_context *table_context = &smu->smu_table; 1055 struct smu_13_0_powerplay_table *powerplay_table = 1056 table_context->power_play_table; 1057 PPTable_t *pptable = smu->smu_table.driver_pptable; 1058 1059 if (!range) 1060 return -EINVAL; 1061 1062 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1063 1064 range->hotspot_crit_max = pptable->ThotspotLimit * 1065 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1066 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1067 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1068 range->mem_crit_max = pptable->TmemLimit * 1069 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1070 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1071 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1072 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1073 1074 return 0; 1075 } 1076 1077 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 1078 enum amd_pp_sensors sensor, 1079 uint32_t *value) 1080 { 1081 int ret = 0; 1082 1083 if (!value) 1084 return -EINVAL; 1085 1086 switch (sensor) { 1087 case AMDGPU_PP_SENSOR_GPU_LOAD: 1088 ret = aldebaran_get_smu_metrics_data(smu, 1089 METRICS_AVERAGE_GFXACTIVITY, 1090 value); 1091 break; 1092 case AMDGPU_PP_SENSOR_MEM_LOAD: 1093 ret = aldebaran_get_smu_metrics_data(smu, 1094 METRICS_AVERAGE_MEMACTIVITY, 1095 value); 1096 break; 1097 default: 1098 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 1099 return -EINVAL; 1100 } 1101 1102 return ret; 1103 } 1104 1105 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value) 1106 { 1107 if (!value) 1108 return -EINVAL; 1109 1110 return aldebaran_get_smu_metrics_data(smu, 1111 METRICS_AVERAGE_SOCKETPOWER, 1112 value); 1113 } 1114 1115 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 1116 enum amd_pp_sensors sensor, 1117 uint32_t *value) 1118 { 1119 int ret = 0; 1120 1121 if (!value) 1122 return -EINVAL; 1123 1124 switch (sensor) { 1125 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1126 ret = aldebaran_get_smu_metrics_data(smu, 1127 METRICS_TEMPERATURE_HOTSPOT, 1128 value); 1129 break; 1130 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1131 ret = aldebaran_get_smu_metrics_data(smu, 1132 METRICS_TEMPERATURE_EDGE, 1133 value); 1134 break; 1135 case AMDGPU_PP_SENSOR_MEM_TEMP: 1136 ret = aldebaran_get_smu_metrics_data(smu, 1137 METRICS_TEMPERATURE_MEM, 1138 value); 1139 break; 1140 default: 1141 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1142 return -EINVAL; 1143 } 1144 1145 return ret; 1146 } 1147 1148 static int aldebaran_read_sensor(struct smu_context *smu, 1149 enum amd_pp_sensors sensor, 1150 void *data, uint32_t *size) 1151 { 1152 int ret = 0; 1153 1154 if (amdgpu_ras_intr_triggered()) 1155 return 0; 1156 1157 if (!data || !size) 1158 return -EINVAL; 1159 1160 mutex_lock(&smu->sensor_lock); 1161 switch (sensor) { 1162 case AMDGPU_PP_SENSOR_MEM_LOAD: 1163 case AMDGPU_PP_SENSOR_GPU_LOAD: 1164 ret = aldebaran_get_current_activity_percent(smu, 1165 sensor, 1166 (uint32_t *)data); 1167 *size = 4; 1168 break; 1169 case AMDGPU_PP_SENSOR_GPU_POWER: 1170 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data); 1171 *size = 4; 1172 break; 1173 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1174 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1175 case AMDGPU_PP_SENSOR_MEM_TEMP: 1176 ret = aldebaran_thermal_get_temperature(smu, sensor, 1177 (uint32_t *)data); 1178 *size = 4; 1179 break; 1180 case AMDGPU_PP_SENSOR_GFX_MCLK: 1181 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1182 /* the output clock frequency in 10K unit */ 1183 *(uint32_t *)data *= 100; 1184 *size = 4; 1185 break; 1186 case AMDGPU_PP_SENSOR_GFX_SCLK: 1187 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1188 *(uint32_t *)data *= 100; 1189 *size = 4; 1190 break; 1191 case AMDGPU_PP_SENSOR_VDDGFX: 1192 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1193 *size = 4; 1194 break; 1195 default: 1196 ret = -EOPNOTSUPP; 1197 break; 1198 } 1199 mutex_unlock(&smu->sensor_lock); 1200 1201 return ret; 1202 } 1203 1204 static int aldebaran_get_power_limit(struct smu_context *smu, 1205 uint32_t *current_power_limit, 1206 uint32_t *default_power_limit, 1207 uint32_t *max_power_limit) 1208 { 1209 PPTable_t *pptable = smu->smu_table.driver_pptable; 1210 uint32_t power_limit = 0; 1211 int ret; 1212 1213 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1214 if (current_power_limit) 1215 *current_power_limit = 0; 1216 if (default_power_limit) 1217 *default_power_limit = 0; 1218 if (max_power_limit) 1219 *max_power_limit = 0; 1220 1221 dev_warn(smu->adev->dev, 1222 "PPT feature is not enabled, power values can't be fetched."); 1223 1224 return 0; 1225 } 1226 1227 /* Valid power data is available only from primary die. 1228 * For secondary die show the value as 0. 1229 */ 1230 if (aldebaran_is_primary(smu)) { 1231 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, 1232 &power_limit); 1233 1234 if (ret) { 1235 /* the last hope to figure out the ppt limit */ 1236 if (!pptable) { 1237 dev_err(smu->adev->dev, 1238 "Cannot get PPT limit due to pptable missing!"); 1239 return -EINVAL; 1240 } 1241 power_limit = pptable->PptLimit; 1242 } 1243 } 1244 1245 if (current_power_limit) 1246 *current_power_limit = power_limit; 1247 if (default_power_limit) 1248 *default_power_limit = power_limit; 1249 1250 if (max_power_limit) { 1251 if (pptable) 1252 *max_power_limit = pptable->PptLimit; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static int aldebaran_set_power_limit(struct smu_context *smu, 1259 enum smu_ppt_limit_type limit_type, 1260 uint32_t limit) 1261 { 1262 /* Power limit can be set only through primary die */ 1263 if (aldebaran_is_primary(smu)) 1264 return smu_v13_0_set_power_limit(smu, limit_type, limit); 1265 1266 return -EINVAL; 1267 } 1268 1269 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1270 { 1271 int ret; 1272 1273 ret = smu_v13_0_system_features_control(smu, enable); 1274 if (!ret && enable) 1275 ret = aldebaran_run_btc(smu); 1276 1277 return ret; 1278 } 1279 1280 static int aldebaran_set_performance_level(struct smu_context *smu, 1281 enum amd_dpm_forced_level level) 1282 { 1283 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1284 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1285 struct smu_13_0_dpm_table *gfx_table = 1286 &dpm_context->dpm_tables.gfx_table; 1287 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1288 1289 /* Disable determinism if switching to another mode */ 1290 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && 1291 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { 1292 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1293 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 1294 } 1295 1296 switch (level) { 1297 1298 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1299 return 0; 1300 1301 case AMD_DPM_FORCED_LEVEL_HIGH: 1302 case AMD_DPM_FORCED_LEVEL_LOW: 1303 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1304 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1305 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1306 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1307 default: 1308 break; 1309 } 1310 1311 return smu_v13_0_set_performance_level(smu, level); 1312 } 1313 1314 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1315 enum smu_clk_type clk_type, 1316 uint32_t min, 1317 uint32_t max) 1318 { 1319 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1320 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1321 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1322 struct amdgpu_device *adev = smu->adev; 1323 uint32_t min_clk; 1324 uint32_t max_clk; 1325 int ret = 0; 1326 1327 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1328 return -EINVAL; 1329 1330 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1331 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1332 return -EINVAL; 1333 1334 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1335 if (min >= max) { 1336 dev_err(smu->adev->dev, 1337 "Minimum GFX clk should be less than the maximum allowed clock\n"); 1338 return -EINVAL; 1339 } 1340 1341 if ((min == pstate_table->gfxclk_pstate.curr.min) && 1342 (max == pstate_table->gfxclk_pstate.curr.max)) 1343 return 0; 1344 1345 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, 1346 min, max); 1347 if (!ret) { 1348 pstate_table->gfxclk_pstate.curr.min = min; 1349 pstate_table->gfxclk_pstate.curr.max = max; 1350 } 1351 1352 return ret; 1353 } 1354 1355 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1356 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1357 (max > dpm_context->dpm_tables.gfx_table.max)) { 1358 dev_warn(adev->dev, 1359 "Invalid max frequency %d MHz specified for determinism\n", max); 1360 return -EINVAL; 1361 } 1362 1363 /* Restore default min/max clocks and enable determinism */ 1364 min_clk = dpm_context->dpm_tables.gfx_table.min; 1365 max_clk = dpm_context->dpm_tables.gfx_table.max; 1366 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1367 if (!ret) { 1368 usleep_range(500, 1000); 1369 ret = smu_cmn_send_smc_msg_with_param(smu, 1370 SMU_MSG_EnableDeterminism, 1371 max, NULL); 1372 if (ret) { 1373 dev_err(adev->dev, 1374 "Failed to enable determinism at GFX clock %d MHz\n", max); 1375 } else { 1376 pstate_table->gfxclk_pstate.curr.min = min_clk; 1377 pstate_table->gfxclk_pstate.curr.max = max; 1378 } 1379 } 1380 } 1381 1382 return ret; 1383 } 1384 1385 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1386 long input[], uint32_t size) 1387 { 1388 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1389 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1390 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1391 uint32_t min_clk; 1392 uint32_t max_clk; 1393 int ret = 0; 1394 1395 /* Only allowed in manual or determinism mode */ 1396 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1397 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1398 return -EINVAL; 1399 1400 switch (type) { 1401 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1402 if (size != 2) { 1403 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1404 return -EINVAL; 1405 } 1406 1407 if (input[0] == 0) { 1408 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1409 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1410 input[1], dpm_context->dpm_tables.gfx_table.min); 1411 pstate_table->gfxclk_pstate.custom.min = 1412 pstate_table->gfxclk_pstate.curr.min; 1413 return -EINVAL; 1414 } 1415 1416 pstate_table->gfxclk_pstate.custom.min = input[1]; 1417 } else if (input[0] == 1) { 1418 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1419 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1420 input[1], dpm_context->dpm_tables.gfx_table.max); 1421 pstate_table->gfxclk_pstate.custom.max = 1422 pstate_table->gfxclk_pstate.curr.max; 1423 return -EINVAL; 1424 } 1425 1426 pstate_table->gfxclk_pstate.custom.max = input[1]; 1427 } else { 1428 return -EINVAL; 1429 } 1430 break; 1431 case PP_OD_RESTORE_DEFAULT_TABLE: 1432 if (size != 0) { 1433 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1434 return -EINVAL; 1435 } else { 1436 /* Use the default frequencies for manual and determinism mode */ 1437 min_clk = dpm_context->dpm_tables.gfx_table.min; 1438 max_clk = dpm_context->dpm_tables.gfx_table.max; 1439 1440 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1441 } 1442 break; 1443 case PP_OD_COMMIT_DPM_TABLE: 1444 if (size != 0) { 1445 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1446 return -EINVAL; 1447 } else { 1448 if (!pstate_table->gfxclk_pstate.custom.min) 1449 pstate_table->gfxclk_pstate.custom.min = 1450 pstate_table->gfxclk_pstate.curr.min; 1451 1452 if (!pstate_table->gfxclk_pstate.custom.max) 1453 pstate_table->gfxclk_pstate.custom.max = 1454 pstate_table->gfxclk_pstate.curr.max; 1455 1456 min_clk = pstate_table->gfxclk_pstate.custom.min; 1457 max_clk = pstate_table->gfxclk_pstate.custom.max; 1458 1459 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1460 } 1461 break; 1462 default: 1463 return -ENOSYS; 1464 } 1465 1466 return ret; 1467 } 1468 1469 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1470 { 1471 int ret; 1472 uint32_t feature_mask[2]; 1473 unsigned long feature_enabled; 1474 1475 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1476 if (ret) 1477 return false; 1478 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 1479 ((uint64_t)feature_mask[1] << 32)); 1480 return !!(feature_enabled & SMC_DPM_FEATURE); 1481 } 1482 1483 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1484 struct i2c_msg *msg, int num_msgs) 1485 { 1486 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 1487 struct smu_table_context *smu_table = &adev->smu.smu_table; 1488 struct smu_table *table = &smu_table->driver_table; 1489 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1490 int i, j, r, c; 1491 u16 dir; 1492 1493 req = kzalloc(sizeof(*req), GFP_KERNEL); 1494 if (!req) 1495 return -ENOMEM; 1496 1497 req->I2CcontrollerPort = 0; 1498 req->I2CSpeed = I2C_SPEED_FAST_400K; 1499 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1500 dir = msg[0].flags & I2C_M_RD; 1501 1502 for (c = i = 0; i < num_msgs; i++) { 1503 for (j = 0; j < msg[i].len; j++, c++) { 1504 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1505 1506 if (!(msg[i].flags & I2C_M_RD)) { 1507 /* write */ 1508 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1509 cmd->ReadWriteData = msg[i].buf[j]; 1510 } 1511 1512 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1513 /* The direction changes. 1514 */ 1515 dir = msg[i].flags & I2C_M_RD; 1516 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1517 } 1518 1519 req->NumCmds++; 1520 1521 /* 1522 * Insert STOP if we are at the last byte of either last 1523 * message for the transaction or the client explicitly 1524 * requires a STOP at this particular message. 1525 */ 1526 if ((j == msg[i].len - 1) && 1527 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1528 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1529 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1530 } 1531 } 1532 } 1533 mutex_lock(&adev->smu.mutex); 1534 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1535 mutex_unlock(&adev->smu.mutex); 1536 if (r) 1537 goto fail; 1538 1539 for (c = i = 0; i < num_msgs; i++) { 1540 if (!(msg[i].flags & I2C_M_RD)) { 1541 c += msg[i].len; 1542 continue; 1543 } 1544 for (j = 0; j < msg[i].len; j++, c++) { 1545 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1546 1547 msg[i].buf[j] = cmd->ReadWriteData; 1548 } 1549 } 1550 r = num_msgs; 1551 fail: 1552 kfree(req); 1553 return r; 1554 } 1555 1556 static u32 aldebaran_i2c_func(struct i2c_adapter *adap) 1557 { 1558 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1559 } 1560 1561 1562 static const struct i2c_algorithm aldebaran_i2c_algo = { 1563 .master_xfer = aldebaran_i2c_xfer, 1564 .functionality = aldebaran_i2c_func, 1565 }; 1566 1567 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = { 1568 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1569 .max_read_len = MAX_SW_I2C_COMMANDS, 1570 .max_write_len = MAX_SW_I2C_COMMANDS, 1571 .max_comb_1st_msg_len = 2, 1572 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1573 }; 1574 1575 static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 1576 { 1577 struct amdgpu_device *adev = to_amdgpu_device(control); 1578 int res; 1579 1580 control->owner = THIS_MODULE; 1581 control->class = I2C_CLASS_SPD; 1582 control->dev.parent = &adev->pdev->dev; 1583 control->algo = &aldebaran_i2c_algo; 1584 snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 1585 control->quirks = &aldebaran_i2c_control_quirks; 1586 1587 res = i2c_add_adapter(control); 1588 if (res) 1589 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1590 1591 return res; 1592 } 1593 1594 static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 1595 { 1596 i2c_del_adapter(control); 1597 } 1598 1599 static void aldebaran_get_unique_id(struct smu_context *smu) 1600 { 1601 struct amdgpu_device *adev = smu->adev; 1602 SmuMetrics_t *metrics = smu->smu_table.metrics_table; 1603 uint32_t upper32 = 0, lower32 = 0; 1604 int ret; 1605 1606 mutex_lock(&smu->metrics_lock); 1607 ret = smu_cmn_get_metrics_table_locked(smu, NULL, false); 1608 if (ret) 1609 goto out_unlock; 1610 1611 upper32 = metrics->PublicSerialNumUpper32; 1612 lower32 = metrics->PublicSerialNumLower32; 1613 1614 out_unlock: 1615 mutex_unlock(&smu->metrics_lock); 1616 1617 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1618 sprintf(adev->serial, "%016llx", adev->unique_id); 1619 } 1620 1621 static bool aldebaran_is_baco_supported(struct smu_context *smu) 1622 { 1623 /* aldebaran is not support baco */ 1624 1625 return false; 1626 } 1627 1628 static int aldebaran_set_df_cstate(struct smu_context *smu, 1629 enum pp_df_cstate state) 1630 { 1631 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1632 } 1633 1634 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) 1635 { 1636 return smu_cmn_send_smc_msg_with_param(smu, 1637 SMU_MSG_GmiPwrDnControl, 1638 en ? 1 : 0, 1639 NULL); 1640 } 1641 1642 static const struct throttling_logging_label { 1643 uint32_t feature_mask; 1644 const char *label; 1645 } logging_label[] = { 1646 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1647 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1648 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1649 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1650 }; 1651 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1652 { 1653 int ret; 1654 int throttler_idx, throtting_events = 0, buf_idx = 0; 1655 struct amdgpu_device *adev = smu->adev; 1656 uint32_t throttler_status; 1657 char log_buf[256]; 1658 1659 ret = aldebaran_get_smu_metrics_data(smu, 1660 METRICS_THROTTLER_STATUS, 1661 &throttler_status); 1662 if (ret) 1663 return; 1664 1665 memset(log_buf, 0, sizeof(log_buf)); 1666 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1667 throttler_idx++) { 1668 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1669 throtting_events++; 1670 buf_idx += snprintf(log_buf + buf_idx, 1671 sizeof(log_buf) - buf_idx, 1672 "%s%s", 1673 throtting_events > 1 ? " and " : "", 1674 logging_label[throttler_idx].label); 1675 if (buf_idx >= sizeof(log_buf)) { 1676 dev_err(adev->dev, "buffer overflow!\n"); 1677 log_buf[sizeof(log_buf) - 1] = '\0'; 1678 break; 1679 } 1680 } 1681 } 1682 1683 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1684 log_buf); 1685 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 1686 smu_cmn_get_indep_throttler_status(throttler_status, 1687 aldebaran_throttler_map)); 1688 } 1689 1690 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1691 { 1692 struct amdgpu_device *adev = smu->adev; 1693 uint32_t esm_ctrl; 1694 1695 /* TODO: confirm this on real target */ 1696 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1697 if ((esm_ctrl >> 15) & 0x1FFFF) 1698 return (((esm_ctrl >> 8) & 0x3F) + 128); 1699 1700 return smu_v13_0_get_current_pcie_link_speed(smu); 1701 } 1702 1703 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1704 void **table) 1705 { 1706 struct smu_table_context *smu_table = &smu->smu_table; 1707 struct gpu_metrics_v1_3 *gpu_metrics = 1708 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1709 SmuMetrics_t metrics; 1710 int i, ret = 0; 1711 1712 ret = smu_cmn_get_metrics_table(smu, 1713 &metrics, 1714 true); 1715 if (ret) 1716 return ret; 1717 1718 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1719 1720 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1721 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1722 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1723 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1724 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1725 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1726 1727 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1728 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1729 gpu_metrics->average_mm_activity = 0; 1730 1731 /* Valid power data is available only from primary die */ 1732 if (aldebaran_is_primary(smu)) { 1733 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1734 gpu_metrics->energy_accumulator = 1735 (uint64_t)metrics.EnergyAcc64bitHigh << 32 | 1736 metrics.EnergyAcc64bitLow; 1737 } else { 1738 gpu_metrics->average_socket_power = 0; 1739 gpu_metrics->energy_accumulator = 0; 1740 } 1741 1742 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1743 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1744 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1745 gpu_metrics->average_vclk0_frequency = 0; 1746 gpu_metrics->average_dclk0_frequency = 0; 1747 1748 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1749 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1750 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1751 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1752 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1753 1754 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1755 gpu_metrics->indep_throttle_status = 1756 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1757 aldebaran_throttler_map); 1758 1759 gpu_metrics->current_fan_speed = 0; 1760 1761 gpu_metrics->pcie_link_width = 1762 smu_v13_0_get_current_pcie_link_width(smu); 1763 gpu_metrics->pcie_link_speed = 1764 aldebaran_get_current_pcie_link_speed(smu); 1765 1766 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1767 1768 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1769 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1770 1771 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1772 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1773 1774 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) | 1775 metrics.TimeStampLow; 1776 1777 *table = (void *)gpu_metrics; 1778 1779 return sizeof(struct gpu_metrics_v1_3); 1780 } 1781 1782 static int aldebaran_check_ecc_table_support(struct smu_context *smu) 1783 { 1784 uint32_t if_version = 0xff, smu_version = 0xff; 1785 int ret = 0; 1786 1787 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 1788 if (ret) { 1789 /* return not support if failed get smu_version */ 1790 ret = -EOPNOTSUPP; 1791 } 1792 1793 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) 1794 ret = -EOPNOTSUPP; 1795 1796 return ret; 1797 } 1798 1799 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, 1800 void *table) 1801 { 1802 struct smu_table_context *smu_table = &smu->smu_table; 1803 EccInfoTable_t *ecc_table = NULL; 1804 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 1805 int i, ret = 0; 1806 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 1807 1808 ret = aldebaran_check_ecc_table_support(smu); 1809 if (ret) 1810 return ret; 1811 1812 ret = smu_cmn_update_table(smu, 1813 SMU_TABLE_ECCINFO, 1814 0, 1815 smu_table->ecc_table, 1816 false); 1817 if (ret) { 1818 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 1819 return ret; 1820 } 1821 1822 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 1823 1824 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1825 ecc_info_per_channel = &(eccinfo->ecc[i]); 1826 ecc_info_per_channel->ce_count_lo_chip = 1827 ecc_table->EccInfo[i].ce_count_lo_chip; 1828 ecc_info_per_channel->ce_count_hi_chip = 1829 ecc_table->EccInfo[i].ce_count_hi_chip; 1830 ecc_info_per_channel->mca_umc_status = 1831 ecc_table->EccInfo[i].mca_umc_status; 1832 ecc_info_per_channel->mca_umc_addr = 1833 ecc_table->EccInfo[i].mca_umc_addr; 1834 } 1835 1836 return ret; 1837 } 1838 1839 static int aldebaran_mode1_reset(struct smu_context *smu) 1840 { 1841 u32 smu_version, fatal_err, param; 1842 int ret = 0; 1843 struct amdgpu_device *adev = smu->adev; 1844 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1845 1846 fatal_err = 0; 1847 param = SMU_RESET_MODE_1; 1848 1849 /* 1850 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 1851 */ 1852 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1853 if (smu_version < 0x00440700) { 1854 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1855 } 1856 else { 1857 /* fatal error triggered by ras, PMFW supports the flag 1858 from 68.44.0 */ 1859 if ((smu_version >= 0x00442c00) && ras && 1860 atomic_read(&ras->in_recovery)) 1861 fatal_err = 1; 1862 1863 param |= (fatal_err << 16); 1864 ret = smu_cmn_send_smc_msg_with_param(smu, 1865 SMU_MSG_GfxDeviceDriverReset, param, NULL); 1866 } 1867 1868 if (!ret) 1869 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 1870 1871 return ret; 1872 } 1873 1874 static int aldebaran_mode2_reset(struct smu_context *smu) 1875 { 1876 u32 smu_version; 1877 int ret = 0, index; 1878 struct amdgpu_device *adev = smu->adev; 1879 int timeout = 10; 1880 1881 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1882 1883 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1884 SMU_MSG_GfxDeviceDriverReset); 1885 1886 mutex_lock(&smu->message_lock); 1887 if (smu_version >= 0x00441400) { 1888 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1889 /* This is similar to FLR, wait till max FLR timeout */ 1890 msleep(100); 1891 dev_dbg(smu->adev->dev, "restore config space...\n"); 1892 /* Restore the config space saved during init */ 1893 amdgpu_device_load_pci_state(adev->pdev); 1894 1895 dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1896 while (ret == -ETIME && timeout) { 1897 ret = smu_cmn_wait_for_response(smu); 1898 /* Wait a bit more time for getting ACK */ 1899 if (ret == -ETIME) { 1900 --timeout; 1901 usleep_range(500, 1000); 1902 continue; 1903 } 1904 1905 if (ret != 1) { 1906 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n", 1907 SMU_RESET_MODE_2, ret); 1908 goto out; 1909 } 1910 } 1911 1912 } else { 1913 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", 1914 smu_version); 1915 } 1916 1917 if (ret == 1) 1918 ret = 0; 1919 out: 1920 mutex_unlock(&smu->message_lock); 1921 1922 return ret; 1923 } 1924 1925 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1926 { 1927 #if 0 1928 struct amdgpu_device *adev = smu->adev; 1929 u32 smu_version; 1930 uint32_t val; 1931 /** 1932 * PM FW version support mode1 reset from 68.07 1933 */ 1934 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1935 if ((smu_version < 0x00440700)) 1936 return false; 1937 /** 1938 * mode1 reset relies on PSP, so we should check if 1939 * PSP is alive. 1940 */ 1941 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1942 1943 return val != 0x0; 1944 #endif 1945 return true; 1946 } 1947 1948 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 1949 { 1950 return true; 1951 } 1952 1953 static int aldebaran_set_mp1_state(struct smu_context *smu, 1954 enum pp_mp1_state mp1_state) 1955 { 1956 switch (mp1_state) { 1957 case PP_MP1_STATE_UNLOAD: 1958 return smu_cmn_set_mp1_state(smu, mp1_state); 1959 default: 1960 return 0; 1961 } 1962 } 1963 1964 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, 1965 uint32_t size) 1966 { 1967 int ret = 0; 1968 1969 /* message SMU to update the bad page number on SMUBUS */ 1970 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL); 1971 if (ret) 1972 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n", 1973 __func__); 1974 1975 return ret; 1976 } 1977 1978 static const struct pptable_funcs aldebaran_ppt_funcs = { 1979 /* init dpm */ 1980 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 1981 /* dpm/clk tables */ 1982 .set_default_dpm_table = aldebaran_set_default_dpm_table, 1983 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 1984 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 1985 .print_clk_levels = aldebaran_print_clk_levels, 1986 .force_clk_levels = aldebaran_force_clk_levels, 1987 .read_sensor = aldebaran_read_sensor, 1988 .set_performance_level = aldebaran_set_performance_level, 1989 .get_power_limit = aldebaran_get_power_limit, 1990 .is_dpm_running = aldebaran_is_dpm_running, 1991 .get_unique_id = aldebaran_get_unique_id, 1992 .init_microcode = smu_v13_0_init_microcode, 1993 .load_microcode = smu_v13_0_load_microcode, 1994 .fini_microcode = smu_v13_0_fini_microcode, 1995 .init_smc_tables = aldebaran_init_smc_tables, 1996 .fini_smc_tables = smu_v13_0_fini_smc_tables, 1997 .init_power = smu_v13_0_init_power, 1998 .fini_power = smu_v13_0_fini_power, 1999 .check_fw_status = smu_v13_0_check_fw_status, 2000 /* pptable related */ 2001 .setup_pptable = aldebaran_setup_pptable, 2002 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 2003 .check_fw_version = smu_v13_0_check_fw_version, 2004 .write_pptable = smu_cmn_write_pptable, 2005 .set_driver_table_location = smu_v13_0_set_driver_table_location, 2006 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2007 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2008 .system_features_control = aldebaran_system_features_control, 2009 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2010 .send_smc_msg = smu_cmn_send_smc_msg, 2011 .get_enabled_mask = smu_cmn_get_enabled_mask, 2012 .feature_is_enabled = smu_cmn_feature_is_enabled, 2013 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2014 .set_power_limit = aldebaran_set_power_limit, 2015 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 2016 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2017 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2018 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 2019 .register_irq_handler = smu_v13_0_register_irq_handler, 2020 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 2021 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 2022 .baco_is_support= aldebaran_is_baco_supported, 2023 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 2024 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 2025 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 2026 .set_df_cstate = aldebaran_set_df_cstate, 2027 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down, 2028 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 2029 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2030 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2031 .get_gpu_metrics = aldebaran_get_gpu_metrics, 2032 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 2033 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 2034 .mode1_reset = aldebaran_mode1_reset, 2035 .set_mp1_state = aldebaran_set_mp1_state, 2036 .mode2_reset = aldebaran_mode2_reset, 2037 .wait_for_event = smu_v13_0_wait_for_event, 2038 .i2c_init = aldebaran_i2c_control_init, 2039 .i2c_fini = aldebaran_i2c_control_fini, 2040 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num, 2041 .get_ecc_info = aldebaran_get_ecc_info, 2042 }; 2043 2044 void aldebaran_set_ppt_funcs(struct smu_context *smu) 2045 { 2046 smu->ppt_funcs = &aldebaran_ppt_funcs; 2047 smu->message_map = aldebaran_message_map; 2048 smu->clock_map = aldebaran_clk_map; 2049 smu->feature_map = aldebaran_feature_mask_map; 2050 smu->table_map = aldebaran_table_map; 2051 } 2052