1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_smu.h" 29 #include "atomfirmware.h" 30 #include "amdgpu_atomfirmware.h" 31 #include "amdgpu_atombios.h" 32 #include "smu_v13_0.h" 33 #include "smu13_driver_if_aldebaran.h" 34 #include "soc15_common.h" 35 #include "atom.h" 36 #include "power_state.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 63 [smu_feature] = {1, (aldebaran_feature)} 64 65 #define FEATURE_MASK(feature) (1ULL << feature) 66 #define SMC_DPM_FEATURE ( \ 67 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 68 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 73 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 74 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 75 76 /* possible frequency drift (1Mhz) */ 77 #define EPSILON 1 78 79 #define smnPCIE_ESM_CTRL 0x111003D0 80 81 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 82 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 83 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 84 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 85 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 86 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0), 88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0), 89 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 90 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 91 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 92 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 93 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 94 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 95 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 96 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 97 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 98 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 99 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 100 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 101 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 102 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 103 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 104 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 105 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 106 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 107 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 108 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 109 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 110 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 111 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 112 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 113 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 114 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 115 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 116 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 117 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 118 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 119 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 120 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 121 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 122 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 123 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 124 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 125 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 126 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 127 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 128 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 129 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 130 }; 131 132 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 133 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 134 CLK_MAP(SCLK, PPCLK_GFXCLK), 135 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 136 CLK_MAP(FCLK, PPCLK_FCLK), 137 CLK_MAP(UCLK, PPCLK_UCLK), 138 CLK_MAP(MCLK, PPCLK_UCLK), 139 CLK_MAP(DCLK, PPCLK_DCLK), 140 CLK_MAP(VCLK, PPCLK_VCLK), 141 CLK_MAP(LCLK, PPCLK_LCLK), 142 }; 143 144 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 145 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_PREFETCHER_BIT, FEATURE_DATA_CALCULATIONS), 146 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 147 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 148 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 149 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 150 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 151 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 152 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 153 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 154 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 155 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 156 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 157 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 158 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT), 159 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 160 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 161 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 162 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 163 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 164 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 165 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 166 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 167 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 168 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 169 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 170 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 175 }; 176 177 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 178 TAB_MAP(PPTABLE), 179 TAB_MAP(AVFS_PSM_DEBUG), 180 TAB_MAP(AVFS_FUSE_OVERRIDE), 181 TAB_MAP(PMSTATUSLOG), 182 TAB_MAP(SMU_METRICS), 183 TAB_MAP(DRIVER_SMU_CONFIG), 184 TAB_MAP(I2C_COMMANDS), 185 }; 186 187 static int aldebaran_tables_init(struct smu_context *smu) 188 { 189 struct smu_table_context *smu_table = &smu->smu_table; 190 struct smu_table *tables = smu_table->tables; 191 192 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 193 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 194 195 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 196 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 197 198 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 199 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 200 201 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 202 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 203 204 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 205 if (!smu_table->metrics_table) 206 return -ENOMEM; 207 smu_table->metrics_time = 0; 208 209 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); 210 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 211 if (!smu_table->gpu_metrics_table) { 212 kfree(smu_table->metrics_table); 213 return -ENOMEM; 214 } 215 216 return 0; 217 } 218 219 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 220 { 221 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 222 223 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 224 GFP_KERNEL); 225 if (!smu_dpm->dpm_context) 226 return -ENOMEM; 227 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 228 229 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state), 230 GFP_KERNEL); 231 if (!smu_dpm->dpm_current_power_state) 232 return -ENOMEM; 233 234 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state), 235 GFP_KERNEL); 236 if (!smu_dpm->dpm_request_power_state) 237 return -ENOMEM; 238 239 return 0; 240 } 241 242 static int aldebaran_init_smc_tables(struct smu_context *smu) 243 { 244 int ret = 0; 245 246 ret = aldebaran_tables_init(smu); 247 if (ret) 248 return ret; 249 250 ret = aldebaran_allocate_dpm_context(smu); 251 if (ret) 252 return ret; 253 254 return smu_v13_0_init_smc_tables(smu); 255 } 256 257 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 258 uint32_t *feature_mask, uint32_t num) 259 { 260 if (num > 2) 261 return -EINVAL; 262 263 /* pptable will handle the features to enable */ 264 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 265 266 return 0; 267 } 268 269 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 270 { 271 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 272 struct smu_13_0_dpm_table *dpm_table = NULL; 273 PPTable_t *pptable = smu->smu_table.driver_pptable; 274 int ret = 0; 275 276 /* socclk dpm table setup */ 277 dpm_table = &dpm_context->dpm_tables.soc_table; 278 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 279 ret = smu_v13_0_set_single_dpm_table(smu, 280 SMU_SOCCLK, 281 dpm_table); 282 if (ret) 283 return ret; 284 } else { 285 dpm_table->count = 1; 286 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 287 dpm_table->dpm_levels[0].enabled = true; 288 dpm_table->min = dpm_table->dpm_levels[0].value; 289 dpm_table->max = dpm_table->dpm_levels[0].value; 290 } 291 292 /* gfxclk dpm table setup */ 293 dpm_table = &dpm_context->dpm_tables.gfx_table; 294 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 295 /* in the case of gfxclk, only fine-grained dpm is honored */ 296 dpm_table->count = 2; 297 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 298 dpm_table->dpm_levels[0].enabled = true; 299 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 300 dpm_table->dpm_levels[1].enabled = true; 301 dpm_table->min = dpm_table->dpm_levels[0].value; 302 dpm_table->max = dpm_table->dpm_levels[1].value; 303 } else { 304 dpm_table->count = 1; 305 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 306 dpm_table->dpm_levels[0].enabled = true; 307 dpm_table->min = dpm_table->dpm_levels[0].value; 308 dpm_table->max = dpm_table->dpm_levels[0].value; 309 } 310 311 /* memclk dpm table setup */ 312 dpm_table = &dpm_context->dpm_tables.uclk_table; 313 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 314 ret = smu_v13_0_set_single_dpm_table(smu, 315 SMU_UCLK, 316 dpm_table); 317 if (ret) 318 return ret; 319 } else { 320 dpm_table->count = 1; 321 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 322 dpm_table->dpm_levels[0].enabled = true; 323 dpm_table->min = dpm_table->dpm_levels[0].value; 324 dpm_table->max = dpm_table->dpm_levels[0].value; 325 } 326 327 /* fclk dpm table setup */ 328 dpm_table = &dpm_context->dpm_tables.fclk_table; 329 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 330 ret = smu_v13_0_set_single_dpm_table(smu, 331 SMU_FCLK, 332 dpm_table); 333 if (ret) 334 return ret; 335 } else { 336 dpm_table->count = 1; 337 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 338 dpm_table->dpm_levels[0].enabled = true; 339 dpm_table->min = dpm_table->dpm_levels[0].value; 340 dpm_table->max = dpm_table->dpm_levels[0].value; 341 } 342 343 return 0; 344 } 345 346 static int aldebaran_check_powerplay_table(struct smu_context *smu) 347 { 348 struct smu_table_context *table_context = &smu->smu_table; 349 struct smu_13_0_powerplay_table *powerplay_table = 350 table_context->power_play_table; 351 struct smu_baco_context *smu_baco = &smu->smu_baco; 352 353 mutex_lock(&smu_baco->mutex); 354 if (powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_BACO || 355 powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_MACO) 356 smu_baco->platform_support = true; 357 mutex_unlock(&smu_baco->mutex); 358 359 table_context->thermal_controller_type = 360 powerplay_table->thermal_controller_type; 361 362 return 0; 363 } 364 365 static int aldebaran_store_powerplay_table(struct smu_context *smu) 366 { 367 struct smu_table_context *table_context = &smu->smu_table; 368 struct smu_13_0_powerplay_table *powerplay_table = 369 table_context->power_play_table; 370 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 371 sizeof(PPTable_t)); 372 373 return 0; 374 } 375 376 static int aldebaran_append_powerplay_table(struct smu_context *smu) 377 { 378 struct smu_table_context *table_context = &smu->smu_table; 379 PPTable_t *smc_pptable = table_context->driver_pptable; 380 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 381 int index, ret; 382 383 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 384 smc_dpm_info); 385 386 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 387 (uint8_t **)&smc_dpm_table); 388 if (ret) 389 return ret; 390 391 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 392 smc_dpm_table->table_header.format_revision, 393 smc_dpm_table->table_header.content_revision); 394 395 if ((smc_dpm_table->table_header.format_revision == 4) && 396 (smc_dpm_table->table_header.content_revision == 10)) 397 memcpy(&smc_pptable->GfxMaxCurrent, 398 &smc_dpm_table->GfxMaxCurrent, 399 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_10, GfxMaxCurrent)); 400 return 0; 401 } 402 403 static int aldebaran_setup_pptable(struct smu_context *smu) 404 { 405 int ret = 0; 406 407 ret = smu_v13_0_setup_pptable(smu); 408 if (ret) 409 return ret; 410 411 ret = aldebaran_store_powerplay_table(smu); 412 if (ret) 413 return ret; 414 415 ret = aldebaran_append_powerplay_table(smu); 416 if (ret) 417 return ret; 418 419 ret = aldebaran_check_powerplay_table(smu); 420 if (ret) 421 return ret; 422 423 return ret; 424 } 425 426 static int aldebaran_run_btc(struct smu_context *smu) 427 { 428 int ret; 429 430 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 431 if (ret) 432 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 433 434 return ret; 435 } 436 437 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 438 { 439 struct smu_13_0_dpm_context *dpm_context = 440 smu->smu_dpm.dpm_context; 441 struct smu_13_0_dpm_table *gfx_table = 442 &dpm_context->dpm_tables.gfx_table; 443 struct smu_13_0_dpm_table *mem_table = 444 &dpm_context->dpm_tables.uclk_table; 445 struct smu_13_0_dpm_table *soc_table = 446 &dpm_context->dpm_tables.soc_table; 447 struct smu_umd_pstate_table *pstate_table = 448 &smu->pstate_table; 449 450 pstate_table->gfxclk_pstate.min = gfx_table->min; 451 pstate_table->gfxclk_pstate.peak = gfx_table->max; 452 453 pstate_table->uclk_pstate.min = mem_table->min; 454 pstate_table->uclk_pstate.peak = mem_table->max; 455 456 pstate_table->socclk_pstate.min = soc_table->min; 457 pstate_table->socclk_pstate.peak = soc_table->max; 458 459 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 460 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 461 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 462 pstate_table->gfxclk_pstate.standard = 463 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 464 pstate_table->uclk_pstate.standard = 465 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 466 pstate_table->socclk_pstate.standard = 467 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 468 } else { 469 pstate_table->gfxclk_pstate.standard = 470 pstate_table->gfxclk_pstate.min; 471 pstate_table->uclk_pstate.standard = 472 pstate_table->uclk_pstate.min; 473 pstate_table->socclk_pstate.standard = 474 pstate_table->socclk_pstate.min; 475 } 476 477 return 0; 478 } 479 480 static int aldebaran_get_clk_table(struct smu_context *smu, 481 struct pp_clock_levels_with_latency *clocks, 482 struct smu_13_0_dpm_table *dpm_table) 483 { 484 int i, count; 485 486 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 487 clocks->num_levels = count; 488 489 for (i = 0; i < count; i++) { 490 clocks->data[i].clocks_in_khz = 491 dpm_table->dpm_levels[i].value * 1000; 492 clocks->data[i].latency_in_us = 0; 493 } 494 495 return 0; 496 } 497 498 static int aldebaran_freqs_in_same_level(int32_t frequency1, 499 int32_t frequency2) 500 { 501 return (abs(frequency1 - frequency2) <= EPSILON); 502 } 503 504 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 505 MetricsMember_t member, 506 uint32_t *value) 507 { 508 struct smu_table_context *smu_table= &smu->smu_table; 509 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 510 int ret = 0; 511 512 mutex_lock(&smu->metrics_lock); 513 514 ret = smu_cmn_get_metrics_table_locked(smu, 515 NULL, 516 false); 517 if (ret) { 518 mutex_unlock(&smu->metrics_lock); 519 return ret; 520 } 521 522 switch (member) { 523 case METRICS_CURR_GFXCLK: 524 *value = metrics->CurrClock[PPCLK_GFXCLK]; 525 break; 526 case METRICS_CURR_SOCCLK: 527 *value = metrics->CurrClock[PPCLK_SOCCLK]; 528 break; 529 case METRICS_CURR_UCLK: 530 *value = metrics->CurrClock[PPCLK_UCLK]; 531 break; 532 case METRICS_CURR_VCLK: 533 *value = metrics->CurrClock[PPCLK_VCLK]; 534 break; 535 case METRICS_CURR_DCLK: 536 *value = metrics->CurrClock[PPCLK_DCLK]; 537 break; 538 case METRICS_CURR_FCLK: 539 *value = metrics->CurrClock[PPCLK_FCLK]; 540 break; 541 case METRICS_AVERAGE_GFXCLK: 542 *value = metrics->AverageGfxclkFrequency; 543 break; 544 case METRICS_AVERAGE_SOCCLK: 545 *value = metrics->AverageSocclkFrequency; 546 break; 547 case METRICS_AVERAGE_UCLK: 548 *value = metrics->AverageUclkFrequency; 549 break; 550 case METRICS_AVERAGE_GFXACTIVITY: 551 *value = metrics->AverageGfxActivity; 552 break; 553 case METRICS_AVERAGE_MEMACTIVITY: 554 *value = metrics->AverageUclkActivity; 555 break; 556 case METRICS_AVERAGE_SOCKETPOWER: 557 *value = metrics->AverageSocketPower << 8; 558 break; 559 case METRICS_TEMPERATURE_EDGE: 560 *value = metrics->TemperatureEdge * 561 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 562 break; 563 case METRICS_TEMPERATURE_HOTSPOT: 564 *value = metrics->TemperatureHotspot * 565 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 566 break; 567 case METRICS_TEMPERATURE_MEM: 568 *value = metrics->TemperatureHBM * 569 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 570 break; 571 case METRICS_TEMPERATURE_VRGFX: 572 *value = metrics->TemperatureVrGfx * 573 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 574 break; 575 case METRICS_TEMPERATURE_VRSOC: 576 *value = metrics->TemperatureVrSoc * 577 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 578 break; 579 case METRICS_TEMPERATURE_VRMEM: 580 *value = metrics->TemperatureVrMem * 581 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 582 break; 583 case METRICS_THROTTLER_STATUS: 584 *value = metrics->ThrottlerStatus; 585 break; 586 default: 587 *value = UINT_MAX; 588 break; 589 } 590 591 mutex_unlock(&smu->metrics_lock); 592 593 return ret; 594 } 595 596 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 597 enum smu_clk_type clk_type, 598 uint32_t *value) 599 { 600 MetricsMember_t member_type; 601 int clk_id = 0; 602 603 if (!value) 604 return -EINVAL; 605 606 clk_id = smu_cmn_to_asic_specific_index(smu, 607 CMN2ASIC_MAPPING_CLK, 608 clk_type); 609 if (clk_id < 0) 610 return -EINVAL; 611 612 switch (clk_id) { 613 case PPCLK_GFXCLK: 614 /* 615 * CurrClock[clk_id] can provide accurate 616 * output only when the dpm feature is enabled. 617 * We can use Average_* for dpm disabled case. 618 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 619 */ 620 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 621 member_type = METRICS_CURR_GFXCLK; 622 else 623 member_type = METRICS_AVERAGE_GFXCLK; 624 break; 625 case PPCLK_UCLK: 626 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 627 member_type = METRICS_CURR_UCLK; 628 else 629 member_type = METRICS_AVERAGE_UCLK; 630 break; 631 case PPCLK_SOCCLK: 632 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 633 member_type = METRICS_CURR_SOCCLK; 634 else 635 member_type = METRICS_AVERAGE_SOCCLK; 636 break; 637 case PPCLK_VCLK: 638 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 639 member_type = METRICS_CURR_VCLK; 640 else 641 member_type = METRICS_AVERAGE_VCLK; 642 break; 643 case PPCLK_DCLK: 644 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 645 member_type = METRICS_CURR_DCLK; 646 else 647 member_type = METRICS_AVERAGE_DCLK; 648 break; 649 case PPCLK_FCLK: 650 member_type = METRICS_CURR_FCLK; 651 break; 652 default: 653 return -EINVAL; 654 } 655 656 return aldebaran_get_smu_metrics_data(smu, 657 member_type, 658 value); 659 } 660 661 static int aldebaran_print_clk_levels(struct smu_context *smu, 662 enum smu_clk_type type, char *buf) 663 { 664 int i, now, size = 0; 665 int ret = 0; 666 struct pp_clock_levels_with_latency clocks; 667 struct smu_13_0_dpm_table *single_dpm_table; 668 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 669 struct smu_13_0_dpm_context *dpm_context = NULL; 670 uint32_t display_levels; 671 uint32_t freq_values[3] = {0}; 672 673 if (amdgpu_ras_intr_triggered()) 674 return snprintf(buf, PAGE_SIZE, "unavailable\n"); 675 676 dpm_context = smu_dpm->dpm_context; 677 678 switch (type) { 679 680 case SMU_OD_SCLK: 681 size = sprintf(buf, "%s:\n", "GFXCLK"); 682 fallthrough; 683 case SMU_SCLK: 684 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 685 if (ret) { 686 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 687 return ret; 688 } 689 690 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 691 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 692 if (ret) { 693 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 694 return ret; 695 } 696 697 display_levels = clocks.num_levels; 698 699 /* fine-grained dpm has only 2 levels */ 700 if (now > single_dpm_table->dpm_levels[0].value && 701 now < single_dpm_table->dpm_levels[1].value) { 702 display_levels = clocks.num_levels + 1; 703 freq_values[0] = single_dpm_table->dpm_levels[0].value; 704 freq_values[2] = single_dpm_table->dpm_levels[1].value; 705 freq_values[1] = now; 706 } 707 708 /* 709 * For DPM disabled case, there will be only one clock level. 710 * And it's safe to assume that is always the current clock. 711 */ 712 if (display_levels == clocks.num_levels) { 713 for (i = 0; i < clocks.num_levels; i++) 714 size += sprintf(buf + size, "%d: %uMhz %s\n", i, 715 clocks.data[i].clocks_in_khz / 1000, 716 (clocks.num_levels == 1) ? "*" : 717 (aldebaran_freqs_in_same_level( 718 clocks.data[i].clocks_in_khz / 1000, 719 now) ? "*" : "")); 720 } else { 721 for (i = 0; i < display_levels; i++) 722 size += sprintf(buf + size, "%d: %uMhz %s\n", i, 723 freq_values[i], i == 1 ? "*" : ""); 724 } 725 726 break; 727 728 case SMU_OD_MCLK: 729 size = sprintf(buf, "%s:\n", "MCLK"); 730 fallthrough; 731 case SMU_MCLK: 732 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 733 if (ret) { 734 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 735 return ret; 736 } 737 738 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 739 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 740 if (ret) { 741 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 742 return ret; 743 } 744 745 for (i = 0; i < clocks.num_levels; i++) 746 size += sprintf(buf + size, "%d: %uMhz %s\n", 747 i, clocks.data[i].clocks_in_khz / 1000, 748 (clocks.num_levels == 1) ? "*" : 749 (aldebaran_freqs_in_same_level( 750 clocks.data[i].clocks_in_khz / 1000, 751 now) ? "*" : "")); 752 break; 753 754 case SMU_SOCCLK: 755 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 756 if (ret) { 757 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 758 return ret; 759 } 760 761 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 762 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 763 if (ret) { 764 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 765 return ret; 766 } 767 768 for (i = 0; i < clocks.num_levels; i++) 769 size += sprintf(buf + size, "%d: %uMhz %s\n", 770 i, clocks.data[i].clocks_in_khz / 1000, 771 (clocks.num_levels == 1) ? "*" : 772 (aldebaran_freqs_in_same_level( 773 clocks.data[i].clocks_in_khz / 1000, 774 now) ? "*" : "")); 775 break; 776 777 case SMU_FCLK: 778 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 779 if (ret) { 780 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 781 return ret; 782 } 783 784 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 785 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 786 if (ret) { 787 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 788 return ret; 789 } 790 791 for (i = 0; i < single_dpm_table->count; i++) 792 size += sprintf(buf + size, "%d: %uMhz %s\n", 793 i, single_dpm_table->dpm_levels[i].value, 794 (clocks.num_levels == 1) ? "*" : 795 (aldebaran_freqs_in_same_level( 796 clocks.data[i].clocks_in_khz / 1000, 797 now) ? "*" : "")); 798 break; 799 800 default: 801 break; 802 } 803 804 return size; 805 } 806 807 static int aldebaran_upload_dpm_level(struct smu_context *smu, 808 bool max, 809 uint32_t feature_mask, 810 uint32_t level) 811 { 812 struct smu_13_0_dpm_context *dpm_context = 813 smu->smu_dpm.dpm_context; 814 uint32_t freq; 815 int ret = 0; 816 817 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 818 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 819 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 820 ret = smu_cmn_send_smc_msg_with_param(smu, 821 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 822 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 823 NULL); 824 if (ret) { 825 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 826 max ? "max" : "min"); 827 return ret; 828 } 829 } 830 831 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 832 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 833 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 834 ret = smu_cmn_send_smc_msg_with_param(smu, 835 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 836 (PPCLK_UCLK << 16) | (freq & 0xffff), 837 NULL); 838 if (ret) { 839 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 840 max ? "max" : "min"); 841 return ret; 842 } 843 } 844 845 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 846 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 847 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 848 ret = smu_cmn_send_smc_msg_with_param(smu, 849 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 850 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 851 NULL); 852 if (ret) { 853 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 854 max ? "max" : "min"); 855 return ret; 856 } 857 } 858 859 return ret; 860 } 861 862 static int aldebaran_force_clk_levels(struct smu_context *smu, 863 enum smu_clk_type type, uint32_t mask) 864 { 865 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 866 struct smu_13_0_dpm_table *single_dpm_table = NULL; 867 uint32_t soft_min_level, soft_max_level; 868 int ret = 0; 869 870 soft_min_level = mask ? (ffs(mask) - 1) : 0; 871 soft_max_level = mask ? (fls(mask) - 1) : 0; 872 873 switch (type) { 874 case SMU_SCLK: 875 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 876 if (soft_max_level >= single_dpm_table->count) { 877 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 878 soft_max_level, single_dpm_table->count - 1); 879 ret = -EINVAL; 880 break; 881 } 882 883 ret = aldebaran_upload_dpm_level(smu, 884 false, 885 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 886 soft_min_level); 887 if (ret) { 888 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 889 break; 890 } 891 892 ret = aldebaran_upload_dpm_level(smu, 893 true, 894 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 895 soft_max_level); 896 if (ret) 897 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 898 899 break; 900 901 case SMU_MCLK: 902 case SMU_SOCCLK: 903 case SMU_FCLK: 904 /* 905 * Should not arrive here since aldebaran does not 906 * support mclk/socclk/fclk softmin/softmax settings 907 */ 908 ret = -EINVAL; 909 break; 910 911 default: 912 break; 913 } 914 915 return ret; 916 } 917 918 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 919 struct smu_temperature_range *range) 920 { 921 struct smu_table_context *table_context = &smu->smu_table; 922 struct smu_13_0_powerplay_table *powerplay_table = 923 table_context->power_play_table; 924 PPTable_t *pptable = smu->smu_table.driver_pptable; 925 926 if (!range) 927 return -EINVAL; 928 929 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 930 931 range->hotspot_crit_max = pptable->ThotspotLimit * 932 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 933 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 934 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 935 range->mem_crit_max = pptable->TmemLimit * 936 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 937 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 938 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 939 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 940 941 return 0; 942 } 943 944 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 945 enum amd_pp_sensors sensor, 946 uint32_t *value) 947 { 948 int ret = 0; 949 950 if (!value) 951 return -EINVAL; 952 953 switch (sensor) { 954 case AMDGPU_PP_SENSOR_GPU_LOAD: 955 ret = aldebaran_get_smu_metrics_data(smu, 956 METRICS_AVERAGE_GFXACTIVITY, 957 value); 958 break; 959 case AMDGPU_PP_SENSOR_MEM_LOAD: 960 ret = aldebaran_get_smu_metrics_data(smu, 961 METRICS_AVERAGE_MEMACTIVITY, 962 value); 963 break; 964 default: 965 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 966 return -EINVAL; 967 } 968 969 return ret; 970 } 971 972 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value) 973 { 974 if (!value) 975 return -EINVAL; 976 977 return aldebaran_get_smu_metrics_data(smu, 978 METRICS_AVERAGE_SOCKETPOWER, 979 value); 980 } 981 982 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 983 enum amd_pp_sensors sensor, 984 uint32_t *value) 985 { 986 int ret = 0; 987 988 if (!value) 989 return -EINVAL; 990 991 switch (sensor) { 992 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 993 ret = aldebaran_get_smu_metrics_data(smu, 994 METRICS_TEMPERATURE_HOTSPOT, 995 value); 996 break; 997 case AMDGPU_PP_SENSOR_EDGE_TEMP: 998 ret = aldebaran_get_smu_metrics_data(smu, 999 METRICS_TEMPERATURE_EDGE, 1000 value); 1001 break; 1002 case AMDGPU_PP_SENSOR_MEM_TEMP: 1003 ret = aldebaran_get_smu_metrics_data(smu, 1004 METRICS_TEMPERATURE_MEM, 1005 value); 1006 break; 1007 default: 1008 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1009 return -EINVAL; 1010 } 1011 1012 return ret; 1013 } 1014 1015 static int aldebaran_read_sensor(struct smu_context *smu, 1016 enum amd_pp_sensors sensor, 1017 void *data, uint32_t *size) 1018 { 1019 int ret = 0; 1020 1021 if (amdgpu_ras_intr_triggered()) 1022 return 0; 1023 1024 if (!data || !size) 1025 return -EINVAL; 1026 1027 mutex_lock(&smu->sensor_lock); 1028 switch (sensor) { 1029 case AMDGPU_PP_SENSOR_MEM_LOAD: 1030 case AMDGPU_PP_SENSOR_GPU_LOAD: 1031 ret = aldebaran_get_current_activity_percent(smu, 1032 sensor, 1033 (uint32_t *)data); 1034 *size = 4; 1035 break; 1036 case AMDGPU_PP_SENSOR_GPU_POWER: 1037 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data); 1038 *size = 4; 1039 break; 1040 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1041 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1042 case AMDGPU_PP_SENSOR_MEM_TEMP: 1043 ret = aldebaran_thermal_get_temperature(smu, sensor, 1044 (uint32_t *)data); 1045 *size = 4; 1046 break; 1047 case AMDGPU_PP_SENSOR_GFX_MCLK: 1048 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1049 /* the output clock frequency in 10K unit */ 1050 *(uint32_t *)data *= 100; 1051 *size = 4; 1052 break; 1053 case AMDGPU_PP_SENSOR_GFX_SCLK: 1054 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1055 *(uint32_t *)data *= 100; 1056 *size = 4; 1057 break; 1058 case AMDGPU_PP_SENSOR_VDDGFX: 1059 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1060 *size = 4; 1061 break; 1062 default: 1063 ret = -EOPNOTSUPP; 1064 break; 1065 } 1066 mutex_unlock(&smu->sensor_lock); 1067 1068 return ret; 1069 } 1070 1071 static int aldebaran_get_power_limit(struct smu_context *smu) 1072 { 1073 PPTable_t *pptable = smu->smu_table.driver_pptable; 1074 uint32_t power_limit = 0; 1075 int ret; 1076 1077 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 1078 return -EINVAL; 1079 1080 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit); 1081 1082 if (ret) { 1083 /* the last hope to figure out the ppt limit */ 1084 if (!pptable) { 1085 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 1086 return -EINVAL; 1087 } 1088 power_limit = pptable->PptLimit; 1089 } 1090 1091 smu->current_power_limit = smu->default_power_limit = power_limit; 1092 if (pptable) 1093 smu->max_power_limit = pptable->PptLimit; 1094 1095 return 0; 1096 } 1097 1098 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1099 { 1100 int ret; 1101 1102 ret = smu_v13_0_system_features_control(smu, enable); 1103 if (!ret && enable) 1104 ret = aldebaran_run_btc(smu); 1105 1106 return ret; 1107 } 1108 1109 static int aldebaran_set_performance_level(struct smu_context *smu, 1110 enum amd_dpm_forced_level level) 1111 { 1112 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1113 1114 /* Disable determinism if switching to another mode */ 1115 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1116 && (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1117 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1118 1119 1120 switch (level) { 1121 1122 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1123 return 0; 1124 1125 case AMD_DPM_FORCED_LEVEL_HIGH: 1126 case AMD_DPM_FORCED_LEVEL_LOW: 1127 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1128 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1129 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1130 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1131 default: 1132 break; 1133 } 1134 1135 return smu_v13_0_set_performance_level(smu, level); 1136 } 1137 1138 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1139 enum smu_clk_type clk_type, 1140 uint32_t min, 1141 uint32_t max) 1142 { 1143 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1144 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1145 struct amdgpu_device *adev = smu->adev; 1146 uint32_t min_clk; 1147 uint32_t max_clk; 1148 int ret = 0; 1149 1150 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1151 return -EINVAL; 1152 1153 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1154 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1155 return -EINVAL; 1156 1157 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1158 min_clk = max(min, dpm_context->dpm_tables.gfx_table.min); 1159 max_clk = min(max, dpm_context->dpm_tables.gfx_table.max); 1160 return smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1161 } 1162 1163 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1164 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1165 (max > dpm_context->dpm_tables.gfx_table.max)) { 1166 dev_warn(adev->dev, 1167 "Invalid max frequency %d MHz specified for determinism\n", max); 1168 return -EINVAL; 1169 } 1170 1171 /* Restore default min/max clocks and enable determinism */ 1172 min_clk = dpm_context->dpm_tables.gfx_table.min; 1173 max_clk = dpm_context->dpm_tables.gfx_table.max; 1174 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1175 if (!ret) { 1176 usleep_range(500, 1000); 1177 ret = smu_cmn_send_smc_msg_with_param(smu, 1178 SMU_MSG_EnableDeterminism, 1179 max, NULL); 1180 if (ret) 1181 dev_err(adev->dev, 1182 "Failed to enable determinism at GFX clock %d MHz\n", max); 1183 } 1184 } 1185 1186 return ret; 1187 } 1188 1189 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1190 long input[], uint32_t size) 1191 { 1192 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1193 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1194 uint32_t min_clk; 1195 uint32_t max_clk; 1196 int ret = 0; 1197 1198 /* Only allowed in manual or determinism mode */ 1199 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1200 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1201 return -EINVAL; 1202 1203 switch (type) { 1204 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1205 if (size != 2) { 1206 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1207 return -EINVAL; 1208 } 1209 1210 if (input[0] == 0) { 1211 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1212 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1213 input[1], dpm_context->dpm_tables.gfx_table.min); 1214 return -EINVAL; 1215 } 1216 smu->gfx_actual_hard_min_freq = input[1]; 1217 } else if (input[0] == 1) { 1218 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1219 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1220 input[1], dpm_context->dpm_tables.gfx_table.max); 1221 return -EINVAL; 1222 } 1223 smu->gfx_actual_soft_max_freq = input[1]; 1224 } else { 1225 return -EINVAL; 1226 } 1227 break; 1228 case PP_OD_RESTORE_DEFAULT_TABLE: 1229 if (size != 0) { 1230 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1231 return -EINVAL; 1232 } else { 1233 /* Use the default frequencies for manual and determinism mode */ 1234 min_clk = dpm_context->dpm_tables.gfx_table.min; 1235 max_clk = dpm_context->dpm_tables.gfx_table.max; 1236 1237 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1238 } 1239 break; 1240 case PP_OD_COMMIT_DPM_TABLE: 1241 if (size != 0) { 1242 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1243 return -EINVAL; 1244 } else { 1245 min_clk = smu->gfx_actual_hard_min_freq; 1246 max_clk = smu->gfx_actual_soft_max_freq; 1247 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1248 } 1249 break; 1250 default: 1251 return -ENOSYS; 1252 } 1253 1254 return ret; 1255 } 1256 1257 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1258 { 1259 int ret = 0; 1260 uint32_t feature_mask[2]; 1261 unsigned long feature_enabled; 1262 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1263 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 1264 ((uint64_t)feature_mask[1] << 32)); 1265 return !!(feature_enabled & SMC_DPM_FEATURE); 1266 } 1267 1268 static void aldebaran_get_unique_id(struct smu_context *smu) 1269 { 1270 struct amdgpu_device *adev = smu->adev; 1271 SmuMetrics_t *metrics = smu->smu_table.metrics_table; 1272 uint32_t upper32 = 0, lower32 = 0; 1273 int ret; 1274 1275 mutex_lock(&smu->metrics_lock); 1276 ret = smu_cmn_get_metrics_table_locked(smu, NULL, false); 1277 if (ret) 1278 goto out_unlock; 1279 1280 upper32 = metrics->PublicSerialNumUpper32; 1281 lower32 = metrics->PublicSerialNumLower32; 1282 1283 out_unlock: 1284 mutex_unlock(&smu->metrics_lock); 1285 1286 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1287 sprintf(adev->serial, "%016llx", adev->unique_id); 1288 } 1289 1290 static bool aldebaran_is_baco_supported(struct smu_context *smu) 1291 { 1292 /* aldebaran is not support baco */ 1293 1294 return false; 1295 } 1296 1297 static int aldebaran_set_df_cstate(struct smu_context *smu, 1298 enum pp_df_cstate state) 1299 { 1300 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1301 } 1302 1303 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) 1304 { 1305 return smu_cmn_send_smc_msg_with_param(smu, 1306 SMU_MSG_GmiPwrDnControl, 1307 en ? 1 : 0, 1308 NULL); 1309 } 1310 1311 static const struct throttling_logging_label { 1312 uint32_t feature_mask; 1313 const char *label; 1314 } logging_label[] = { 1315 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1316 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1317 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1318 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1319 }; 1320 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1321 { 1322 int ret; 1323 int throttler_idx, throtting_events = 0, buf_idx = 0; 1324 struct amdgpu_device *adev = smu->adev; 1325 uint32_t throttler_status; 1326 char log_buf[256]; 1327 1328 ret = aldebaran_get_smu_metrics_data(smu, 1329 METRICS_THROTTLER_STATUS, 1330 &throttler_status); 1331 if (ret) 1332 return; 1333 1334 memset(log_buf, 0, sizeof(log_buf)); 1335 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1336 throttler_idx++) { 1337 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1338 throtting_events++; 1339 buf_idx += snprintf(log_buf + buf_idx, 1340 sizeof(log_buf) - buf_idx, 1341 "%s%s", 1342 throtting_events > 1 ? " and " : "", 1343 logging_label[throttler_idx].label); 1344 if (buf_idx >= sizeof(log_buf)) { 1345 dev_err(adev->dev, "buffer overflow!\n"); 1346 log_buf[sizeof(log_buf) - 1] = '\0'; 1347 break; 1348 } 1349 } 1350 } 1351 1352 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1353 log_buf); 1354 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status); 1355 } 1356 1357 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1358 { 1359 struct amdgpu_device *adev = smu->adev; 1360 uint32_t esm_ctrl; 1361 1362 /* TODO: confirm this on real target */ 1363 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1364 if ((esm_ctrl >> 15) & 0x1FFFF) 1365 return (((esm_ctrl >> 8) & 0x3F) + 128); 1366 1367 return smu_v13_0_get_current_pcie_link_speed(smu); 1368 } 1369 1370 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1371 void **table) 1372 { 1373 struct smu_table_context *smu_table = &smu->smu_table; 1374 struct gpu_metrics_v1_1 *gpu_metrics = 1375 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; 1376 SmuMetrics_t metrics; 1377 int i, ret = 0; 1378 1379 ret = smu_cmn_get_metrics_table(smu, 1380 &metrics, 1381 true); 1382 if (ret) 1383 return ret; 1384 1385 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); 1386 1387 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1388 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1389 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1390 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1391 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1392 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1393 1394 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1395 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1396 gpu_metrics->average_mm_activity = 0; 1397 1398 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1399 gpu_metrics->energy_accumulator = 0; 1400 1401 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1402 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1403 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1404 gpu_metrics->average_vclk0_frequency = 0; 1405 gpu_metrics->average_dclk0_frequency = 0; 1406 1407 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1408 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1409 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1410 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1411 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1412 1413 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1414 1415 gpu_metrics->current_fan_speed = 0; 1416 1417 gpu_metrics->pcie_link_width = 1418 smu_v13_0_get_current_pcie_link_width(smu); 1419 gpu_metrics->pcie_link_speed = 1420 aldebaran_get_current_pcie_link_speed(smu); 1421 1422 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1423 1424 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1425 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1426 1427 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1428 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1429 1430 *table = (void *)gpu_metrics; 1431 1432 return sizeof(struct gpu_metrics_v1_1); 1433 } 1434 1435 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1436 { 1437 #if 0 1438 struct amdgpu_device *adev = smu->adev; 1439 u32 smu_version; 1440 uint32_t val; 1441 /** 1442 * PM FW version support mode1 reset from 68.07 1443 */ 1444 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1445 if ((smu_version < 0x00440700)) 1446 return false; 1447 /** 1448 * mode1 reset relies on PSP, so we should check if 1449 * PSP is alive. 1450 */ 1451 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1452 1453 return val != 0x0; 1454 #endif 1455 return true; 1456 } 1457 1458 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 1459 { 1460 return true; 1461 } 1462 1463 static int aldebaran_set_mp1_state(struct smu_context *smu, 1464 enum pp_mp1_state mp1_state) 1465 { 1466 switch (mp1_state) { 1467 case PP_MP1_STATE_UNLOAD: 1468 return smu_cmn_set_mp1_state(smu, mp1_state); 1469 default: 1470 return -EINVAL; 1471 } 1472 1473 return 0; 1474 } 1475 1476 static const struct pptable_funcs aldebaran_ppt_funcs = { 1477 /* init dpm */ 1478 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 1479 /* dpm/clk tables */ 1480 .set_default_dpm_table = aldebaran_set_default_dpm_table, 1481 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 1482 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 1483 .print_clk_levels = aldebaran_print_clk_levels, 1484 .force_clk_levels = aldebaran_force_clk_levels, 1485 .read_sensor = aldebaran_read_sensor, 1486 .set_performance_level = aldebaran_set_performance_level, 1487 .get_power_limit = aldebaran_get_power_limit, 1488 .is_dpm_running = aldebaran_is_dpm_running, 1489 .get_unique_id = aldebaran_get_unique_id, 1490 .init_microcode = smu_v13_0_init_microcode, 1491 .load_microcode = smu_v13_0_load_microcode, 1492 .fini_microcode = smu_v13_0_fini_microcode, 1493 .init_smc_tables = aldebaran_init_smc_tables, 1494 .fini_smc_tables = smu_v13_0_fini_smc_tables, 1495 .init_power = smu_v13_0_init_power, 1496 .fini_power = smu_v13_0_fini_power, 1497 .check_fw_status = smu_v13_0_check_fw_status, 1498 /* pptable related */ 1499 .setup_pptable = aldebaran_setup_pptable, 1500 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1501 .check_fw_version = smu_v13_0_check_fw_version, 1502 .write_pptable = smu_cmn_write_pptable, 1503 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1504 .set_tool_table_location = smu_v13_0_set_tool_table_location, 1505 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 1506 .system_features_control = aldebaran_system_features_control, 1507 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1508 .send_smc_msg = smu_cmn_send_smc_msg, 1509 .get_enabled_mask = smu_cmn_get_enabled_mask, 1510 .feature_is_enabled = smu_cmn_feature_is_enabled, 1511 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1512 .set_power_limit = smu_v13_0_set_power_limit, 1513 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 1514 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 1515 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 1516 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 1517 .register_irq_handler = smu_v13_0_register_irq_handler, 1518 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 1519 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 1520 .baco_is_support= aldebaran_is_baco_supported, 1521 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 1522 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 1523 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 1524 .set_df_cstate = aldebaran_set_df_cstate, 1525 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down, 1526 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 1527 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1528 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1529 .get_gpu_metrics = aldebaran_get_gpu_metrics, 1530 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 1531 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 1532 .mode1_reset = smu_v13_0_mode1_reset, 1533 .mode2_reset = smu_v13_0_mode2_reset, 1534 .set_mp1_state = aldebaran_set_mp1_state, 1535 }; 1536 1537 void aldebaran_set_ppt_funcs(struct smu_context *smu) 1538 { 1539 smu->ppt_funcs = &aldebaran_ppt_funcs; 1540 smu->message_map = aldebaran_message_map; 1541 smu->clock_map = aldebaran_clk_map; 1542 smu->feature_map = aldebaran_feature_mask_map; 1543 smu->table_map = aldebaran_table_map; 1544 } 1545