1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_dpm.h" 29 #include "amdgpu_smu.h" 30 #include "atomfirmware.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_atombios.h" 33 #include "smu_v13_0.h" 34 #include "smu13_driver_if_aldebaran.h" 35 #include "soc15_common.h" 36 #include "atom.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 61 [smu_feature] = {1, (aldebaran_feature)} 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 73 74 /* possible frequency drift (1Mhz) */ 75 #define EPSILON 1 76 77 #define smnPCIE_ESM_CTRL 0x111003D0 78 79 /* 80 * SMU support ECCTABLE since version 68.42.0, 81 * use this to check ECCTALE feature whether support 82 */ 83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00 84 85 static const struct smu_temperature_range smu13_thermal_policy[] = 86 { 87 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 88 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 89 }; 90 91 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 94 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 95 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 96 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 97 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 98 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 99 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 100 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 101 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 102 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 103 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 104 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 105 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 106 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 107 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 108 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 109 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 110 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 111 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 112 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 113 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 114 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 115 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 116 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 117 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 118 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 119 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 120 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 121 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 122 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 123 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 124 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 125 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 126 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 127 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 128 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 129 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 130 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 131 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 132 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 133 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 134 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 135 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 136 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 137 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 138 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 139 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 140 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 141 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0), 142 MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0), 143 }; 144 145 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 146 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 147 CLK_MAP(SCLK, PPCLK_GFXCLK), 148 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 149 CLK_MAP(FCLK, PPCLK_FCLK), 150 CLK_MAP(UCLK, PPCLK_UCLK), 151 CLK_MAP(MCLK, PPCLK_UCLK), 152 CLK_MAP(DCLK, PPCLK_DCLK), 153 CLK_MAP(VCLK, PPCLK_VCLK), 154 CLK_MAP(LCLK, PPCLK_LCLK), 155 }; 156 157 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 158 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS), 159 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 160 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 161 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 162 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 163 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 164 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 165 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 166 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 167 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 168 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 169 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 170 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 175 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 176 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 177 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 178 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 179 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 180 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 181 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 182 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 183 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 184 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 185 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 186 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN), 187 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 188 }; 189 190 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 191 TAB_MAP(PPTABLE), 192 TAB_MAP(AVFS_PSM_DEBUG), 193 TAB_MAP(AVFS_FUSE_OVERRIDE), 194 TAB_MAP(PMSTATUSLOG), 195 TAB_MAP(SMU_METRICS), 196 TAB_MAP(DRIVER_SMU_CONFIG), 197 TAB_MAP(I2C_COMMANDS), 198 TAB_MAP(ECCINFO), 199 }; 200 201 static const uint8_t aldebaran_throttler_map[] = { 202 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 203 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 204 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 205 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 206 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT), 207 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), 208 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 209 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 210 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 211 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 212 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 213 }; 214 215 static int aldebaran_tables_init(struct smu_context *smu) 216 { 217 struct smu_table_context *smu_table = &smu->smu_table; 218 struct smu_table *tables = smu_table->tables; 219 220 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 221 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 222 223 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 224 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 225 226 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 227 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 228 229 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 230 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 231 232 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 233 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 234 235 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 236 if (!smu_table->metrics_table) 237 return -ENOMEM; 238 smu_table->metrics_time = 0; 239 240 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 241 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 242 if (!smu_table->gpu_metrics_table) { 243 kfree(smu_table->metrics_table); 244 return -ENOMEM; 245 } 246 247 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 248 if (!smu_table->ecc_table) 249 return -ENOMEM; 250 251 return 0; 252 } 253 254 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 255 { 256 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 257 258 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 259 GFP_KERNEL); 260 if (!smu_dpm->dpm_context) 261 return -ENOMEM; 262 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 263 264 return 0; 265 } 266 267 static int aldebaran_init_smc_tables(struct smu_context *smu) 268 { 269 int ret = 0; 270 271 ret = aldebaran_tables_init(smu); 272 if (ret) 273 return ret; 274 275 ret = aldebaran_allocate_dpm_context(smu); 276 if (ret) 277 return ret; 278 279 return smu_v13_0_init_smc_tables(smu); 280 } 281 282 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 283 uint32_t *feature_mask, uint32_t num) 284 { 285 if (num > 2) 286 return -EINVAL; 287 288 /* pptable will handle the features to enable */ 289 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 290 291 return 0; 292 } 293 294 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 295 { 296 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 297 struct smu_13_0_dpm_table *dpm_table = NULL; 298 PPTable_t *pptable = smu->smu_table.driver_pptable; 299 int ret = 0; 300 301 /* socclk dpm table setup */ 302 dpm_table = &dpm_context->dpm_tables.soc_table; 303 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 304 ret = smu_v13_0_set_single_dpm_table(smu, 305 SMU_SOCCLK, 306 dpm_table); 307 if (ret) 308 return ret; 309 } else { 310 dpm_table->count = 1; 311 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 312 dpm_table->dpm_levels[0].enabled = true; 313 dpm_table->min = dpm_table->dpm_levels[0].value; 314 dpm_table->max = dpm_table->dpm_levels[0].value; 315 } 316 317 /* gfxclk dpm table setup */ 318 dpm_table = &dpm_context->dpm_tables.gfx_table; 319 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 320 /* in the case of gfxclk, only fine-grained dpm is honored */ 321 dpm_table->count = 2; 322 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 323 dpm_table->dpm_levels[0].enabled = true; 324 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 325 dpm_table->dpm_levels[1].enabled = true; 326 dpm_table->min = dpm_table->dpm_levels[0].value; 327 dpm_table->max = dpm_table->dpm_levels[1].value; 328 } else { 329 dpm_table->count = 1; 330 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 331 dpm_table->dpm_levels[0].enabled = true; 332 dpm_table->min = dpm_table->dpm_levels[0].value; 333 dpm_table->max = dpm_table->dpm_levels[0].value; 334 } 335 336 /* memclk dpm table setup */ 337 dpm_table = &dpm_context->dpm_tables.uclk_table; 338 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 339 ret = smu_v13_0_set_single_dpm_table(smu, 340 SMU_UCLK, 341 dpm_table); 342 if (ret) 343 return ret; 344 } else { 345 dpm_table->count = 1; 346 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 347 dpm_table->dpm_levels[0].enabled = true; 348 dpm_table->min = dpm_table->dpm_levels[0].value; 349 dpm_table->max = dpm_table->dpm_levels[0].value; 350 } 351 352 /* fclk dpm table setup */ 353 dpm_table = &dpm_context->dpm_tables.fclk_table; 354 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 355 ret = smu_v13_0_set_single_dpm_table(smu, 356 SMU_FCLK, 357 dpm_table); 358 if (ret) 359 return ret; 360 } else { 361 dpm_table->count = 1; 362 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 363 dpm_table->dpm_levels[0].enabled = true; 364 dpm_table->min = dpm_table->dpm_levels[0].value; 365 dpm_table->max = dpm_table->dpm_levels[0].value; 366 } 367 368 return 0; 369 } 370 371 static int aldebaran_check_powerplay_table(struct smu_context *smu) 372 { 373 struct smu_table_context *table_context = &smu->smu_table; 374 struct smu_13_0_powerplay_table *powerplay_table = 375 table_context->power_play_table; 376 377 table_context->thermal_controller_type = 378 powerplay_table->thermal_controller_type; 379 380 return 0; 381 } 382 383 static int aldebaran_store_powerplay_table(struct smu_context *smu) 384 { 385 struct smu_table_context *table_context = &smu->smu_table; 386 struct smu_13_0_powerplay_table *powerplay_table = 387 table_context->power_play_table; 388 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 389 sizeof(PPTable_t)); 390 391 return 0; 392 } 393 394 static int aldebaran_append_powerplay_table(struct smu_context *smu) 395 { 396 struct smu_table_context *table_context = &smu->smu_table; 397 PPTable_t *smc_pptable = table_context->driver_pptable; 398 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 399 int index, ret; 400 401 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 402 smc_dpm_info); 403 404 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 405 (uint8_t **)&smc_dpm_table); 406 if (ret) 407 return ret; 408 409 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 410 smc_dpm_table->table_header.format_revision, 411 smc_dpm_table->table_header.content_revision); 412 413 if ((smc_dpm_table->table_header.format_revision == 4) && 414 (smc_dpm_table->table_header.content_revision == 10)) 415 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved, 416 smc_dpm_table, GfxMaxCurrent); 417 return 0; 418 } 419 420 static int aldebaran_setup_pptable(struct smu_context *smu) 421 { 422 int ret = 0; 423 424 /* VBIOS pptable is the first choice */ 425 smu->smu_table.boot_values.pp_table_id = 0; 426 427 ret = smu_v13_0_setup_pptable(smu); 428 if (ret) 429 return ret; 430 431 ret = aldebaran_store_powerplay_table(smu); 432 if (ret) 433 return ret; 434 435 ret = aldebaran_append_powerplay_table(smu); 436 if (ret) 437 return ret; 438 439 ret = aldebaran_check_powerplay_table(smu); 440 if (ret) 441 return ret; 442 443 return ret; 444 } 445 446 static bool aldebaran_is_primary(struct smu_context *smu) 447 { 448 struct amdgpu_device *adev = smu->adev; 449 450 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) 451 return adev->smuio.funcs->get_die_id(adev) == 0; 452 453 return true; 454 } 455 456 static int aldebaran_run_board_btc(struct smu_context *smu) 457 { 458 u32 smu_version; 459 int ret; 460 461 if (!aldebaran_is_primary(smu)) 462 return 0; 463 464 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 465 if (ret) { 466 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 467 return ret; 468 } 469 if (smu_version <= 0x00441d00) 470 return 0; 471 472 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL); 473 if (ret) 474 dev_err(smu->adev->dev, "Board power calibration failed!\n"); 475 476 return ret; 477 } 478 479 static int aldebaran_run_btc(struct smu_context *smu) 480 { 481 int ret; 482 483 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 484 if (ret) 485 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 486 else 487 ret = aldebaran_run_board_btc(smu); 488 489 return ret; 490 } 491 492 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 493 { 494 struct smu_13_0_dpm_context *dpm_context = 495 smu->smu_dpm.dpm_context; 496 struct smu_13_0_dpm_table *gfx_table = 497 &dpm_context->dpm_tables.gfx_table; 498 struct smu_13_0_dpm_table *mem_table = 499 &dpm_context->dpm_tables.uclk_table; 500 struct smu_13_0_dpm_table *soc_table = 501 &dpm_context->dpm_tables.soc_table; 502 struct smu_umd_pstate_table *pstate_table = 503 &smu->pstate_table; 504 505 pstate_table->gfxclk_pstate.min = gfx_table->min; 506 pstate_table->gfxclk_pstate.peak = gfx_table->max; 507 pstate_table->gfxclk_pstate.curr.min = gfx_table->min; 508 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 509 510 pstate_table->uclk_pstate.min = mem_table->min; 511 pstate_table->uclk_pstate.peak = mem_table->max; 512 pstate_table->uclk_pstate.curr.min = mem_table->min; 513 pstate_table->uclk_pstate.curr.max = mem_table->max; 514 515 pstate_table->socclk_pstate.min = soc_table->min; 516 pstate_table->socclk_pstate.peak = soc_table->max; 517 pstate_table->socclk_pstate.curr.min = soc_table->min; 518 pstate_table->socclk_pstate.curr.max = soc_table->max; 519 520 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 521 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 522 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 523 pstate_table->gfxclk_pstate.standard = 524 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 525 pstate_table->uclk_pstate.standard = 526 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 527 pstate_table->socclk_pstate.standard = 528 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 529 } else { 530 pstate_table->gfxclk_pstate.standard = 531 pstate_table->gfxclk_pstate.min; 532 pstate_table->uclk_pstate.standard = 533 pstate_table->uclk_pstate.min; 534 pstate_table->socclk_pstate.standard = 535 pstate_table->socclk_pstate.min; 536 } 537 538 return 0; 539 } 540 541 static int aldebaran_get_clk_table(struct smu_context *smu, 542 struct pp_clock_levels_with_latency *clocks, 543 struct smu_13_0_dpm_table *dpm_table) 544 { 545 int i, count; 546 547 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 548 clocks->num_levels = count; 549 550 for (i = 0; i < count; i++) { 551 clocks->data[i].clocks_in_khz = 552 dpm_table->dpm_levels[i].value * 1000; 553 clocks->data[i].latency_in_us = 0; 554 } 555 556 return 0; 557 } 558 559 static int aldebaran_freqs_in_same_level(int32_t frequency1, 560 int32_t frequency2) 561 { 562 return (abs(frequency1 - frequency2) <= EPSILON); 563 } 564 565 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 566 MetricsMember_t member, 567 uint32_t *value) 568 { 569 struct smu_table_context *smu_table= &smu->smu_table; 570 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 571 int ret = 0; 572 573 ret = smu_cmn_get_metrics_table(smu, 574 NULL, 575 false); 576 if (ret) 577 return ret; 578 579 switch (member) { 580 case METRICS_CURR_GFXCLK: 581 *value = metrics->CurrClock[PPCLK_GFXCLK]; 582 break; 583 case METRICS_CURR_SOCCLK: 584 *value = metrics->CurrClock[PPCLK_SOCCLK]; 585 break; 586 case METRICS_CURR_UCLK: 587 *value = metrics->CurrClock[PPCLK_UCLK]; 588 break; 589 case METRICS_CURR_VCLK: 590 *value = metrics->CurrClock[PPCLK_VCLK]; 591 break; 592 case METRICS_CURR_DCLK: 593 *value = metrics->CurrClock[PPCLK_DCLK]; 594 break; 595 case METRICS_CURR_FCLK: 596 *value = metrics->CurrClock[PPCLK_FCLK]; 597 break; 598 case METRICS_AVERAGE_GFXCLK: 599 *value = metrics->AverageGfxclkFrequency; 600 break; 601 case METRICS_AVERAGE_SOCCLK: 602 *value = metrics->AverageSocclkFrequency; 603 break; 604 case METRICS_AVERAGE_UCLK: 605 *value = metrics->AverageUclkFrequency; 606 break; 607 case METRICS_AVERAGE_GFXACTIVITY: 608 *value = metrics->AverageGfxActivity; 609 break; 610 case METRICS_AVERAGE_MEMACTIVITY: 611 *value = metrics->AverageUclkActivity; 612 break; 613 case METRICS_AVERAGE_SOCKETPOWER: 614 /* Valid power data is available only from primary die */ 615 *value = aldebaran_is_primary(smu) ? 616 metrics->AverageSocketPower << 8 : 617 0; 618 break; 619 case METRICS_TEMPERATURE_EDGE: 620 *value = metrics->TemperatureEdge * 621 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 622 break; 623 case METRICS_TEMPERATURE_HOTSPOT: 624 *value = metrics->TemperatureHotspot * 625 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 626 break; 627 case METRICS_TEMPERATURE_MEM: 628 *value = metrics->TemperatureHBM * 629 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 630 break; 631 case METRICS_TEMPERATURE_VRGFX: 632 *value = metrics->TemperatureVrGfx * 633 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 634 break; 635 case METRICS_TEMPERATURE_VRSOC: 636 *value = metrics->TemperatureVrSoc * 637 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 638 break; 639 case METRICS_TEMPERATURE_VRMEM: 640 *value = metrics->TemperatureVrMem * 641 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 642 break; 643 case METRICS_THROTTLER_STATUS: 644 *value = metrics->ThrottlerStatus; 645 break; 646 default: 647 *value = UINT_MAX; 648 break; 649 } 650 651 return ret; 652 } 653 654 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 655 enum smu_clk_type clk_type, 656 uint32_t *value) 657 { 658 MetricsMember_t member_type; 659 int clk_id = 0; 660 661 if (!value) 662 return -EINVAL; 663 664 clk_id = smu_cmn_to_asic_specific_index(smu, 665 CMN2ASIC_MAPPING_CLK, 666 clk_type); 667 if (clk_id < 0) 668 return -EINVAL; 669 670 switch (clk_id) { 671 case PPCLK_GFXCLK: 672 /* 673 * CurrClock[clk_id] can provide accurate 674 * output only when the dpm feature is enabled. 675 * We can use Average_* for dpm disabled case. 676 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 677 */ 678 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 679 member_type = METRICS_CURR_GFXCLK; 680 else 681 member_type = METRICS_AVERAGE_GFXCLK; 682 break; 683 case PPCLK_UCLK: 684 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 685 member_type = METRICS_CURR_UCLK; 686 else 687 member_type = METRICS_AVERAGE_UCLK; 688 break; 689 case PPCLK_SOCCLK: 690 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 691 member_type = METRICS_CURR_SOCCLK; 692 else 693 member_type = METRICS_AVERAGE_SOCCLK; 694 break; 695 case PPCLK_VCLK: 696 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 697 member_type = METRICS_CURR_VCLK; 698 else 699 member_type = METRICS_AVERAGE_VCLK; 700 break; 701 case PPCLK_DCLK: 702 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 703 member_type = METRICS_CURR_DCLK; 704 else 705 member_type = METRICS_AVERAGE_DCLK; 706 break; 707 case PPCLK_FCLK: 708 member_type = METRICS_CURR_FCLK; 709 break; 710 default: 711 return -EINVAL; 712 } 713 714 return aldebaran_get_smu_metrics_data(smu, 715 member_type, 716 value); 717 } 718 719 static int aldebaran_print_clk_levels(struct smu_context *smu, 720 enum smu_clk_type type, char *buf) 721 { 722 int i, now, size = 0; 723 int ret = 0; 724 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 725 struct pp_clock_levels_with_latency clocks; 726 struct smu_13_0_dpm_table *single_dpm_table; 727 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 728 struct smu_13_0_dpm_context *dpm_context = NULL; 729 uint32_t display_levels; 730 uint32_t freq_values[3] = {0}; 731 uint32_t min_clk, max_clk; 732 733 smu_cmn_get_sysfs_buf(&buf, &size); 734 735 if (amdgpu_ras_intr_triggered()) { 736 size += sysfs_emit_at(buf, size, "unavailable\n"); 737 return size; 738 } 739 740 dpm_context = smu_dpm->dpm_context; 741 742 switch (type) { 743 744 case SMU_OD_SCLK: 745 size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK"); 746 fallthrough; 747 case SMU_SCLK: 748 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 749 if (ret) { 750 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 751 return ret; 752 } 753 754 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 755 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 756 if (ret) { 757 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 758 return ret; 759 } 760 761 display_levels = clocks.num_levels; 762 763 min_clk = pstate_table->gfxclk_pstate.curr.min; 764 max_clk = pstate_table->gfxclk_pstate.curr.max; 765 766 freq_values[0] = min_clk; 767 freq_values[1] = max_clk; 768 769 /* fine-grained dpm has only 2 levels */ 770 if (now > min_clk && now < max_clk) { 771 display_levels = clocks.num_levels + 1; 772 freq_values[2] = max_clk; 773 freq_values[1] = now; 774 } 775 776 /* 777 * For DPM disabled case, there will be only one clock level. 778 * And it's safe to assume that is always the current clock. 779 */ 780 if (display_levels == clocks.num_levels) { 781 for (i = 0; i < clocks.num_levels; i++) 782 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 783 freq_values[i], 784 (clocks.num_levels == 1) ? 785 "*" : 786 (aldebaran_freqs_in_same_level( 787 freq_values[i], now) ? 788 "*" : 789 "")); 790 } else { 791 for (i = 0; i < display_levels; i++) 792 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 793 freq_values[i], i == 1 ? "*" : ""); 794 } 795 796 break; 797 798 case SMU_OD_MCLK: 799 size += sysfs_emit_at(buf, size, "%s:\n", "MCLK"); 800 fallthrough; 801 case SMU_MCLK: 802 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 803 if (ret) { 804 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 805 return ret; 806 } 807 808 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 809 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 810 if (ret) { 811 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 812 return ret; 813 } 814 815 for (i = 0; i < clocks.num_levels; i++) 816 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 817 i, clocks.data[i].clocks_in_khz / 1000, 818 (clocks.num_levels == 1) ? "*" : 819 (aldebaran_freqs_in_same_level( 820 clocks.data[i].clocks_in_khz / 1000, 821 now) ? "*" : "")); 822 break; 823 824 case SMU_SOCCLK: 825 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 826 if (ret) { 827 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 828 return ret; 829 } 830 831 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 832 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 833 if (ret) { 834 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 835 return ret; 836 } 837 838 for (i = 0; i < clocks.num_levels; i++) 839 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 840 i, clocks.data[i].clocks_in_khz / 1000, 841 (clocks.num_levels == 1) ? "*" : 842 (aldebaran_freqs_in_same_level( 843 clocks.data[i].clocks_in_khz / 1000, 844 now) ? "*" : "")); 845 break; 846 847 case SMU_FCLK: 848 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 849 if (ret) { 850 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 851 return ret; 852 } 853 854 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 855 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 856 if (ret) { 857 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 858 return ret; 859 } 860 861 for (i = 0; i < single_dpm_table->count; i++) 862 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 863 i, single_dpm_table->dpm_levels[i].value, 864 (clocks.num_levels == 1) ? "*" : 865 (aldebaran_freqs_in_same_level( 866 clocks.data[i].clocks_in_khz / 1000, 867 now) ? "*" : "")); 868 break; 869 870 case SMU_VCLK: 871 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); 872 if (ret) { 873 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); 874 return ret; 875 } 876 877 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 878 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 879 if (ret) { 880 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); 881 return ret; 882 } 883 884 for (i = 0; i < single_dpm_table->count; i++) 885 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 886 i, single_dpm_table->dpm_levels[i].value, 887 (clocks.num_levels == 1) ? "*" : 888 (aldebaran_freqs_in_same_level( 889 clocks.data[i].clocks_in_khz / 1000, 890 now) ? "*" : "")); 891 break; 892 893 case SMU_DCLK: 894 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); 895 if (ret) { 896 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); 897 return ret; 898 } 899 900 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 901 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 902 if (ret) { 903 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); 904 return ret; 905 } 906 907 for (i = 0; i < single_dpm_table->count; i++) 908 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 909 i, single_dpm_table->dpm_levels[i].value, 910 (clocks.num_levels == 1) ? "*" : 911 (aldebaran_freqs_in_same_level( 912 clocks.data[i].clocks_in_khz / 1000, 913 now) ? "*" : "")); 914 break; 915 916 default: 917 break; 918 } 919 920 return size; 921 } 922 923 static int aldebaran_upload_dpm_level(struct smu_context *smu, 924 bool max, 925 uint32_t feature_mask, 926 uint32_t level) 927 { 928 struct smu_13_0_dpm_context *dpm_context = 929 smu->smu_dpm.dpm_context; 930 uint32_t freq; 931 int ret = 0; 932 933 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 934 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 935 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 936 ret = smu_cmn_send_smc_msg_with_param(smu, 937 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 938 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 939 NULL); 940 if (ret) { 941 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 942 max ? "max" : "min"); 943 return ret; 944 } 945 } 946 947 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 948 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 949 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 950 ret = smu_cmn_send_smc_msg_with_param(smu, 951 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 952 (PPCLK_UCLK << 16) | (freq & 0xffff), 953 NULL); 954 if (ret) { 955 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 956 max ? "max" : "min"); 957 return ret; 958 } 959 } 960 961 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 962 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 963 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 964 ret = smu_cmn_send_smc_msg_with_param(smu, 965 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 966 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 967 NULL); 968 if (ret) { 969 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 970 max ? "max" : "min"); 971 return ret; 972 } 973 } 974 975 return ret; 976 } 977 978 static int aldebaran_force_clk_levels(struct smu_context *smu, 979 enum smu_clk_type type, uint32_t mask) 980 { 981 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 982 struct smu_13_0_dpm_table *single_dpm_table = NULL; 983 uint32_t soft_min_level, soft_max_level; 984 int ret = 0; 985 986 soft_min_level = mask ? (ffs(mask) - 1) : 0; 987 soft_max_level = mask ? (fls(mask) - 1) : 0; 988 989 switch (type) { 990 case SMU_SCLK: 991 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 992 if (soft_max_level >= single_dpm_table->count) { 993 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 994 soft_max_level, single_dpm_table->count - 1); 995 ret = -EINVAL; 996 break; 997 } 998 999 ret = aldebaran_upload_dpm_level(smu, 1000 false, 1001 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1002 soft_min_level); 1003 if (ret) { 1004 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1005 break; 1006 } 1007 1008 ret = aldebaran_upload_dpm_level(smu, 1009 true, 1010 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1011 soft_max_level); 1012 if (ret) 1013 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1014 1015 break; 1016 1017 case SMU_MCLK: 1018 case SMU_SOCCLK: 1019 case SMU_FCLK: 1020 /* 1021 * Should not arrive here since aldebaran does not 1022 * support mclk/socclk/fclk softmin/softmax settings 1023 */ 1024 ret = -EINVAL; 1025 break; 1026 1027 default: 1028 break; 1029 } 1030 1031 return ret; 1032 } 1033 1034 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 1035 struct smu_temperature_range *range) 1036 { 1037 struct smu_table_context *table_context = &smu->smu_table; 1038 struct smu_13_0_powerplay_table *powerplay_table = 1039 table_context->power_play_table; 1040 PPTable_t *pptable = smu->smu_table.driver_pptable; 1041 1042 if (!range) 1043 return -EINVAL; 1044 1045 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1046 1047 range->hotspot_crit_max = pptable->ThotspotLimit * 1048 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1049 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1050 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1051 range->mem_crit_max = pptable->TmemLimit * 1052 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1053 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1054 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1055 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1056 1057 return 0; 1058 } 1059 1060 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 1061 enum amd_pp_sensors sensor, 1062 uint32_t *value) 1063 { 1064 int ret = 0; 1065 1066 if (!value) 1067 return -EINVAL; 1068 1069 switch (sensor) { 1070 case AMDGPU_PP_SENSOR_GPU_LOAD: 1071 ret = aldebaran_get_smu_metrics_data(smu, 1072 METRICS_AVERAGE_GFXACTIVITY, 1073 value); 1074 break; 1075 case AMDGPU_PP_SENSOR_MEM_LOAD: 1076 ret = aldebaran_get_smu_metrics_data(smu, 1077 METRICS_AVERAGE_MEMACTIVITY, 1078 value); 1079 break; 1080 default: 1081 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 1082 return -EINVAL; 1083 } 1084 1085 return ret; 1086 } 1087 1088 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value) 1089 { 1090 if (!value) 1091 return -EINVAL; 1092 1093 return aldebaran_get_smu_metrics_data(smu, 1094 METRICS_AVERAGE_SOCKETPOWER, 1095 value); 1096 } 1097 1098 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 1099 enum amd_pp_sensors sensor, 1100 uint32_t *value) 1101 { 1102 int ret = 0; 1103 1104 if (!value) 1105 return -EINVAL; 1106 1107 switch (sensor) { 1108 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1109 ret = aldebaran_get_smu_metrics_data(smu, 1110 METRICS_TEMPERATURE_HOTSPOT, 1111 value); 1112 break; 1113 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1114 ret = aldebaran_get_smu_metrics_data(smu, 1115 METRICS_TEMPERATURE_EDGE, 1116 value); 1117 break; 1118 case AMDGPU_PP_SENSOR_MEM_TEMP: 1119 ret = aldebaran_get_smu_metrics_data(smu, 1120 METRICS_TEMPERATURE_MEM, 1121 value); 1122 break; 1123 default: 1124 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1125 return -EINVAL; 1126 } 1127 1128 return ret; 1129 } 1130 1131 static int aldebaran_read_sensor(struct smu_context *smu, 1132 enum amd_pp_sensors sensor, 1133 void *data, uint32_t *size) 1134 { 1135 int ret = 0; 1136 1137 if (amdgpu_ras_intr_triggered()) 1138 return 0; 1139 1140 if (!data || !size) 1141 return -EINVAL; 1142 1143 switch (sensor) { 1144 case AMDGPU_PP_SENSOR_MEM_LOAD: 1145 case AMDGPU_PP_SENSOR_GPU_LOAD: 1146 ret = aldebaran_get_current_activity_percent(smu, 1147 sensor, 1148 (uint32_t *)data); 1149 *size = 4; 1150 break; 1151 case AMDGPU_PP_SENSOR_GPU_POWER: 1152 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data); 1153 *size = 4; 1154 break; 1155 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1156 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1157 case AMDGPU_PP_SENSOR_MEM_TEMP: 1158 ret = aldebaran_thermal_get_temperature(smu, sensor, 1159 (uint32_t *)data); 1160 *size = 4; 1161 break; 1162 case AMDGPU_PP_SENSOR_GFX_MCLK: 1163 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1164 /* the output clock frequency in 10K unit */ 1165 *(uint32_t *)data *= 100; 1166 *size = 4; 1167 break; 1168 case AMDGPU_PP_SENSOR_GFX_SCLK: 1169 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1170 *(uint32_t *)data *= 100; 1171 *size = 4; 1172 break; 1173 case AMDGPU_PP_SENSOR_VDDGFX: 1174 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1175 *size = 4; 1176 break; 1177 default: 1178 ret = -EOPNOTSUPP; 1179 break; 1180 } 1181 1182 return ret; 1183 } 1184 1185 static int aldebaran_get_power_limit(struct smu_context *smu, 1186 uint32_t *current_power_limit, 1187 uint32_t *default_power_limit, 1188 uint32_t *max_power_limit) 1189 { 1190 PPTable_t *pptable = smu->smu_table.driver_pptable; 1191 uint32_t power_limit = 0; 1192 int ret; 1193 1194 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1195 if (current_power_limit) 1196 *current_power_limit = 0; 1197 if (default_power_limit) 1198 *default_power_limit = 0; 1199 if (max_power_limit) 1200 *max_power_limit = 0; 1201 1202 dev_warn(smu->adev->dev, 1203 "PPT feature is not enabled, power values can't be fetched."); 1204 1205 return 0; 1206 } 1207 1208 /* Valid power data is available only from primary die. 1209 * For secondary die show the value as 0. 1210 */ 1211 if (aldebaran_is_primary(smu)) { 1212 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, 1213 &power_limit); 1214 1215 if (ret) { 1216 /* the last hope to figure out the ppt limit */ 1217 if (!pptable) { 1218 dev_err(smu->adev->dev, 1219 "Cannot get PPT limit due to pptable missing!"); 1220 return -EINVAL; 1221 } 1222 power_limit = pptable->PptLimit; 1223 } 1224 } 1225 1226 if (current_power_limit) 1227 *current_power_limit = power_limit; 1228 if (default_power_limit) 1229 *default_power_limit = power_limit; 1230 1231 if (max_power_limit) { 1232 if (pptable) 1233 *max_power_limit = pptable->PptLimit; 1234 } 1235 1236 return 0; 1237 } 1238 1239 static int aldebaran_set_power_limit(struct smu_context *smu, 1240 enum smu_ppt_limit_type limit_type, 1241 uint32_t limit) 1242 { 1243 /* Power limit can be set only through primary die */ 1244 if (aldebaran_is_primary(smu)) 1245 return smu_v13_0_set_power_limit(smu, limit_type, limit); 1246 1247 return -EINVAL; 1248 } 1249 1250 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1251 { 1252 int ret; 1253 1254 ret = smu_v13_0_system_features_control(smu, enable); 1255 if (!ret && enable) 1256 ret = aldebaran_run_btc(smu); 1257 1258 return ret; 1259 } 1260 1261 static int aldebaran_set_performance_level(struct smu_context *smu, 1262 enum amd_dpm_forced_level level) 1263 { 1264 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1265 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1266 struct smu_13_0_dpm_table *gfx_table = 1267 &dpm_context->dpm_tables.gfx_table; 1268 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1269 1270 /* Disable determinism if switching to another mode */ 1271 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && 1272 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { 1273 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1274 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 1275 } 1276 1277 switch (level) { 1278 1279 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1280 return 0; 1281 1282 case AMD_DPM_FORCED_LEVEL_HIGH: 1283 case AMD_DPM_FORCED_LEVEL_LOW: 1284 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1285 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1286 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1287 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1288 default: 1289 break; 1290 } 1291 1292 return smu_v13_0_set_performance_level(smu, level); 1293 } 1294 1295 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1296 enum smu_clk_type clk_type, 1297 uint32_t min, 1298 uint32_t max) 1299 { 1300 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1301 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1302 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1303 struct amdgpu_device *adev = smu->adev; 1304 uint32_t min_clk; 1305 uint32_t max_clk; 1306 int ret = 0; 1307 1308 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1309 return -EINVAL; 1310 1311 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1312 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1313 return -EINVAL; 1314 1315 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1316 if (min >= max) { 1317 dev_err(smu->adev->dev, 1318 "Minimum GFX clk should be less than the maximum allowed clock\n"); 1319 return -EINVAL; 1320 } 1321 1322 if ((min == pstate_table->gfxclk_pstate.curr.min) && 1323 (max == pstate_table->gfxclk_pstate.curr.max)) 1324 return 0; 1325 1326 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, 1327 min, max); 1328 if (!ret) { 1329 pstate_table->gfxclk_pstate.curr.min = min; 1330 pstate_table->gfxclk_pstate.curr.max = max; 1331 } 1332 1333 return ret; 1334 } 1335 1336 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1337 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1338 (max > dpm_context->dpm_tables.gfx_table.max)) { 1339 dev_warn(adev->dev, 1340 "Invalid max frequency %d MHz specified for determinism\n", max); 1341 return -EINVAL; 1342 } 1343 1344 /* Restore default min/max clocks and enable determinism */ 1345 min_clk = dpm_context->dpm_tables.gfx_table.min; 1346 max_clk = dpm_context->dpm_tables.gfx_table.max; 1347 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1348 if (!ret) { 1349 usleep_range(500, 1000); 1350 ret = smu_cmn_send_smc_msg_with_param(smu, 1351 SMU_MSG_EnableDeterminism, 1352 max, NULL); 1353 if (ret) { 1354 dev_err(adev->dev, 1355 "Failed to enable determinism at GFX clock %d MHz\n", max); 1356 } else { 1357 pstate_table->gfxclk_pstate.curr.min = min_clk; 1358 pstate_table->gfxclk_pstate.curr.max = max; 1359 } 1360 } 1361 } 1362 1363 return ret; 1364 } 1365 1366 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1367 long input[], uint32_t size) 1368 { 1369 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1370 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1371 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1372 uint32_t min_clk; 1373 uint32_t max_clk; 1374 int ret = 0; 1375 1376 /* Only allowed in manual or determinism mode */ 1377 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1378 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1379 return -EINVAL; 1380 1381 switch (type) { 1382 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1383 if (size != 2) { 1384 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1385 return -EINVAL; 1386 } 1387 1388 if (input[0] == 0) { 1389 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1390 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1391 input[1], dpm_context->dpm_tables.gfx_table.min); 1392 pstate_table->gfxclk_pstate.custom.min = 1393 pstate_table->gfxclk_pstate.curr.min; 1394 return -EINVAL; 1395 } 1396 1397 pstate_table->gfxclk_pstate.custom.min = input[1]; 1398 } else if (input[0] == 1) { 1399 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1400 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1401 input[1], dpm_context->dpm_tables.gfx_table.max); 1402 pstate_table->gfxclk_pstate.custom.max = 1403 pstate_table->gfxclk_pstate.curr.max; 1404 return -EINVAL; 1405 } 1406 1407 pstate_table->gfxclk_pstate.custom.max = input[1]; 1408 } else { 1409 return -EINVAL; 1410 } 1411 break; 1412 case PP_OD_RESTORE_DEFAULT_TABLE: 1413 if (size != 0) { 1414 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1415 return -EINVAL; 1416 } else { 1417 /* Use the default frequencies for manual and determinism mode */ 1418 min_clk = dpm_context->dpm_tables.gfx_table.min; 1419 max_clk = dpm_context->dpm_tables.gfx_table.max; 1420 1421 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1422 } 1423 break; 1424 case PP_OD_COMMIT_DPM_TABLE: 1425 if (size != 0) { 1426 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1427 return -EINVAL; 1428 } else { 1429 if (!pstate_table->gfxclk_pstate.custom.min) 1430 pstate_table->gfxclk_pstate.custom.min = 1431 pstate_table->gfxclk_pstate.curr.min; 1432 1433 if (!pstate_table->gfxclk_pstate.custom.max) 1434 pstate_table->gfxclk_pstate.custom.max = 1435 pstate_table->gfxclk_pstate.curr.max; 1436 1437 min_clk = pstate_table->gfxclk_pstate.custom.min; 1438 max_clk = pstate_table->gfxclk_pstate.custom.max; 1439 1440 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1441 } 1442 break; 1443 default: 1444 return -ENOSYS; 1445 } 1446 1447 return ret; 1448 } 1449 1450 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1451 { 1452 int ret; 1453 uint64_t feature_enabled; 1454 1455 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1456 if (ret) 1457 return false; 1458 return !!(feature_enabled & SMC_DPM_FEATURE); 1459 } 1460 1461 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1462 struct i2c_msg *msg, int num_msgs) 1463 { 1464 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 1465 struct amdgpu_device *adev = smu_i2c->adev; 1466 struct smu_context *smu = adev->powerplay.pp_handle; 1467 struct smu_table_context *smu_table = &smu->smu_table; 1468 struct smu_table *table = &smu_table->driver_table; 1469 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1470 int i, j, r, c; 1471 u16 dir; 1472 1473 if (!adev->pm.dpm_enabled) 1474 return -EBUSY; 1475 1476 req = kzalloc(sizeof(*req), GFP_KERNEL); 1477 if (!req) 1478 return -ENOMEM; 1479 1480 req->I2CcontrollerPort = smu_i2c->port; 1481 req->I2CSpeed = I2C_SPEED_FAST_400K; 1482 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1483 dir = msg[0].flags & I2C_M_RD; 1484 1485 for (c = i = 0; i < num_msgs; i++) { 1486 for (j = 0; j < msg[i].len; j++, c++) { 1487 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1488 1489 if (!(msg[i].flags & I2C_M_RD)) { 1490 /* write */ 1491 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1492 cmd->ReadWriteData = msg[i].buf[j]; 1493 } 1494 1495 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1496 /* The direction changes. 1497 */ 1498 dir = msg[i].flags & I2C_M_RD; 1499 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1500 } 1501 1502 req->NumCmds++; 1503 1504 /* 1505 * Insert STOP if we are at the last byte of either last 1506 * message for the transaction or the client explicitly 1507 * requires a STOP at this particular message. 1508 */ 1509 if ((j == msg[i].len - 1) && 1510 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1511 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1512 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1513 } 1514 } 1515 } 1516 mutex_lock(&adev->pm.mutex); 1517 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1518 mutex_unlock(&adev->pm.mutex); 1519 if (r) 1520 goto fail; 1521 1522 for (c = i = 0; i < num_msgs; i++) { 1523 if (!(msg[i].flags & I2C_M_RD)) { 1524 c += msg[i].len; 1525 continue; 1526 } 1527 for (j = 0; j < msg[i].len; j++, c++) { 1528 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1529 1530 msg[i].buf[j] = cmd->ReadWriteData; 1531 } 1532 } 1533 r = num_msgs; 1534 fail: 1535 kfree(req); 1536 return r; 1537 } 1538 1539 static u32 aldebaran_i2c_func(struct i2c_adapter *adap) 1540 { 1541 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1542 } 1543 1544 1545 static const struct i2c_algorithm aldebaran_i2c_algo = { 1546 .master_xfer = aldebaran_i2c_xfer, 1547 .functionality = aldebaran_i2c_func, 1548 }; 1549 1550 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = { 1551 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1552 .max_read_len = MAX_SW_I2C_COMMANDS, 1553 .max_write_len = MAX_SW_I2C_COMMANDS, 1554 .max_comb_1st_msg_len = 2, 1555 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1556 }; 1557 1558 static int aldebaran_i2c_control_init(struct smu_context *smu) 1559 { 1560 struct amdgpu_device *adev = smu->adev; 1561 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0]; 1562 struct i2c_adapter *control = &smu_i2c->adapter; 1563 int res; 1564 1565 smu_i2c->adev = adev; 1566 smu_i2c->port = 0; 1567 mutex_init(&smu_i2c->mutex); 1568 control->owner = THIS_MODULE; 1569 control->class = I2C_CLASS_SPD; 1570 control->dev.parent = &adev->pdev->dev; 1571 control->algo = &aldebaran_i2c_algo; 1572 snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); 1573 control->quirks = &aldebaran_i2c_control_quirks; 1574 i2c_set_adapdata(control, smu_i2c); 1575 1576 res = i2c_add_adapter(control); 1577 if (res) { 1578 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1579 goto Out_err; 1580 } 1581 1582 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1583 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1584 1585 return 0; 1586 Out_err: 1587 i2c_del_adapter(control); 1588 1589 return res; 1590 } 1591 1592 static void aldebaran_i2c_control_fini(struct smu_context *smu) 1593 { 1594 struct amdgpu_device *adev = smu->adev; 1595 int i; 1596 1597 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1598 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1599 struct i2c_adapter *control = &smu_i2c->adapter; 1600 1601 i2c_del_adapter(control); 1602 } 1603 adev->pm.ras_eeprom_i2c_bus = NULL; 1604 adev->pm.fru_eeprom_i2c_bus = NULL; 1605 } 1606 1607 static void aldebaran_get_unique_id(struct smu_context *smu) 1608 { 1609 struct amdgpu_device *adev = smu->adev; 1610 SmuMetrics_t *metrics = smu->smu_table.metrics_table; 1611 uint32_t upper32 = 0, lower32 = 0; 1612 int ret; 1613 1614 ret = smu_cmn_get_metrics_table(smu, NULL, false); 1615 if (ret) 1616 goto out; 1617 1618 upper32 = metrics->PublicSerialNumUpper32; 1619 lower32 = metrics->PublicSerialNumLower32; 1620 1621 out: 1622 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1623 if (adev->serial[0] == '\0') 1624 sprintf(adev->serial, "%016llx", adev->unique_id); 1625 } 1626 1627 static bool aldebaran_is_baco_supported(struct smu_context *smu) 1628 { 1629 /* aldebaran is not support baco */ 1630 1631 return false; 1632 } 1633 1634 static int aldebaran_set_df_cstate(struct smu_context *smu, 1635 enum pp_df_cstate state) 1636 { 1637 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1638 } 1639 1640 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) 1641 { 1642 struct amdgpu_device *adev = smu->adev; 1643 1644 /* The message only works on master die and NACK will be sent 1645 back for other dies, only send it on master die */ 1646 if (!adev->smuio.funcs->get_socket_id(adev) && 1647 !adev->smuio.funcs->get_die_id(adev)) 1648 return smu_cmn_send_smc_msg_with_param(smu, 1649 SMU_MSG_GmiPwrDnControl, 1650 en ? 0 : 1, 1651 NULL); 1652 else 1653 return 0; 1654 } 1655 1656 static const struct throttling_logging_label { 1657 uint32_t feature_mask; 1658 const char *label; 1659 } logging_label[] = { 1660 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1661 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1662 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1663 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1664 }; 1665 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1666 { 1667 int ret; 1668 int throttler_idx, throtting_events = 0, buf_idx = 0; 1669 struct amdgpu_device *adev = smu->adev; 1670 uint32_t throttler_status; 1671 char log_buf[256]; 1672 1673 ret = aldebaran_get_smu_metrics_data(smu, 1674 METRICS_THROTTLER_STATUS, 1675 &throttler_status); 1676 if (ret) 1677 return; 1678 1679 memset(log_buf, 0, sizeof(log_buf)); 1680 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1681 throttler_idx++) { 1682 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1683 throtting_events++; 1684 buf_idx += snprintf(log_buf + buf_idx, 1685 sizeof(log_buf) - buf_idx, 1686 "%s%s", 1687 throtting_events > 1 ? " and " : "", 1688 logging_label[throttler_idx].label); 1689 if (buf_idx >= sizeof(log_buf)) { 1690 dev_err(adev->dev, "buffer overflow!\n"); 1691 log_buf[sizeof(log_buf) - 1] = '\0'; 1692 break; 1693 } 1694 } 1695 } 1696 1697 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1698 log_buf); 1699 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 1700 smu_cmn_get_indep_throttler_status(throttler_status, 1701 aldebaran_throttler_map)); 1702 } 1703 1704 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1705 { 1706 struct amdgpu_device *adev = smu->adev; 1707 uint32_t esm_ctrl; 1708 1709 /* TODO: confirm this on real target */ 1710 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1711 if ((esm_ctrl >> 15) & 0x1FFFF) 1712 return (((esm_ctrl >> 8) & 0x3F) + 128); 1713 1714 return smu_v13_0_get_current_pcie_link_speed(smu); 1715 } 1716 1717 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1718 void **table) 1719 { 1720 struct smu_table_context *smu_table = &smu->smu_table; 1721 struct gpu_metrics_v1_3 *gpu_metrics = 1722 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1723 SmuMetrics_t metrics; 1724 int i, ret = 0; 1725 1726 ret = smu_cmn_get_metrics_table(smu, 1727 &metrics, 1728 true); 1729 if (ret) 1730 return ret; 1731 1732 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1733 1734 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1735 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1736 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1737 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1738 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1739 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1740 1741 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1742 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1743 gpu_metrics->average_mm_activity = 0; 1744 1745 /* Valid power data is available only from primary die */ 1746 if (aldebaran_is_primary(smu)) { 1747 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1748 gpu_metrics->energy_accumulator = 1749 (uint64_t)metrics.EnergyAcc64bitHigh << 32 | 1750 metrics.EnergyAcc64bitLow; 1751 } else { 1752 gpu_metrics->average_socket_power = 0; 1753 gpu_metrics->energy_accumulator = 0; 1754 } 1755 1756 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1757 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1758 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1759 gpu_metrics->average_vclk0_frequency = 0; 1760 gpu_metrics->average_dclk0_frequency = 0; 1761 1762 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1763 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1764 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1765 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1766 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1767 1768 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1769 gpu_metrics->indep_throttle_status = 1770 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1771 aldebaran_throttler_map); 1772 1773 gpu_metrics->current_fan_speed = 0; 1774 1775 gpu_metrics->pcie_link_width = 1776 smu_v13_0_get_current_pcie_link_width(smu); 1777 gpu_metrics->pcie_link_speed = 1778 aldebaran_get_current_pcie_link_speed(smu); 1779 1780 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1781 1782 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1783 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1784 1785 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1786 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1787 1788 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) | 1789 metrics.TimeStampLow; 1790 1791 *table = (void *)gpu_metrics; 1792 1793 return sizeof(struct gpu_metrics_v1_3); 1794 } 1795 1796 static int aldebaran_check_ecc_table_support(struct smu_context *smu) 1797 { 1798 uint32_t if_version = 0xff, smu_version = 0xff; 1799 int ret = 0; 1800 1801 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 1802 if (ret) { 1803 /* return not support if failed get smu_version */ 1804 ret = -EOPNOTSUPP; 1805 } 1806 1807 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) 1808 ret = -EOPNOTSUPP; 1809 1810 return ret; 1811 } 1812 1813 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, 1814 void *table) 1815 { 1816 struct smu_table_context *smu_table = &smu->smu_table; 1817 EccInfoTable_t *ecc_table = NULL; 1818 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 1819 int i, ret = 0; 1820 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 1821 1822 ret = aldebaran_check_ecc_table_support(smu); 1823 if (ret) 1824 return ret; 1825 1826 ret = smu_cmn_update_table(smu, 1827 SMU_TABLE_ECCINFO, 1828 0, 1829 smu_table->ecc_table, 1830 false); 1831 if (ret) { 1832 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 1833 return ret; 1834 } 1835 1836 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 1837 1838 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1839 ecc_info_per_channel = &(eccinfo->ecc[i]); 1840 ecc_info_per_channel->ce_count_lo_chip = 1841 ecc_table->EccInfo[i].ce_count_lo_chip; 1842 ecc_info_per_channel->ce_count_hi_chip = 1843 ecc_table->EccInfo[i].ce_count_hi_chip; 1844 ecc_info_per_channel->mca_umc_status = 1845 ecc_table->EccInfo[i].mca_umc_status; 1846 ecc_info_per_channel->mca_umc_addr = 1847 ecc_table->EccInfo[i].mca_umc_addr; 1848 } 1849 1850 return ret; 1851 } 1852 1853 static int aldebaran_mode1_reset(struct smu_context *smu) 1854 { 1855 u32 smu_version, fatal_err, param; 1856 int ret = 0; 1857 struct amdgpu_device *adev = smu->adev; 1858 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1859 1860 fatal_err = 0; 1861 param = SMU_RESET_MODE_1; 1862 1863 /* 1864 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 1865 */ 1866 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1867 if (smu_version < 0x00440700) { 1868 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1869 } 1870 else { 1871 /* fatal error triggered by ras, PMFW supports the flag 1872 from 68.44.0 */ 1873 if ((smu_version >= 0x00442c00) && ras && 1874 atomic_read(&ras->in_recovery)) 1875 fatal_err = 1; 1876 1877 param |= (fatal_err << 16); 1878 ret = smu_cmn_send_smc_msg_with_param(smu, 1879 SMU_MSG_GfxDeviceDriverReset, param, NULL); 1880 } 1881 1882 if (!ret) 1883 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 1884 1885 return ret; 1886 } 1887 1888 static int aldebaran_mode2_reset(struct smu_context *smu) 1889 { 1890 u32 smu_version; 1891 int ret = 0, index; 1892 struct amdgpu_device *adev = smu->adev; 1893 int timeout = 10; 1894 1895 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1896 1897 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1898 SMU_MSG_GfxDeviceDriverReset); 1899 1900 mutex_lock(&smu->message_lock); 1901 if (smu_version >= 0x00441400) { 1902 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1903 /* This is similar to FLR, wait till max FLR timeout */ 1904 msleep(100); 1905 dev_dbg(smu->adev->dev, "restore config space...\n"); 1906 /* Restore the config space saved during init */ 1907 amdgpu_device_load_pci_state(adev->pdev); 1908 1909 dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1910 while (ret == -ETIME && timeout) { 1911 ret = smu_cmn_wait_for_response(smu); 1912 /* Wait a bit more time for getting ACK */ 1913 if (ret == -ETIME) { 1914 --timeout; 1915 usleep_range(500, 1000); 1916 continue; 1917 } 1918 1919 if (ret != 1) { 1920 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n", 1921 SMU_RESET_MODE_2, ret); 1922 goto out; 1923 } 1924 } 1925 1926 } else { 1927 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", 1928 smu_version); 1929 } 1930 1931 if (ret == 1) 1932 ret = 0; 1933 out: 1934 mutex_unlock(&smu->message_lock); 1935 1936 return ret; 1937 } 1938 1939 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 1940 { 1941 int ret = 0; 1942 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL); 1943 1944 return ret; 1945 } 1946 1947 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1948 { 1949 #if 0 1950 struct amdgpu_device *adev = smu->adev; 1951 u32 smu_version; 1952 uint32_t val; 1953 /** 1954 * PM FW version support mode1 reset from 68.07 1955 */ 1956 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1957 if ((smu_version < 0x00440700)) 1958 return false; 1959 /** 1960 * mode1 reset relies on PSP, so we should check if 1961 * PSP is alive. 1962 */ 1963 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1964 1965 return val != 0x0; 1966 #endif 1967 return true; 1968 } 1969 1970 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 1971 { 1972 return true; 1973 } 1974 1975 static int aldebaran_set_mp1_state(struct smu_context *smu, 1976 enum pp_mp1_state mp1_state) 1977 { 1978 switch (mp1_state) { 1979 case PP_MP1_STATE_UNLOAD: 1980 return smu_cmn_set_mp1_state(smu, mp1_state); 1981 default: 1982 return 0; 1983 } 1984 } 1985 1986 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, 1987 uint32_t size) 1988 { 1989 int ret = 0; 1990 1991 /* message SMU to update the bad page number on SMUBUS */ 1992 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL); 1993 if (ret) 1994 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n", 1995 __func__); 1996 1997 return ret; 1998 } 1999 2000 static const struct pptable_funcs aldebaran_ppt_funcs = { 2001 /* init dpm */ 2002 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 2003 /* dpm/clk tables */ 2004 .set_default_dpm_table = aldebaran_set_default_dpm_table, 2005 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 2006 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 2007 .print_clk_levels = aldebaran_print_clk_levels, 2008 .force_clk_levels = aldebaran_force_clk_levels, 2009 .read_sensor = aldebaran_read_sensor, 2010 .set_performance_level = aldebaran_set_performance_level, 2011 .get_power_limit = aldebaran_get_power_limit, 2012 .is_dpm_running = aldebaran_is_dpm_running, 2013 .get_unique_id = aldebaran_get_unique_id, 2014 .init_microcode = smu_v13_0_init_microcode, 2015 .load_microcode = smu_v13_0_load_microcode, 2016 .fini_microcode = smu_v13_0_fini_microcode, 2017 .init_smc_tables = aldebaran_init_smc_tables, 2018 .fini_smc_tables = smu_v13_0_fini_smc_tables, 2019 .init_power = smu_v13_0_init_power, 2020 .fini_power = smu_v13_0_fini_power, 2021 .check_fw_status = smu_v13_0_check_fw_status, 2022 /* pptable related */ 2023 .setup_pptable = aldebaran_setup_pptable, 2024 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 2025 .check_fw_version = smu_v13_0_check_fw_version, 2026 .write_pptable = smu_cmn_write_pptable, 2027 .set_driver_table_location = smu_v13_0_set_driver_table_location, 2028 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2029 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2030 .system_features_control = aldebaran_system_features_control, 2031 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2032 .send_smc_msg = smu_cmn_send_smc_msg, 2033 .get_enabled_mask = smu_cmn_get_enabled_mask, 2034 .feature_is_enabled = smu_cmn_feature_is_enabled, 2035 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2036 .set_power_limit = aldebaran_set_power_limit, 2037 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 2038 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2039 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2040 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 2041 .register_irq_handler = smu_v13_0_register_irq_handler, 2042 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 2043 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 2044 .baco_is_support= aldebaran_is_baco_supported, 2045 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 2046 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 2047 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 2048 .set_df_cstate = aldebaran_set_df_cstate, 2049 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down, 2050 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 2051 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2052 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2053 .get_gpu_metrics = aldebaran_get_gpu_metrics, 2054 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 2055 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 2056 .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr, 2057 .mode1_reset = aldebaran_mode1_reset, 2058 .set_mp1_state = aldebaran_set_mp1_state, 2059 .mode2_reset = aldebaran_mode2_reset, 2060 .wait_for_event = smu_v13_0_wait_for_event, 2061 .i2c_init = aldebaran_i2c_control_init, 2062 .i2c_fini = aldebaran_i2c_control_fini, 2063 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num, 2064 .get_ecc_info = aldebaran_get_ecc_info, 2065 }; 2066 2067 void aldebaran_set_ppt_funcs(struct smu_context *smu) 2068 { 2069 smu->ppt_funcs = &aldebaran_ppt_funcs; 2070 smu->message_map = aldebaran_message_map; 2071 smu->clock_map = aldebaran_clk_map; 2072 smu->feature_map = aldebaran_feature_mask_map; 2073 smu->table_map = aldebaran_table_map; 2074 } 2075