1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_smu.h" 29 #include "atomfirmware.h" 30 #include "amdgpu_atomfirmware.h" 31 #include "amdgpu_atombios.h" 32 #include "smu_v13_0.h" 33 #include "smu13_driver_if_aldebaran.h" 34 #include "soc15_common.h" 35 #include "atom.h" 36 #include "power_state.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 63 [smu_feature] = {1, (aldebaran_feature)} 64 65 #define FEATURE_MASK(feature) (1ULL << feature) 66 #define SMC_DPM_FEATURE ( \ 67 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 68 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 73 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 74 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 75 76 /* possible frequency drift (1Mhz) */ 77 #define EPSILON 1 78 79 #define smnPCIE_ESM_CTRL 0x111003D0 80 81 #define CLOCK_VALID (1 << 31) 82 83 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 84 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 85 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 86 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 87 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 88 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 89 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0), 90 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0), 91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 98 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 99 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 107 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 108 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 109 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 110 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 111 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 112 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 113 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 114 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 115 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 116 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 117 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 118 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 119 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 120 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 121 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 122 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 123 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 124 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 125 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 126 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 127 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 128 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 129 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 130 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 131 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 132 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 133 }; 134 135 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 136 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 137 CLK_MAP(SCLK, PPCLK_GFXCLK), 138 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 139 CLK_MAP(FCLK, PPCLK_FCLK), 140 CLK_MAP(UCLK, PPCLK_UCLK), 141 CLK_MAP(MCLK, PPCLK_UCLK), 142 CLK_MAP(DCLK, PPCLK_DCLK), 143 CLK_MAP(VCLK, PPCLK_VCLK), 144 CLK_MAP(LCLK, PPCLK_LCLK), 145 }; 146 147 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 148 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_PREFETCHER_BIT, FEATURE_DATA_CALCULATIONS), 149 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 150 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 151 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 152 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 153 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 154 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 155 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 156 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 157 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 158 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 159 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 160 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 161 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT), 162 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 163 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 164 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 165 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 166 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 167 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 168 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 169 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 170 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 175 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 176 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN), 177 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 178 }; 179 180 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 181 TAB_MAP(PPTABLE), 182 TAB_MAP(AVFS_PSM_DEBUG), 183 TAB_MAP(AVFS_FUSE_OVERRIDE), 184 TAB_MAP(PMSTATUSLOG), 185 TAB_MAP(SMU_METRICS), 186 TAB_MAP(DRIVER_SMU_CONFIG), 187 TAB_MAP(I2C_COMMANDS), 188 }; 189 190 static int aldebaran_tables_init(struct smu_context *smu) 191 { 192 struct smu_table_context *smu_table = &smu->smu_table; 193 struct smu_table *tables = smu_table->tables; 194 195 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 196 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 197 198 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 199 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 200 201 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 202 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 203 204 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 205 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 206 207 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 208 if (!smu_table->metrics_table) 209 return -ENOMEM; 210 smu_table->metrics_time = 0; 211 212 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); 213 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 214 if (!smu_table->gpu_metrics_table) { 215 kfree(smu_table->metrics_table); 216 return -ENOMEM; 217 } 218 219 return 0; 220 } 221 222 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 223 { 224 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 225 226 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 227 GFP_KERNEL); 228 if (!smu_dpm->dpm_context) 229 return -ENOMEM; 230 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 231 232 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state), 233 GFP_KERNEL); 234 if (!smu_dpm->dpm_current_power_state) 235 return -ENOMEM; 236 237 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state), 238 GFP_KERNEL); 239 if (!smu_dpm->dpm_request_power_state) 240 return -ENOMEM; 241 242 return 0; 243 } 244 245 static int aldebaran_init_smc_tables(struct smu_context *smu) 246 { 247 int ret = 0; 248 249 ret = aldebaran_tables_init(smu); 250 if (ret) 251 return ret; 252 253 ret = aldebaran_allocate_dpm_context(smu); 254 if (ret) 255 return ret; 256 257 return smu_v13_0_init_smc_tables(smu); 258 } 259 260 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 261 uint32_t *feature_mask, uint32_t num) 262 { 263 if (num > 2) 264 return -EINVAL; 265 266 /* pptable will handle the features to enable */ 267 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 268 269 return 0; 270 } 271 272 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 273 { 274 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 275 struct smu_13_0_dpm_table *dpm_table = NULL; 276 PPTable_t *pptable = smu->smu_table.driver_pptable; 277 int ret = 0; 278 279 /* socclk dpm table setup */ 280 dpm_table = &dpm_context->dpm_tables.soc_table; 281 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 282 ret = smu_v13_0_set_single_dpm_table(smu, 283 SMU_SOCCLK, 284 dpm_table); 285 if (ret) 286 return ret; 287 } else { 288 dpm_table->count = 1; 289 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 290 dpm_table->dpm_levels[0].enabled = true; 291 dpm_table->min = dpm_table->dpm_levels[0].value; 292 dpm_table->max = dpm_table->dpm_levels[0].value; 293 } 294 295 /* gfxclk dpm table setup */ 296 dpm_table = &dpm_context->dpm_tables.gfx_table; 297 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 298 /* in the case of gfxclk, only fine-grained dpm is honored */ 299 dpm_table->count = 2; 300 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 301 dpm_table->dpm_levels[0].enabled = true; 302 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 303 dpm_table->dpm_levels[1].enabled = true; 304 dpm_table->min = dpm_table->dpm_levels[0].value; 305 dpm_table->max = dpm_table->dpm_levels[1].value; 306 } else { 307 dpm_table->count = 1; 308 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 309 dpm_table->dpm_levels[0].enabled = true; 310 dpm_table->min = dpm_table->dpm_levels[0].value; 311 dpm_table->max = dpm_table->dpm_levels[0].value; 312 } 313 314 /* memclk dpm table setup */ 315 dpm_table = &dpm_context->dpm_tables.uclk_table; 316 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 317 ret = smu_v13_0_set_single_dpm_table(smu, 318 SMU_UCLK, 319 dpm_table); 320 if (ret) 321 return ret; 322 } else { 323 dpm_table->count = 1; 324 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 325 dpm_table->dpm_levels[0].enabled = true; 326 dpm_table->min = dpm_table->dpm_levels[0].value; 327 dpm_table->max = dpm_table->dpm_levels[0].value; 328 } 329 330 /* fclk dpm table setup */ 331 dpm_table = &dpm_context->dpm_tables.fclk_table; 332 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 333 ret = smu_v13_0_set_single_dpm_table(smu, 334 SMU_FCLK, 335 dpm_table); 336 if (ret) 337 return ret; 338 } else { 339 dpm_table->count = 1; 340 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 341 dpm_table->dpm_levels[0].enabled = true; 342 dpm_table->min = dpm_table->dpm_levels[0].value; 343 dpm_table->max = dpm_table->dpm_levels[0].value; 344 } 345 346 return 0; 347 } 348 349 static int aldebaran_check_powerplay_table(struct smu_context *smu) 350 { 351 struct smu_table_context *table_context = &smu->smu_table; 352 struct smu_13_0_powerplay_table *powerplay_table = 353 table_context->power_play_table; 354 struct smu_baco_context *smu_baco = &smu->smu_baco; 355 356 mutex_lock(&smu_baco->mutex); 357 if (powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_BACO || 358 powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_MACO) 359 smu_baco->platform_support = true; 360 mutex_unlock(&smu_baco->mutex); 361 362 table_context->thermal_controller_type = 363 powerplay_table->thermal_controller_type; 364 365 return 0; 366 } 367 368 static int aldebaran_store_powerplay_table(struct smu_context *smu) 369 { 370 struct smu_table_context *table_context = &smu->smu_table; 371 struct smu_13_0_powerplay_table *powerplay_table = 372 table_context->power_play_table; 373 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 374 sizeof(PPTable_t)); 375 376 return 0; 377 } 378 379 static int aldebaran_append_powerplay_table(struct smu_context *smu) 380 { 381 struct smu_table_context *table_context = &smu->smu_table; 382 PPTable_t *smc_pptable = table_context->driver_pptable; 383 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 384 int index, ret; 385 386 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 387 smc_dpm_info); 388 389 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 390 (uint8_t **)&smc_dpm_table); 391 if (ret) 392 return ret; 393 394 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 395 smc_dpm_table->table_header.format_revision, 396 smc_dpm_table->table_header.content_revision); 397 398 if ((smc_dpm_table->table_header.format_revision == 4) && 399 (smc_dpm_table->table_header.content_revision == 10)) 400 memcpy(&smc_pptable->GfxMaxCurrent, 401 &smc_dpm_table->GfxMaxCurrent, 402 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_10, GfxMaxCurrent)); 403 return 0; 404 } 405 406 static int aldebaran_setup_pptable(struct smu_context *smu) 407 { 408 int ret = 0; 409 410 /* VBIOS pptable is the first choice */ 411 smu->smu_table.boot_values.pp_table_id = 0; 412 413 ret = smu_v13_0_setup_pptable(smu); 414 if (ret) 415 return ret; 416 417 ret = aldebaran_store_powerplay_table(smu); 418 if (ret) 419 return ret; 420 421 ret = aldebaran_append_powerplay_table(smu); 422 if (ret) 423 return ret; 424 425 ret = aldebaran_check_powerplay_table(smu); 426 if (ret) 427 return ret; 428 429 return ret; 430 } 431 432 static int aldebaran_run_btc(struct smu_context *smu) 433 { 434 int ret; 435 436 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 437 if (ret) 438 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 439 440 return ret; 441 } 442 443 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 444 { 445 struct smu_13_0_dpm_context *dpm_context = 446 smu->smu_dpm.dpm_context; 447 struct smu_13_0_dpm_table *gfx_table = 448 &dpm_context->dpm_tables.gfx_table; 449 struct smu_13_0_dpm_table *mem_table = 450 &dpm_context->dpm_tables.uclk_table; 451 struct smu_13_0_dpm_table *soc_table = 452 &dpm_context->dpm_tables.soc_table; 453 struct smu_umd_pstate_table *pstate_table = 454 &smu->pstate_table; 455 456 pstate_table->gfxclk_pstate.min = gfx_table->min; 457 pstate_table->gfxclk_pstate.peak = gfx_table->max; 458 459 pstate_table->uclk_pstate.min = mem_table->min; 460 pstate_table->uclk_pstate.peak = mem_table->max; 461 462 pstate_table->socclk_pstate.min = soc_table->min; 463 pstate_table->socclk_pstate.peak = soc_table->max; 464 465 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 466 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 467 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 468 pstate_table->gfxclk_pstate.standard = 469 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 470 pstate_table->uclk_pstate.standard = 471 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 472 pstate_table->socclk_pstate.standard = 473 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 474 } else { 475 pstate_table->gfxclk_pstate.standard = 476 pstate_table->gfxclk_pstate.min; 477 pstate_table->uclk_pstate.standard = 478 pstate_table->uclk_pstate.min; 479 pstate_table->socclk_pstate.standard = 480 pstate_table->socclk_pstate.min; 481 } 482 483 return 0; 484 } 485 486 static int aldebaran_get_clk_table(struct smu_context *smu, 487 struct pp_clock_levels_with_latency *clocks, 488 struct smu_13_0_dpm_table *dpm_table) 489 { 490 int i, count; 491 492 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 493 clocks->num_levels = count; 494 495 for (i = 0; i < count; i++) { 496 clocks->data[i].clocks_in_khz = 497 dpm_table->dpm_levels[i].value * 1000; 498 clocks->data[i].latency_in_us = 0; 499 } 500 501 return 0; 502 } 503 504 static int aldebaran_freqs_in_same_level(int32_t frequency1, 505 int32_t frequency2) 506 { 507 return (abs(frequency1 - frequency2) <= EPSILON); 508 } 509 510 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 511 MetricsMember_t member, 512 uint32_t *value) 513 { 514 struct smu_table_context *smu_table= &smu->smu_table; 515 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 516 int ret = 0; 517 518 mutex_lock(&smu->metrics_lock); 519 520 ret = smu_cmn_get_metrics_table_locked(smu, 521 NULL, 522 false); 523 if (ret) { 524 mutex_unlock(&smu->metrics_lock); 525 return ret; 526 } 527 528 switch (member) { 529 case METRICS_CURR_GFXCLK: 530 *value = metrics->CurrClock[PPCLK_GFXCLK]; 531 break; 532 case METRICS_CURR_SOCCLK: 533 *value = metrics->CurrClock[PPCLK_SOCCLK]; 534 break; 535 case METRICS_CURR_UCLK: 536 *value = metrics->CurrClock[PPCLK_UCLK]; 537 break; 538 case METRICS_CURR_VCLK: 539 *value = metrics->CurrClock[PPCLK_VCLK]; 540 break; 541 case METRICS_CURR_DCLK: 542 *value = metrics->CurrClock[PPCLK_DCLK]; 543 break; 544 case METRICS_CURR_FCLK: 545 *value = metrics->CurrClock[PPCLK_FCLK]; 546 break; 547 case METRICS_AVERAGE_GFXCLK: 548 *value = metrics->AverageGfxclkFrequency; 549 break; 550 case METRICS_AVERAGE_SOCCLK: 551 *value = metrics->AverageSocclkFrequency; 552 break; 553 case METRICS_AVERAGE_UCLK: 554 *value = metrics->AverageUclkFrequency; 555 break; 556 case METRICS_AVERAGE_GFXACTIVITY: 557 *value = metrics->AverageGfxActivity; 558 break; 559 case METRICS_AVERAGE_MEMACTIVITY: 560 *value = metrics->AverageUclkActivity; 561 break; 562 case METRICS_AVERAGE_SOCKETPOWER: 563 *value = metrics->AverageSocketPower << 8; 564 break; 565 case METRICS_TEMPERATURE_EDGE: 566 *value = metrics->TemperatureEdge * 567 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 568 break; 569 case METRICS_TEMPERATURE_HOTSPOT: 570 *value = metrics->TemperatureHotspot * 571 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 572 break; 573 case METRICS_TEMPERATURE_MEM: 574 *value = metrics->TemperatureHBM * 575 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 576 break; 577 case METRICS_TEMPERATURE_VRGFX: 578 *value = metrics->TemperatureVrGfx * 579 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 580 break; 581 case METRICS_TEMPERATURE_VRSOC: 582 *value = metrics->TemperatureVrSoc * 583 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 584 break; 585 case METRICS_TEMPERATURE_VRMEM: 586 *value = metrics->TemperatureVrMem * 587 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 588 break; 589 case METRICS_THROTTLER_STATUS: 590 *value = metrics->ThrottlerStatus; 591 break; 592 default: 593 *value = UINT_MAX; 594 break; 595 } 596 597 mutex_unlock(&smu->metrics_lock); 598 599 return ret; 600 } 601 602 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 603 enum smu_clk_type clk_type, 604 uint32_t *value) 605 { 606 MetricsMember_t member_type; 607 int clk_id = 0; 608 609 if (!value) 610 return -EINVAL; 611 612 clk_id = smu_cmn_to_asic_specific_index(smu, 613 CMN2ASIC_MAPPING_CLK, 614 clk_type); 615 if (clk_id < 0) 616 return -EINVAL; 617 618 switch (clk_id) { 619 case PPCLK_GFXCLK: 620 /* 621 * CurrClock[clk_id] can provide accurate 622 * output only when the dpm feature is enabled. 623 * We can use Average_* for dpm disabled case. 624 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 625 */ 626 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 627 member_type = METRICS_CURR_GFXCLK; 628 else 629 member_type = METRICS_AVERAGE_GFXCLK; 630 break; 631 case PPCLK_UCLK: 632 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 633 member_type = METRICS_CURR_UCLK; 634 else 635 member_type = METRICS_AVERAGE_UCLK; 636 break; 637 case PPCLK_SOCCLK: 638 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 639 member_type = METRICS_CURR_SOCCLK; 640 else 641 member_type = METRICS_AVERAGE_SOCCLK; 642 break; 643 case PPCLK_VCLK: 644 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 645 member_type = METRICS_CURR_VCLK; 646 else 647 member_type = METRICS_AVERAGE_VCLK; 648 break; 649 case PPCLK_DCLK: 650 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 651 member_type = METRICS_CURR_DCLK; 652 else 653 member_type = METRICS_AVERAGE_DCLK; 654 break; 655 case PPCLK_FCLK: 656 member_type = METRICS_CURR_FCLK; 657 break; 658 default: 659 return -EINVAL; 660 } 661 662 return aldebaran_get_smu_metrics_data(smu, 663 member_type, 664 value); 665 } 666 667 static int aldebaran_print_clk_levels(struct smu_context *smu, 668 enum smu_clk_type type, char *buf) 669 { 670 int i, now, size = 0; 671 int ret = 0; 672 struct pp_clock_levels_with_latency clocks; 673 struct smu_13_0_dpm_table *single_dpm_table; 674 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 675 struct smu_13_0_dpm_context *dpm_context = NULL; 676 uint32_t display_levels; 677 uint32_t freq_values[3] = {0}; 678 uint32_t min_clk, max_clk; 679 680 if (amdgpu_ras_intr_triggered()) 681 return snprintf(buf, PAGE_SIZE, "unavailable\n"); 682 683 dpm_context = smu_dpm->dpm_context; 684 685 switch (type) { 686 687 case SMU_OD_SCLK: 688 size = sprintf(buf, "%s:\n", "GFXCLK"); 689 fallthrough; 690 case SMU_SCLK: 691 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 692 if (ret) { 693 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 694 return ret; 695 } 696 697 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 698 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 699 if (ret) { 700 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 701 return ret; 702 } 703 704 display_levels = clocks.num_levels; 705 706 min_clk = smu->gfx_actual_hard_min_freq & CLOCK_VALID ? 707 smu->gfx_actual_hard_min_freq & ~CLOCK_VALID : 708 single_dpm_table->dpm_levels[0].value; 709 max_clk = smu->gfx_actual_soft_max_freq & CLOCK_VALID ? 710 smu->gfx_actual_soft_max_freq & ~CLOCK_VALID : 711 single_dpm_table->dpm_levels[1].value; 712 713 freq_values[0] = min_clk; 714 freq_values[1] = max_clk; 715 716 /* fine-grained dpm has only 2 levels */ 717 if (now > min_clk && now < max_clk) { 718 display_levels = clocks.num_levels + 1; 719 freq_values[2] = max_clk; 720 freq_values[1] = now; 721 } 722 723 /* 724 * For DPM disabled case, there will be only one clock level. 725 * And it's safe to assume that is always the current clock. 726 */ 727 if (display_levels == clocks.num_levels) { 728 for (i = 0; i < clocks.num_levels; i++) 729 size += sprintf( 730 buf + size, "%d: %uMhz %s\n", i, 731 freq_values[i], 732 (clocks.num_levels == 1) ? 733 "*" : 734 (aldebaran_freqs_in_same_level( 735 freq_values[i], now) ? 736 "*" : 737 "")); 738 } else { 739 for (i = 0; i < display_levels; i++) 740 size += sprintf(buf + size, "%d: %uMhz %s\n", i, 741 freq_values[i], i == 1 ? "*" : ""); 742 } 743 744 break; 745 746 case SMU_OD_MCLK: 747 size = sprintf(buf, "%s:\n", "MCLK"); 748 fallthrough; 749 case SMU_MCLK: 750 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 751 if (ret) { 752 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 753 return ret; 754 } 755 756 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 757 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 758 if (ret) { 759 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 760 return ret; 761 } 762 763 for (i = 0; i < clocks.num_levels; i++) 764 size += sprintf(buf + size, "%d: %uMhz %s\n", 765 i, clocks.data[i].clocks_in_khz / 1000, 766 (clocks.num_levels == 1) ? "*" : 767 (aldebaran_freqs_in_same_level( 768 clocks.data[i].clocks_in_khz / 1000, 769 now) ? "*" : "")); 770 break; 771 772 case SMU_SOCCLK: 773 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 774 if (ret) { 775 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 776 return ret; 777 } 778 779 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 780 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 781 if (ret) { 782 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 783 return ret; 784 } 785 786 for (i = 0; i < clocks.num_levels; i++) 787 size += sprintf(buf + size, "%d: %uMhz %s\n", 788 i, clocks.data[i].clocks_in_khz / 1000, 789 (clocks.num_levels == 1) ? "*" : 790 (aldebaran_freqs_in_same_level( 791 clocks.data[i].clocks_in_khz / 1000, 792 now) ? "*" : "")); 793 break; 794 795 case SMU_FCLK: 796 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 797 if (ret) { 798 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 799 return ret; 800 } 801 802 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 803 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 804 if (ret) { 805 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 806 return ret; 807 } 808 809 for (i = 0; i < single_dpm_table->count; i++) 810 size += sprintf(buf + size, "%d: %uMhz %s\n", 811 i, single_dpm_table->dpm_levels[i].value, 812 (clocks.num_levels == 1) ? "*" : 813 (aldebaran_freqs_in_same_level( 814 clocks.data[i].clocks_in_khz / 1000, 815 now) ? "*" : "")); 816 break; 817 818 default: 819 break; 820 } 821 822 return size; 823 } 824 825 static int aldebaran_upload_dpm_level(struct smu_context *smu, 826 bool max, 827 uint32_t feature_mask, 828 uint32_t level) 829 { 830 struct smu_13_0_dpm_context *dpm_context = 831 smu->smu_dpm.dpm_context; 832 uint32_t freq; 833 int ret = 0; 834 835 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 836 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 837 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 838 ret = smu_cmn_send_smc_msg_with_param(smu, 839 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 840 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 841 NULL); 842 if (ret) { 843 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 844 max ? "max" : "min"); 845 return ret; 846 } 847 } 848 849 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 850 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 851 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 852 ret = smu_cmn_send_smc_msg_with_param(smu, 853 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 854 (PPCLK_UCLK << 16) | (freq & 0xffff), 855 NULL); 856 if (ret) { 857 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 858 max ? "max" : "min"); 859 return ret; 860 } 861 } 862 863 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 864 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 865 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 866 ret = smu_cmn_send_smc_msg_with_param(smu, 867 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 868 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 869 NULL); 870 if (ret) { 871 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 872 max ? "max" : "min"); 873 return ret; 874 } 875 } 876 877 return ret; 878 } 879 880 static int aldebaran_force_clk_levels(struct smu_context *smu, 881 enum smu_clk_type type, uint32_t mask) 882 { 883 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 884 struct smu_13_0_dpm_table *single_dpm_table = NULL; 885 uint32_t soft_min_level, soft_max_level; 886 int ret = 0; 887 888 soft_min_level = mask ? (ffs(mask) - 1) : 0; 889 soft_max_level = mask ? (fls(mask) - 1) : 0; 890 891 switch (type) { 892 case SMU_SCLK: 893 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 894 if (soft_max_level >= single_dpm_table->count) { 895 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 896 soft_max_level, single_dpm_table->count - 1); 897 ret = -EINVAL; 898 break; 899 } 900 901 ret = aldebaran_upload_dpm_level(smu, 902 false, 903 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 904 soft_min_level); 905 if (ret) { 906 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 907 break; 908 } 909 910 ret = aldebaran_upload_dpm_level(smu, 911 true, 912 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 913 soft_max_level); 914 if (ret) 915 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 916 917 break; 918 919 case SMU_MCLK: 920 case SMU_SOCCLK: 921 case SMU_FCLK: 922 /* 923 * Should not arrive here since aldebaran does not 924 * support mclk/socclk/fclk softmin/softmax settings 925 */ 926 ret = -EINVAL; 927 break; 928 929 default: 930 break; 931 } 932 933 return ret; 934 } 935 936 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 937 struct smu_temperature_range *range) 938 { 939 struct smu_table_context *table_context = &smu->smu_table; 940 struct smu_13_0_powerplay_table *powerplay_table = 941 table_context->power_play_table; 942 PPTable_t *pptable = smu->smu_table.driver_pptable; 943 944 if (!range) 945 return -EINVAL; 946 947 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 948 949 range->hotspot_crit_max = pptable->ThotspotLimit * 950 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 951 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 952 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 953 range->mem_crit_max = pptable->TmemLimit * 954 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 955 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 956 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 957 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 958 959 return 0; 960 } 961 962 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 963 enum amd_pp_sensors sensor, 964 uint32_t *value) 965 { 966 int ret = 0; 967 968 if (!value) 969 return -EINVAL; 970 971 switch (sensor) { 972 case AMDGPU_PP_SENSOR_GPU_LOAD: 973 ret = aldebaran_get_smu_metrics_data(smu, 974 METRICS_AVERAGE_GFXACTIVITY, 975 value); 976 break; 977 case AMDGPU_PP_SENSOR_MEM_LOAD: 978 ret = aldebaran_get_smu_metrics_data(smu, 979 METRICS_AVERAGE_MEMACTIVITY, 980 value); 981 break; 982 default: 983 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 984 return -EINVAL; 985 } 986 987 return ret; 988 } 989 990 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value) 991 { 992 if (!value) 993 return -EINVAL; 994 995 return aldebaran_get_smu_metrics_data(smu, 996 METRICS_AVERAGE_SOCKETPOWER, 997 value); 998 } 999 1000 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 1001 enum amd_pp_sensors sensor, 1002 uint32_t *value) 1003 { 1004 int ret = 0; 1005 1006 if (!value) 1007 return -EINVAL; 1008 1009 switch (sensor) { 1010 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1011 ret = aldebaran_get_smu_metrics_data(smu, 1012 METRICS_TEMPERATURE_HOTSPOT, 1013 value); 1014 break; 1015 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1016 ret = aldebaran_get_smu_metrics_data(smu, 1017 METRICS_TEMPERATURE_EDGE, 1018 value); 1019 break; 1020 case AMDGPU_PP_SENSOR_MEM_TEMP: 1021 ret = aldebaran_get_smu_metrics_data(smu, 1022 METRICS_TEMPERATURE_MEM, 1023 value); 1024 break; 1025 default: 1026 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1027 return -EINVAL; 1028 } 1029 1030 return ret; 1031 } 1032 1033 static int aldebaran_read_sensor(struct smu_context *smu, 1034 enum amd_pp_sensors sensor, 1035 void *data, uint32_t *size) 1036 { 1037 int ret = 0; 1038 1039 if (amdgpu_ras_intr_triggered()) 1040 return 0; 1041 1042 if (!data || !size) 1043 return -EINVAL; 1044 1045 mutex_lock(&smu->sensor_lock); 1046 switch (sensor) { 1047 case AMDGPU_PP_SENSOR_MEM_LOAD: 1048 case AMDGPU_PP_SENSOR_GPU_LOAD: 1049 ret = aldebaran_get_current_activity_percent(smu, 1050 sensor, 1051 (uint32_t *)data); 1052 *size = 4; 1053 break; 1054 case AMDGPU_PP_SENSOR_GPU_POWER: 1055 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data); 1056 *size = 4; 1057 break; 1058 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1059 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1060 case AMDGPU_PP_SENSOR_MEM_TEMP: 1061 ret = aldebaran_thermal_get_temperature(smu, sensor, 1062 (uint32_t *)data); 1063 *size = 4; 1064 break; 1065 case AMDGPU_PP_SENSOR_GFX_MCLK: 1066 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1067 /* the output clock frequency in 10K unit */ 1068 *(uint32_t *)data *= 100; 1069 *size = 4; 1070 break; 1071 case AMDGPU_PP_SENSOR_GFX_SCLK: 1072 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1073 *(uint32_t *)data *= 100; 1074 *size = 4; 1075 break; 1076 case AMDGPU_PP_SENSOR_VDDGFX: 1077 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1078 *size = 4; 1079 break; 1080 default: 1081 ret = -EOPNOTSUPP; 1082 break; 1083 } 1084 mutex_unlock(&smu->sensor_lock); 1085 1086 return ret; 1087 } 1088 1089 static int aldebaran_get_power_limit(struct smu_context *smu) 1090 { 1091 PPTable_t *pptable = smu->smu_table.driver_pptable; 1092 uint32_t power_limit = 0; 1093 int ret; 1094 1095 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 1096 return -EINVAL; 1097 1098 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit); 1099 1100 if (ret) { 1101 /* the last hope to figure out the ppt limit */ 1102 if (!pptable) { 1103 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 1104 return -EINVAL; 1105 } 1106 power_limit = pptable->PptLimit; 1107 } 1108 1109 smu->current_power_limit = smu->default_power_limit = power_limit; 1110 if (pptable) 1111 smu->max_power_limit = pptable->PptLimit; 1112 1113 return 0; 1114 } 1115 1116 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1117 { 1118 int ret; 1119 1120 ret = smu_v13_0_system_features_control(smu, enable); 1121 if (!ret && enable) 1122 ret = aldebaran_run_btc(smu); 1123 1124 return ret; 1125 } 1126 1127 static int aldebaran_set_performance_level(struct smu_context *smu, 1128 enum amd_dpm_forced_level level) 1129 { 1130 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1131 1132 /* Disable determinism if switching to another mode */ 1133 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1134 && (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1135 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1136 1137 /* Reset user min/max gfx clock */ 1138 smu->gfx_actual_hard_min_freq = 0; 1139 smu->gfx_actual_soft_max_freq = 0; 1140 1141 switch (level) { 1142 1143 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1144 return 0; 1145 1146 case AMD_DPM_FORCED_LEVEL_HIGH: 1147 case AMD_DPM_FORCED_LEVEL_LOW: 1148 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1149 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1150 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1151 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1152 default: 1153 break; 1154 } 1155 1156 return smu_v13_0_set_performance_level(smu, level); 1157 } 1158 1159 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1160 enum smu_clk_type clk_type, 1161 uint32_t min, 1162 uint32_t max) 1163 { 1164 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1165 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1166 struct amdgpu_device *adev = smu->adev; 1167 uint32_t min_clk; 1168 uint32_t max_clk; 1169 int ret = 0; 1170 1171 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1172 return -EINVAL; 1173 1174 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1175 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1176 return -EINVAL; 1177 1178 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1179 min_clk = max(min, dpm_context->dpm_tables.gfx_table.min); 1180 max_clk = min(max, dpm_context->dpm_tables.gfx_table.max); 1181 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, 1182 min_clk, max_clk); 1183 1184 if (!ret) { 1185 smu->gfx_actual_hard_min_freq = min_clk | CLOCK_VALID; 1186 smu->gfx_actual_soft_max_freq = max_clk | CLOCK_VALID; 1187 } 1188 return ret; 1189 } 1190 1191 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1192 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1193 (max > dpm_context->dpm_tables.gfx_table.max)) { 1194 dev_warn(adev->dev, 1195 "Invalid max frequency %d MHz specified for determinism\n", max); 1196 return -EINVAL; 1197 } 1198 1199 /* Restore default min/max clocks and enable determinism */ 1200 min_clk = dpm_context->dpm_tables.gfx_table.min; 1201 max_clk = dpm_context->dpm_tables.gfx_table.max; 1202 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1203 if (!ret) { 1204 usleep_range(500, 1000); 1205 ret = smu_cmn_send_smc_msg_with_param(smu, 1206 SMU_MSG_EnableDeterminism, 1207 max, NULL); 1208 if (ret) { 1209 dev_err(adev->dev, 1210 "Failed to enable determinism at GFX clock %d MHz\n", max); 1211 } else { 1212 smu->gfx_actual_hard_min_freq = 1213 min_clk | CLOCK_VALID; 1214 smu->gfx_actual_soft_max_freq = 1215 max | CLOCK_VALID; 1216 } 1217 } 1218 } 1219 1220 return ret; 1221 } 1222 1223 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1224 long input[], uint32_t size) 1225 { 1226 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1227 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1228 uint32_t min_clk; 1229 uint32_t max_clk; 1230 int ret = 0; 1231 1232 /* Only allowed in manual or determinism mode */ 1233 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1234 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1235 return -EINVAL; 1236 1237 switch (type) { 1238 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1239 if (size != 2) { 1240 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1241 return -EINVAL; 1242 } 1243 1244 if (input[0] == 0) { 1245 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1246 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1247 input[1], dpm_context->dpm_tables.gfx_table.min); 1248 return -EINVAL; 1249 } 1250 smu->gfx_actual_hard_min_freq = input[1]; 1251 } else if (input[0] == 1) { 1252 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1253 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1254 input[1], dpm_context->dpm_tables.gfx_table.max); 1255 return -EINVAL; 1256 } 1257 smu->gfx_actual_soft_max_freq = input[1]; 1258 } else { 1259 return -EINVAL; 1260 } 1261 break; 1262 case PP_OD_RESTORE_DEFAULT_TABLE: 1263 if (size != 0) { 1264 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1265 return -EINVAL; 1266 } else { 1267 /* Use the default frequencies for manual and determinism mode */ 1268 min_clk = dpm_context->dpm_tables.gfx_table.min; 1269 max_clk = dpm_context->dpm_tables.gfx_table.max; 1270 1271 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1272 } 1273 break; 1274 case PP_OD_COMMIT_DPM_TABLE: 1275 if (size != 0) { 1276 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1277 return -EINVAL; 1278 } else { 1279 min_clk = smu->gfx_actual_hard_min_freq; 1280 max_clk = smu->gfx_actual_soft_max_freq; 1281 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1282 } 1283 break; 1284 default: 1285 return -ENOSYS; 1286 } 1287 1288 return ret; 1289 } 1290 1291 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1292 { 1293 int ret = 0; 1294 uint32_t feature_mask[2]; 1295 unsigned long feature_enabled; 1296 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1297 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 1298 ((uint64_t)feature_mask[1] << 32)); 1299 return !!(feature_enabled & SMC_DPM_FEATURE); 1300 } 1301 1302 static void aldebaran_fill_i2c_req(SwI2cRequest_t *req, bool write, 1303 uint8_t address, uint32_t numbytes, 1304 uint8_t *data) 1305 { 1306 int i; 1307 1308 req->I2CcontrollerPort = 0; 1309 req->I2CSpeed = 2; 1310 req->SlaveAddress = address; 1311 req->NumCmds = numbytes; 1312 1313 for (i = 0; i < numbytes; i++) { 1314 SwI2cCmd_t *cmd = &req->SwI2cCmds[i]; 1315 1316 /* First 2 bytes are always write for lower 2b EEPROM address */ 1317 if (i < 2) 1318 cmd->CmdConfig = CMDCONFIG_READWRITE_MASK; 1319 else 1320 cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0; 1321 1322 1323 /* Add RESTART for read after address filled */ 1324 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0; 1325 1326 /* Add STOP in the end */ 1327 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0; 1328 1329 /* Fill with data regardless if read or write to simplify code */ 1330 cmd->ReadWriteData = data[i]; 1331 } 1332 } 1333 1334 static int aldebaran_i2c_read_data(struct i2c_adapter *control, 1335 uint8_t address, 1336 uint8_t *data, 1337 uint32_t numbytes) 1338 { 1339 uint32_t i, ret = 0; 1340 SwI2cRequest_t req; 1341 struct amdgpu_device *adev = to_amdgpu_device(control); 1342 struct smu_table_context *smu_table = &adev->smu.smu_table; 1343 struct smu_table *table = &smu_table->driver_table; 1344 1345 if (numbytes > MAX_SW_I2C_COMMANDS) { 1346 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n", 1347 numbytes, MAX_SW_I2C_COMMANDS); 1348 return -EINVAL; 1349 } 1350 1351 memset(&req, 0, sizeof(req)); 1352 aldebaran_fill_i2c_req(&req, false, address, numbytes, data); 1353 1354 mutex_lock(&adev->smu.mutex); 1355 /* Now read data starting with that address */ 1356 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, 1357 true); 1358 mutex_unlock(&adev->smu.mutex); 1359 1360 if (!ret) { 1361 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr; 1362 1363 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */ 1364 for (i = 0; i < numbytes; i++) 1365 data[i] = res->SwI2cCmds[i].ReadWriteData; 1366 1367 dev_dbg(adev->dev, "aldebaran_i2c_read_data, address = %x, bytes = %d, data :", 1368 (uint16_t)address, numbytes); 1369 1370 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE, 1371 8, 1, data, numbytes, false); 1372 } else 1373 dev_err(adev->dev, "aldebaran_i2c_read_data - error occurred :%x", ret); 1374 1375 return ret; 1376 } 1377 1378 static int aldebaran_i2c_write_data(struct i2c_adapter *control, 1379 uint8_t address, 1380 uint8_t *data, 1381 uint32_t numbytes) 1382 { 1383 uint32_t ret; 1384 SwI2cRequest_t req; 1385 struct amdgpu_device *adev = to_amdgpu_device(control); 1386 1387 if (numbytes > MAX_SW_I2C_COMMANDS) { 1388 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n", 1389 numbytes, MAX_SW_I2C_COMMANDS); 1390 return -EINVAL; 1391 } 1392 1393 memset(&req, 0, sizeof(req)); 1394 aldebaran_fill_i2c_req(&req, true, address, numbytes, data); 1395 1396 mutex_lock(&adev->smu.mutex); 1397 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true); 1398 mutex_unlock(&adev->smu.mutex); 1399 1400 if (!ret) { 1401 dev_dbg(adev->dev, "aldebaran_i2c_write(), address = %x, bytes = %d , data: ", 1402 (uint16_t)address, numbytes); 1403 1404 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE, 1405 8, 1, data, numbytes, false); 1406 /* 1407 * According to EEPROM spec there is a MAX of 10 ms required for 1408 * EEPROM to flush internal RX buffer after STOP was issued at the 1409 * end of write transaction. During this time the EEPROM will not be 1410 * responsive to any more commands - so wait a bit more. 1411 */ 1412 msleep(10); 1413 1414 } else 1415 dev_err(adev->dev, "aldebaran_i2c_write- error occurred :%x", ret); 1416 1417 return ret; 1418 } 1419 1420 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1421 struct i2c_msg *msgs, int num) 1422 { 1423 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0; 1424 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 }; 1425 1426 for (i = 0; i < num; i++) { 1427 /* 1428 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at 1429 * once and hence the data needs to be spliced into chunks and sent each 1430 * chunk separately 1431 */ 1432 data_size = msgs[i].len - 2; 1433 data_chunk_size = MAX_SW_I2C_COMMANDS - 2; 1434 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff); 1435 data_ptr = msgs[i].buf + 2; 1436 1437 for (j = 0; j < data_size / data_chunk_size; j++) { 1438 /* Insert the EEPROM dest addess, bits 0-15 */ 1439 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff); 1440 data_chunk[1] = (next_eeprom_addr & 0xff); 1441 1442 if (msgs[i].flags & I2C_M_RD) { 1443 ret = aldebaran_i2c_read_data(i2c_adap, 1444 (uint8_t)msgs[i].addr, 1445 data_chunk, MAX_SW_I2C_COMMANDS); 1446 1447 memcpy(data_ptr, data_chunk + 2, data_chunk_size); 1448 } else { 1449 1450 memcpy(data_chunk + 2, data_ptr, data_chunk_size); 1451 1452 ret = aldebaran_i2c_write_data(i2c_adap, 1453 (uint8_t)msgs[i].addr, 1454 data_chunk, MAX_SW_I2C_COMMANDS); 1455 } 1456 1457 if (ret) { 1458 num = -EIO; 1459 goto fail; 1460 } 1461 1462 next_eeprom_addr += data_chunk_size; 1463 data_ptr += data_chunk_size; 1464 } 1465 1466 if (data_size % data_chunk_size) { 1467 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff); 1468 data_chunk[1] = (next_eeprom_addr & 0xff); 1469 1470 if (msgs[i].flags & I2C_M_RD) { 1471 ret = aldebaran_i2c_read_data(i2c_adap, 1472 (uint8_t)msgs[i].addr, 1473 data_chunk, (data_size % data_chunk_size) + 2); 1474 1475 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size); 1476 } else { 1477 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size); 1478 1479 ret = aldebaran_i2c_write_data(i2c_adap, 1480 (uint8_t)msgs[i].addr, 1481 data_chunk, (data_size % data_chunk_size) + 2); 1482 } 1483 1484 if (ret) { 1485 num = -EIO; 1486 goto fail; 1487 } 1488 } 1489 } 1490 1491 fail: 1492 return num; 1493 } 1494 1495 static u32 aldebaran_i2c_func(struct i2c_adapter *adap) 1496 { 1497 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1498 } 1499 1500 1501 static const struct i2c_algorithm aldebaran_i2c_algo = { 1502 .master_xfer = aldebaran_i2c_xfer, 1503 .functionality = aldebaran_i2c_func, 1504 }; 1505 1506 static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 1507 { 1508 struct amdgpu_device *adev = to_amdgpu_device(control); 1509 int res; 1510 1511 control->owner = THIS_MODULE; 1512 control->class = I2C_CLASS_SPD; 1513 control->dev.parent = &adev->pdev->dev; 1514 control->algo = &aldebaran_i2c_algo; 1515 snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 1516 1517 res = i2c_add_adapter(control); 1518 if (res) 1519 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1520 1521 return res; 1522 } 1523 1524 static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 1525 { 1526 i2c_del_adapter(control); 1527 } 1528 1529 static void aldebaran_get_unique_id(struct smu_context *smu) 1530 { 1531 struct amdgpu_device *adev = smu->adev; 1532 SmuMetrics_t *metrics = smu->smu_table.metrics_table; 1533 uint32_t upper32 = 0, lower32 = 0; 1534 int ret; 1535 1536 mutex_lock(&smu->metrics_lock); 1537 ret = smu_cmn_get_metrics_table_locked(smu, NULL, false); 1538 if (ret) 1539 goto out_unlock; 1540 1541 upper32 = metrics->PublicSerialNumUpper32; 1542 lower32 = metrics->PublicSerialNumLower32; 1543 1544 out_unlock: 1545 mutex_unlock(&smu->metrics_lock); 1546 1547 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1548 sprintf(adev->serial, "%016llx", adev->unique_id); 1549 } 1550 1551 static bool aldebaran_is_baco_supported(struct smu_context *smu) 1552 { 1553 /* aldebaran is not support baco */ 1554 1555 return false; 1556 } 1557 1558 static int aldebaran_set_df_cstate(struct smu_context *smu, 1559 enum pp_df_cstate state) 1560 { 1561 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1562 } 1563 1564 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en) 1565 { 1566 return smu_cmn_send_smc_msg_with_param(smu, 1567 SMU_MSG_GmiPwrDnControl, 1568 en ? 1 : 0, 1569 NULL); 1570 } 1571 1572 static const struct throttling_logging_label { 1573 uint32_t feature_mask; 1574 const char *label; 1575 } logging_label[] = { 1576 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1577 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1578 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1579 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1580 }; 1581 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1582 { 1583 int ret; 1584 int throttler_idx, throtting_events = 0, buf_idx = 0; 1585 struct amdgpu_device *adev = smu->adev; 1586 uint32_t throttler_status; 1587 char log_buf[256]; 1588 1589 ret = aldebaran_get_smu_metrics_data(smu, 1590 METRICS_THROTTLER_STATUS, 1591 &throttler_status); 1592 if (ret) 1593 return; 1594 1595 memset(log_buf, 0, sizeof(log_buf)); 1596 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1597 throttler_idx++) { 1598 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1599 throtting_events++; 1600 buf_idx += snprintf(log_buf + buf_idx, 1601 sizeof(log_buf) - buf_idx, 1602 "%s%s", 1603 throtting_events > 1 ? " and " : "", 1604 logging_label[throttler_idx].label); 1605 if (buf_idx >= sizeof(log_buf)) { 1606 dev_err(adev->dev, "buffer overflow!\n"); 1607 log_buf[sizeof(log_buf) - 1] = '\0'; 1608 break; 1609 } 1610 } 1611 } 1612 1613 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1614 log_buf); 1615 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status); 1616 } 1617 1618 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1619 { 1620 struct amdgpu_device *adev = smu->adev; 1621 uint32_t esm_ctrl; 1622 1623 /* TODO: confirm this on real target */ 1624 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1625 if ((esm_ctrl >> 15) & 0x1FFFF) 1626 return (((esm_ctrl >> 8) & 0x3F) + 128); 1627 1628 return smu_v13_0_get_current_pcie_link_speed(smu); 1629 } 1630 1631 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1632 void **table) 1633 { 1634 struct smu_table_context *smu_table = &smu->smu_table; 1635 struct gpu_metrics_v1_1 *gpu_metrics = 1636 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; 1637 SmuMetrics_t metrics; 1638 int i, ret = 0; 1639 1640 ret = smu_cmn_get_metrics_table(smu, 1641 &metrics, 1642 true); 1643 if (ret) 1644 return ret; 1645 1646 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); 1647 1648 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1649 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1650 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1651 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1652 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1653 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1654 1655 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1656 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1657 gpu_metrics->average_mm_activity = 0; 1658 1659 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1660 gpu_metrics->energy_accumulator = 0; 1661 1662 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1663 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1664 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1665 gpu_metrics->average_vclk0_frequency = 0; 1666 gpu_metrics->average_dclk0_frequency = 0; 1667 1668 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1669 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1670 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1671 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1672 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1673 1674 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1675 1676 gpu_metrics->current_fan_speed = 0; 1677 1678 gpu_metrics->pcie_link_width = 1679 smu_v13_0_get_current_pcie_link_width(smu); 1680 gpu_metrics->pcie_link_speed = 1681 aldebaran_get_current_pcie_link_speed(smu); 1682 1683 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1684 1685 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1686 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1687 1688 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1689 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1690 1691 *table = (void *)gpu_metrics; 1692 1693 return sizeof(struct gpu_metrics_v1_1); 1694 } 1695 1696 static int aldebaran_mode2_reset(struct smu_context *smu) 1697 { 1698 u32 smu_version; 1699 int ret = 0, index; 1700 struct amdgpu_device *adev = smu->adev; 1701 int timeout = 10; 1702 1703 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1704 1705 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1706 SMU_MSG_GfxDeviceDriverReset); 1707 1708 mutex_lock(&smu->message_lock); 1709 if (smu_version >= 0x00441400) { 1710 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1711 /* This is similar to FLR, wait till max FLR timeout */ 1712 msleep(100); 1713 dev_dbg(smu->adev->dev, "restore config space...\n"); 1714 /* Restore the config space saved during init */ 1715 amdgpu_device_load_pci_state(adev->pdev); 1716 1717 dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1718 while (ret == -ETIME && timeout) { 1719 ret = smu_cmn_wait_for_response(smu); 1720 /* Wait a bit more time for getting ACK */ 1721 if (ret == -ETIME) { 1722 --timeout; 1723 usleep_range(500, 1000); 1724 continue; 1725 } 1726 1727 if (ret != 1) { 1728 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n", 1729 SMU_RESET_MODE_2, ret); 1730 goto out; 1731 } 1732 } 1733 1734 } else { 1735 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", 1736 smu_version); 1737 } 1738 1739 if (ret == 1) 1740 ret = 0; 1741 out: 1742 mutex_unlock(&smu->message_lock); 1743 1744 return ret; 1745 } 1746 1747 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1748 { 1749 #if 0 1750 struct amdgpu_device *adev = smu->adev; 1751 u32 smu_version; 1752 uint32_t val; 1753 /** 1754 * PM FW version support mode1 reset from 68.07 1755 */ 1756 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1757 if ((smu_version < 0x00440700)) 1758 return false; 1759 /** 1760 * mode1 reset relies on PSP, so we should check if 1761 * PSP is alive. 1762 */ 1763 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1764 1765 return val != 0x0; 1766 #endif 1767 return true; 1768 } 1769 1770 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 1771 { 1772 return true; 1773 } 1774 1775 static int aldebaran_set_mp1_state(struct smu_context *smu, 1776 enum pp_mp1_state mp1_state) 1777 { 1778 switch (mp1_state) { 1779 case PP_MP1_STATE_UNLOAD: 1780 return smu_cmn_set_mp1_state(smu, mp1_state); 1781 default: 1782 return -EINVAL; 1783 } 1784 1785 return 0; 1786 } 1787 1788 static const struct pptable_funcs aldebaran_ppt_funcs = { 1789 /* init dpm */ 1790 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 1791 /* dpm/clk tables */ 1792 .set_default_dpm_table = aldebaran_set_default_dpm_table, 1793 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 1794 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 1795 .print_clk_levels = aldebaran_print_clk_levels, 1796 .force_clk_levels = aldebaran_force_clk_levels, 1797 .read_sensor = aldebaran_read_sensor, 1798 .set_performance_level = aldebaran_set_performance_level, 1799 .get_power_limit = aldebaran_get_power_limit, 1800 .is_dpm_running = aldebaran_is_dpm_running, 1801 .get_unique_id = aldebaran_get_unique_id, 1802 .init_microcode = smu_v13_0_init_microcode, 1803 .load_microcode = smu_v13_0_load_microcode, 1804 .fini_microcode = smu_v13_0_fini_microcode, 1805 .init_smc_tables = aldebaran_init_smc_tables, 1806 .fini_smc_tables = smu_v13_0_fini_smc_tables, 1807 .init_power = smu_v13_0_init_power, 1808 .fini_power = smu_v13_0_fini_power, 1809 .check_fw_status = smu_v13_0_check_fw_status, 1810 /* pptable related */ 1811 .setup_pptable = aldebaran_setup_pptable, 1812 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1813 .check_fw_version = smu_v13_0_check_fw_version, 1814 .write_pptable = smu_cmn_write_pptable, 1815 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1816 .set_tool_table_location = smu_v13_0_set_tool_table_location, 1817 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 1818 .system_features_control = aldebaran_system_features_control, 1819 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1820 .send_smc_msg = smu_cmn_send_smc_msg, 1821 .get_enabled_mask = smu_cmn_get_enabled_mask, 1822 .feature_is_enabled = smu_cmn_feature_is_enabled, 1823 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1824 .set_power_limit = smu_v13_0_set_power_limit, 1825 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 1826 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 1827 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 1828 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 1829 .register_irq_handler = smu_v13_0_register_irq_handler, 1830 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 1831 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 1832 .baco_is_support= aldebaran_is_baco_supported, 1833 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 1834 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 1835 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 1836 .set_df_cstate = aldebaran_set_df_cstate, 1837 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down, 1838 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 1839 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1840 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1841 .get_gpu_metrics = aldebaran_get_gpu_metrics, 1842 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 1843 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 1844 .mode1_reset = smu_v13_0_mode1_reset, 1845 .set_mp1_state = aldebaran_set_mp1_state, 1846 .mode2_reset = aldebaran_mode2_reset, 1847 .wait_for_event = smu_v13_0_wait_for_event, 1848 .i2c_init = aldebaran_i2c_control_init, 1849 .i2c_fini = aldebaran_i2c_control_fini, 1850 }; 1851 1852 void aldebaran_set_ppt_funcs(struct smu_context *smu) 1853 { 1854 smu->ppt_funcs = &aldebaran_ppt_funcs; 1855 smu->message_map = aldebaran_message_map; 1856 smu->clock_map = aldebaran_clk_map; 1857 smu->feature_map = aldebaran_feature_mask_map; 1858 smu->table_map = aldebaran_table_map; 1859 } 1860