1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v12_0_ppsmc.h" 29 #include "smu12_driver_if.h" 30 #include "smu_v12_0.h" 31 #include "renoir_ppt.h" 32 #include "smu_cmn.h" 33 34 /* 35 * DO NOT use these for err/warn/info/debug messages. 36 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 37 * They are more MGPU friendly. 38 */ 39 #undef pr_err 40 #undef pr_warn 41 #undef pr_info 42 #undef pr_debug 43 44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { 45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1), 49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1), 50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1), 51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1), 56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1), 57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1), 58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 59 MSG_MAP(Spare1, PPSMC_MSG_spare1, 1), 60 MSG_MAP(Spare2, PPSMC_MSG_spare2, 1), 61 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1), 62 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1), 63 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1), 64 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1), 65 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1), 66 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1), 67 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1), 68 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 69 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 70 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 71 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 72 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 73 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1), 74 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1), 75 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 76 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1), 77 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1), 78 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1), 79 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1), 80 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1), 81 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1), 82 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 83 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1), 84 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 85 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 86 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1), 87 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1), 88 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1), 89 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1), 90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 95 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1), 96 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1), 97 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1), 98 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 99 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1), 100 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1), 101 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 102 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 103 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1), 104 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1), 105 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 106 }; 107 108 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { 109 CLK_MAP(GFXCLK, CLOCK_GFXCLK), 110 CLK_MAP(SCLK, CLOCK_GFXCLK), 111 CLK_MAP(SOCCLK, CLOCK_SOCCLK), 112 CLK_MAP(UCLK, CLOCK_FCLK), 113 CLK_MAP(MCLK, CLOCK_FCLK), 114 }; 115 116 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { 117 TAB_MAP_VALID(WATERMARKS), 118 TAB_MAP_INVALID(CUSTOM_DPM), 119 TAB_MAP_VALID(DPMCLOCKS), 120 TAB_MAP_VALID(SMU_METRICS), 121 }; 122 123 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 127 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 128 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 129 }; 130 131 static int renoir_init_smc_tables(struct smu_context *smu) 132 { 133 struct smu_table_context *smu_table = &smu->smu_table; 134 struct smu_table *tables = smu_table->tables; 135 136 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 137 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 138 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 139 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 140 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 141 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 142 143 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 144 if (!smu_table->clocks_table) 145 goto err0_out; 146 147 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 148 if (!smu_table->metrics_table) 149 goto err1_out; 150 smu_table->metrics_time = 0; 151 152 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 153 if (!smu_table->watermarks_table) 154 goto err2_out; 155 156 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); 157 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 158 if (!smu_table->gpu_metrics_table) 159 goto err3_out; 160 161 return 0; 162 163 err3_out: 164 kfree(smu_table->watermarks_table); 165 err2_out: 166 kfree(smu_table->metrics_table); 167 err1_out: 168 kfree(smu_table->clocks_table); 169 err0_out: 170 return -ENOMEM; 171 } 172 173 /* 174 * This interface just for getting uclk ultimate freq and should't introduce 175 * other likewise function result in overmuch callback. 176 */ 177 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 178 uint32_t dpm_level, uint32_t *freq) 179 { 180 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 181 182 if (!clk_table || clk_type >= SMU_CLK_COUNT) 183 return -EINVAL; 184 185 switch (clk_type) { 186 case SMU_SOCCLK: 187 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) 188 return -EINVAL; 189 *freq = clk_table->SocClocks[dpm_level].Freq; 190 break; 191 case SMU_UCLK: 192 case SMU_MCLK: 193 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 194 return -EINVAL; 195 *freq = clk_table->FClocks[dpm_level].Freq; 196 break; 197 case SMU_DCEFCLK: 198 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) 199 return -EINVAL; 200 *freq = clk_table->DcfClocks[dpm_level].Freq; 201 break; 202 case SMU_FCLK: 203 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 204 return -EINVAL; 205 *freq = clk_table->FClocks[dpm_level].Freq; 206 break; 207 default: 208 return -EINVAL; 209 } 210 211 return 0; 212 } 213 214 static int renoir_get_profiling_clk_mask(struct smu_context *smu, 215 enum amd_dpm_forced_level level, 216 uint32_t *sclk_mask, 217 uint32_t *mclk_mask, 218 uint32_t *soc_mask) 219 { 220 221 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 222 if (sclk_mask) 223 *sclk_mask = 0; 224 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 225 if (mclk_mask) 226 /* mclk levels are in reverse order */ 227 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; 228 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 229 if(sclk_mask) 230 /* The sclk as gfxclk and has three level about max/min/current */ 231 *sclk_mask = 3 - 1; 232 233 if(mclk_mask) 234 /* mclk levels are in reverse order */ 235 *mclk_mask = 0; 236 237 if(soc_mask) 238 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; 239 } 240 241 return 0; 242 } 243 244 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu, 245 enum smu_clk_type clk_type, 246 uint32_t *min, 247 uint32_t *max) 248 { 249 int ret = 0; 250 uint32_t mclk_mask, soc_mask; 251 uint32_t clock_limit; 252 253 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 254 switch (clk_type) { 255 case SMU_MCLK: 256 case SMU_UCLK: 257 clock_limit = smu->smu_table.boot_values.uclk; 258 break; 259 case SMU_GFXCLK: 260 case SMU_SCLK: 261 clock_limit = smu->smu_table.boot_values.gfxclk; 262 break; 263 case SMU_SOCCLK: 264 clock_limit = smu->smu_table.boot_values.socclk; 265 break; 266 default: 267 clock_limit = 0; 268 break; 269 } 270 271 /* clock in Mhz unit */ 272 if (min) 273 *min = clock_limit / 100; 274 if (max) 275 *max = clock_limit / 100; 276 277 return 0; 278 } 279 280 if (max) { 281 ret = renoir_get_profiling_clk_mask(smu, 282 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 283 NULL, 284 &mclk_mask, 285 &soc_mask); 286 if (ret) 287 goto failed; 288 289 switch (clk_type) { 290 case SMU_GFXCLK: 291 case SMU_SCLK: 292 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max); 293 if (ret) { 294 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n"); 295 goto failed; 296 } 297 break; 298 case SMU_UCLK: 299 case SMU_FCLK: 300 case SMU_MCLK: 301 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 302 if (ret) 303 goto failed; 304 break; 305 case SMU_SOCCLK: 306 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 307 if (ret) 308 goto failed; 309 break; 310 default: 311 ret = -EINVAL; 312 goto failed; 313 } 314 } 315 316 if (min) { 317 switch (clk_type) { 318 case SMU_GFXCLK: 319 case SMU_SCLK: 320 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min); 321 if (ret) { 322 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n"); 323 goto failed; 324 } 325 break; 326 case SMU_UCLK: 327 case SMU_FCLK: 328 case SMU_MCLK: 329 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min); 330 if (ret) 331 goto failed; 332 break; 333 case SMU_SOCCLK: 334 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min); 335 if (ret) 336 goto failed; 337 break; 338 default: 339 ret = -EINVAL; 340 goto failed; 341 } 342 } 343 failed: 344 return ret; 345 } 346 347 static int renoir_od_edit_dpm_table(struct smu_context *smu, 348 enum PP_OD_DPM_TABLE_COMMAND type, 349 long input[], uint32_t size) 350 { 351 int ret = 0; 352 353 if (!smu->fine_grain_enabled) { 354 dev_warn(smu->adev->dev, "Fine grain is not enabled!\n"); 355 return -EINVAL; 356 } 357 358 if (!smu->fine_grain_started) { 359 dev_warn(smu->adev->dev, "Fine grain is enabled but not started!\n"); 360 return -EINVAL; 361 } 362 363 switch (type) { 364 case PP_OD_EDIT_SCLK_VDDC_TABLE: 365 if (size != 2) { 366 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 367 return -EINVAL; 368 } 369 370 if (input[0] == 0) { 371 if (input[1] < smu->gfx_default_hard_min_freq) { 372 dev_warn(smu->adev->dev, 373 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 374 input[1], smu->gfx_default_hard_min_freq); 375 return -EINVAL; 376 } 377 smu->gfx_actual_hard_min_freq = input[1]; 378 } else if (input[0] == 1) { 379 if (input[1] > smu->gfx_default_soft_max_freq) { 380 dev_warn(smu->adev->dev, 381 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 382 input[1], smu->gfx_default_soft_max_freq); 383 return -EINVAL; 384 } 385 smu->gfx_actual_soft_max_freq = input[1]; 386 } else { 387 return -EINVAL; 388 } 389 break; 390 case PP_OD_RESTORE_DEFAULT_TABLE: 391 if (size != 0) { 392 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 393 return -EINVAL; 394 } 395 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 396 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 397 398 ret = smu_cmn_send_smc_msg_with_param(smu, 399 SMU_MSG_SetHardMinGfxClk, 400 smu->gfx_actual_hard_min_freq, 401 NULL); 402 if (ret) { 403 dev_err(smu->adev->dev, "Restore the default hard min sclk failed!"); 404 return ret; 405 } 406 407 ret = smu_cmn_send_smc_msg_with_param(smu, 408 SMU_MSG_SetSoftMaxGfxClk, 409 smu->gfx_actual_soft_max_freq, 410 NULL); 411 if (ret) { 412 dev_err(smu->adev->dev, "Restore the default soft max sclk failed!"); 413 return ret; 414 } 415 break; 416 case PP_OD_COMMIT_DPM_TABLE: 417 if (size != 0) { 418 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 419 return -EINVAL; 420 } else { 421 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 422 dev_err(smu->adev->dev, 423 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 424 smu->gfx_actual_hard_min_freq, 425 smu->gfx_actual_soft_max_freq); 426 return -EINVAL; 427 } 428 429 ret = smu_cmn_send_smc_msg_with_param(smu, 430 SMU_MSG_SetHardMinGfxClk, 431 smu->gfx_actual_hard_min_freq, 432 NULL); 433 if (ret) { 434 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 435 return ret; 436 } 437 438 ret = smu_cmn_send_smc_msg_with_param(smu, 439 SMU_MSG_SetSoftMaxGfxClk, 440 smu->gfx_actual_soft_max_freq, 441 NULL); 442 if (ret) { 443 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 444 return ret; 445 } 446 } 447 break; 448 default: 449 return -ENOSYS; 450 } 451 452 return ret; 453 } 454 455 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 456 { 457 uint32_t min = 0, max = 0; 458 uint32_t ret = 0; 459 460 ret = smu_cmn_send_smc_msg_with_param(smu, 461 SMU_MSG_GetMinGfxclkFrequency, 462 0, &min); 463 if (ret) 464 return ret; 465 ret = smu_cmn_send_smc_msg_with_param(smu, 466 SMU_MSG_GetMaxGfxclkFrequency, 467 0, &max); 468 if (ret) 469 return ret; 470 471 smu->gfx_default_hard_min_freq = min; 472 smu->gfx_default_soft_max_freq = max; 473 smu->gfx_actual_hard_min_freq = 0; 474 smu->gfx_actual_soft_max_freq = 0; 475 476 return 0; 477 } 478 479 static int renoir_print_clk_levels(struct smu_context *smu, 480 enum smu_clk_type clk_type, char *buf) 481 { 482 int i, size = 0, ret = 0; 483 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; 484 SmuMetrics_t metrics; 485 bool cur_value_match_level = false; 486 487 memset(&metrics, 0, sizeof(metrics)); 488 489 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 490 if (ret) 491 return ret; 492 493 switch (clk_type) { 494 case SMU_OD_RANGE: 495 if (smu->fine_grain_enabled) { 496 ret = smu_cmn_send_smc_msg_with_param(smu, 497 SMU_MSG_GetMinGfxclkFrequency, 498 0, &min); 499 if (ret) 500 return ret; 501 ret = smu_cmn_send_smc_msg_with_param(smu, 502 SMU_MSG_GetMaxGfxclkFrequency, 503 0, &max); 504 if (ret) 505 return ret; 506 size += sprintf(buf + size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max); 507 } 508 break; 509 case SMU_OD_SCLK: 510 if (smu->fine_grain_enabled) { 511 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 512 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 513 size += sprintf(buf + size, "OD_SCLK\n"); 514 size += sprintf(buf + size, "0:%10uMhz\n", min); 515 size += sprintf(buf + size, "1:%10uMhz\n", max); 516 } 517 break; 518 case SMU_GFXCLK: 519 case SMU_SCLK: 520 /* retirve table returned paramters unit is MHz */ 521 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; 522 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max); 523 if (!ret) { 524 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 525 if (cur_value == max) 526 i = 2; 527 else if (cur_value == min) 528 i = 0; 529 else 530 i = 1; 531 532 size += sprintf(buf + size, "0: %uMhz %s\n", min, 533 i == 0 ? "*" : ""); 534 size += sprintf(buf + size, "1: %uMhz %s\n", 535 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, 536 i == 1 ? "*" : ""); 537 size += sprintf(buf + size, "2: %uMhz %s\n", max, 538 i == 2 ? "*" : ""); 539 } 540 return size; 541 case SMU_SOCCLK: 542 count = NUM_SOCCLK_DPM_LEVELS; 543 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; 544 break; 545 case SMU_MCLK: 546 count = NUM_MEMCLK_DPM_LEVELS; 547 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 548 break; 549 case SMU_DCEFCLK: 550 count = NUM_DCFCLK_DPM_LEVELS; 551 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK]; 552 break; 553 case SMU_FCLK: 554 count = NUM_FCLK_DPM_LEVELS; 555 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 556 break; 557 default: 558 break; 559 } 560 561 switch (clk_type) { 562 case SMU_GFXCLK: 563 case SMU_SCLK: 564 case SMU_SOCCLK: 565 case SMU_MCLK: 566 case SMU_DCEFCLK: 567 case SMU_FCLK: 568 for (i = 0; i < count; i++) { 569 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); 570 if (ret) 571 return ret; 572 if (!value) 573 continue; 574 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 575 cur_value == value ? "*" : ""); 576 if (cur_value == value) 577 cur_value_match_level = true; 578 } 579 580 if (!cur_value_match_level) 581 size += sprintf(buf + size, " %uMhz *\n", cur_value); 582 583 break; 584 default: 585 break; 586 } 587 588 return size; 589 } 590 591 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) 592 { 593 enum amd_pm_state_type pm_type; 594 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 595 596 if (!smu_dpm_ctx->dpm_context || 597 !smu_dpm_ctx->dpm_current_power_state) 598 return -EINVAL; 599 600 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) { 601 case SMU_STATE_UI_LABEL_BATTERY: 602 pm_type = POWER_STATE_TYPE_BATTERY; 603 break; 604 case SMU_STATE_UI_LABEL_BALLANCED: 605 pm_type = POWER_STATE_TYPE_BALANCED; 606 break; 607 case SMU_STATE_UI_LABEL_PERFORMANCE: 608 pm_type = POWER_STATE_TYPE_PERFORMANCE; 609 break; 610 default: 611 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT) 612 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 613 else 614 pm_type = POWER_STATE_TYPE_DEFAULT; 615 break; 616 } 617 618 return pm_type; 619 } 620 621 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 622 { 623 int ret = 0; 624 625 if (enable) { 626 /* vcn dpm on is a prerequisite for vcn power gate messages */ 627 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 628 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 629 if (ret) 630 return ret; 631 } 632 } else { 633 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 634 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 635 if (ret) 636 return ret; 637 } 638 } 639 640 return ret; 641 } 642 643 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 644 { 645 int ret = 0; 646 647 if (enable) { 648 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 649 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 650 if (ret) 651 return ret; 652 } 653 } else { 654 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 655 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 656 if (ret) 657 return ret; 658 } 659 } 660 661 return ret; 662 } 663 664 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest) 665 { 666 int ret = 0, i = 0; 667 uint32_t min_freq, max_freq, force_freq; 668 enum smu_clk_type clk_type; 669 670 enum smu_clk_type clks[] = { 671 SMU_GFXCLK, 672 SMU_MCLK, 673 SMU_SOCCLK, 674 }; 675 676 for (i = 0; i < ARRAY_SIZE(clks); i++) { 677 clk_type = clks[i]; 678 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 679 if (ret) 680 return ret; 681 682 force_freq = highest ? max_freq : min_freq; 683 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 684 if (ret) 685 return ret; 686 } 687 688 return ret; 689 } 690 691 static int renoir_unforce_dpm_levels(struct smu_context *smu) { 692 693 int ret = 0, i = 0; 694 uint32_t min_freq, max_freq; 695 enum smu_clk_type clk_type; 696 697 struct clk_feature_map { 698 enum smu_clk_type clk_type; 699 uint32_t feature; 700 } clk_feature_map[] = { 701 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, 702 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, 703 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 704 }; 705 706 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 707 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 708 continue; 709 710 clk_type = clk_feature_map[i].clk_type; 711 712 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 713 if (ret) 714 return ret; 715 716 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 717 if (ret) 718 return ret; 719 } 720 721 return ret; 722 } 723 724 /* 725 * This interface get dpm clock table for dc 726 */ 727 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 728 { 729 DpmClocks_t *table = smu->smu_table.clocks_table; 730 int i; 731 732 if (!clock_table || !table) 733 return -EINVAL; 734 735 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { 736 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; 737 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; 738 } 739 740 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 741 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq; 742 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; 743 } 744 745 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 746 clock_table->FClocks[i].Freq = table->FClocks[i].Freq; 747 clock_table->FClocks[i].Vol = table->FClocks[i].Vol; 748 } 749 750 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) { 751 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq; 752 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; 753 } 754 755 return 0; 756 } 757 758 static int renoir_force_clk_levels(struct smu_context *smu, 759 enum smu_clk_type clk_type, uint32_t mask) 760 { 761 762 int ret = 0 ; 763 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 764 765 soft_min_level = mask ? (ffs(mask) - 1) : 0; 766 soft_max_level = mask ? (fls(mask) - 1) : 0; 767 768 switch (clk_type) { 769 case SMU_GFXCLK: 770 case SMU_SCLK: 771 if (soft_min_level > 2 || soft_max_level > 2) { 772 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n"); 773 return -EINVAL; 774 } 775 776 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq); 777 if (ret) 778 return ret; 779 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 780 soft_max_level == 0 ? min_freq : 781 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq, 782 NULL); 783 if (ret) 784 return ret; 785 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 786 soft_min_level == 2 ? max_freq : 787 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq, 788 NULL); 789 if (ret) 790 return ret; 791 break; 792 case SMU_SOCCLK: 793 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 794 if (ret) 795 return ret; 796 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 797 if (ret) 798 return ret; 799 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); 800 if (ret) 801 return ret; 802 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); 803 if (ret) 804 return ret; 805 break; 806 case SMU_MCLK: 807 case SMU_FCLK: 808 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 809 if (ret) 810 return ret; 811 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 812 if (ret) 813 return ret; 814 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); 815 if (ret) 816 return ret; 817 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); 818 if (ret) 819 return ret; 820 break; 821 default: 822 break; 823 } 824 825 return ret; 826 } 827 828 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 829 { 830 int workload_type, ret; 831 uint32_t profile_mode = input[size]; 832 833 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 834 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 835 return -EINVAL; 836 } 837 838 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 839 workload_type = smu_cmn_to_asic_specific_index(smu, 840 CMN2ASIC_MAPPING_WORKLOAD, 841 profile_mode); 842 if (workload_type < 0) { 843 /* 844 * TODO: If some case need switch to powersave/default power mode 845 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving. 846 */ 847 dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode); 848 return -EINVAL; 849 } 850 851 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 852 1 << workload_type, 853 NULL); 854 if (ret) { 855 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 856 return ret; 857 } 858 859 smu->power_profile_mode = profile_mode; 860 861 return 0; 862 } 863 864 static int renoir_set_peak_clock_by_device(struct smu_context *smu) 865 { 866 int ret = 0; 867 uint32_t sclk_freq = 0, uclk_freq = 0; 868 869 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq); 870 if (ret) 871 return ret; 872 873 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq); 874 if (ret) 875 return ret; 876 877 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq); 878 if (ret) 879 return ret; 880 881 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq); 882 if (ret) 883 return ret; 884 885 return ret; 886 } 887 888 static int renoir_set_performance_level(struct smu_context *smu, 889 enum amd_dpm_forced_level level) 890 { 891 int ret = 0; 892 uint32_t sclk_mask, mclk_mask, soc_mask; 893 894 switch (level) { 895 case AMD_DPM_FORCED_LEVEL_HIGH: 896 smu->fine_grain_started = 0; 897 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 898 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 899 900 ret = renoir_force_dpm_limit_value(smu, true); 901 break; 902 case AMD_DPM_FORCED_LEVEL_LOW: 903 smu->fine_grain_started = 0; 904 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 905 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 906 907 ret = renoir_force_dpm_limit_value(smu, false); 908 break; 909 case AMD_DPM_FORCED_LEVEL_AUTO: 910 smu->fine_grain_started = 0; 911 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 912 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 913 914 ret = renoir_unforce_dpm_levels(smu); 915 break; 916 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 917 smu->fine_grain_started = 0; 918 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 919 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 920 921 ret = smu_cmn_send_smc_msg_with_param(smu, 922 SMU_MSG_SetHardMinGfxClk, 923 RENOIR_UMD_PSTATE_GFXCLK, 924 NULL); 925 if (ret) 926 return ret; 927 ret = smu_cmn_send_smc_msg_with_param(smu, 928 SMU_MSG_SetHardMinFclkByFreq, 929 RENOIR_UMD_PSTATE_FCLK, 930 NULL); 931 if (ret) 932 return ret; 933 ret = smu_cmn_send_smc_msg_with_param(smu, 934 SMU_MSG_SetHardMinSocclkByFreq, 935 RENOIR_UMD_PSTATE_SOCCLK, 936 NULL); 937 if (ret) 938 return ret; 939 ret = smu_cmn_send_smc_msg_with_param(smu, 940 SMU_MSG_SetHardMinVcn, 941 RENOIR_UMD_PSTATE_VCNCLK, 942 NULL); 943 if (ret) 944 return ret; 945 946 ret = smu_cmn_send_smc_msg_with_param(smu, 947 SMU_MSG_SetSoftMaxGfxClk, 948 RENOIR_UMD_PSTATE_GFXCLK, 949 NULL); 950 if (ret) 951 return ret; 952 ret = smu_cmn_send_smc_msg_with_param(smu, 953 SMU_MSG_SetSoftMaxFclkByFreq, 954 RENOIR_UMD_PSTATE_FCLK, 955 NULL); 956 if (ret) 957 return ret; 958 ret = smu_cmn_send_smc_msg_with_param(smu, 959 SMU_MSG_SetSoftMaxSocclkByFreq, 960 RENOIR_UMD_PSTATE_SOCCLK, 961 NULL); 962 if (ret) 963 return ret; 964 ret = smu_cmn_send_smc_msg_with_param(smu, 965 SMU_MSG_SetSoftMaxVcn, 966 RENOIR_UMD_PSTATE_VCNCLK, 967 NULL); 968 if (ret) 969 return ret; 970 break; 971 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 972 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 973 smu->fine_grain_started = 0; 974 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 975 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 976 977 ret = renoir_get_profiling_clk_mask(smu, level, 978 &sclk_mask, 979 &mclk_mask, 980 &soc_mask); 981 if (ret) 982 return ret; 983 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); 984 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 985 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 986 break; 987 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 988 smu->fine_grain_started = 0; 989 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 990 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 991 992 ret = renoir_set_peak_clock_by_device(smu); 993 break; 994 case AMD_DPM_FORCED_LEVEL_MANUAL: 995 smu->fine_grain_started = 1; 996 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 997 default: 998 break; 999 } 1000 return ret; 1001 } 1002 1003 /* save watermark settings into pplib smu structure, 1004 * also pass data to smu controller 1005 */ 1006 static int renoir_set_watermarks_table( 1007 struct smu_context *smu, 1008 struct pp_smu_wm_range_sets *clock_ranges) 1009 { 1010 Watermarks_t *table = smu->smu_table.watermarks_table; 1011 int ret = 0; 1012 int i; 1013 1014 if (clock_ranges) { 1015 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1016 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1017 return -EINVAL; 1018 1019 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/ 1020 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1021 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1022 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1023 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1024 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1025 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1026 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1027 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1028 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1029 1030 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1031 clock_ranges->reader_wm_sets[i].wm_inst; 1032 table->WatermarkRow[WM_DCFCLK][i].WmType = 1033 clock_ranges->reader_wm_sets[i].wm_type; 1034 } 1035 1036 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1037 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1038 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1039 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1040 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1041 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1042 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1043 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1044 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1045 1046 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1047 clock_ranges->writer_wm_sets[i].wm_inst; 1048 table->WatermarkRow[WM_SOCCLK][i].WmType = 1049 clock_ranges->writer_wm_sets[i].wm_type; 1050 } 1051 1052 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1053 } 1054 1055 /* pass data to smu controller */ 1056 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1057 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1058 ret = smu_cmn_write_watermarks_table(smu); 1059 if (ret) { 1060 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1061 return ret; 1062 } 1063 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1064 } 1065 1066 return 0; 1067 } 1068 1069 static int renoir_get_power_profile_mode(struct smu_context *smu, 1070 char *buf) 1071 { 1072 static const char *profile_name[] = { 1073 "BOOTUP_DEFAULT", 1074 "3D_FULL_SCREEN", 1075 "POWER_SAVING", 1076 "VIDEO", 1077 "VR", 1078 "COMPUTE", 1079 "CUSTOM"}; 1080 uint32_t i, size = 0; 1081 int16_t workload_type = 0; 1082 1083 if (!buf) 1084 return -EINVAL; 1085 1086 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1087 /* 1088 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1089 * Not all profile modes are supported on arcturus. 1090 */ 1091 workload_type = smu_cmn_to_asic_specific_index(smu, 1092 CMN2ASIC_MAPPING_WORKLOAD, 1093 i); 1094 if (workload_type < 0) 1095 continue; 1096 1097 size += sprintf(buf + size, "%2d %14s%s\n", 1098 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1099 } 1100 1101 return size; 1102 } 1103 1104 static int renoir_get_smu_metrics_data(struct smu_context *smu, 1105 MetricsMember_t member, 1106 uint32_t *value) 1107 { 1108 struct smu_table_context *smu_table = &smu->smu_table; 1109 1110 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 1111 int ret = 0; 1112 1113 mutex_lock(&smu->metrics_lock); 1114 1115 ret = smu_cmn_get_metrics_table_locked(smu, 1116 NULL, 1117 false); 1118 if (ret) { 1119 mutex_unlock(&smu->metrics_lock); 1120 return ret; 1121 } 1122 1123 switch (member) { 1124 case METRICS_AVERAGE_GFXCLK: 1125 *value = metrics->ClockFrequency[CLOCK_GFXCLK]; 1126 break; 1127 case METRICS_AVERAGE_SOCCLK: 1128 *value = metrics->ClockFrequency[CLOCK_SOCCLK]; 1129 break; 1130 case METRICS_AVERAGE_UCLK: 1131 *value = metrics->ClockFrequency[CLOCK_FCLK]; 1132 break; 1133 case METRICS_AVERAGE_GFXACTIVITY: 1134 *value = metrics->AverageGfxActivity / 100; 1135 break; 1136 case METRICS_AVERAGE_VCNACTIVITY: 1137 *value = metrics->AverageUvdActivity / 100; 1138 break; 1139 case METRICS_AVERAGE_SOCKETPOWER: 1140 *value = metrics->CurrentSocketPower << 8; 1141 break; 1142 case METRICS_TEMPERATURE_EDGE: 1143 *value = (metrics->GfxTemperature / 100) * 1144 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1145 break; 1146 case METRICS_TEMPERATURE_HOTSPOT: 1147 *value = (metrics->SocTemperature / 100) * 1148 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1149 break; 1150 case METRICS_THROTTLER_STATUS: 1151 *value = metrics->ThrottlerStatus; 1152 break; 1153 case METRICS_VOLTAGE_VDDGFX: 1154 *value = metrics->Voltage[0]; 1155 break; 1156 case METRICS_VOLTAGE_VDDSOC: 1157 *value = metrics->Voltage[1]; 1158 break; 1159 default: 1160 *value = UINT_MAX; 1161 break; 1162 } 1163 1164 mutex_unlock(&smu->metrics_lock); 1165 1166 return ret; 1167 } 1168 1169 static int renoir_read_sensor(struct smu_context *smu, 1170 enum amd_pp_sensors sensor, 1171 void *data, uint32_t *size) 1172 { 1173 int ret = 0; 1174 1175 if (!data || !size) 1176 return -EINVAL; 1177 1178 mutex_lock(&smu->sensor_lock); 1179 switch (sensor) { 1180 case AMDGPU_PP_SENSOR_GPU_LOAD: 1181 ret = renoir_get_smu_metrics_data(smu, 1182 METRICS_AVERAGE_GFXACTIVITY, 1183 (uint32_t *)data); 1184 *size = 4; 1185 break; 1186 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1187 ret = renoir_get_smu_metrics_data(smu, 1188 METRICS_TEMPERATURE_EDGE, 1189 (uint32_t *)data); 1190 *size = 4; 1191 break; 1192 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1193 ret = renoir_get_smu_metrics_data(smu, 1194 METRICS_TEMPERATURE_HOTSPOT, 1195 (uint32_t *)data); 1196 *size = 4; 1197 break; 1198 case AMDGPU_PP_SENSOR_GFX_MCLK: 1199 ret = renoir_get_smu_metrics_data(smu, 1200 METRICS_AVERAGE_UCLK, 1201 (uint32_t *)data); 1202 *(uint32_t *)data *= 100; 1203 *size = 4; 1204 break; 1205 case AMDGPU_PP_SENSOR_GFX_SCLK: 1206 ret = renoir_get_smu_metrics_data(smu, 1207 METRICS_AVERAGE_GFXCLK, 1208 (uint32_t *)data); 1209 *(uint32_t *)data *= 100; 1210 *size = 4; 1211 break; 1212 case AMDGPU_PP_SENSOR_VDDGFX: 1213 ret = renoir_get_smu_metrics_data(smu, 1214 METRICS_VOLTAGE_VDDGFX, 1215 (uint32_t *)data); 1216 *size = 4; 1217 break; 1218 case AMDGPU_PP_SENSOR_VDDNB: 1219 ret = renoir_get_smu_metrics_data(smu, 1220 METRICS_VOLTAGE_VDDSOC, 1221 (uint32_t *)data); 1222 *size = 4; 1223 break; 1224 case AMDGPU_PP_SENSOR_GPU_POWER: 1225 ret = renoir_get_smu_metrics_data(smu, 1226 METRICS_AVERAGE_SOCKETPOWER, 1227 (uint32_t *)data); 1228 *size = 4; 1229 break; 1230 default: 1231 ret = -EOPNOTSUPP; 1232 break; 1233 } 1234 mutex_unlock(&smu->sensor_lock); 1235 1236 return ret; 1237 } 1238 1239 static bool renoir_is_dpm_running(struct smu_context *smu) 1240 { 1241 struct amdgpu_device *adev = smu->adev; 1242 1243 /* 1244 * Until now, the pmfw hasn't exported the interface of SMU 1245 * feature mask to APU SKU so just force on all the feature 1246 * at early initial stage. 1247 */ 1248 if (adev->in_suspend) 1249 return false; 1250 else 1251 return true; 1252 1253 } 1254 1255 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, 1256 void **table) 1257 { 1258 struct smu_table_context *smu_table = &smu->smu_table; 1259 struct gpu_metrics_v2_0 *gpu_metrics = 1260 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; 1261 SmuMetrics_t metrics; 1262 int ret = 0; 1263 1264 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1265 if (ret) 1266 return ret; 1267 1268 smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics); 1269 1270 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1271 gpu_metrics->temperature_soc = metrics.SocTemperature; 1272 memcpy(&gpu_metrics->temperature_core[0], 1273 &metrics.CoreTemperature[0], 1274 sizeof(uint16_t) * 8); 1275 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1276 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1277 1278 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1279 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity; 1280 1281 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1282 gpu_metrics->average_cpu_power = metrics.Power[0]; 1283 gpu_metrics->average_soc_power = metrics.Power[1]; 1284 memcpy(&gpu_metrics->average_core_power[0], 1285 &metrics.CorePower[0], 1286 sizeof(uint16_t) * 8); 1287 1288 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1289 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1290 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency; 1291 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency; 1292 1293 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK]; 1294 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK]; 1295 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK]; 1296 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK]; 1297 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK]; 1298 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK]; 1299 memcpy(&gpu_metrics->current_coreclk[0], 1300 &metrics.CoreFrequency[0], 1301 sizeof(uint16_t) * 8); 1302 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1303 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1304 1305 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1306 1307 gpu_metrics->fan_pwm = metrics.FanPwm; 1308 1309 *table = (void *)gpu_metrics; 1310 1311 return sizeof(struct gpu_metrics_v2_0); 1312 } 1313 1314 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) 1315 { 1316 1317 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GpuChangeState, state, NULL); 1318 } 1319 1320 static const struct pptable_funcs renoir_ppt_funcs = { 1321 .set_power_state = NULL, 1322 .print_clk_levels = renoir_print_clk_levels, 1323 .get_current_power_state = renoir_get_current_power_state, 1324 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable, 1325 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable, 1326 .force_clk_levels = renoir_force_clk_levels, 1327 .set_power_profile_mode = renoir_set_power_profile_mode, 1328 .set_performance_level = renoir_set_performance_level, 1329 .get_dpm_clock_table = renoir_get_dpm_clock_table, 1330 .set_watermarks_table = renoir_set_watermarks_table, 1331 .get_power_profile_mode = renoir_get_power_profile_mode, 1332 .read_sensor = renoir_read_sensor, 1333 .check_fw_status = smu_v12_0_check_fw_status, 1334 .check_fw_version = smu_v12_0_check_fw_version, 1335 .powergate_sdma = smu_v12_0_powergate_sdma, 1336 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1337 .send_smc_msg = smu_cmn_send_smc_msg, 1338 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, 1339 .gfx_off_control = smu_v12_0_gfx_off_control, 1340 .get_gfx_off_status = smu_v12_0_get_gfxoff_status, 1341 .init_smc_tables = renoir_init_smc_tables, 1342 .fini_smc_tables = smu_v12_0_fini_smc_tables, 1343 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables, 1344 .get_enabled_mask = smu_cmn_get_enabled_mask, 1345 .feature_is_enabled = smu_cmn_feature_is_enabled, 1346 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1347 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq, 1348 .mode2_reset = smu_v12_0_mode2_reset, 1349 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, 1350 .set_driver_table_location = smu_v12_0_set_driver_table_location, 1351 .is_dpm_running = renoir_is_dpm_running, 1352 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1353 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1354 .get_gpu_metrics = renoir_get_gpu_metrics, 1355 .gfx_state_change_set = renoir_gfx_state_change_set, 1356 .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters, 1357 .od_edit_dpm_table = renoir_od_edit_dpm_table, 1358 }; 1359 1360 void renoir_set_ppt_funcs(struct smu_context *smu) 1361 { 1362 smu->ppt_funcs = &renoir_ppt_funcs; 1363 smu->message_map = renoir_message_map; 1364 smu->clock_map = renoir_clk_map; 1365 smu->table_map = renoir_table_map; 1366 smu->workload_map = renoir_workload_map; 1367 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; 1368 smu->is_apu = true; 1369 } 1370