1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v12_0_ppsmc.h" 29 #include "smu12_driver_if.h" 30 #include "smu_v12_0.h" 31 #include "renoir_ppt.h" 32 #include "smu_cmn.h" 33 34 /* 35 * DO NOT use these for err/warn/info/debug messages. 36 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 37 * They are more MGPU friendly. 38 */ 39 #undef pr_err 40 #undef pr_warn 41 #undef pr_info 42 #undef pr_debug 43 44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { 45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1), 49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1), 50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1), 51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1), 56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1), 57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1), 58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 59 MSG_MAP(Spare1, PPSMC_MSG_spare1, 1), 60 MSG_MAP(Spare2, PPSMC_MSG_spare2, 1), 61 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1), 62 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1), 63 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1), 64 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1), 65 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1), 66 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1), 67 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1), 68 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 69 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 70 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 71 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 72 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 73 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1), 74 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1), 75 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 76 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1), 77 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1), 78 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1), 79 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1), 80 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1), 81 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1), 82 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 83 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1), 84 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 85 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 86 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1), 87 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1), 88 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1), 89 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1), 90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 95 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1), 96 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1), 97 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1), 98 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 99 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1), 100 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1), 101 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 102 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 103 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1), 104 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1), 105 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 106 }; 107 108 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { 109 CLK_MAP(GFXCLK, CLOCK_GFXCLK), 110 CLK_MAP(SCLK, CLOCK_GFXCLK), 111 CLK_MAP(SOCCLK, CLOCK_SOCCLK), 112 CLK_MAP(UCLK, CLOCK_FCLK), 113 CLK_MAP(MCLK, CLOCK_FCLK), 114 }; 115 116 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { 117 TAB_MAP_VALID(WATERMARKS), 118 TAB_MAP_INVALID(CUSTOM_DPM), 119 TAB_MAP_VALID(DPMCLOCKS), 120 TAB_MAP_VALID(SMU_METRICS), 121 }; 122 123 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 127 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 128 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 129 }; 130 131 static int renoir_init_smc_tables(struct smu_context *smu) 132 { 133 struct smu_table_context *smu_table = &smu->smu_table; 134 struct smu_table *tables = smu_table->tables; 135 136 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 137 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 138 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 139 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 140 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 141 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 142 143 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 144 if (!smu_table->clocks_table) 145 goto err0_out; 146 147 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 148 if (!smu_table->metrics_table) 149 goto err1_out; 150 smu_table->metrics_time = 0; 151 152 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 153 if (!smu_table->watermarks_table) 154 goto err2_out; 155 156 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); 157 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 158 if (!smu_table->gpu_metrics_table) 159 goto err3_out; 160 161 return 0; 162 163 err3_out: 164 kfree(smu_table->watermarks_table); 165 err2_out: 166 kfree(smu_table->metrics_table); 167 err1_out: 168 kfree(smu_table->clocks_table); 169 err0_out: 170 return -ENOMEM; 171 } 172 173 /* 174 * This interface just for getting uclk ultimate freq and should't introduce 175 * other likewise function result in overmuch callback. 176 */ 177 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 178 uint32_t dpm_level, uint32_t *freq) 179 { 180 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 181 182 if (!clk_table || clk_type >= SMU_CLK_COUNT) 183 return -EINVAL; 184 185 switch (clk_type) { 186 case SMU_SOCCLK: 187 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) 188 return -EINVAL; 189 *freq = clk_table->SocClocks[dpm_level].Freq; 190 break; 191 case SMU_MCLK: 192 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 193 return -EINVAL; 194 *freq = clk_table->FClocks[dpm_level].Freq; 195 break; 196 case SMU_DCEFCLK: 197 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) 198 return -EINVAL; 199 *freq = clk_table->DcfClocks[dpm_level].Freq; 200 break; 201 case SMU_FCLK: 202 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 203 return -EINVAL; 204 *freq = clk_table->FClocks[dpm_level].Freq; 205 break; 206 default: 207 return -EINVAL; 208 } 209 210 return 0; 211 } 212 213 static int renoir_get_profiling_clk_mask(struct smu_context *smu, 214 enum amd_dpm_forced_level level, 215 uint32_t *sclk_mask, 216 uint32_t *mclk_mask, 217 uint32_t *soc_mask) 218 { 219 220 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 221 if (sclk_mask) 222 *sclk_mask = 0; 223 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 224 if (mclk_mask) 225 /* mclk levels are in reverse order */ 226 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; 227 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 228 if(sclk_mask) 229 /* The sclk as gfxclk and has three level about max/min/current */ 230 *sclk_mask = 3 - 1; 231 232 if(mclk_mask) 233 /* mclk levels are in reverse order */ 234 *mclk_mask = 0; 235 236 if(soc_mask) 237 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; 238 } 239 240 return 0; 241 } 242 243 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu, 244 enum smu_clk_type clk_type, 245 uint32_t *min, 246 uint32_t *max) 247 { 248 int ret = 0; 249 uint32_t mclk_mask, soc_mask; 250 uint32_t clock_limit; 251 252 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 253 switch (clk_type) { 254 case SMU_MCLK: 255 case SMU_UCLK: 256 clock_limit = smu->smu_table.boot_values.uclk; 257 break; 258 case SMU_GFXCLK: 259 case SMU_SCLK: 260 clock_limit = smu->smu_table.boot_values.gfxclk; 261 break; 262 case SMU_SOCCLK: 263 clock_limit = smu->smu_table.boot_values.socclk; 264 break; 265 default: 266 clock_limit = 0; 267 break; 268 } 269 270 /* clock in Mhz unit */ 271 if (min) 272 *min = clock_limit / 100; 273 if (max) 274 *max = clock_limit / 100; 275 276 return 0; 277 } 278 279 if (max) { 280 ret = renoir_get_profiling_clk_mask(smu, 281 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 282 NULL, 283 &mclk_mask, 284 &soc_mask); 285 if (ret) 286 goto failed; 287 288 switch (clk_type) { 289 case SMU_GFXCLK: 290 case SMU_SCLK: 291 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max); 292 if (ret) { 293 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n"); 294 goto failed; 295 } 296 break; 297 case SMU_UCLK: 298 case SMU_FCLK: 299 case SMU_MCLK: 300 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 301 if (ret) 302 goto failed; 303 break; 304 case SMU_SOCCLK: 305 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 306 if (ret) 307 goto failed; 308 break; 309 default: 310 ret = -EINVAL; 311 goto failed; 312 } 313 } 314 315 if (min) { 316 switch (clk_type) { 317 case SMU_GFXCLK: 318 case SMU_SCLK: 319 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min); 320 if (ret) { 321 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n"); 322 goto failed; 323 } 324 break; 325 case SMU_UCLK: 326 case SMU_FCLK: 327 case SMU_MCLK: 328 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min); 329 if (ret) 330 goto failed; 331 break; 332 case SMU_SOCCLK: 333 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min); 334 if (ret) 335 goto failed; 336 break; 337 default: 338 ret = -EINVAL; 339 goto failed; 340 } 341 } 342 failed: 343 return ret; 344 } 345 346 static int renoir_print_clk_levels(struct smu_context *smu, 347 enum smu_clk_type clk_type, char *buf) 348 { 349 int i, size = 0, ret = 0; 350 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; 351 SmuMetrics_t metrics; 352 bool cur_value_match_level = false; 353 354 memset(&metrics, 0, sizeof(metrics)); 355 356 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 357 if (ret) 358 return ret; 359 360 switch (clk_type) { 361 case SMU_GFXCLK: 362 case SMU_SCLK: 363 /* retirve table returned paramters unit is MHz */ 364 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; 365 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max); 366 if (!ret) { 367 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 368 if (cur_value == max) 369 i = 2; 370 else if (cur_value == min) 371 i = 0; 372 else 373 i = 1; 374 375 size += sprintf(buf + size, "0: %uMhz %s\n", min, 376 i == 0 ? "*" : ""); 377 size += sprintf(buf + size, "1: %uMhz %s\n", 378 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, 379 i == 1 ? "*" : ""); 380 size += sprintf(buf + size, "2: %uMhz %s\n", max, 381 i == 2 ? "*" : ""); 382 } 383 return size; 384 case SMU_SOCCLK: 385 count = NUM_SOCCLK_DPM_LEVELS; 386 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; 387 break; 388 case SMU_MCLK: 389 count = NUM_MEMCLK_DPM_LEVELS; 390 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 391 break; 392 case SMU_DCEFCLK: 393 count = NUM_DCFCLK_DPM_LEVELS; 394 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK]; 395 break; 396 case SMU_FCLK: 397 count = NUM_FCLK_DPM_LEVELS; 398 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 399 break; 400 default: 401 return -EINVAL; 402 } 403 404 for (i = 0; i < count; i++) { 405 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); 406 if (ret) 407 return ret; 408 if (!value) 409 continue; 410 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 411 cur_value == value ? "*" : ""); 412 if (cur_value == value) 413 cur_value_match_level = true; 414 } 415 416 if (!cur_value_match_level) 417 size += sprintf(buf + size, " %uMhz *\n", cur_value); 418 419 return size; 420 } 421 422 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) 423 { 424 enum amd_pm_state_type pm_type; 425 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 426 427 if (!smu_dpm_ctx->dpm_context || 428 !smu_dpm_ctx->dpm_current_power_state) 429 return -EINVAL; 430 431 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) { 432 case SMU_STATE_UI_LABEL_BATTERY: 433 pm_type = POWER_STATE_TYPE_BATTERY; 434 break; 435 case SMU_STATE_UI_LABEL_BALLANCED: 436 pm_type = POWER_STATE_TYPE_BALANCED; 437 break; 438 case SMU_STATE_UI_LABEL_PERFORMANCE: 439 pm_type = POWER_STATE_TYPE_PERFORMANCE; 440 break; 441 default: 442 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT) 443 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 444 else 445 pm_type = POWER_STATE_TYPE_DEFAULT; 446 break; 447 } 448 449 return pm_type; 450 } 451 452 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 453 { 454 int ret = 0; 455 456 if (enable) { 457 /* vcn dpm on is a prerequisite for vcn power gate messages */ 458 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 459 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 460 if (ret) 461 return ret; 462 } 463 } else { 464 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 465 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 466 if (ret) 467 return ret; 468 } 469 } 470 471 return ret; 472 } 473 474 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 475 { 476 int ret = 0; 477 478 if (enable) { 479 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 480 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 481 if (ret) 482 return ret; 483 } 484 } else { 485 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 486 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 487 if (ret) 488 return ret; 489 } 490 } 491 492 return ret; 493 } 494 495 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest) 496 { 497 int ret = 0, i = 0; 498 uint32_t min_freq, max_freq, force_freq; 499 enum smu_clk_type clk_type; 500 501 enum smu_clk_type clks[] = { 502 SMU_GFXCLK, 503 SMU_MCLK, 504 SMU_SOCCLK, 505 }; 506 507 for (i = 0; i < ARRAY_SIZE(clks); i++) { 508 clk_type = clks[i]; 509 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 510 if (ret) 511 return ret; 512 513 force_freq = highest ? max_freq : min_freq; 514 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 515 if (ret) 516 return ret; 517 } 518 519 return ret; 520 } 521 522 static int renoir_unforce_dpm_levels(struct smu_context *smu) { 523 524 int ret = 0, i = 0; 525 uint32_t min_freq, max_freq; 526 enum smu_clk_type clk_type; 527 528 struct clk_feature_map { 529 enum smu_clk_type clk_type; 530 uint32_t feature; 531 } clk_feature_map[] = { 532 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, 533 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, 534 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 535 }; 536 537 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 538 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 539 continue; 540 541 clk_type = clk_feature_map[i].clk_type; 542 543 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 544 if (ret) 545 return ret; 546 547 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 548 if (ret) 549 return ret; 550 } 551 552 return ret; 553 } 554 555 /* 556 * This interface get dpm clock table for dc 557 */ 558 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 559 { 560 DpmClocks_t *table = smu->smu_table.clocks_table; 561 int i; 562 563 if (!clock_table || !table) 564 return -EINVAL; 565 566 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { 567 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; 568 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; 569 } 570 571 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 572 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq; 573 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; 574 } 575 576 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 577 clock_table->FClocks[i].Freq = table->FClocks[i].Freq; 578 clock_table->FClocks[i].Vol = table->FClocks[i].Vol; 579 } 580 581 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) { 582 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq; 583 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; 584 } 585 586 return 0; 587 } 588 589 static int renoir_force_clk_levels(struct smu_context *smu, 590 enum smu_clk_type clk_type, uint32_t mask) 591 { 592 593 int ret = 0 ; 594 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 595 596 soft_min_level = mask ? (ffs(mask) - 1) : 0; 597 soft_max_level = mask ? (fls(mask) - 1) : 0; 598 599 switch (clk_type) { 600 case SMU_GFXCLK: 601 case SMU_SCLK: 602 if (soft_min_level > 2 || soft_max_level > 2) { 603 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n"); 604 return -EINVAL; 605 } 606 607 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq); 608 if (ret) 609 return ret; 610 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 611 soft_max_level == 0 ? min_freq : 612 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq, 613 NULL); 614 if (ret) 615 return ret; 616 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 617 soft_min_level == 2 ? max_freq : 618 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq, 619 NULL); 620 if (ret) 621 return ret; 622 break; 623 case SMU_SOCCLK: 624 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 625 if (ret) 626 return ret; 627 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 628 if (ret) 629 return ret; 630 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); 631 if (ret) 632 return ret; 633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); 634 if (ret) 635 return ret; 636 break; 637 case SMU_MCLK: 638 case SMU_FCLK: 639 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 640 if (ret) 641 return ret; 642 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 643 if (ret) 644 return ret; 645 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); 646 if (ret) 647 return ret; 648 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); 649 if (ret) 650 return ret; 651 break; 652 default: 653 break; 654 } 655 656 return ret; 657 } 658 659 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 660 { 661 int workload_type, ret; 662 uint32_t profile_mode = input[size]; 663 664 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 665 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 666 return -EINVAL; 667 } 668 669 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 670 workload_type = smu_cmn_to_asic_specific_index(smu, 671 CMN2ASIC_MAPPING_WORKLOAD, 672 profile_mode); 673 if (workload_type < 0) { 674 /* 675 * TODO: If some case need switch to powersave/default power mode 676 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving. 677 */ 678 dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode); 679 return -EINVAL; 680 } 681 682 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 683 1 << workload_type, 684 NULL); 685 if (ret) { 686 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 687 return ret; 688 } 689 690 smu->power_profile_mode = profile_mode; 691 692 return 0; 693 } 694 695 static int renoir_set_peak_clock_by_device(struct smu_context *smu) 696 { 697 int ret = 0; 698 uint32_t sclk_freq = 0, uclk_freq = 0; 699 700 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq); 701 if (ret) 702 return ret; 703 704 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq); 705 if (ret) 706 return ret; 707 708 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq); 709 if (ret) 710 return ret; 711 712 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq); 713 if (ret) 714 return ret; 715 716 return ret; 717 } 718 719 static int renoir_set_performance_level(struct smu_context *smu, 720 enum amd_dpm_forced_level level) 721 { 722 int ret = 0; 723 uint32_t sclk_mask, mclk_mask, soc_mask; 724 725 switch (level) { 726 case AMD_DPM_FORCED_LEVEL_HIGH: 727 ret = renoir_force_dpm_limit_value(smu, true); 728 break; 729 case AMD_DPM_FORCED_LEVEL_LOW: 730 ret = renoir_force_dpm_limit_value(smu, false); 731 break; 732 case AMD_DPM_FORCED_LEVEL_AUTO: 733 ret = renoir_unforce_dpm_levels(smu); 734 break; 735 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 736 ret = smu_cmn_send_smc_msg_with_param(smu, 737 SMU_MSG_SetHardMinGfxClk, 738 RENOIR_UMD_PSTATE_GFXCLK, 739 NULL); 740 if (ret) 741 return ret; 742 ret = smu_cmn_send_smc_msg_with_param(smu, 743 SMU_MSG_SetHardMinFclkByFreq, 744 RENOIR_UMD_PSTATE_FCLK, 745 NULL); 746 if (ret) 747 return ret; 748 ret = smu_cmn_send_smc_msg_with_param(smu, 749 SMU_MSG_SetHardMinSocclkByFreq, 750 RENOIR_UMD_PSTATE_SOCCLK, 751 NULL); 752 if (ret) 753 return ret; 754 ret = smu_cmn_send_smc_msg_with_param(smu, 755 SMU_MSG_SetHardMinVcn, 756 RENOIR_UMD_PSTATE_VCNCLK, 757 NULL); 758 if (ret) 759 return ret; 760 761 ret = smu_cmn_send_smc_msg_with_param(smu, 762 SMU_MSG_SetSoftMaxGfxClk, 763 RENOIR_UMD_PSTATE_GFXCLK, 764 NULL); 765 if (ret) 766 return ret; 767 ret = smu_cmn_send_smc_msg_with_param(smu, 768 SMU_MSG_SetSoftMaxFclkByFreq, 769 RENOIR_UMD_PSTATE_FCLK, 770 NULL); 771 if (ret) 772 return ret; 773 ret = smu_cmn_send_smc_msg_with_param(smu, 774 SMU_MSG_SetSoftMaxSocclkByFreq, 775 RENOIR_UMD_PSTATE_SOCCLK, 776 NULL); 777 if (ret) 778 return ret; 779 ret = smu_cmn_send_smc_msg_with_param(smu, 780 SMU_MSG_SetSoftMaxVcn, 781 RENOIR_UMD_PSTATE_VCNCLK, 782 NULL); 783 if (ret) 784 return ret; 785 break; 786 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 787 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 788 ret = renoir_get_profiling_clk_mask(smu, level, 789 &sclk_mask, 790 &mclk_mask, 791 &soc_mask); 792 if (ret) 793 return ret; 794 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); 795 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 796 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 797 break; 798 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 799 ret = renoir_set_peak_clock_by_device(smu); 800 break; 801 case AMD_DPM_FORCED_LEVEL_MANUAL: 802 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 803 default: 804 break; 805 } 806 return ret; 807 } 808 809 /* save watermark settings into pplib smu structure, 810 * also pass data to smu controller 811 */ 812 static int renoir_set_watermarks_table( 813 struct smu_context *smu, 814 struct pp_smu_wm_range_sets *clock_ranges) 815 { 816 Watermarks_t *table = smu->smu_table.watermarks_table; 817 int ret = 0; 818 int i; 819 820 if (clock_ranges) { 821 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 822 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 823 return -EINVAL; 824 825 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/ 826 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 827 table->WatermarkRow[WM_DCFCLK][i].MinClock = 828 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 829 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 830 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 831 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 832 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 833 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 834 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 835 836 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 837 clock_ranges->reader_wm_sets[i].wm_inst; 838 table->WatermarkRow[WM_DCFCLK][i].WmType = 839 clock_ranges->reader_wm_sets[i].wm_type; 840 } 841 842 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 843 table->WatermarkRow[WM_SOCCLK][i].MinClock = 844 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 845 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 846 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 847 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 848 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 849 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 850 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 851 852 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 853 clock_ranges->writer_wm_sets[i].wm_inst; 854 table->WatermarkRow[WM_SOCCLK][i].WmType = 855 clock_ranges->writer_wm_sets[i].wm_type; 856 } 857 858 smu->watermarks_bitmap |= WATERMARKS_EXIST; 859 } 860 861 /* pass data to smu controller */ 862 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 863 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 864 ret = smu_cmn_write_watermarks_table(smu); 865 if (ret) { 866 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 867 return ret; 868 } 869 smu->watermarks_bitmap |= WATERMARKS_LOADED; 870 } 871 872 return 0; 873 } 874 875 static int renoir_get_power_profile_mode(struct smu_context *smu, 876 char *buf) 877 { 878 static const char *profile_name[] = { 879 "BOOTUP_DEFAULT", 880 "3D_FULL_SCREEN", 881 "POWER_SAVING", 882 "VIDEO", 883 "VR", 884 "COMPUTE", 885 "CUSTOM"}; 886 uint32_t i, size = 0; 887 int16_t workload_type = 0; 888 889 if (!buf) 890 return -EINVAL; 891 892 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 893 /* 894 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 895 * Not all profile modes are supported on arcturus. 896 */ 897 workload_type = smu_cmn_to_asic_specific_index(smu, 898 CMN2ASIC_MAPPING_WORKLOAD, 899 i); 900 if (workload_type < 0) 901 continue; 902 903 size += sprintf(buf + size, "%2d %14s%s\n", 904 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 905 } 906 907 return size; 908 } 909 910 static int renoir_get_smu_metrics_data(struct smu_context *smu, 911 MetricsMember_t member, 912 uint32_t *value) 913 { 914 struct smu_table_context *smu_table = &smu->smu_table; 915 916 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 917 int ret = 0; 918 919 mutex_lock(&smu->metrics_lock); 920 921 ret = smu_cmn_get_metrics_table_locked(smu, 922 NULL, 923 false); 924 if (ret) { 925 mutex_unlock(&smu->metrics_lock); 926 return ret; 927 } 928 929 switch (member) { 930 case METRICS_AVERAGE_GFXCLK: 931 *value = metrics->ClockFrequency[CLOCK_GFXCLK]; 932 break; 933 case METRICS_AVERAGE_SOCCLK: 934 *value = metrics->ClockFrequency[CLOCK_SOCCLK]; 935 break; 936 case METRICS_AVERAGE_UCLK: 937 *value = metrics->ClockFrequency[CLOCK_FCLK]; 938 break; 939 case METRICS_AVERAGE_GFXACTIVITY: 940 *value = metrics->AverageGfxActivity / 100; 941 break; 942 case METRICS_AVERAGE_VCNACTIVITY: 943 *value = metrics->AverageUvdActivity / 100; 944 break; 945 case METRICS_AVERAGE_SOCKETPOWER: 946 *value = metrics->CurrentSocketPower << 8; 947 break; 948 case METRICS_TEMPERATURE_EDGE: 949 *value = (metrics->GfxTemperature / 100) * 950 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 951 break; 952 case METRICS_TEMPERATURE_HOTSPOT: 953 *value = (metrics->SocTemperature / 100) * 954 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 955 break; 956 case METRICS_THROTTLER_STATUS: 957 *value = metrics->ThrottlerStatus; 958 break; 959 case METRICS_VOLTAGE_VDDGFX: 960 *value = metrics->Voltage[0]; 961 break; 962 case METRICS_VOLTAGE_VDDSOC: 963 *value = metrics->Voltage[1]; 964 break; 965 default: 966 *value = UINT_MAX; 967 break; 968 } 969 970 mutex_unlock(&smu->metrics_lock); 971 972 return ret; 973 } 974 975 static int renoir_read_sensor(struct smu_context *smu, 976 enum amd_pp_sensors sensor, 977 void *data, uint32_t *size) 978 { 979 int ret = 0; 980 981 if (!data || !size) 982 return -EINVAL; 983 984 mutex_lock(&smu->sensor_lock); 985 switch (sensor) { 986 case AMDGPU_PP_SENSOR_GPU_LOAD: 987 ret = renoir_get_smu_metrics_data(smu, 988 METRICS_AVERAGE_GFXACTIVITY, 989 (uint32_t *)data); 990 *size = 4; 991 break; 992 case AMDGPU_PP_SENSOR_EDGE_TEMP: 993 ret = renoir_get_smu_metrics_data(smu, 994 METRICS_TEMPERATURE_EDGE, 995 (uint32_t *)data); 996 *size = 4; 997 break; 998 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 999 ret = renoir_get_smu_metrics_data(smu, 1000 METRICS_TEMPERATURE_HOTSPOT, 1001 (uint32_t *)data); 1002 *size = 4; 1003 break; 1004 case AMDGPU_PP_SENSOR_GFX_MCLK: 1005 ret = renoir_get_smu_metrics_data(smu, 1006 METRICS_AVERAGE_UCLK, 1007 (uint32_t *)data); 1008 *(uint32_t *)data *= 100; 1009 *size = 4; 1010 break; 1011 case AMDGPU_PP_SENSOR_GFX_SCLK: 1012 ret = renoir_get_smu_metrics_data(smu, 1013 METRICS_AVERAGE_GFXCLK, 1014 (uint32_t *)data); 1015 *(uint32_t *)data *= 100; 1016 *size = 4; 1017 break; 1018 case AMDGPU_PP_SENSOR_VDDGFX: 1019 ret = renoir_get_smu_metrics_data(smu, 1020 METRICS_VOLTAGE_VDDGFX, 1021 (uint32_t *)data); 1022 *size = 4; 1023 break; 1024 case AMDGPU_PP_SENSOR_VDDNB: 1025 ret = renoir_get_smu_metrics_data(smu, 1026 METRICS_VOLTAGE_VDDSOC, 1027 (uint32_t *)data); 1028 *size = 4; 1029 break; 1030 case AMDGPU_PP_SENSOR_GPU_POWER: 1031 ret = renoir_get_smu_metrics_data(smu, 1032 METRICS_AVERAGE_SOCKETPOWER, 1033 (uint32_t *)data); 1034 *size = 4; 1035 break; 1036 default: 1037 ret = -EOPNOTSUPP; 1038 break; 1039 } 1040 mutex_unlock(&smu->sensor_lock); 1041 1042 return ret; 1043 } 1044 1045 static bool renoir_is_dpm_running(struct smu_context *smu) 1046 { 1047 struct amdgpu_device *adev = smu->adev; 1048 1049 /* 1050 * Until now, the pmfw hasn't exported the interface of SMU 1051 * feature mask to APU SKU so just force on all the feature 1052 * at early initial stage. 1053 */ 1054 if (adev->in_suspend) 1055 return false; 1056 else 1057 return true; 1058 1059 } 1060 1061 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, 1062 void **table) 1063 { 1064 struct smu_table_context *smu_table = &smu->smu_table; 1065 struct gpu_metrics_v2_0 *gpu_metrics = 1066 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; 1067 SmuMetrics_t metrics; 1068 int ret = 0; 1069 1070 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1071 if (ret) 1072 return ret; 1073 1074 smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics); 1075 1076 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1077 gpu_metrics->temperature_soc = metrics.SocTemperature; 1078 memcpy(&gpu_metrics->temperature_core[0], 1079 &metrics.CoreTemperature[0], 1080 sizeof(uint16_t) * 8); 1081 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1082 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1083 1084 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1085 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity; 1086 1087 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1088 gpu_metrics->average_cpu_power = metrics.Power[0]; 1089 gpu_metrics->average_soc_power = metrics.Power[1]; 1090 memcpy(&gpu_metrics->average_core_power[0], 1091 &metrics.CorePower[0], 1092 sizeof(uint16_t) * 8); 1093 1094 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1095 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1096 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency; 1097 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency; 1098 1099 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK]; 1100 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK]; 1101 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK]; 1102 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK]; 1103 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK]; 1104 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK]; 1105 memcpy(&gpu_metrics->current_coreclk[0], 1106 &metrics.CoreFrequency[0], 1107 sizeof(uint16_t) * 8); 1108 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1109 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1110 1111 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1112 1113 gpu_metrics->fan_pwm = metrics.FanPwm; 1114 1115 *table = (void *)gpu_metrics; 1116 1117 return sizeof(struct gpu_metrics_v2_0); 1118 } 1119 1120 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) 1121 { 1122 1123 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GpuChangeState, state, NULL); 1124 } 1125 1126 static const struct pptable_funcs renoir_ppt_funcs = { 1127 .set_power_state = NULL, 1128 .print_clk_levels = renoir_print_clk_levels, 1129 .get_current_power_state = renoir_get_current_power_state, 1130 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable, 1131 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable, 1132 .force_clk_levels = renoir_force_clk_levels, 1133 .set_power_profile_mode = renoir_set_power_profile_mode, 1134 .set_performance_level = renoir_set_performance_level, 1135 .get_dpm_clock_table = renoir_get_dpm_clock_table, 1136 .set_watermarks_table = renoir_set_watermarks_table, 1137 .get_power_profile_mode = renoir_get_power_profile_mode, 1138 .read_sensor = renoir_read_sensor, 1139 .check_fw_status = smu_v12_0_check_fw_status, 1140 .check_fw_version = smu_v12_0_check_fw_version, 1141 .powergate_sdma = smu_v12_0_powergate_sdma, 1142 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1143 .send_smc_msg = smu_cmn_send_smc_msg, 1144 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, 1145 .gfx_off_control = smu_v12_0_gfx_off_control, 1146 .get_gfx_off_status = smu_v12_0_get_gfxoff_status, 1147 .init_smc_tables = renoir_init_smc_tables, 1148 .fini_smc_tables = smu_v12_0_fini_smc_tables, 1149 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables, 1150 .get_enabled_mask = smu_cmn_get_enabled_mask, 1151 .feature_is_enabled = smu_cmn_feature_is_enabled, 1152 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1153 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq, 1154 .mode2_reset = smu_v12_0_mode2_reset, 1155 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, 1156 .set_driver_table_location = smu_v12_0_set_driver_table_location, 1157 .is_dpm_running = renoir_is_dpm_running, 1158 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1159 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1160 .get_gpu_metrics = renoir_get_gpu_metrics, 1161 .gfx_state_change_set = renoir_gfx_state_change_set, 1162 }; 1163 1164 void renoir_set_ppt_funcs(struct smu_context *smu) 1165 { 1166 smu->ppt_funcs = &renoir_ppt_funcs; 1167 smu->message_map = renoir_message_map; 1168 smu->clock_map = renoir_clk_map; 1169 smu->table_map = renoir_table_map; 1170 smu->workload_map = renoir_workload_map; 1171 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; 1172 smu->is_apu = true; 1173 } 1174