1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v12_0_ppsmc.h" 29 #include "smu12_driver_if.h" 30 #include "smu_v12_0.h" 31 #include "renoir_ppt.h" 32 #include "smu_cmn.h" 33 34 /* 35 * DO NOT use these for err/warn/info/debug messages. 36 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 37 * They are more MGPU friendly. 38 */ 39 #undef pr_err 40 #undef pr_warn 41 #undef pr_info 42 #undef pr_debug 43 44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { 45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1), 49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1), 50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1), 51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1), 56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1), 57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1), 58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 59 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1), 60 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1), 61 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1), 62 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1), 63 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1), 64 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1), 65 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1), 66 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 67 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 68 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 69 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 70 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 71 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1), 72 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1), 73 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 74 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1), 75 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1), 76 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1), 77 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1), 78 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1), 79 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1), 80 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 81 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1), 82 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 83 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 84 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1), 85 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1), 86 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1), 87 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1), 88 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 89 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 90 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 91 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 92 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 93 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1), 94 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1), 95 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1), 96 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 97 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1), 98 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1), 99 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 100 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 101 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1), 102 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1), 103 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 104 }; 105 106 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { 107 CLK_MAP(GFXCLK, CLOCK_GFXCLK), 108 CLK_MAP(SCLK, CLOCK_GFXCLK), 109 CLK_MAP(SOCCLK, CLOCK_SOCCLK), 110 CLK_MAP(UCLK, CLOCK_FCLK), 111 CLK_MAP(MCLK, CLOCK_FCLK), 112 CLK_MAP(VCLK, CLOCK_VCLK), 113 CLK_MAP(DCLK, CLOCK_DCLK), 114 }; 115 116 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { 117 TAB_MAP_VALID(WATERMARKS), 118 TAB_MAP_INVALID(CUSTOM_DPM), 119 TAB_MAP_VALID(DPMCLOCKS), 120 TAB_MAP_VALID(SMU_METRICS), 121 }; 122 123 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 127 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 128 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 129 }; 130 131 static int renoir_init_smc_tables(struct smu_context *smu) 132 { 133 struct smu_table_context *smu_table = &smu->smu_table; 134 struct smu_table *tables = smu_table->tables; 135 136 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 137 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 138 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 139 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 140 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 141 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 142 143 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 144 if (!smu_table->clocks_table) 145 goto err0_out; 146 147 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 148 if (!smu_table->metrics_table) 149 goto err1_out; 150 smu_table->metrics_time = 0; 151 152 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 153 if (!smu_table->watermarks_table) 154 goto err2_out; 155 156 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); 157 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 158 if (!smu_table->gpu_metrics_table) 159 goto err3_out; 160 161 return 0; 162 163 err3_out: 164 kfree(smu_table->watermarks_table); 165 err2_out: 166 kfree(smu_table->metrics_table); 167 err1_out: 168 kfree(smu_table->clocks_table); 169 err0_out: 170 return -ENOMEM; 171 } 172 173 /* 174 * This interface just for getting uclk ultimate freq and should't introduce 175 * other likewise function result in overmuch callback. 176 */ 177 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 178 uint32_t dpm_level, uint32_t *freq) 179 { 180 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 181 182 if (!clk_table || clk_type >= SMU_CLK_COUNT) 183 return -EINVAL; 184 185 switch (clk_type) { 186 case SMU_SOCCLK: 187 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) 188 return -EINVAL; 189 *freq = clk_table->SocClocks[dpm_level].Freq; 190 break; 191 case SMU_UCLK: 192 case SMU_MCLK: 193 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 194 return -EINVAL; 195 *freq = clk_table->FClocks[dpm_level].Freq; 196 break; 197 case SMU_DCEFCLK: 198 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) 199 return -EINVAL; 200 *freq = clk_table->DcfClocks[dpm_level].Freq; 201 break; 202 case SMU_FCLK: 203 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 204 return -EINVAL; 205 *freq = clk_table->FClocks[dpm_level].Freq; 206 break; 207 case SMU_VCLK: 208 if (dpm_level >= NUM_VCN_DPM_LEVELS) 209 return -EINVAL; 210 *freq = clk_table->VClocks[dpm_level].Freq; 211 break; 212 case SMU_DCLK: 213 if (dpm_level >= NUM_VCN_DPM_LEVELS) 214 return -EINVAL; 215 *freq = clk_table->DClocks[dpm_level].Freq; 216 break; 217 218 default: 219 return -EINVAL; 220 } 221 222 return 0; 223 } 224 225 static int renoir_get_profiling_clk_mask(struct smu_context *smu, 226 enum amd_dpm_forced_level level, 227 uint32_t *sclk_mask, 228 uint32_t *mclk_mask, 229 uint32_t *soc_mask) 230 { 231 232 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 233 if (sclk_mask) 234 *sclk_mask = 0; 235 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 236 if (mclk_mask) 237 /* mclk levels are in reverse order */ 238 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; 239 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 240 if(sclk_mask) 241 /* The sclk as gfxclk and has three level about max/min/current */ 242 *sclk_mask = 3 - 1; 243 244 if(mclk_mask) 245 /* mclk levels are in reverse order */ 246 *mclk_mask = 0; 247 248 if(soc_mask) 249 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; 250 } 251 252 return 0; 253 } 254 255 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu, 256 enum smu_clk_type clk_type, 257 uint32_t *min, 258 uint32_t *max) 259 { 260 int ret = 0; 261 uint32_t mclk_mask, soc_mask; 262 uint32_t clock_limit; 263 264 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 265 switch (clk_type) { 266 case SMU_MCLK: 267 case SMU_UCLK: 268 clock_limit = smu->smu_table.boot_values.uclk; 269 break; 270 case SMU_GFXCLK: 271 case SMU_SCLK: 272 clock_limit = smu->smu_table.boot_values.gfxclk; 273 break; 274 case SMU_SOCCLK: 275 clock_limit = smu->smu_table.boot_values.socclk; 276 break; 277 default: 278 clock_limit = 0; 279 break; 280 } 281 282 /* clock in Mhz unit */ 283 if (min) 284 *min = clock_limit / 100; 285 if (max) 286 *max = clock_limit / 100; 287 288 return 0; 289 } 290 291 if (max) { 292 ret = renoir_get_profiling_clk_mask(smu, 293 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 294 NULL, 295 &mclk_mask, 296 &soc_mask); 297 if (ret) 298 goto failed; 299 300 switch (clk_type) { 301 case SMU_GFXCLK: 302 case SMU_SCLK: 303 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max); 304 if (ret) { 305 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n"); 306 goto failed; 307 } 308 break; 309 case SMU_UCLK: 310 case SMU_FCLK: 311 case SMU_MCLK: 312 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 313 if (ret) 314 goto failed; 315 break; 316 case SMU_SOCCLK: 317 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 318 if (ret) 319 goto failed; 320 break; 321 default: 322 ret = -EINVAL; 323 goto failed; 324 } 325 } 326 327 if (min) { 328 switch (clk_type) { 329 case SMU_GFXCLK: 330 case SMU_SCLK: 331 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min); 332 if (ret) { 333 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n"); 334 goto failed; 335 } 336 break; 337 case SMU_UCLK: 338 case SMU_FCLK: 339 case SMU_MCLK: 340 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min); 341 if (ret) 342 goto failed; 343 break; 344 case SMU_SOCCLK: 345 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min); 346 if (ret) 347 goto failed; 348 break; 349 default: 350 ret = -EINVAL; 351 goto failed; 352 } 353 } 354 failed: 355 return ret; 356 } 357 358 static int renoir_od_edit_dpm_table(struct smu_context *smu, 359 enum PP_OD_DPM_TABLE_COMMAND type, 360 long input[], uint32_t size) 361 { 362 int ret = 0; 363 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 364 365 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 366 dev_warn(smu->adev->dev, 367 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 368 return -EINVAL; 369 } 370 371 switch (type) { 372 case PP_OD_EDIT_SCLK_VDDC_TABLE: 373 if (size != 2) { 374 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 375 return -EINVAL; 376 } 377 378 if (input[0] == 0) { 379 if (input[1] < smu->gfx_default_hard_min_freq) { 380 dev_warn(smu->adev->dev, 381 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 382 input[1], smu->gfx_default_hard_min_freq); 383 return -EINVAL; 384 } 385 smu->gfx_actual_hard_min_freq = input[1]; 386 } else if (input[0] == 1) { 387 if (input[1] > smu->gfx_default_soft_max_freq) { 388 dev_warn(smu->adev->dev, 389 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 390 input[1], smu->gfx_default_soft_max_freq); 391 return -EINVAL; 392 } 393 smu->gfx_actual_soft_max_freq = input[1]; 394 } else { 395 return -EINVAL; 396 } 397 break; 398 case PP_OD_RESTORE_DEFAULT_TABLE: 399 if (size != 0) { 400 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 401 return -EINVAL; 402 } 403 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 404 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 405 break; 406 case PP_OD_COMMIT_DPM_TABLE: 407 if (size != 0) { 408 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 409 return -EINVAL; 410 } else { 411 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 412 dev_err(smu->adev->dev, 413 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 414 smu->gfx_actual_hard_min_freq, 415 smu->gfx_actual_soft_max_freq); 416 return -EINVAL; 417 } 418 419 ret = smu_cmn_send_smc_msg_with_param(smu, 420 SMU_MSG_SetHardMinGfxClk, 421 smu->gfx_actual_hard_min_freq, 422 NULL); 423 if (ret) { 424 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 425 return ret; 426 } 427 428 ret = smu_cmn_send_smc_msg_with_param(smu, 429 SMU_MSG_SetSoftMaxGfxClk, 430 smu->gfx_actual_soft_max_freq, 431 NULL); 432 if (ret) { 433 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 434 return ret; 435 } 436 } 437 break; 438 default: 439 return -ENOSYS; 440 } 441 442 return ret; 443 } 444 445 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 446 { 447 uint32_t min = 0, max = 0; 448 uint32_t ret = 0; 449 450 ret = smu_cmn_send_smc_msg_with_param(smu, 451 SMU_MSG_GetMinGfxclkFrequency, 452 0, &min); 453 if (ret) 454 return ret; 455 ret = smu_cmn_send_smc_msg_with_param(smu, 456 SMU_MSG_GetMaxGfxclkFrequency, 457 0, &max); 458 if (ret) 459 return ret; 460 461 smu->gfx_default_hard_min_freq = min; 462 smu->gfx_default_soft_max_freq = max; 463 smu->gfx_actual_hard_min_freq = 0; 464 smu->gfx_actual_soft_max_freq = 0; 465 466 return 0; 467 } 468 469 static int renoir_print_clk_levels(struct smu_context *smu, 470 enum smu_clk_type clk_type, char *buf) 471 { 472 int i, size = 0, ret = 0; 473 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; 474 SmuMetrics_t metrics; 475 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 476 bool cur_value_match_level = false; 477 478 memset(&metrics, 0, sizeof(metrics)); 479 480 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 481 if (ret) 482 return ret; 483 484 switch (clk_type) { 485 case SMU_OD_RANGE: 486 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 487 ret = smu_cmn_send_smc_msg_with_param(smu, 488 SMU_MSG_GetMinGfxclkFrequency, 489 0, &min); 490 if (ret) 491 return ret; 492 ret = smu_cmn_send_smc_msg_with_param(smu, 493 SMU_MSG_GetMaxGfxclkFrequency, 494 0, &max); 495 if (ret) 496 return ret; 497 size += sprintf(buf + size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max); 498 } 499 break; 500 case SMU_OD_SCLK: 501 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 502 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 503 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 504 size += sprintf(buf + size, "OD_SCLK\n"); 505 size += sprintf(buf + size, "0:%10uMhz\n", min); 506 size += sprintf(buf + size, "1:%10uMhz\n", max); 507 } 508 break; 509 case SMU_GFXCLK: 510 case SMU_SCLK: 511 /* retirve table returned paramters unit is MHz */ 512 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; 513 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max); 514 if (!ret) { 515 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 516 if (cur_value == max) 517 i = 2; 518 else if (cur_value == min) 519 i = 0; 520 else 521 i = 1; 522 523 size += sprintf(buf + size, "0: %uMhz %s\n", min, 524 i == 0 ? "*" : ""); 525 size += sprintf(buf + size, "1: %uMhz %s\n", 526 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, 527 i == 1 ? "*" : ""); 528 size += sprintf(buf + size, "2: %uMhz %s\n", max, 529 i == 2 ? "*" : ""); 530 } 531 return size; 532 case SMU_SOCCLK: 533 count = NUM_SOCCLK_DPM_LEVELS; 534 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; 535 break; 536 case SMU_MCLK: 537 count = NUM_MEMCLK_DPM_LEVELS; 538 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 539 break; 540 case SMU_DCEFCLK: 541 count = NUM_DCFCLK_DPM_LEVELS; 542 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK]; 543 break; 544 case SMU_FCLK: 545 count = NUM_FCLK_DPM_LEVELS; 546 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 547 break; 548 case SMU_VCLK: 549 count = NUM_VCN_DPM_LEVELS; 550 cur_value = metrics.ClockFrequency[CLOCK_VCLK]; 551 break; 552 case SMU_DCLK: 553 count = NUM_VCN_DPM_LEVELS; 554 cur_value = metrics.ClockFrequency[CLOCK_DCLK]; 555 break; 556 default: 557 break; 558 } 559 560 switch (clk_type) { 561 case SMU_GFXCLK: 562 case SMU_SCLK: 563 case SMU_SOCCLK: 564 case SMU_MCLK: 565 case SMU_DCEFCLK: 566 case SMU_FCLK: 567 case SMU_VCLK: 568 case SMU_DCLK: 569 for (i = 0; i < count; i++) { 570 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); 571 if (ret) 572 return ret; 573 if (!value) 574 continue; 575 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 576 cur_value == value ? "*" : ""); 577 if (cur_value == value) 578 cur_value_match_level = true; 579 } 580 581 if (!cur_value_match_level) 582 size += sprintf(buf + size, " %uMhz *\n", cur_value); 583 584 break; 585 default: 586 break; 587 } 588 589 return size; 590 } 591 592 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) 593 { 594 enum amd_pm_state_type pm_type; 595 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 596 597 if (!smu_dpm_ctx->dpm_context || 598 !smu_dpm_ctx->dpm_current_power_state) 599 return -EINVAL; 600 601 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) { 602 case SMU_STATE_UI_LABEL_BATTERY: 603 pm_type = POWER_STATE_TYPE_BATTERY; 604 break; 605 case SMU_STATE_UI_LABEL_BALLANCED: 606 pm_type = POWER_STATE_TYPE_BALANCED; 607 break; 608 case SMU_STATE_UI_LABEL_PERFORMANCE: 609 pm_type = POWER_STATE_TYPE_PERFORMANCE; 610 break; 611 default: 612 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT) 613 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 614 else 615 pm_type = POWER_STATE_TYPE_DEFAULT; 616 break; 617 } 618 619 return pm_type; 620 } 621 622 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 623 { 624 int ret = 0; 625 626 if (enable) { 627 /* vcn dpm on is a prerequisite for vcn power gate messages */ 628 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 629 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 630 if (ret) 631 return ret; 632 } 633 } else { 634 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 635 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 636 if (ret) 637 return ret; 638 } 639 } 640 641 return ret; 642 } 643 644 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 645 { 646 int ret = 0; 647 648 if (enable) { 649 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 650 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 651 if (ret) 652 return ret; 653 } 654 } else { 655 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 656 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 657 if (ret) 658 return ret; 659 } 660 } 661 662 return ret; 663 } 664 665 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest) 666 { 667 int ret = 0, i = 0; 668 uint32_t min_freq, max_freq, force_freq; 669 enum smu_clk_type clk_type; 670 671 enum smu_clk_type clks[] = { 672 SMU_GFXCLK, 673 SMU_MCLK, 674 SMU_SOCCLK, 675 }; 676 677 for (i = 0; i < ARRAY_SIZE(clks); i++) { 678 clk_type = clks[i]; 679 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 680 if (ret) 681 return ret; 682 683 force_freq = highest ? max_freq : min_freq; 684 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 685 if (ret) 686 return ret; 687 } 688 689 return ret; 690 } 691 692 static int renoir_unforce_dpm_levels(struct smu_context *smu) { 693 694 int ret = 0, i = 0; 695 uint32_t min_freq, max_freq; 696 enum smu_clk_type clk_type; 697 698 struct clk_feature_map { 699 enum smu_clk_type clk_type; 700 uint32_t feature; 701 } clk_feature_map[] = { 702 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, 703 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, 704 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 705 }; 706 707 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 708 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 709 continue; 710 711 clk_type = clk_feature_map[i].clk_type; 712 713 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 714 if (ret) 715 return ret; 716 717 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 718 if (ret) 719 return ret; 720 } 721 722 return ret; 723 } 724 725 /* 726 * This interface get dpm clock table for dc 727 */ 728 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 729 { 730 DpmClocks_t *table = smu->smu_table.clocks_table; 731 int i; 732 733 if (!clock_table || !table) 734 return -EINVAL; 735 736 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { 737 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; 738 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; 739 } 740 741 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 742 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq; 743 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; 744 } 745 746 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 747 clock_table->FClocks[i].Freq = table->FClocks[i].Freq; 748 clock_table->FClocks[i].Vol = table->FClocks[i].Vol; 749 } 750 751 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) { 752 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq; 753 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; 754 } 755 756 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { 757 clock_table->VClocks[i].Freq = table->VClocks[i].Freq; 758 clock_table->VClocks[i].Vol = table->VClocks[i].Vol; 759 } 760 761 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { 762 clock_table->DClocks[i].Freq = table->DClocks[i].Freq; 763 clock_table->DClocks[i].Vol = table->DClocks[i].Vol; 764 } 765 766 return 0; 767 } 768 769 static int renoir_force_clk_levels(struct smu_context *smu, 770 enum smu_clk_type clk_type, uint32_t mask) 771 { 772 773 int ret = 0 ; 774 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 775 776 soft_min_level = mask ? (ffs(mask) - 1) : 0; 777 soft_max_level = mask ? (fls(mask) - 1) : 0; 778 779 switch (clk_type) { 780 case SMU_GFXCLK: 781 case SMU_SCLK: 782 if (soft_min_level > 2 || soft_max_level > 2) { 783 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n"); 784 return -EINVAL; 785 } 786 787 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq); 788 if (ret) 789 return ret; 790 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 791 soft_max_level == 0 ? min_freq : 792 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq, 793 NULL); 794 if (ret) 795 return ret; 796 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 797 soft_min_level == 2 ? max_freq : 798 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq, 799 NULL); 800 if (ret) 801 return ret; 802 break; 803 case SMU_SOCCLK: 804 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 805 if (ret) 806 return ret; 807 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 808 if (ret) 809 return ret; 810 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); 811 if (ret) 812 return ret; 813 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); 814 if (ret) 815 return ret; 816 break; 817 case SMU_MCLK: 818 case SMU_FCLK: 819 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 820 if (ret) 821 return ret; 822 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 823 if (ret) 824 return ret; 825 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); 826 if (ret) 827 return ret; 828 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); 829 if (ret) 830 return ret; 831 break; 832 default: 833 break; 834 } 835 836 return ret; 837 } 838 839 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 840 { 841 int workload_type, ret; 842 uint32_t profile_mode = input[size]; 843 844 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 845 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 846 return -EINVAL; 847 } 848 849 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 850 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 851 return 0; 852 853 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 854 workload_type = smu_cmn_to_asic_specific_index(smu, 855 CMN2ASIC_MAPPING_WORKLOAD, 856 profile_mode); 857 if (workload_type < 0) { 858 /* 859 * TODO: If some case need switch to powersave/default power mode 860 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving. 861 */ 862 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode); 863 return -EINVAL; 864 } 865 866 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 867 1 << workload_type, 868 NULL); 869 if (ret) { 870 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 871 return ret; 872 } 873 874 smu->power_profile_mode = profile_mode; 875 876 return 0; 877 } 878 879 static int renoir_set_peak_clock_by_device(struct smu_context *smu) 880 { 881 int ret = 0; 882 uint32_t sclk_freq = 0, uclk_freq = 0; 883 884 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq); 885 if (ret) 886 return ret; 887 888 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq); 889 if (ret) 890 return ret; 891 892 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq); 893 if (ret) 894 return ret; 895 896 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq); 897 if (ret) 898 return ret; 899 900 return ret; 901 } 902 903 static int renoir_set_performance_level(struct smu_context *smu, 904 enum amd_dpm_forced_level level) 905 { 906 int ret = 0; 907 uint32_t sclk_mask, mclk_mask, soc_mask; 908 909 switch (level) { 910 case AMD_DPM_FORCED_LEVEL_HIGH: 911 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 912 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 913 914 ret = renoir_force_dpm_limit_value(smu, true); 915 break; 916 case AMD_DPM_FORCED_LEVEL_LOW: 917 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 918 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 919 920 ret = renoir_force_dpm_limit_value(smu, false); 921 break; 922 case AMD_DPM_FORCED_LEVEL_AUTO: 923 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 924 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 925 926 ret = renoir_unforce_dpm_levels(smu); 927 break; 928 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 929 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 930 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 931 932 ret = smu_cmn_send_smc_msg_with_param(smu, 933 SMU_MSG_SetHardMinGfxClk, 934 RENOIR_UMD_PSTATE_GFXCLK, 935 NULL); 936 if (ret) 937 return ret; 938 ret = smu_cmn_send_smc_msg_with_param(smu, 939 SMU_MSG_SetHardMinFclkByFreq, 940 RENOIR_UMD_PSTATE_FCLK, 941 NULL); 942 if (ret) 943 return ret; 944 ret = smu_cmn_send_smc_msg_with_param(smu, 945 SMU_MSG_SetHardMinSocclkByFreq, 946 RENOIR_UMD_PSTATE_SOCCLK, 947 NULL); 948 if (ret) 949 return ret; 950 ret = smu_cmn_send_smc_msg_with_param(smu, 951 SMU_MSG_SetHardMinVcn, 952 RENOIR_UMD_PSTATE_VCNCLK, 953 NULL); 954 if (ret) 955 return ret; 956 957 ret = smu_cmn_send_smc_msg_with_param(smu, 958 SMU_MSG_SetSoftMaxGfxClk, 959 RENOIR_UMD_PSTATE_GFXCLK, 960 NULL); 961 if (ret) 962 return ret; 963 ret = smu_cmn_send_smc_msg_with_param(smu, 964 SMU_MSG_SetSoftMaxFclkByFreq, 965 RENOIR_UMD_PSTATE_FCLK, 966 NULL); 967 if (ret) 968 return ret; 969 ret = smu_cmn_send_smc_msg_with_param(smu, 970 SMU_MSG_SetSoftMaxSocclkByFreq, 971 RENOIR_UMD_PSTATE_SOCCLK, 972 NULL); 973 if (ret) 974 return ret; 975 ret = smu_cmn_send_smc_msg_with_param(smu, 976 SMU_MSG_SetSoftMaxVcn, 977 RENOIR_UMD_PSTATE_VCNCLK, 978 NULL); 979 if (ret) 980 return ret; 981 break; 982 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 983 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 984 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 985 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 986 987 ret = renoir_get_profiling_clk_mask(smu, level, 988 &sclk_mask, 989 &mclk_mask, 990 &soc_mask); 991 if (ret) 992 return ret; 993 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); 994 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 995 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 996 break; 997 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 998 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 999 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1000 1001 ret = renoir_set_peak_clock_by_device(smu); 1002 break; 1003 case AMD_DPM_FORCED_LEVEL_MANUAL: 1004 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1005 default: 1006 break; 1007 } 1008 return ret; 1009 } 1010 1011 /* save watermark settings into pplib smu structure, 1012 * also pass data to smu controller 1013 */ 1014 static int renoir_set_watermarks_table( 1015 struct smu_context *smu, 1016 struct pp_smu_wm_range_sets *clock_ranges) 1017 { 1018 Watermarks_t *table = smu->smu_table.watermarks_table; 1019 int ret = 0; 1020 int i; 1021 1022 if (clock_ranges) { 1023 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1024 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1025 return -EINVAL; 1026 1027 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/ 1028 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1029 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1030 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1031 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1032 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1033 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1034 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1035 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1036 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1037 1038 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1039 clock_ranges->reader_wm_sets[i].wm_inst; 1040 table->WatermarkRow[WM_DCFCLK][i].WmType = 1041 clock_ranges->reader_wm_sets[i].wm_type; 1042 } 1043 1044 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1045 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1046 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1047 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1048 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1049 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1050 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1051 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1052 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1053 1054 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1055 clock_ranges->writer_wm_sets[i].wm_inst; 1056 table->WatermarkRow[WM_SOCCLK][i].WmType = 1057 clock_ranges->writer_wm_sets[i].wm_type; 1058 } 1059 1060 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1061 } 1062 1063 /* pass data to smu controller */ 1064 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1065 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1066 ret = smu_cmn_write_watermarks_table(smu); 1067 if (ret) { 1068 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1069 return ret; 1070 } 1071 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1072 } 1073 1074 return 0; 1075 } 1076 1077 static int renoir_get_power_profile_mode(struct smu_context *smu, 1078 char *buf) 1079 { 1080 static const char *profile_name[] = { 1081 "BOOTUP_DEFAULT", 1082 "3D_FULL_SCREEN", 1083 "POWER_SAVING", 1084 "VIDEO", 1085 "VR", 1086 "COMPUTE", 1087 "CUSTOM"}; 1088 uint32_t i, size = 0; 1089 int16_t workload_type = 0; 1090 1091 if (!buf) 1092 return -EINVAL; 1093 1094 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1095 /* 1096 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1097 * Not all profile modes are supported on arcturus. 1098 */ 1099 workload_type = smu_cmn_to_asic_specific_index(smu, 1100 CMN2ASIC_MAPPING_WORKLOAD, 1101 i); 1102 if (workload_type < 0) 1103 continue; 1104 1105 size += sprintf(buf + size, "%2d %14s%s\n", 1106 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1107 } 1108 1109 return size; 1110 } 1111 1112 static int renoir_get_smu_metrics_data(struct smu_context *smu, 1113 MetricsMember_t member, 1114 uint32_t *value) 1115 { 1116 struct smu_table_context *smu_table = &smu->smu_table; 1117 1118 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 1119 int ret = 0; 1120 1121 mutex_lock(&smu->metrics_lock); 1122 1123 ret = smu_cmn_get_metrics_table_locked(smu, 1124 NULL, 1125 false); 1126 if (ret) { 1127 mutex_unlock(&smu->metrics_lock); 1128 return ret; 1129 } 1130 1131 switch (member) { 1132 case METRICS_AVERAGE_GFXCLK: 1133 *value = metrics->ClockFrequency[CLOCK_GFXCLK]; 1134 break; 1135 case METRICS_AVERAGE_SOCCLK: 1136 *value = metrics->ClockFrequency[CLOCK_SOCCLK]; 1137 break; 1138 case METRICS_AVERAGE_UCLK: 1139 *value = metrics->ClockFrequency[CLOCK_FCLK]; 1140 break; 1141 case METRICS_AVERAGE_GFXACTIVITY: 1142 *value = metrics->AverageGfxActivity / 100; 1143 break; 1144 case METRICS_AVERAGE_VCNACTIVITY: 1145 *value = metrics->AverageUvdActivity / 100; 1146 break; 1147 case METRICS_AVERAGE_SOCKETPOWER: 1148 *value = (metrics->CurrentSocketPower << 8) / 1000; 1149 break; 1150 case METRICS_TEMPERATURE_EDGE: 1151 *value = (metrics->GfxTemperature / 100) * 1152 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1153 break; 1154 case METRICS_TEMPERATURE_HOTSPOT: 1155 *value = (metrics->SocTemperature / 100) * 1156 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1157 break; 1158 case METRICS_THROTTLER_STATUS: 1159 *value = metrics->ThrottlerStatus; 1160 break; 1161 case METRICS_VOLTAGE_VDDGFX: 1162 *value = metrics->Voltage[0]; 1163 break; 1164 case METRICS_VOLTAGE_VDDSOC: 1165 *value = metrics->Voltage[1]; 1166 break; 1167 default: 1168 *value = UINT_MAX; 1169 break; 1170 } 1171 1172 mutex_unlock(&smu->metrics_lock); 1173 1174 return ret; 1175 } 1176 1177 static int renoir_read_sensor(struct smu_context *smu, 1178 enum amd_pp_sensors sensor, 1179 void *data, uint32_t *size) 1180 { 1181 int ret = 0; 1182 1183 if (!data || !size) 1184 return -EINVAL; 1185 1186 mutex_lock(&smu->sensor_lock); 1187 switch (sensor) { 1188 case AMDGPU_PP_SENSOR_GPU_LOAD: 1189 ret = renoir_get_smu_metrics_data(smu, 1190 METRICS_AVERAGE_GFXACTIVITY, 1191 (uint32_t *)data); 1192 *size = 4; 1193 break; 1194 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1195 ret = renoir_get_smu_metrics_data(smu, 1196 METRICS_TEMPERATURE_EDGE, 1197 (uint32_t *)data); 1198 *size = 4; 1199 break; 1200 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1201 ret = renoir_get_smu_metrics_data(smu, 1202 METRICS_TEMPERATURE_HOTSPOT, 1203 (uint32_t *)data); 1204 *size = 4; 1205 break; 1206 case AMDGPU_PP_SENSOR_GFX_MCLK: 1207 ret = renoir_get_smu_metrics_data(smu, 1208 METRICS_AVERAGE_UCLK, 1209 (uint32_t *)data); 1210 *(uint32_t *)data *= 100; 1211 *size = 4; 1212 break; 1213 case AMDGPU_PP_SENSOR_GFX_SCLK: 1214 ret = renoir_get_smu_metrics_data(smu, 1215 METRICS_AVERAGE_GFXCLK, 1216 (uint32_t *)data); 1217 *(uint32_t *)data *= 100; 1218 *size = 4; 1219 break; 1220 case AMDGPU_PP_SENSOR_VDDGFX: 1221 ret = renoir_get_smu_metrics_data(smu, 1222 METRICS_VOLTAGE_VDDGFX, 1223 (uint32_t *)data); 1224 *size = 4; 1225 break; 1226 case AMDGPU_PP_SENSOR_VDDNB: 1227 ret = renoir_get_smu_metrics_data(smu, 1228 METRICS_VOLTAGE_VDDSOC, 1229 (uint32_t *)data); 1230 *size = 4; 1231 break; 1232 case AMDGPU_PP_SENSOR_GPU_POWER: 1233 ret = renoir_get_smu_metrics_data(smu, 1234 METRICS_AVERAGE_SOCKETPOWER, 1235 (uint32_t *)data); 1236 *size = 4; 1237 break; 1238 default: 1239 ret = -EOPNOTSUPP; 1240 break; 1241 } 1242 mutex_unlock(&smu->sensor_lock); 1243 1244 return ret; 1245 } 1246 1247 static bool renoir_is_dpm_running(struct smu_context *smu) 1248 { 1249 struct amdgpu_device *adev = smu->adev; 1250 1251 /* 1252 * Until now, the pmfw hasn't exported the interface of SMU 1253 * feature mask to APU SKU so just force on all the feature 1254 * at early initial stage. 1255 */ 1256 if (adev->in_suspend) 1257 return false; 1258 else 1259 return true; 1260 1261 } 1262 1263 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, 1264 void **table) 1265 { 1266 struct smu_table_context *smu_table = &smu->smu_table; 1267 struct gpu_metrics_v2_1 *gpu_metrics = 1268 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; 1269 SmuMetrics_t metrics; 1270 int ret = 0; 1271 1272 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1273 if (ret) 1274 return ret; 1275 1276 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); 1277 1278 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1279 gpu_metrics->temperature_soc = metrics.SocTemperature; 1280 memcpy(&gpu_metrics->temperature_core[0], 1281 &metrics.CoreTemperature[0], 1282 sizeof(uint16_t) * 8); 1283 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1284 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1285 1286 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1287 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity; 1288 1289 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1290 gpu_metrics->average_cpu_power = metrics.Power[0]; 1291 gpu_metrics->average_soc_power = metrics.Power[1]; 1292 memcpy(&gpu_metrics->average_core_power[0], 1293 &metrics.CorePower[0], 1294 sizeof(uint16_t) * 8); 1295 1296 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1297 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1298 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency; 1299 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency; 1300 1301 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK]; 1302 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK]; 1303 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK]; 1304 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK]; 1305 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK]; 1306 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK]; 1307 memcpy(&gpu_metrics->current_coreclk[0], 1308 &metrics.CoreFrequency[0], 1309 sizeof(uint16_t) * 8); 1310 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1311 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1312 1313 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1314 1315 gpu_metrics->fan_pwm = metrics.FanPwm; 1316 1317 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1318 1319 *table = (void *)gpu_metrics; 1320 1321 return sizeof(struct gpu_metrics_v2_1); 1322 } 1323 1324 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) 1325 { 1326 1327 return 0; 1328 } 1329 1330 static const struct pptable_funcs renoir_ppt_funcs = { 1331 .set_power_state = NULL, 1332 .print_clk_levels = renoir_print_clk_levels, 1333 .get_current_power_state = renoir_get_current_power_state, 1334 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable, 1335 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable, 1336 .force_clk_levels = renoir_force_clk_levels, 1337 .set_power_profile_mode = renoir_set_power_profile_mode, 1338 .set_performance_level = renoir_set_performance_level, 1339 .get_dpm_clock_table = renoir_get_dpm_clock_table, 1340 .set_watermarks_table = renoir_set_watermarks_table, 1341 .get_power_profile_mode = renoir_get_power_profile_mode, 1342 .read_sensor = renoir_read_sensor, 1343 .check_fw_status = smu_v12_0_check_fw_status, 1344 .check_fw_version = smu_v12_0_check_fw_version, 1345 .powergate_sdma = smu_v12_0_powergate_sdma, 1346 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1347 .send_smc_msg = smu_cmn_send_smc_msg, 1348 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, 1349 .gfx_off_control = smu_v12_0_gfx_off_control, 1350 .get_gfx_off_status = smu_v12_0_get_gfxoff_status, 1351 .init_smc_tables = renoir_init_smc_tables, 1352 .fini_smc_tables = smu_v12_0_fini_smc_tables, 1353 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables, 1354 .get_enabled_mask = smu_cmn_get_enabled_mask, 1355 .feature_is_enabled = smu_cmn_feature_is_enabled, 1356 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1357 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq, 1358 .mode2_reset = smu_v12_0_mode2_reset, 1359 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, 1360 .set_driver_table_location = smu_v12_0_set_driver_table_location, 1361 .is_dpm_running = renoir_is_dpm_running, 1362 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1363 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1364 .get_gpu_metrics = renoir_get_gpu_metrics, 1365 .gfx_state_change_set = renoir_gfx_state_change_set, 1366 .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters, 1367 .od_edit_dpm_table = renoir_od_edit_dpm_table, 1368 .get_vbios_bootup_values = smu_v12_0_get_vbios_bootup_values, 1369 }; 1370 1371 void renoir_set_ppt_funcs(struct smu_context *smu) 1372 { 1373 smu->ppt_funcs = &renoir_ppt_funcs; 1374 smu->message_map = renoir_message_map; 1375 smu->clock_map = renoir_clk_map; 1376 smu->table_map = renoir_table_map; 1377 smu->workload_map = renoir_workload_map; 1378 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; 1379 smu->is_apu = true; 1380 } 1381