1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v12_0_ppsmc.h" 29 #include "smu12_driver_if.h" 30 #include "smu_v12_0.h" 31 #include "renoir_ppt.h" 32 #include "smu_cmn.h" 33 34 /* 35 * DO NOT use these for err/warn/info/debug messages. 36 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 37 * They are more MGPU friendly. 38 */ 39 #undef pr_err 40 #undef pr_warn 41 #undef pr_info 42 #undef pr_debug 43 44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { 45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1), 49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1), 50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1), 51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1), 56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1), 57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1), 58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 59 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1), 60 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1), 61 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1), 62 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1), 63 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1), 64 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1), 65 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1), 66 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 67 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 68 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 69 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 70 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 71 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1), 72 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1), 73 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 74 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1), 75 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1), 76 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1), 77 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1), 78 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1), 79 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1), 80 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 81 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1), 82 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 83 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 84 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1), 85 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1), 86 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1), 87 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1), 88 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 89 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 90 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 91 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 92 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 93 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1), 94 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1), 95 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1), 96 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 97 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1), 98 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1), 99 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 100 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 101 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1), 102 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1), 103 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 104 }; 105 106 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { 107 CLK_MAP(GFXCLK, CLOCK_GFXCLK), 108 CLK_MAP(SCLK, CLOCK_GFXCLK), 109 CLK_MAP(SOCCLK, CLOCK_SOCCLK), 110 CLK_MAP(UCLK, CLOCK_FCLK), 111 CLK_MAP(MCLK, CLOCK_FCLK), 112 }; 113 114 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { 115 TAB_MAP_VALID(WATERMARKS), 116 TAB_MAP_INVALID(CUSTOM_DPM), 117 TAB_MAP_VALID(DPMCLOCKS), 118 TAB_MAP_VALID(SMU_METRICS), 119 }; 120 121 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 122 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 123 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 127 }; 128 129 static int renoir_init_smc_tables(struct smu_context *smu) 130 { 131 struct smu_table_context *smu_table = &smu->smu_table; 132 struct smu_table *tables = smu_table->tables; 133 134 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 135 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 136 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 137 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 138 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 139 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 140 141 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 142 if (!smu_table->clocks_table) 143 goto err0_out; 144 145 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 146 if (!smu_table->metrics_table) 147 goto err1_out; 148 smu_table->metrics_time = 0; 149 150 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 151 if (!smu_table->watermarks_table) 152 goto err2_out; 153 154 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); 155 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 156 if (!smu_table->gpu_metrics_table) 157 goto err3_out; 158 159 return 0; 160 161 err3_out: 162 kfree(smu_table->watermarks_table); 163 err2_out: 164 kfree(smu_table->metrics_table); 165 err1_out: 166 kfree(smu_table->clocks_table); 167 err0_out: 168 return -ENOMEM; 169 } 170 171 /* 172 * This interface just for getting uclk ultimate freq and should't introduce 173 * other likewise function result in overmuch callback. 174 */ 175 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 176 uint32_t dpm_level, uint32_t *freq) 177 { 178 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 179 180 if (!clk_table || clk_type >= SMU_CLK_COUNT) 181 return -EINVAL; 182 183 switch (clk_type) { 184 case SMU_SOCCLK: 185 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) 186 return -EINVAL; 187 *freq = clk_table->SocClocks[dpm_level].Freq; 188 break; 189 case SMU_UCLK: 190 case SMU_MCLK: 191 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 192 return -EINVAL; 193 *freq = clk_table->FClocks[dpm_level].Freq; 194 break; 195 case SMU_DCEFCLK: 196 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) 197 return -EINVAL; 198 *freq = clk_table->DcfClocks[dpm_level].Freq; 199 break; 200 case SMU_FCLK: 201 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 202 return -EINVAL; 203 *freq = clk_table->FClocks[dpm_level].Freq; 204 break; 205 default: 206 return -EINVAL; 207 } 208 209 return 0; 210 } 211 212 static int renoir_get_profiling_clk_mask(struct smu_context *smu, 213 enum amd_dpm_forced_level level, 214 uint32_t *sclk_mask, 215 uint32_t *mclk_mask, 216 uint32_t *soc_mask) 217 { 218 219 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 220 if (sclk_mask) 221 *sclk_mask = 0; 222 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 223 if (mclk_mask) 224 /* mclk levels are in reverse order */ 225 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; 226 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 227 if(sclk_mask) 228 /* The sclk as gfxclk and has three level about max/min/current */ 229 *sclk_mask = 3 - 1; 230 231 if(mclk_mask) 232 /* mclk levels are in reverse order */ 233 *mclk_mask = 0; 234 235 if(soc_mask) 236 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; 237 } 238 239 return 0; 240 } 241 242 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu, 243 enum smu_clk_type clk_type, 244 uint32_t *min, 245 uint32_t *max) 246 { 247 int ret = 0; 248 uint32_t mclk_mask, soc_mask; 249 uint32_t clock_limit; 250 251 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 252 switch (clk_type) { 253 case SMU_MCLK: 254 case SMU_UCLK: 255 clock_limit = smu->smu_table.boot_values.uclk; 256 break; 257 case SMU_GFXCLK: 258 case SMU_SCLK: 259 clock_limit = smu->smu_table.boot_values.gfxclk; 260 break; 261 case SMU_SOCCLK: 262 clock_limit = smu->smu_table.boot_values.socclk; 263 break; 264 default: 265 clock_limit = 0; 266 break; 267 } 268 269 /* clock in Mhz unit */ 270 if (min) 271 *min = clock_limit / 100; 272 if (max) 273 *max = clock_limit / 100; 274 275 return 0; 276 } 277 278 if (max) { 279 ret = renoir_get_profiling_clk_mask(smu, 280 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 281 NULL, 282 &mclk_mask, 283 &soc_mask); 284 if (ret) 285 goto failed; 286 287 switch (clk_type) { 288 case SMU_GFXCLK: 289 case SMU_SCLK: 290 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max); 291 if (ret) { 292 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n"); 293 goto failed; 294 } 295 break; 296 case SMU_UCLK: 297 case SMU_FCLK: 298 case SMU_MCLK: 299 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 300 if (ret) 301 goto failed; 302 break; 303 case SMU_SOCCLK: 304 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 305 if (ret) 306 goto failed; 307 break; 308 default: 309 ret = -EINVAL; 310 goto failed; 311 } 312 } 313 314 if (min) { 315 switch (clk_type) { 316 case SMU_GFXCLK: 317 case SMU_SCLK: 318 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min); 319 if (ret) { 320 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n"); 321 goto failed; 322 } 323 break; 324 case SMU_UCLK: 325 case SMU_FCLK: 326 case SMU_MCLK: 327 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min); 328 if (ret) 329 goto failed; 330 break; 331 case SMU_SOCCLK: 332 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min); 333 if (ret) 334 goto failed; 335 break; 336 default: 337 ret = -EINVAL; 338 goto failed; 339 } 340 } 341 failed: 342 return ret; 343 } 344 345 static int renoir_od_edit_dpm_table(struct smu_context *smu, 346 enum PP_OD_DPM_TABLE_COMMAND type, 347 long input[], uint32_t size) 348 { 349 int ret = 0; 350 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 351 352 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 353 dev_warn(smu->adev->dev, 354 "pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); 355 return -EINVAL; 356 } 357 358 switch (type) { 359 case PP_OD_EDIT_SCLK_VDDC_TABLE: 360 if (size != 2) { 361 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 362 return -EINVAL; 363 } 364 365 if (input[0] == 0) { 366 if (input[1] < smu->gfx_default_hard_min_freq) { 367 dev_warn(smu->adev->dev, 368 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 369 input[1], smu->gfx_default_hard_min_freq); 370 return -EINVAL; 371 } 372 smu->gfx_actual_hard_min_freq = input[1]; 373 } else if (input[0] == 1) { 374 if (input[1] > smu->gfx_default_soft_max_freq) { 375 dev_warn(smu->adev->dev, 376 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 377 input[1], smu->gfx_default_soft_max_freq); 378 return -EINVAL; 379 } 380 smu->gfx_actual_soft_max_freq = input[1]; 381 } else { 382 return -EINVAL; 383 } 384 break; 385 case PP_OD_RESTORE_DEFAULT_TABLE: 386 if (size != 0) { 387 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 388 return -EINVAL; 389 } 390 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 391 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 392 393 ret = smu_cmn_send_smc_msg_with_param(smu, 394 SMU_MSG_SetHardMinGfxClk, 395 smu->gfx_actual_hard_min_freq, 396 NULL); 397 if (ret) { 398 dev_err(smu->adev->dev, "Restore the default hard min sclk failed!"); 399 return ret; 400 } 401 402 ret = smu_cmn_send_smc_msg_with_param(smu, 403 SMU_MSG_SetSoftMaxGfxClk, 404 smu->gfx_actual_soft_max_freq, 405 NULL); 406 if (ret) { 407 dev_err(smu->adev->dev, "Restore the default soft max sclk failed!"); 408 return ret; 409 } 410 break; 411 case PP_OD_COMMIT_DPM_TABLE: 412 if (size != 0) { 413 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 414 return -EINVAL; 415 } else { 416 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 417 dev_err(smu->adev->dev, 418 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 419 smu->gfx_actual_hard_min_freq, 420 smu->gfx_actual_soft_max_freq); 421 return -EINVAL; 422 } 423 424 ret = smu_cmn_send_smc_msg_with_param(smu, 425 SMU_MSG_SetHardMinGfxClk, 426 smu->gfx_actual_hard_min_freq, 427 NULL); 428 if (ret) { 429 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 430 return ret; 431 } 432 433 ret = smu_cmn_send_smc_msg_with_param(smu, 434 SMU_MSG_SetSoftMaxGfxClk, 435 smu->gfx_actual_soft_max_freq, 436 NULL); 437 if (ret) { 438 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 439 return ret; 440 } 441 } 442 break; 443 default: 444 return -ENOSYS; 445 } 446 447 return ret; 448 } 449 450 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 451 { 452 uint32_t min = 0, max = 0; 453 uint32_t ret = 0; 454 455 ret = smu_cmn_send_smc_msg_with_param(smu, 456 SMU_MSG_GetMinGfxclkFrequency, 457 0, &min); 458 if (ret) 459 return ret; 460 ret = smu_cmn_send_smc_msg_with_param(smu, 461 SMU_MSG_GetMaxGfxclkFrequency, 462 0, &max); 463 if (ret) 464 return ret; 465 466 smu->gfx_default_hard_min_freq = min; 467 smu->gfx_default_soft_max_freq = max; 468 smu->gfx_actual_hard_min_freq = 0; 469 smu->gfx_actual_soft_max_freq = 0; 470 471 return 0; 472 } 473 474 static int renoir_print_clk_levels(struct smu_context *smu, 475 enum smu_clk_type clk_type, char *buf) 476 { 477 int i, size = 0, ret = 0; 478 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; 479 SmuMetrics_t metrics; 480 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 481 bool cur_value_match_level = false; 482 483 memset(&metrics, 0, sizeof(metrics)); 484 485 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 486 if (ret) 487 return ret; 488 489 switch (clk_type) { 490 case SMU_OD_RANGE: 491 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 492 ret = smu_cmn_send_smc_msg_with_param(smu, 493 SMU_MSG_GetMinGfxclkFrequency, 494 0, &min); 495 if (ret) 496 return ret; 497 ret = smu_cmn_send_smc_msg_with_param(smu, 498 SMU_MSG_GetMaxGfxclkFrequency, 499 0, &max); 500 if (ret) 501 return ret; 502 size += sprintf(buf + size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max); 503 } 504 break; 505 case SMU_OD_SCLK: 506 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 507 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 508 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 509 size += sprintf(buf + size, "OD_SCLK\n"); 510 size += sprintf(buf + size, "0:%10uMhz\n", min); 511 size += sprintf(buf + size, "1:%10uMhz\n", max); 512 } 513 break; 514 case SMU_GFXCLK: 515 case SMU_SCLK: 516 /* retirve table returned paramters unit is MHz */ 517 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; 518 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max); 519 if (!ret) { 520 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 521 if (cur_value == max) 522 i = 2; 523 else if (cur_value == min) 524 i = 0; 525 else 526 i = 1; 527 528 size += sprintf(buf + size, "0: %uMhz %s\n", min, 529 i == 0 ? "*" : ""); 530 size += sprintf(buf + size, "1: %uMhz %s\n", 531 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, 532 i == 1 ? "*" : ""); 533 size += sprintf(buf + size, "2: %uMhz %s\n", max, 534 i == 2 ? "*" : ""); 535 } 536 return size; 537 case SMU_SOCCLK: 538 count = NUM_SOCCLK_DPM_LEVELS; 539 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; 540 break; 541 case SMU_MCLK: 542 count = NUM_MEMCLK_DPM_LEVELS; 543 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 544 break; 545 case SMU_DCEFCLK: 546 count = NUM_DCFCLK_DPM_LEVELS; 547 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK]; 548 break; 549 case SMU_FCLK: 550 count = NUM_FCLK_DPM_LEVELS; 551 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 552 break; 553 default: 554 break; 555 } 556 557 switch (clk_type) { 558 case SMU_GFXCLK: 559 case SMU_SCLK: 560 case SMU_SOCCLK: 561 case SMU_MCLK: 562 case SMU_DCEFCLK: 563 case SMU_FCLK: 564 for (i = 0; i < count; i++) { 565 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); 566 if (ret) 567 return ret; 568 if (!value) 569 continue; 570 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 571 cur_value == value ? "*" : ""); 572 if (cur_value == value) 573 cur_value_match_level = true; 574 } 575 576 if (!cur_value_match_level) 577 size += sprintf(buf + size, " %uMhz *\n", cur_value); 578 579 break; 580 default: 581 break; 582 } 583 584 return size; 585 } 586 587 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) 588 { 589 enum amd_pm_state_type pm_type; 590 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 591 592 if (!smu_dpm_ctx->dpm_context || 593 !smu_dpm_ctx->dpm_current_power_state) 594 return -EINVAL; 595 596 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) { 597 case SMU_STATE_UI_LABEL_BATTERY: 598 pm_type = POWER_STATE_TYPE_BATTERY; 599 break; 600 case SMU_STATE_UI_LABEL_BALLANCED: 601 pm_type = POWER_STATE_TYPE_BALANCED; 602 break; 603 case SMU_STATE_UI_LABEL_PERFORMANCE: 604 pm_type = POWER_STATE_TYPE_PERFORMANCE; 605 break; 606 default: 607 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT) 608 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 609 else 610 pm_type = POWER_STATE_TYPE_DEFAULT; 611 break; 612 } 613 614 return pm_type; 615 } 616 617 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 618 { 619 int ret = 0; 620 621 if (enable) { 622 /* vcn dpm on is a prerequisite for vcn power gate messages */ 623 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 624 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 625 if (ret) 626 return ret; 627 } 628 } else { 629 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 630 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 631 if (ret) 632 return ret; 633 } 634 } 635 636 return ret; 637 } 638 639 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 640 { 641 int ret = 0; 642 643 if (enable) { 644 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 645 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 646 if (ret) 647 return ret; 648 } 649 } else { 650 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 651 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 652 if (ret) 653 return ret; 654 } 655 } 656 657 return ret; 658 } 659 660 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest) 661 { 662 int ret = 0, i = 0; 663 uint32_t min_freq, max_freq, force_freq; 664 enum smu_clk_type clk_type; 665 666 enum smu_clk_type clks[] = { 667 SMU_GFXCLK, 668 SMU_MCLK, 669 SMU_SOCCLK, 670 }; 671 672 for (i = 0; i < ARRAY_SIZE(clks); i++) { 673 clk_type = clks[i]; 674 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 675 if (ret) 676 return ret; 677 678 force_freq = highest ? max_freq : min_freq; 679 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 680 if (ret) 681 return ret; 682 } 683 684 return ret; 685 } 686 687 static int renoir_unforce_dpm_levels(struct smu_context *smu) { 688 689 int ret = 0, i = 0; 690 uint32_t min_freq, max_freq; 691 enum smu_clk_type clk_type; 692 693 struct clk_feature_map { 694 enum smu_clk_type clk_type; 695 uint32_t feature; 696 } clk_feature_map[] = { 697 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, 698 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, 699 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 700 }; 701 702 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 703 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 704 continue; 705 706 clk_type = clk_feature_map[i].clk_type; 707 708 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 709 if (ret) 710 return ret; 711 712 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 713 if (ret) 714 return ret; 715 } 716 717 return ret; 718 } 719 720 /* 721 * This interface get dpm clock table for dc 722 */ 723 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 724 { 725 DpmClocks_t *table = smu->smu_table.clocks_table; 726 int i; 727 728 if (!clock_table || !table) 729 return -EINVAL; 730 731 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { 732 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; 733 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; 734 } 735 736 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 737 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq; 738 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; 739 } 740 741 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 742 clock_table->FClocks[i].Freq = table->FClocks[i].Freq; 743 clock_table->FClocks[i].Vol = table->FClocks[i].Vol; 744 } 745 746 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) { 747 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq; 748 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; 749 } 750 751 return 0; 752 } 753 754 static int renoir_force_clk_levels(struct smu_context *smu, 755 enum smu_clk_type clk_type, uint32_t mask) 756 { 757 758 int ret = 0 ; 759 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 760 761 soft_min_level = mask ? (ffs(mask) - 1) : 0; 762 soft_max_level = mask ? (fls(mask) - 1) : 0; 763 764 switch (clk_type) { 765 case SMU_GFXCLK: 766 case SMU_SCLK: 767 if (soft_min_level > 2 || soft_max_level > 2) { 768 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n"); 769 return -EINVAL; 770 } 771 772 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq); 773 if (ret) 774 return ret; 775 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 776 soft_max_level == 0 ? min_freq : 777 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq, 778 NULL); 779 if (ret) 780 return ret; 781 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 782 soft_min_level == 2 ? max_freq : 783 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq, 784 NULL); 785 if (ret) 786 return ret; 787 break; 788 case SMU_SOCCLK: 789 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 790 if (ret) 791 return ret; 792 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 793 if (ret) 794 return ret; 795 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); 796 if (ret) 797 return ret; 798 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); 799 if (ret) 800 return ret; 801 break; 802 case SMU_MCLK: 803 case SMU_FCLK: 804 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 805 if (ret) 806 return ret; 807 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 808 if (ret) 809 return ret; 810 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); 811 if (ret) 812 return ret; 813 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); 814 if (ret) 815 return ret; 816 break; 817 default: 818 break; 819 } 820 821 return ret; 822 } 823 824 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 825 { 826 int workload_type, ret; 827 uint32_t profile_mode = input[size]; 828 829 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 830 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 831 return -EINVAL; 832 } 833 834 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 835 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 836 return 0; 837 838 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 839 workload_type = smu_cmn_to_asic_specific_index(smu, 840 CMN2ASIC_MAPPING_WORKLOAD, 841 profile_mode); 842 if (workload_type < 0) { 843 /* 844 * TODO: If some case need switch to powersave/default power mode 845 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving. 846 */ 847 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode); 848 return -EINVAL; 849 } 850 851 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 852 1 << workload_type, 853 NULL); 854 if (ret) { 855 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 856 return ret; 857 } 858 859 smu->power_profile_mode = profile_mode; 860 861 return 0; 862 } 863 864 static int renoir_set_peak_clock_by_device(struct smu_context *smu) 865 { 866 int ret = 0; 867 uint32_t sclk_freq = 0, uclk_freq = 0; 868 869 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq); 870 if (ret) 871 return ret; 872 873 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq); 874 if (ret) 875 return ret; 876 877 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq); 878 if (ret) 879 return ret; 880 881 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq); 882 if (ret) 883 return ret; 884 885 return ret; 886 } 887 888 static int renoir_set_performance_level(struct smu_context *smu, 889 enum amd_dpm_forced_level level) 890 { 891 int ret = 0; 892 uint32_t sclk_mask, mclk_mask, soc_mask; 893 894 switch (level) { 895 case AMD_DPM_FORCED_LEVEL_HIGH: 896 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 897 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 898 899 ret = renoir_force_dpm_limit_value(smu, true); 900 break; 901 case AMD_DPM_FORCED_LEVEL_LOW: 902 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 903 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 904 905 ret = renoir_force_dpm_limit_value(smu, false); 906 break; 907 case AMD_DPM_FORCED_LEVEL_AUTO: 908 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 909 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 910 911 ret = renoir_unforce_dpm_levels(smu); 912 break; 913 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 914 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 915 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 916 917 ret = smu_cmn_send_smc_msg_with_param(smu, 918 SMU_MSG_SetHardMinGfxClk, 919 RENOIR_UMD_PSTATE_GFXCLK, 920 NULL); 921 if (ret) 922 return ret; 923 ret = smu_cmn_send_smc_msg_with_param(smu, 924 SMU_MSG_SetHardMinFclkByFreq, 925 RENOIR_UMD_PSTATE_FCLK, 926 NULL); 927 if (ret) 928 return ret; 929 ret = smu_cmn_send_smc_msg_with_param(smu, 930 SMU_MSG_SetHardMinSocclkByFreq, 931 RENOIR_UMD_PSTATE_SOCCLK, 932 NULL); 933 if (ret) 934 return ret; 935 ret = smu_cmn_send_smc_msg_with_param(smu, 936 SMU_MSG_SetHardMinVcn, 937 RENOIR_UMD_PSTATE_VCNCLK, 938 NULL); 939 if (ret) 940 return ret; 941 942 ret = smu_cmn_send_smc_msg_with_param(smu, 943 SMU_MSG_SetSoftMaxGfxClk, 944 RENOIR_UMD_PSTATE_GFXCLK, 945 NULL); 946 if (ret) 947 return ret; 948 ret = smu_cmn_send_smc_msg_with_param(smu, 949 SMU_MSG_SetSoftMaxFclkByFreq, 950 RENOIR_UMD_PSTATE_FCLK, 951 NULL); 952 if (ret) 953 return ret; 954 ret = smu_cmn_send_smc_msg_with_param(smu, 955 SMU_MSG_SetSoftMaxSocclkByFreq, 956 RENOIR_UMD_PSTATE_SOCCLK, 957 NULL); 958 if (ret) 959 return ret; 960 ret = smu_cmn_send_smc_msg_with_param(smu, 961 SMU_MSG_SetSoftMaxVcn, 962 RENOIR_UMD_PSTATE_VCNCLK, 963 NULL); 964 if (ret) 965 return ret; 966 break; 967 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 968 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 969 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 970 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 971 972 ret = renoir_get_profiling_clk_mask(smu, level, 973 &sclk_mask, 974 &mclk_mask, 975 &soc_mask); 976 if (ret) 977 return ret; 978 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); 979 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 980 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 981 break; 982 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 983 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 984 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 985 986 ret = renoir_set_peak_clock_by_device(smu); 987 break; 988 case AMD_DPM_FORCED_LEVEL_MANUAL: 989 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 990 default: 991 break; 992 } 993 return ret; 994 } 995 996 /* save watermark settings into pplib smu structure, 997 * also pass data to smu controller 998 */ 999 static int renoir_set_watermarks_table( 1000 struct smu_context *smu, 1001 struct pp_smu_wm_range_sets *clock_ranges) 1002 { 1003 Watermarks_t *table = smu->smu_table.watermarks_table; 1004 int ret = 0; 1005 int i; 1006 1007 if (clock_ranges) { 1008 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1009 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1010 return -EINVAL; 1011 1012 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/ 1013 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1014 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1015 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1016 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1017 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1018 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1019 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1020 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1021 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1022 1023 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1024 clock_ranges->reader_wm_sets[i].wm_inst; 1025 table->WatermarkRow[WM_DCFCLK][i].WmType = 1026 clock_ranges->reader_wm_sets[i].wm_type; 1027 } 1028 1029 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1030 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1031 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1032 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1033 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1034 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1035 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1036 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1037 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1038 1039 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1040 clock_ranges->writer_wm_sets[i].wm_inst; 1041 table->WatermarkRow[WM_SOCCLK][i].WmType = 1042 clock_ranges->writer_wm_sets[i].wm_type; 1043 } 1044 1045 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1046 } 1047 1048 /* pass data to smu controller */ 1049 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1050 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1051 ret = smu_cmn_write_watermarks_table(smu); 1052 if (ret) { 1053 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1054 return ret; 1055 } 1056 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1057 } 1058 1059 return 0; 1060 } 1061 1062 static int renoir_get_power_profile_mode(struct smu_context *smu, 1063 char *buf) 1064 { 1065 static const char *profile_name[] = { 1066 "BOOTUP_DEFAULT", 1067 "3D_FULL_SCREEN", 1068 "POWER_SAVING", 1069 "VIDEO", 1070 "VR", 1071 "COMPUTE", 1072 "CUSTOM"}; 1073 uint32_t i, size = 0; 1074 int16_t workload_type = 0; 1075 1076 if (!buf) 1077 return -EINVAL; 1078 1079 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1080 /* 1081 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1082 * Not all profile modes are supported on arcturus. 1083 */ 1084 workload_type = smu_cmn_to_asic_specific_index(smu, 1085 CMN2ASIC_MAPPING_WORKLOAD, 1086 i); 1087 if (workload_type < 0) 1088 continue; 1089 1090 size += sprintf(buf + size, "%2d %14s%s\n", 1091 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1092 } 1093 1094 return size; 1095 } 1096 1097 static int renoir_get_smu_metrics_data(struct smu_context *smu, 1098 MetricsMember_t member, 1099 uint32_t *value) 1100 { 1101 struct smu_table_context *smu_table = &smu->smu_table; 1102 1103 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 1104 int ret = 0; 1105 1106 mutex_lock(&smu->metrics_lock); 1107 1108 ret = smu_cmn_get_metrics_table_locked(smu, 1109 NULL, 1110 false); 1111 if (ret) { 1112 mutex_unlock(&smu->metrics_lock); 1113 return ret; 1114 } 1115 1116 switch (member) { 1117 case METRICS_AVERAGE_GFXCLK: 1118 *value = metrics->ClockFrequency[CLOCK_GFXCLK]; 1119 break; 1120 case METRICS_AVERAGE_SOCCLK: 1121 *value = metrics->ClockFrequency[CLOCK_SOCCLK]; 1122 break; 1123 case METRICS_AVERAGE_UCLK: 1124 *value = metrics->ClockFrequency[CLOCK_FCLK]; 1125 break; 1126 case METRICS_AVERAGE_GFXACTIVITY: 1127 *value = metrics->AverageGfxActivity / 100; 1128 break; 1129 case METRICS_AVERAGE_VCNACTIVITY: 1130 *value = metrics->AverageUvdActivity / 100; 1131 break; 1132 case METRICS_AVERAGE_SOCKETPOWER: 1133 *value = (metrics->CurrentSocketPower << 8) / 1000; 1134 break; 1135 case METRICS_TEMPERATURE_EDGE: 1136 *value = (metrics->GfxTemperature / 100) * 1137 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1138 break; 1139 case METRICS_TEMPERATURE_HOTSPOT: 1140 *value = (metrics->SocTemperature / 100) * 1141 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1142 break; 1143 case METRICS_THROTTLER_STATUS: 1144 *value = metrics->ThrottlerStatus; 1145 break; 1146 case METRICS_VOLTAGE_VDDGFX: 1147 *value = metrics->Voltage[0]; 1148 break; 1149 case METRICS_VOLTAGE_VDDSOC: 1150 *value = metrics->Voltage[1]; 1151 break; 1152 default: 1153 *value = UINT_MAX; 1154 break; 1155 } 1156 1157 mutex_unlock(&smu->metrics_lock); 1158 1159 return ret; 1160 } 1161 1162 static int renoir_read_sensor(struct smu_context *smu, 1163 enum amd_pp_sensors sensor, 1164 void *data, uint32_t *size) 1165 { 1166 int ret = 0; 1167 1168 if (!data || !size) 1169 return -EINVAL; 1170 1171 mutex_lock(&smu->sensor_lock); 1172 switch (sensor) { 1173 case AMDGPU_PP_SENSOR_GPU_LOAD: 1174 ret = renoir_get_smu_metrics_data(smu, 1175 METRICS_AVERAGE_GFXACTIVITY, 1176 (uint32_t *)data); 1177 *size = 4; 1178 break; 1179 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1180 ret = renoir_get_smu_metrics_data(smu, 1181 METRICS_TEMPERATURE_EDGE, 1182 (uint32_t *)data); 1183 *size = 4; 1184 break; 1185 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1186 ret = renoir_get_smu_metrics_data(smu, 1187 METRICS_TEMPERATURE_HOTSPOT, 1188 (uint32_t *)data); 1189 *size = 4; 1190 break; 1191 case AMDGPU_PP_SENSOR_GFX_MCLK: 1192 ret = renoir_get_smu_metrics_data(smu, 1193 METRICS_AVERAGE_UCLK, 1194 (uint32_t *)data); 1195 *(uint32_t *)data *= 100; 1196 *size = 4; 1197 break; 1198 case AMDGPU_PP_SENSOR_GFX_SCLK: 1199 ret = renoir_get_smu_metrics_data(smu, 1200 METRICS_AVERAGE_GFXCLK, 1201 (uint32_t *)data); 1202 *(uint32_t *)data *= 100; 1203 *size = 4; 1204 break; 1205 case AMDGPU_PP_SENSOR_VDDGFX: 1206 ret = renoir_get_smu_metrics_data(smu, 1207 METRICS_VOLTAGE_VDDGFX, 1208 (uint32_t *)data); 1209 *size = 4; 1210 break; 1211 case AMDGPU_PP_SENSOR_VDDNB: 1212 ret = renoir_get_smu_metrics_data(smu, 1213 METRICS_VOLTAGE_VDDSOC, 1214 (uint32_t *)data); 1215 *size = 4; 1216 break; 1217 case AMDGPU_PP_SENSOR_GPU_POWER: 1218 ret = renoir_get_smu_metrics_data(smu, 1219 METRICS_AVERAGE_SOCKETPOWER, 1220 (uint32_t *)data); 1221 *size = 4; 1222 break; 1223 default: 1224 ret = -EOPNOTSUPP; 1225 break; 1226 } 1227 mutex_unlock(&smu->sensor_lock); 1228 1229 return ret; 1230 } 1231 1232 static bool renoir_is_dpm_running(struct smu_context *smu) 1233 { 1234 struct amdgpu_device *adev = smu->adev; 1235 1236 /* 1237 * Until now, the pmfw hasn't exported the interface of SMU 1238 * feature mask to APU SKU so just force on all the feature 1239 * at early initial stage. 1240 */ 1241 if (adev->in_suspend) 1242 return false; 1243 else 1244 return true; 1245 1246 } 1247 1248 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, 1249 void **table) 1250 { 1251 struct smu_table_context *smu_table = &smu->smu_table; 1252 struct gpu_metrics_v2_0 *gpu_metrics = 1253 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; 1254 SmuMetrics_t metrics; 1255 int ret = 0; 1256 1257 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1258 if (ret) 1259 return ret; 1260 1261 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 0); 1262 1263 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1264 gpu_metrics->temperature_soc = metrics.SocTemperature; 1265 memcpy(&gpu_metrics->temperature_core[0], 1266 &metrics.CoreTemperature[0], 1267 sizeof(uint16_t) * 8); 1268 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1269 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1270 1271 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1272 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity; 1273 1274 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1275 gpu_metrics->average_cpu_power = metrics.Power[0]; 1276 gpu_metrics->average_soc_power = metrics.Power[1]; 1277 memcpy(&gpu_metrics->average_core_power[0], 1278 &metrics.CorePower[0], 1279 sizeof(uint16_t) * 8); 1280 1281 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1282 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1283 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency; 1284 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency; 1285 1286 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK]; 1287 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK]; 1288 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK]; 1289 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK]; 1290 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK]; 1291 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK]; 1292 memcpy(&gpu_metrics->current_coreclk[0], 1293 &metrics.CoreFrequency[0], 1294 sizeof(uint16_t) * 8); 1295 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1296 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1297 1298 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1299 1300 gpu_metrics->fan_pwm = metrics.FanPwm; 1301 1302 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1303 1304 *table = (void *)gpu_metrics; 1305 1306 return sizeof(struct gpu_metrics_v2_0); 1307 } 1308 1309 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) 1310 { 1311 1312 return 0; 1313 } 1314 1315 static const struct pptable_funcs renoir_ppt_funcs = { 1316 .set_power_state = NULL, 1317 .print_clk_levels = renoir_print_clk_levels, 1318 .get_current_power_state = renoir_get_current_power_state, 1319 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable, 1320 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable, 1321 .force_clk_levels = renoir_force_clk_levels, 1322 .set_power_profile_mode = renoir_set_power_profile_mode, 1323 .set_performance_level = renoir_set_performance_level, 1324 .get_dpm_clock_table = renoir_get_dpm_clock_table, 1325 .set_watermarks_table = renoir_set_watermarks_table, 1326 .get_power_profile_mode = renoir_get_power_profile_mode, 1327 .read_sensor = renoir_read_sensor, 1328 .check_fw_status = smu_v12_0_check_fw_status, 1329 .check_fw_version = smu_v12_0_check_fw_version, 1330 .powergate_sdma = smu_v12_0_powergate_sdma, 1331 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1332 .send_smc_msg = smu_cmn_send_smc_msg, 1333 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, 1334 .gfx_off_control = smu_v12_0_gfx_off_control, 1335 .get_gfx_off_status = smu_v12_0_get_gfxoff_status, 1336 .init_smc_tables = renoir_init_smc_tables, 1337 .fini_smc_tables = smu_v12_0_fini_smc_tables, 1338 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables, 1339 .get_enabled_mask = smu_cmn_get_enabled_mask, 1340 .feature_is_enabled = smu_cmn_feature_is_enabled, 1341 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1342 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq, 1343 .mode2_reset = smu_v12_0_mode2_reset, 1344 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, 1345 .set_driver_table_location = smu_v12_0_set_driver_table_location, 1346 .is_dpm_running = renoir_is_dpm_running, 1347 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1348 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1349 .get_gpu_metrics = renoir_get_gpu_metrics, 1350 .gfx_state_change_set = renoir_gfx_state_change_set, 1351 .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters, 1352 .od_edit_dpm_table = renoir_od_edit_dpm_table, 1353 }; 1354 1355 void renoir_set_ppt_funcs(struct smu_context *smu) 1356 { 1357 smu->ppt_funcs = &renoir_ppt_funcs; 1358 smu->message_map = renoir_message_map; 1359 smu->clock_map = renoir_clk_map; 1360 smu->table_map = renoir_table_map; 1361 smu->workload_map = renoir_workload_map; 1362 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; 1363 smu->is_apu = true; 1364 } 1365