1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #define SWSMU_CODE_LAYER_L2
25 
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v12_0_ppsmc.h"
29 #include "smu12_driver_if.h"
30 #include "smu_v12_0.h"
31 #include "renoir_ppt.h"
32 #include "smu_cmn.h"
33 
34 /*
35  * DO NOT use these for err/warn/info/debug messages.
36  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
37  * They are more MGPU friendly.
38  */
39 #undef pr_err
40 #undef pr_warn
41 #undef pr_info
42 #undef pr_debug
43 
44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
45 	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
46 	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
47 	MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
48 	MSG_MAP(PowerUpGfx,                     PPSMC_MSG_PowerUpGfx,                   1),
49 	MSG_MAP(AllowGfxOff,                    PPSMC_MSG_EnableGfxOff,                 1),
50 	MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisableGfxOff,                1),
51 	MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,           1),
52 	MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile,             1),
53 	MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 1),
54 	MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   1),
55 	MSG_MAP(PowerDownSdma,                  PPSMC_MSG_PowerDownSdma,                1),
56 	MSG_MAP(PowerUpSdma,                    PPSMC_MSG_PowerUpSdma,                  1),
57 	MSG_MAP(SetHardMinIspclkByFreq,         PPSMC_MSG_SetHardMinIspclkByFreq,       1),
58 	MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,                1),
59 	MSG_MAP(Spare1,                         PPSMC_MSG_spare1,                       1),
60 	MSG_MAP(Spare2,                         PPSMC_MSG_spare2,                       1),
61 	MSG_MAP(SetAllowFclkSwitch,             PPSMC_MSG_SetAllowFclkSwitch,           1),
62 	MSG_MAP(SetMinVideoGfxclkFreq,          PPSMC_MSG_SetMinVideoGfxclkFreq,        1),
63 	MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,          1),
64 	MSG_MAP(SetCustomPolicy,                PPSMC_MSG_SetCustomPolicy,              1),
65 	MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                  1),
66 	MSG_MAP(NumOfDisplays,                  PPSMC_MSG_SetDisplayCount,              1),
67 	MSG_MAP(QueryPowerLimit,                PPSMC_MSG_QueryPowerLimit,              1),
68 	MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        1),
69 	MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         1),
70 	MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        1),
71 	MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        1),
72 	MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,         1),
73 	MSG_MAP(SetGfxclkOverdriveByFreqVid,    PPSMC_MSG_SetGfxclkOverdriveByFreqVid,  1),
74 	MSG_MAP(SetHardMinDcfclkByFreq,         PPSMC_MSG_SetHardMinDcfclkByFreq,       1),
75 	MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,       1),
76 	MSG_MAP(ControlIgpuATS,                 PPSMC_MSG_ControlIgpuATS,               1),
77 	MSG_MAP(SetMinVideoFclkFreq,            PPSMC_MSG_SetMinVideoFclkFreq,          1),
78 	MSG_MAP(SetMinDeepSleepDcfclk,          PPSMC_MSG_SetMinDeepSleepDcfclk,        1),
79 	MSG_MAP(ForcePowerDownGfx,              PPSMC_MSG_ForcePowerDownGfx,            1),
80 	MSG_MAP(SetPhyclkVoltageByFreq,         PPSMC_MSG_SetPhyclkVoltageByFreq,       1),
81 	MSG_MAP(SetDppclkVoltageByFreq,         PPSMC_MSG_SetDppclkVoltageByFreq,       1),
82 	MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,                1),
83 	MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode,               1),
84 	MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,           1),
85 	MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,             1),
86 	MSG_MAP(GetMinGfxclkFrequency,          PPSMC_MSG_GetMinGfxclkFrequency,        1),
87 	MSG_MAP(GetMaxGfxclkFrequency,          PPSMC_MSG_GetMaxGfxclkFrequency,        1),
88 	MSG_MAP(SoftReset,                      PPSMC_MSG_SoftReset,                    1),
89 	MSG_MAP(SetGfxCGPG,                     PPSMC_MSG_SetGfxCGPG,                   1),
90 	MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,             1),
91 	MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,             1),
92 	MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,       1),
93 	MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,         1),
94 	MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,                1),
95 	MSG_MAP(PowerGateMmHub,                 PPSMC_MSG_PowerGateMmHub,               1),
96 	MSG_MAP(UpdatePmeRestore,               PPSMC_MSG_UpdatePmeRestore,             1),
97 	MSG_MAP(GpuChangeState,                 PPSMC_MSG_GpuChangeState,               1),
98 	MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,      1),
99 	MSG_MAP(ForceGfxContentSave,            PPSMC_MSG_ForceGfxContentSave,          1),
100 	MSG_MAP(EnableTmdp48MHzRefclkPwrDown,   PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
101 	MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                1),
102 	MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  1),
103 	MSG_MAP(PowerGateAtHub,                 PPSMC_MSG_PowerGateAtHub,               1),
104 	MSG_MAP(SetSoftMinJpeg,                 PPSMC_MSG_SetSoftMinJpeg,               1),
105 	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,         1),
106 };
107 
108 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
109 	CLK_MAP(GFXCLK, CLOCK_GFXCLK),
110 	CLK_MAP(SCLK,	CLOCK_GFXCLK),
111 	CLK_MAP(SOCCLK, CLOCK_SOCCLK),
112 	CLK_MAP(UCLK, CLOCK_FCLK),
113 	CLK_MAP(MCLK, CLOCK_FCLK),
114 };
115 
116 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
117 	TAB_MAP_VALID(WATERMARKS),
118 	TAB_MAP_INVALID(CUSTOM_DPM),
119 	TAB_MAP_VALID(DPMCLOCKS),
120 	TAB_MAP_VALID(SMU_METRICS),
121 };
122 
123 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
124 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
125 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
126 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,			WORKLOAD_PPLIB_VR_BIT),
127 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
128 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
129 };
130 
131 static int renoir_init_smc_tables(struct smu_context *smu)
132 {
133 	struct smu_table_context *smu_table = &smu->smu_table;
134 	struct smu_table *tables = smu_table->tables;
135 
136 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
137 		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
138 	SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
139 		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
140 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
141 		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
142 
143 	smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
144 	if (!smu_table->clocks_table)
145 		goto err0_out;
146 
147 	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
148 	if (!smu_table->metrics_table)
149 		goto err1_out;
150 	smu_table->metrics_time = 0;
151 
152 	smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
153 	if (!smu_table->watermarks_table)
154 		goto err2_out;
155 
156 	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0);
157 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
158 	if (!smu_table->gpu_metrics_table)
159 		goto err3_out;
160 
161 	return 0;
162 
163 err3_out:
164 	kfree(smu_table->watermarks_table);
165 err2_out:
166 	kfree(smu_table->metrics_table);
167 err1_out:
168 	kfree(smu_table->clocks_table);
169 err0_out:
170 	return -ENOMEM;
171 }
172 
173 /**
174  * This interface just for getting uclk ultimate freq and should't introduce
175  * other likewise function result in overmuch callback.
176  */
177 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
178 						uint32_t dpm_level, uint32_t *freq)
179 {
180 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
181 
182 	if (!clk_table || clk_type >= SMU_CLK_COUNT)
183 		return -EINVAL;
184 
185 	switch (clk_type) {
186 	case SMU_SOCCLK:
187 		if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
188 			return -EINVAL;
189 		*freq = clk_table->SocClocks[dpm_level].Freq;
190 		break;
191 	case SMU_MCLK:
192 		if (dpm_level >= NUM_FCLK_DPM_LEVELS)
193 			return -EINVAL;
194 		*freq = clk_table->FClocks[dpm_level].Freq;
195 		break;
196 	case SMU_DCEFCLK:
197 		if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
198 			return -EINVAL;
199 		*freq = clk_table->DcfClocks[dpm_level].Freq;
200 		break;
201 	case SMU_FCLK:
202 		if (dpm_level >= NUM_FCLK_DPM_LEVELS)
203 			return -EINVAL;
204 		*freq = clk_table->FClocks[dpm_level].Freq;
205 		break;
206 	default:
207 		return -EINVAL;
208 	}
209 
210 	return 0;
211 }
212 
213 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
214 					 enum amd_dpm_forced_level level,
215 					 uint32_t *sclk_mask,
216 					 uint32_t *mclk_mask,
217 					 uint32_t *soc_mask)
218 {
219 
220 	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
221 		if (sclk_mask)
222 			*sclk_mask = 0;
223 	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
224 		if (mclk_mask)
225 			*mclk_mask = 0;
226 	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
227 		if(sclk_mask)
228 			/* The sclk as gfxclk and has three level about max/min/current */
229 			*sclk_mask = 3 - 1;
230 
231 		if(mclk_mask)
232 			*mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
233 
234 		if(soc_mask)
235 			*soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
236 	}
237 
238 	return 0;
239 }
240 
241 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
242 					enum smu_clk_type clk_type,
243 					uint32_t *min,
244 					uint32_t *max)
245 {
246 	int ret = 0;
247 	uint32_t mclk_mask, soc_mask;
248 	uint32_t clock_limit;
249 
250 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
251 		switch (clk_type) {
252 		case SMU_MCLK:
253 		case SMU_UCLK:
254 			clock_limit = smu->smu_table.boot_values.uclk;
255 			break;
256 		case SMU_GFXCLK:
257 		case SMU_SCLK:
258 			clock_limit = smu->smu_table.boot_values.gfxclk;
259 			break;
260 		case SMU_SOCCLK:
261 			clock_limit = smu->smu_table.boot_values.socclk;
262 			break;
263 		default:
264 			clock_limit = 0;
265 			break;
266 		}
267 
268 		/* clock in Mhz unit */
269 		if (min)
270 			*min = clock_limit / 100;
271 		if (max)
272 			*max = clock_limit / 100;
273 
274 		return 0;
275 	}
276 
277 	if (max) {
278 		ret = renoir_get_profiling_clk_mask(smu,
279 						    AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
280 						    NULL,
281 						    &mclk_mask,
282 						    &soc_mask);
283 		if (ret)
284 			goto failed;
285 
286 		switch (clk_type) {
287 		case SMU_GFXCLK:
288 		case SMU_SCLK:
289 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
290 			if (ret) {
291 				dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
292 				goto failed;
293 			}
294 			break;
295 		case SMU_UCLK:
296 		case SMU_FCLK:
297 		case SMU_MCLK:
298 			ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
299 			if (ret)
300 				goto failed;
301 			break;
302 		case SMU_SOCCLK:
303 			ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
304 			if (ret)
305 				goto failed;
306 			break;
307 		default:
308 			ret = -EINVAL;
309 			goto failed;
310 		}
311 	}
312 
313 	if (min) {
314 		switch (clk_type) {
315 		case SMU_GFXCLK:
316 		case SMU_SCLK:
317 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
318 			if (ret) {
319 				dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
320 				goto failed;
321 			}
322 			break;
323 		case SMU_UCLK:
324 		case SMU_FCLK:
325 		case SMU_MCLK:
326 			ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
327 			if (ret)
328 				goto failed;
329 			break;
330 		case SMU_SOCCLK:
331 			ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
332 			if (ret)
333 				goto failed;
334 			break;
335 		default:
336 			ret = -EINVAL;
337 			goto failed;
338 		}
339 	}
340 failed:
341 	return ret;
342 }
343 
344 static int renoir_print_clk_levels(struct smu_context *smu,
345 			enum smu_clk_type clk_type, char *buf)
346 {
347 	int i, size = 0, ret = 0;
348 	uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
349 	SmuMetrics_t metrics;
350 	bool cur_value_match_level = false;
351 
352 	memset(&metrics, 0, sizeof(metrics));
353 
354 	ret = smu_cmn_get_metrics_table(smu, &metrics, false);
355 	if (ret)
356 		return ret;
357 
358 	switch (clk_type) {
359 	case SMU_GFXCLK:
360 	case SMU_SCLK:
361 		/* retirve table returned paramters unit is MHz */
362 		cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
363 		ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
364 		if (!ret) {
365 			/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
366 			if (cur_value  == max)
367 				i = 2;
368 			else if (cur_value == min)
369 				i = 0;
370 			else
371 				i = 1;
372 
373 			size += sprintf(buf + size, "0: %uMhz %s\n", min,
374 					i == 0 ? "*" : "");
375 			size += sprintf(buf + size, "1: %uMhz %s\n",
376 					i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
377 					i == 1 ? "*" : "");
378 			size += sprintf(buf + size, "2: %uMhz %s\n", max,
379 					i == 2 ? "*" : "");
380 		}
381 		return size;
382 	case SMU_SOCCLK:
383 		count = NUM_SOCCLK_DPM_LEVELS;
384 		cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
385 		break;
386 	case SMU_MCLK:
387 		count = NUM_MEMCLK_DPM_LEVELS;
388 		cur_value = metrics.ClockFrequency[CLOCK_FCLK];
389 		break;
390 	case SMU_DCEFCLK:
391 		count = NUM_DCFCLK_DPM_LEVELS;
392 		cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
393 		break;
394 	case SMU_FCLK:
395 		count = NUM_FCLK_DPM_LEVELS;
396 		cur_value = metrics.ClockFrequency[CLOCK_FCLK];
397 		break;
398 	default:
399 		return -EINVAL;
400 	}
401 
402 	for (i = 0; i < count; i++) {
403 		ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);
404 		if (ret)
405 			return ret;
406 		if (!value)
407 			continue;
408 		size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
409 				cur_value == value ? "*" : "");
410 		if (cur_value == value)
411 			cur_value_match_level = true;
412 	}
413 
414 	if (!cur_value_match_level)
415 		size += sprintf(buf + size, "   %uMhz *\n", cur_value);
416 
417 	return size;
418 }
419 
420 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
421 {
422 	enum amd_pm_state_type pm_type;
423 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
424 
425 	if (!smu_dpm_ctx->dpm_context ||
426 	    !smu_dpm_ctx->dpm_current_power_state)
427 		return -EINVAL;
428 
429 	switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
430 	case SMU_STATE_UI_LABEL_BATTERY:
431 		pm_type = POWER_STATE_TYPE_BATTERY;
432 		break;
433 	case SMU_STATE_UI_LABEL_BALLANCED:
434 		pm_type = POWER_STATE_TYPE_BALANCED;
435 		break;
436 	case SMU_STATE_UI_LABEL_PERFORMANCE:
437 		pm_type = POWER_STATE_TYPE_PERFORMANCE;
438 		break;
439 	default:
440 		if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
441 			pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
442 		else
443 			pm_type = POWER_STATE_TYPE_DEFAULT;
444 		break;
445 	}
446 
447 	return pm_type;
448 }
449 
450 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
451 {
452 	int ret = 0;
453 
454 	if (enable) {
455 		/* vcn dpm on is a prerequisite for vcn power gate messages */
456 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
457 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
458 			if (ret)
459 				return ret;
460 		}
461 	} else {
462 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
463 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
464 			if (ret)
465 				return ret;
466 		}
467 	}
468 
469 	return ret;
470 }
471 
472 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
473 {
474 	int ret = 0;
475 
476 	if (enable) {
477 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
478 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
479 			if (ret)
480 				return ret;
481 		}
482 	} else {
483 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
484 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
485 			if (ret)
486 				return ret;
487 		}
488 	}
489 
490 	return ret;
491 }
492 
493 static int renoir_get_current_clk_freq_by_table(struct smu_context *smu,
494 				       enum smu_clk_type clk_type,
495 				       uint32_t *value)
496 {
497 	int ret = 0, clk_id = 0;
498 	SmuMetrics_t metrics;
499 
500 	ret = smu_cmn_get_metrics_table(smu, &metrics, false);
501 	if (ret)
502 		return ret;
503 
504 	clk_id = smu_cmn_to_asic_specific_index(smu,
505 						CMN2ASIC_MAPPING_CLK,
506 						clk_type);
507 	if (clk_id < 0)
508 		return clk_id;
509 
510 	*value = metrics.ClockFrequency[clk_id];
511 
512 	return ret;
513 }
514 
515 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
516 {
517 	int ret = 0, i = 0;
518 	uint32_t min_freq, max_freq, force_freq;
519 	enum smu_clk_type clk_type;
520 
521 	enum smu_clk_type clks[] = {
522 		SMU_GFXCLK,
523 		SMU_MCLK,
524 		SMU_SOCCLK,
525 	};
526 
527 	for (i = 0; i < ARRAY_SIZE(clks); i++) {
528 		clk_type = clks[i];
529 		ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
530 		if (ret)
531 			return ret;
532 
533 		force_freq = highest ? max_freq : min_freq;
534 		ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
535 		if (ret)
536 			return ret;
537 	}
538 
539 	return ret;
540 }
541 
542 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
543 
544 	int ret = 0, i = 0;
545 	uint32_t min_freq, max_freq;
546 	enum smu_clk_type clk_type;
547 
548 	struct clk_feature_map {
549 		enum smu_clk_type clk_type;
550 		uint32_t	feature;
551 	} clk_feature_map[] = {
552 		{SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
553 		{SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
554 		{SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
555 	};
556 
557 	for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
558 		if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
559 		    continue;
560 
561 		clk_type = clk_feature_map[i].clk_type;
562 
563 		ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
564 		if (ret)
565 			return ret;
566 
567 		ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
568 		if (ret)
569 			return ret;
570 	}
571 
572 	return ret;
573 }
574 
575 static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value)
576 {
577 	int ret = 0;
578 	SmuMetrics_t metrics;
579 
580 	if (!value)
581 		return -EINVAL;
582 
583 	ret = smu_cmn_get_metrics_table(smu, &metrics, false);
584 	if (ret)
585 		return ret;
586 
587 	*value = (metrics.GfxTemperature / 100) *
588 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
589 
590 	return 0;
591 }
592 
593 static int renoir_get_current_activity_percent(struct smu_context *smu,
594 					       enum amd_pp_sensors sensor,
595 					       uint32_t *value)
596 {
597 	int ret = 0;
598 	SmuMetrics_t metrics;
599 
600 	if (!value)
601 		return -EINVAL;
602 
603 	ret = smu_cmn_get_metrics_table(smu, &metrics, false);
604 	if (ret)
605 		return ret;
606 
607 	switch (sensor) {
608 	case AMDGPU_PP_SENSOR_GPU_LOAD:
609 		*value = metrics.AverageGfxActivity / 100;
610 		break;
611 	default:
612 		dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
613 		return -EINVAL;
614 	}
615 
616 	return 0;
617 }
618 
619 static int renoir_get_vddc(struct smu_context *smu, uint32_t *value,
620 			   unsigned int index)
621 {
622 	int ret = 0;
623 	SmuMetrics_t metrics;
624 
625 	if (index >= 2)
626 		return -EINVAL;
627 
628 	if (!value)
629 		return -EINVAL;
630 
631 	ret = smu_cmn_get_metrics_table(smu, &metrics, false);
632 	if (ret)
633 		return ret;
634 
635 	*value = metrics.Voltage[index];
636 
637 	return 0;
638 }
639 
640 static int renoir_get_power(struct smu_context *smu, uint32_t *value)
641 {
642 	int ret = 0;
643 	SmuMetrics_t metrics;
644 
645 	if (!value)
646 		return -EINVAL;
647 
648 	ret = smu_cmn_get_metrics_table(smu, &metrics, false);
649 	if (ret)
650 		return ret;
651 
652 	*value = metrics.CurrentSocketPower << 8;
653 
654 	return 0;
655 }
656 
657 /**
658  * This interface get dpm clock table for dc
659  */
660 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
661 {
662 	DpmClocks_t *table = smu->smu_table.clocks_table;
663 	int i;
664 
665 	if (!clock_table || !table)
666 		return -EINVAL;
667 
668 	for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
669 		clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
670 		clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
671 	}
672 
673 	for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
674 		clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
675 		clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
676 	}
677 
678 	for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
679 		clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
680 		clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
681 	}
682 
683 	for (i = 0; i<  NUM_MEMCLK_DPM_LEVELS; i++) {
684 		clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
685 		clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
686 	}
687 
688 	return 0;
689 }
690 
691 static int renoir_force_clk_levels(struct smu_context *smu,
692 				   enum smu_clk_type clk_type, uint32_t mask)
693 {
694 
695 	int ret = 0 ;
696 	uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
697 
698 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
699 	soft_max_level = mask ? (fls(mask) - 1) : 0;
700 
701 	switch (clk_type) {
702 	case SMU_GFXCLK:
703 	case SMU_SCLK:
704 		if (soft_min_level > 2 || soft_max_level > 2) {
705 			dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
706 			return -EINVAL;
707 		}
708 
709 		ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
710 		if (ret)
711 			return ret;
712 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
713 					soft_max_level == 0 ? min_freq :
714 					soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
715 					NULL);
716 		if (ret)
717 			return ret;
718 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
719 					soft_min_level == 2 ? max_freq :
720 					soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
721 					NULL);
722 		if (ret)
723 			return ret;
724 		break;
725 	case SMU_SOCCLK:
726 		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
727 		if (ret)
728 			return ret;
729 		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
730 		if (ret)
731 			return ret;
732 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
733 		if (ret)
734 			return ret;
735 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
736 		if (ret)
737 			return ret;
738 		break;
739 	case SMU_MCLK:
740 	case SMU_FCLK:
741 		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
742 		if (ret)
743 			return ret;
744 		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
745 		if (ret)
746 			return ret;
747 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
748 		if (ret)
749 			return ret;
750 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
751 		if (ret)
752 			return ret;
753 		break;
754 	default:
755 		break;
756 	}
757 
758 	return ret;
759 }
760 
761 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
762 {
763 	int workload_type, ret;
764 	uint32_t profile_mode = input[size];
765 
766 	if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
767 		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
768 		return -EINVAL;
769 	}
770 
771 	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
772 	workload_type = smu_cmn_to_asic_specific_index(smu,
773 						       CMN2ASIC_MAPPING_WORKLOAD,
774 						       profile_mode);
775 	if (workload_type < 0) {
776 		/*
777 		 * TODO: If some case need switch to powersave/default power mode
778 		 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving.
779 		 */
780 		dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
781 		return -EINVAL;
782 	}
783 
784 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
785 				    1 << workload_type,
786 				    NULL);
787 	if (ret) {
788 		dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
789 		return ret;
790 	}
791 
792 	smu->power_profile_mode = profile_mode;
793 
794 	return 0;
795 }
796 
797 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
798 {
799 	int ret = 0;
800 	uint32_t sclk_freq = 0, uclk_freq = 0;
801 
802 	ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
803 	if (ret)
804 		return ret;
805 
806 	ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
807 	if (ret)
808 		return ret;
809 
810 	ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
811 	if (ret)
812 		return ret;
813 
814 	ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
815 	if (ret)
816 		return ret;
817 
818 	return ret;
819 }
820 
821 static int renoir_set_performance_level(struct smu_context *smu,
822 					enum amd_dpm_forced_level level)
823 {
824 	int ret = 0;
825 	uint32_t sclk_mask, mclk_mask, soc_mask;
826 
827 	switch (level) {
828 	case AMD_DPM_FORCED_LEVEL_HIGH:
829 		ret = renoir_force_dpm_limit_value(smu, true);
830 		break;
831 	case AMD_DPM_FORCED_LEVEL_LOW:
832 		ret = renoir_force_dpm_limit_value(smu, false);
833 		break;
834 	case AMD_DPM_FORCED_LEVEL_AUTO:
835 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
836 		ret = renoir_unforce_dpm_levels(smu);
837 		break;
838 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
839 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
840 		ret = renoir_get_profiling_clk_mask(smu, level,
841 						    &sclk_mask,
842 						    &mclk_mask,
843 						    &soc_mask);
844 		if (ret)
845 			return ret;
846 		renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
847 		renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
848 		renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
849 		break;
850 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
851 		ret = renoir_set_peak_clock_by_device(smu);
852 		break;
853 	case AMD_DPM_FORCED_LEVEL_MANUAL:
854 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
855 	default:
856 		break;
857 	}
858 	return ret;
859 }
860 
861 /* save watermark settings into pplib smu structure,
862  * also pass data to smu controller
863  */
864 static int renoir_set_watermarks_table(
865 		struct smu_context *smu,
866 		struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
867 {
868 	Watermarks_t *table = smu->smu_table.watermarks_table;
869 	int ret = 0;
870 	int i;
871 
872 	if (clock_ranges) {
873 		if (clock_ranges->num_wm_dmif_sets > 4 ||
874 				clock_ranges->num_wm_mcif_sets > 4)
875 			return -EINVAL;
876 
877 		/* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
878 		for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
879 			table->WatermarkRow[WM_DCFCLK][i].MinClock =
880 				cpu_to_le16((uint16_t)
881 				(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
882 			table->WatermarkRow[WM_DCFCLK][i].MaxClock =
883 				cpu_to_le16((uint16_t)
884 				(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
885 			table->WatermarkRow[WM_DCFCLK][i].MinMclk =
886 				cpu_to_le16((uint16_t)
887 				(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
888 			table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
889 				cpu_to_le16((uint16_t)
890 				(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
891 			table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
892 					clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
893 		}
894 
895 		for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
896 			table->WatermarkRow[WM_SOCCLK][i].MinClock =
897 				cpu_to_le16((uint16_t)
898 				(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
899 			table->WatermarkRow[WM_SOCCLK][i].MaxClock =
900 				cpu_to_le16((uint16_t)
901 				(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
902 			table->WatermarkRow[WM_SOCCLK][i].MinMclk =
903 				cpu_to_le16((uint16_t)
904 				(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
905 			table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
906 				cpu_to_le16((uint16_t)
907 				(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
908 			table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
909 					clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
910 		}
911 
912 		smu->watermarks_bitmap |= WATERMARKS_EXIST;
913 	}
914 
915 	/* pass data to smu controller */
916 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
917 	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
918 		ret = smu_cmn_write_watermarks_table(smu);
919 		if (ret) {
920 			dev_err(smu->adev->dev, "Failed to update WMTABLE!");
921 			return ret;
922 		}
923 		smu->watermarks_bitmap |= WATERMARKS_LOADED;
924 	}
925 
926 	return 0;
927 }
928 
929 static int renoir_get_power_profile_mode(struct smu_context *smu,
930 					   char *buf)
931 {
932 	static const char *profile_name[] = {
933 					"BOOTUP_DEFAULT",
934 					"3D_FULL_SCREEN",
935 					"POWER_SAVING",
936 					"VIDEO",
937 					"VR",
938 					"COMPUTE",
939 					"CUSTOM"};
940 	uint32_t i, size = 0;
941 	int16_t workload_type = 0;
942 
943 	if (!buf)
944 		return -EINVAL;
945 
946 	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
947 		/*
948 		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
949 		 * Not all profile modes are supported on arcturus.
950 		 */
951 		workload_type = smu_cmn_to_asic_specific_index(smu,
952 							       CMN2ASIC_MAPPING_WORKLOAD,
953 							       i);
954 		if (workload_type < 0)
955 			continue;
956 
957 		size += sprintf(buf + size, "%2d %14s%s\n",
958 			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
959 	}
960 
961 	return size;
962 }
963 
964 static int renoir_read_sensor(struct smu_context *smu,
965 				 enum amd_pp_sensors sensor,
966 				 void *data, uint32_t *size)
967 {
968 	int ret = 0;
969 
970 	if (!data || !size)
971 		return -EINVAL;
972 
973 	mutex_lock(&smu->sensor_lock);
974 	switch (sensor) {
975 	case AMDGPU_PP_SENSOR_GPU_LOAD:
976 		ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
977 		*size = 4;
978 		break;
979 	case AMDGPU_PP_SENSOR_GPU_TEMP:
980 		ret = renoir_get_gpu_temperature(smu, (uint32_t *)data);
981 		*size = 4;
982 		break;
983 	case AMDGPU_PP_SENSOR_GFX_MCLK:
984 		ret = renoir_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
985 		*(uint32_t *)data *= 100;
986 		*size = 4;
987 		break;
988 	case AMDGPU_PP_SENSOR_GFX_SCLK:
989 		ret = renoir_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
990 		*(uint32_t *)data *= 100;
991 		*size = 4;
992 		break;
993 	case AMDGPU_PP_SENSOR_VDDGFX:
994 		ret = renoir_get_vddc(smu, (uint32_t *)data, 0);
995 		*size = 4;
996 		break;
997 	case AMDGPU_PP_SENSOR_VDDNB:
998 		ret = renoir_get_vddc(smu, (uint32_t *)data, 1);
999 		*size = 4;
1000 		break;
1001 	case AMDGPU_PP_SENSOR_GPU_POWER:
1002 		ret = renoir_get_power(smu, (uint32_t *)data);
1003 		*size = 4;
1004 		break;
1005 	default:
1006 		ret = -EOPNOTSUPP;
1007 		break;
1008 	}
1009 	mutex_unlock(&smu->sensor_lock);
1010 
1011 	return ret;
1012 }
1013 
1014 static bool renoir_is_dpm_running(struct smu_context *smu)
1015 {
1016 	struct amdgpu_device *adev = smu->adev;
1017 
1018 	/*
1019 	 * Until now, the pmfw hasn't exported the interface of SMU
1020 	 * feature mask to APU SKU so just force on all the feature
1021 	 * at early initial stage.
1022 	 */
1023 	if (adev->in_suspend)
1024 		return false;
1025 	else
1026 		return true;
1027 
1028 }
1029 
1030 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1031 				      void **table)
1032 {
1033 	struct smu_table_context *smu_table = &smu->smu_table;
1034 	struct gpu_metrics_v2_0 *gpu_metrics =
1035 		(struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table;
1036 	SmuMetrics_t metrics;
1037 	int ret = 0;
1038 
1039 	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1040 	if (ret)
1041 		return ret;
1042 
1043 	smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics);
1044 
1045 	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1046 	gpu_metrics->temperature_soc = metrics.SocTemperature;
1047 	memcpy(&gpu_metrics->temperature_core[0],
1048 		&metrics.CoreTemperature[0],
1049 		sizeof(uint16_t) * 8);
1050 	gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1051 	gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1052 
1053 	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1054 	gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1055 
1056 	gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1057 	gpu_metrics->average_cpu_power = metrics.Power[0];
1058 	gpu_metrics->average_soc_power = metrics.Power[1];
1059 	memcpy(&gpu_metrics->average_core_power[0],
1060 		&metrics.CorePower[0],
1061 		sizeof(uint16_t) * 8);
1062 
1063 	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1064 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1065 	gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1066 	gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1067 
1068 	gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1069 	gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1070 	gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1071 	gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1072 	gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1073 	gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1074 	memcpy(&gpu_metrics->current_coreclk[0],
1075 		&metrics.CoreFrequency[0],
1076 		sizeof(uint16_t) * 8);
1077 	gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1078 	gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1079 
1080 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1081 
1082 	gpu_metrics->fan_pwm = metrics.FanPwm;
1083 
1084 	*table = (void *)gpu_metrics;
1085 
1086 	return sizeof(struct gpu_metrics_v2_0);
1087 }
1088 
1089 static const struct pptable_funcs renoir_ppt_funcs = {
1090 	.set_power_state = NULL,
1091 	.print_clk_levels = renoir_print_clk_levels,
1092 	.get_current_power_state = renoir_get_current_power_state,
1093 	.dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1094 	.dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1095 	.force_clk_levels = renoir_force_clk_levels,
1096 	.set_power_profile_mode = renoir_set_power_profile_mode,
1097 	.set_performance_level = renoir_set_performance_level,
1098 	.get_dpm_clock_table = renoir_get_dpm_clock_table,
1099 	.set_watermarks_table = renoir_set_watermarks_table,
1100 	.get_power_profile_mode = renoir_get_power_profile_mode,
1101 	.read_sensor = renoir_read_sensor,
1102 	.check_fw_status = smu_v12_0_check_fw_status,
1103 	.check_fw_version = smu_v12_0_check_fw_version,
1104 	.powergate_sdma = smu_v12_0_powergate_sdma,
1105 	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1106 	.send_smc_msg = smu_cmn_send_smc_msg,
1107 	.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1108 	.gfx_off_control = smu_v12_0_gfx_off_control,
1109 	.get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1110 	.init_smc_tables = renoir_init_smc_tables,
1111 	.fini_smc_tables = smu_v12_0_fini_smc_tables,
1112 	.set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1113 	.get_enabled_mask = smu_cmn_get_enabled_mask,
1114 	.feature_is_enabled = smu_cmn_feature_is_enabled,
1115 	.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1116 	.get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1117 	.mode2_reset = smu_v12_0_mode2_reset,
1118 	.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1119 	.set_driver_table_location = smu_v12_0_set_driver_table_location,
1120 	.is_dpm_running = renoir_is_dpm_running,
1121 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1122 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1123 	.get_gpu_metrics = renoir_get_gpu_metrics,
1124 };
1125 
1126 void renoir_set_ppt_funcs(struct smu_context *smu)
1127 {
1128 	smu->ppt_funcs = &renoir_ppt_funcs;
1129 	smu->message_map = renoir_message_map;
1130 	smu->clock_map = renoir_clk_map;
1131 	smu->table_map = renoir_table_map;
1132 	smu->workload_map = renoir_workload_map;
1133 	smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1134 	smu->is_apu = true;
1135 }
1136