1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v12_0_ppsmc.h" 29 #include "smu12_driver_if.h" 30 #include "smu_v12_0.h" 31 #include "renoir_ppt.h" 32 #include "smu_cmn.h" 33 34 /* 35 * DO NOT use these for err/warn/info/debug messages. 36 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 37 * They are more MGPU friendly. 38 */ 39 #undef pr_err 40 #undef pr_warn 41 #undef pr_info 42 #undef pr_debug 43 44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { 45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1), 49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1), 50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1), 51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1), 56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1), 57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1), 58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 59 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1), 60 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1), 61 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1), 62 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1), 63 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1), 64 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1), 65 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1), 66 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 67 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 68 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 69 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 70 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 71 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1), 72 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1), 73 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 74 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1), 75 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1), 76 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1), 77 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1), 78 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1), 79 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1), 80 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 81 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1), 82 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 83 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 84 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1), 85 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1), 86 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1), 87 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1), 88 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 89 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 90 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 91 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 92 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 93 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1), 94 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1), 95 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1), 96 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 97 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1), 98 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1), 99 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 100 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 101 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1), 102 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1), 103 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 104 }; 105 106 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { 107 CLK_MAP(GFXCLK, CLOCK_GFXCLK), 108 CLK_MAP(SCLK, CLOCK_GFXCLK), 109 CLK_MAP(SOCCLK, CLOCK_SOCCLK), 110 CLK_MAP(UCLK, CLOCK_FCLK), 111 CLK_MAP(MCLK, CLOCK_FCLK), 112 }; 113 114 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { 115 TAB_MAP_VALID(WATERMARKS), 116 TAB_MAP_INVALID(CUSTOM_DPM), 117 TAB_MAP_VALID(DPMCLOCKS), 118 TAB_MAP_VALID(SMU_METRICS), 119 }; 120 121 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 122 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 123 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 127 }; 128 129 static int renoir_init_smc_tables(struct smu_context *smu) 130 { 131 struct smu_table_context *smu_table = &smu->smu_table; 132 struct smu_table *tables = smu_table->tables; 133 134 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 135 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 136 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 137 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 138 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 139 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 140 141 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 142 if (!smu_table->clocks_table) 143 goto err0_out; 144 145 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 146 if (!smu_table->metrics_table) 147 goto err1_out; 148 smu_table->metrics_time = 0; 149 150 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 151 if (!smu_table->watermarks_table) 152 goto err2_out; 153 154 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); 155 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 156 if (!smu_table->gpu_metrics_table) 157 goto err3_out; 158 159 return 0; 160 161 err3_out: 162 kfree(smu_table->watermarks_table); 163 err2_out: 164 kfree(smu_table->metrics_table); 165 err1_out: 166 kfree(smu_table->clocks_table); 167 err0_out: 168 return -ENOMEM; 169 } 170 171 /* 172 * This interface just for getting uclk ultimate freq and should't introduce 173 * other likewise function result in overmuch callback. 174 */ 175 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 176 uint32_t dpm_level, uint32_t *freq) 177 { 178 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 179 180 if (!clk_table || clk_type >= SMU_CLK_COUNT) 181 return -EINVAL; 182 183 switch (clk_type) { 184 case SMU_SOCCLK: 185 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) 186 return -EINVAL; 187 *freq = clk_table->SocClocks[dpm_level].Freq; 188 break; 189 case SMU_UCLK: 190 case SMU_MCLK: 191 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 192 return -EINVAL; 193 *freq = clk_table->FClocks[dpm_level].Freq; 194 break; 195 case SMU_DCEFCLK: 196 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) 197 return -EINVAL; 198 *freq = clk_table->DcfClocks[dpm_level].Freq; 199 break; 200 case SMU_FCLK: 201 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 202 return -EINVAL; 203 *freq = clk_table->FClocks[dpm_level].Freq; 204 break; 205 default: 206 return -EINVAL; 207 } 208 209 return 0; 210 } 211 212 static int renoir_get_profiling_clk_mask(struct smu_context *smu, 213 enum amd_dpm_forced_level level, 214 uint32_t *sclk_mask, 215 uint32_t *mclk_mask, 216 uint32_t *soc_mask) 217 { 218 219 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 220 if (sclk_mask) 221 *sclk_mask = 0; 222 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 223 if (mclk_mask) 224 /* mclk levels are in reverse order */ 225 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; 226 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 227 if(sclk_mask) 228 /* The sclk as gfxclk and has three level about max/min/current */ 229 *sclk_mask = 3 - 1; 230 231 if(mclk_mask) 232 /* mclk levels are in reverse order */ 233 *mclk_mask = 0; 234 235 if(soc_mask) 236 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; 237 } 238 239 return 0; 240 } 241 242 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu, 243 enum smu_clk_type clk_type, 244 uint32_t *min, 245 uint32_t *max) 246 { 247 int ret = 0; 248 uint32_t mclk_mask, soc_mask; 249 uint32_t clock_limit; 250 251 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 252 switch (clk_type) { 253 case SMU_MCLK: 254 case SMU_UCLK: 255 clock_limit = smu->smu_table.boot_values.uclk; 256 break; 257 case SMU_GFXCLK: 258 case SMU_SCLK: 259 clock_limit = smu->smu_table.boot_values.gfxclk; 260 break; 261 case SMU_SOCCLK: 262 clock_limit = smu->smu_table.boot_values.socclk; 263 break; 264 default: 265 clock_limit = 0; 266 break; 267 } 268 269 /* clock in Mhz unit */ 270 if (min) 271 *min = clock_limit / 100; 272 if (max) 273 *max = clock_limit / 100; 274 275 return 0; 276 } 277 278 if (max) { 279 ret = renoir_get_profiling_clk_mask(smu, 280 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 281 NULL, 282 &mclk_mask, 283 &soc_mask); 284 if (ret) 285 goto failed; 286 287 switch (clk_type) { 288 case SMU_GFXCLK: 289 case SMU_SCLK: 290 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max); 291 if (ret) { 292 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n"); 293 goto failed; 294 } 295 break; 296 case SMU_UCLK: 297 case SMU_FCLK: 298 case SMU_MCLK: 299 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 300 if (ret) 301 goto failed; 302 break; 303 case SMU_SOCCLK: 304 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 305 if (ret) 306 goto failed; 307 break; 308 default: 309 ret = -EINVAL; 310 goto failed; 311 } 312 } 313 314 if (min) { 315 switch (clk_type) { 316 case SMU_GFXCLK: 317 case SMU_SCLK: 318 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min); 319 if (ret) { 320 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n"); 321 goto failed; 322 } 323 break; 324 case SMU_UCLK: 325 case SMU_FCLK: 326 case SMU_MCLK: 327 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min); 328 if (ret) 329 goto failed; 330 break; 331 case SMU_SOCCLK: 332 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min); 333 if (ret) 334 goto failed; 335 break; 336 default: 337 ret = -EINVAL; 338 goto failed; 339 } 340 } 341 failed: 342 return ret; 343 } 344 345 static int renoir_od_edit_dpm_table(struct smu_context *smu, 346 enum PP_OD_DPM_TABLE_COMMAND type, 347 long input[], uint32_t size) 348 { 349 int ret = 0; 350 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 351 352 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 353 dev_warn(smu->adev->dev, 354 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 355 return -EINVAL; 356 } 357 358 switch (type) { 359 case PP_OD_EDIT_SCLK_VDDC_TABLE: 360 if (size != 2) { 361 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 362 return -EINVAL; 363 } 364 365 if (input[0] == 0) { 366 if (input[1] < smu->gfx_default_hard_min_freq) { 367 dev_warn(smu->adev->dev, 368 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 369 input[1], smu->gfx_default_hard_min_freq); 370 return -EINVAL; 371 } 372 smu->gfx_actual_hard_min_freq = input[1]; 373 } else if (input[0] == 1) { 374 if (input[1] > smu->gfx_default_soft_max_freq) { 375 dev_warn(smu->adev->dev, 376 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 377 input[1], smu->gfx_default_soft_max_freq); 378 return -EINVAL; 379 } 380 smu->gfx_actual_soft_max_freq = input[1]; 381 } else { 382 return -EINVAL; 383 } 384 break; 385 case PP_OD_RESTORE_DEFAULT_TABLE: 386 if (size != 0) { 387 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 388 return -EINVAL; 389 } 390 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 391 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 392 break; 393 case PP_OD_COMMIT_DPM_TABLE: 394 if (size != 0) { 395 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 396 return -EINVAL; 397 } else { 398 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 399 dev_err(smu->adev->dev, 400 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 401 smu->gfx_actual_hard_min_freq, 402 smu->gfx_actual_soft_max_freq); 403 return -EINVAL; 404 } 405 406 ret = smu_cmn_send_smc_msg_with_param(smu, 407 SMU_MSG_SetHardMinGfxClk, 408 smu->gfx_actual_hard_min_freq, 409 NULL); 410 if (ret) { 411 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 412 return ret; 413 } 414 415 ret = smu_cmn_send_smc_msg_with_param(smu, 416 SMU_MSG_SetSoftMaxGfxClk, 417 smu->gfx_actual_soft_max_freq, 418 NULL); 419 if (ret) { 420 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 421 return ret; 422 } 423 } 424 break; 425 default: 426 return -ENOSYS; 427 } 428 429 return ret; 430 } 431 432 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 433 { 434 uint32_t min = 0, max = 0; 435 uint32_t ret = 0; 436 437 ret = smu_cmn_send_smc_msg_with_param(smu, 438 SMU_MSG_GetMinGfxclkFrequency, 439 0, &min); 440 if (ret) 441 return ret; 442 ret = smu_cmn_send_smc_msg_with_param(smu, 443 SMU_MSG_GetMaxGfxclkFrequency, 444 0, &max); 445 if (ret) 446 return ret; 447 448 smu->gfx_default_hard_min_freq = min; 449 smu->gfx_default_soft_max_freq = max; 450 smu->gfx_actual_hard_min_freq = 0; 451 smu->gfx_actual_soft_max_freq = 0; 452 453 return 0; 454 } 455 456 static int renoir_print_clk_levels(struct smu_context *smu, 457 enum smu_clk_type clk_type, char *buf) 458 { 459 int i, size = 0, ret = 0; 460 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; 461 SmuMetrics_t metrics; 462 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 463 bool cur_value_match_level = false; 464 465 memset(&metrics, 0, sizeof(metrics)); 466 467 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 468 if (ret) 469 return ret; 470 471 switch (clk_type) { 472 case SMU_OD_RANGE: 473 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 474 ret = smu_cmn_send_smc_msg_with_param(smu, 475 SMU_MSG_GetMinGfxclkFrequency, 476 0, &min); 477 if (ret) 478 return ret; 479 ret = smu_cmn_send_smc_msg_with_param(smu, 480 SMU_MSG_GetMaxGfxclkFrequency, 481 0, &max); 482 if (ret) 483 return ret; 484 size += sprintf(buf + size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max); 485 } 486 break; 487 case SMU_OD_SCLK: 488 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 489 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 490 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 491 size += sprintf(buf + size, "OD_SCLK\n"); 492 size += sprintf(buf + size, "0:%10uMhz\n", min); 493 size += sprintf(buf + size, "1:%10uMhz\n", max); 494 } 495 break; 496 case SMU_GFXCLK: 497 case SMU_SCLK: 498 /* retirve table returned paramters unit is MHz */ 499 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; 500 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max); 501 if (!ret) { 502 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 503 if (cur_value == max) 504 i = 2; 505 else if (cur_value == min) 506 i = 0; 507 else 508 i = 1; 509 510 size += sprintf(buf + size, "0: %uMhz %s\n", min, 511 i == 0 ? "*" : ""); 512 size += sprintf(buf + size, "1: %uMhz %s\n", 513 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, 514 i == 1 ? "*" : ""); 515 size += sprintf(buf + size, "2: %uMhz %s\n", max, 516 i == 2 ? "*" : ""); 517 } 518 return size; 519 case SMU_SOCCLK: 520 count = NUM_SOCCLK_DPM_LEVELS; 521 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; 522 break; 523 case SMU_MCLK: 524 count = NUM_MEMCLK_DPM_LEVELS; 525 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 526 break; 527 case SMU_DCEFCLK: 528 count = NUM_DCFCLK_DPM_LEVELS; 529 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK]; 530 break; 531 case SMU_FCLK: 532 count = NUM_FCLK_DPM_LEVELS; 533 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 534 break; 535 default: 536 break; 537 } 538 539 switch (clk_type) { 540 case SMU_GFXCLK: 541 case SMU_SCLK: 542 case SMU_SOCCLK: 543 case SMU_MCLK: 544 case SMU_DCEFCLK: 545 case SMU_FCLK: 546 for (i = 0; i < count; i++) { 547 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); 548 if (ret) 549 return ret; 550 if (!value) 551 continue; 552 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 553 cur_value == value ? "*" : ""); 554 if (cur_value == value) 555 cur_value_match_level = true; 556 } 557 558 if (!cur_value_match_level) 559 size += sprintf(buf + size, " %uMhz *\n", cur_value); 560 561 break; 562 default: 563 break; 564 } 565 566 return size; 567 } 568 569 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) 570 { 571 enum amd_pm_state_type pm_type; 572 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 573 574 if (!smu_dpm_ctx->dpm_context || 575 !smu_dpm_ctx->dpm_current_power_state) 576 return -EINVAL; 577 578 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) { 579 case SMU_STATE_UI_LABEL_BATTERY: 580 pm_type = POWER_STATE_TYPE_BATTERY; 581 break; 582 case SMU_STATE_UI_LABEL_BALLANCED: 583 pm_type = POWER_STATE_TYPE_BALANCED; 584 break; 585 case SMU_STATE_UI_LABEL_PERFORMANCE: 586 pm_type = POWER_STATE_TYPE_PERFORMANCE; 587 break; 588 default: 589 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT) 590 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 591 else 592 pm_type = POWER_STATE_TYPE_DEFAULT; 593 break; 594 } 595 596 return pm_type; 597 } 598 599 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 600 { 601 int ret = 0; 602 603 if (enable) { 604 /* vcn dpm on is a prerequisite for vcn power gate messages */ 605 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 606 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 607 if (ret) 608 return ret; 609 } 610 } else { 611 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 612 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 613 if (ret) 614 return ret; 615 } 616 } 617 618 return ret; 619 } 620 621 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 622 { 623 int ret = 0; 624 625 if (enable) { 626 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 627 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 628 if (ret) 629 return ret; 630 } 631 } else { 632 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 634 if (ret) 635 return ret; 636 } 637 } 638 639 return ret; 640 } 641 642 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest) 643 { 644 int ret = 0, i = 0; 645 uint32_t min_freq, max_freq, force_freq; 646 enum smu_clk_type clk_type; 647 648 enum smu_clk_type clks[] = { 649 SMU_GFXCLK, 650 SMU_MCLK, 651 SMU_SOCCLK, 652 }; 653 654 for (i = 0; i < ARRAY_SIZE(clks); i++) { 655 clk_type = clks[i]; 656 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 657 if (ret) 658 return ret; 659 660 force_freq = highest ? max_freq : min_freq; 661 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 662 if (ret) 663 return ret; 664 } 665 666 return ret; 667 } 668 669 static int renoir_unforce_dpm_levels(struct smu_context *smu) { 670 671 int ret = 0, i = 0; 672 uint32_t min_freq, max_freq; 673 enum smu_clk_type clk_type; 674 675 struct clk_feature_map { 676 enum smu_clk_type clk_type; 677 uint32_t feature; 678 } clk_feature_map[] = { 679 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, 680 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, 681 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 682 }; 683 684 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 685 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 686 continue; 687 688 clk_type = clk_feature_map[i].clk_type; 689 690 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 691 if (ret) 692 return ret; 693 694 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 695 if (ret) 696 return ret; 697 } 698 699 return ret; 700 } 701 702 /* 703 * This interface get dpm clock table for dc 704 */ 705 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 706 { 707 DpmClocks_t *table = smu->smu_table.clocks_table; 708 int i; 709 710 if (!clock_table || !table) 711 return -EINVAL; 712 713 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { 714 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; 715 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; 716 } 717 718 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 719 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq; 720 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; 721 } 722 723 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 724 clock_table->FClocks[i].Freq = table->FClocks[i].Freq; 725 clock_table->FClocks[i].Vol = table->FClocks[i].Vol; 726 } 727 728 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) { 729 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq; 730 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; 731 } 732 733 return 0; 734 } 735 736 static int renoir_force_clk_levels(struct smu_context *smu, 737 enum smu_clk_type clk_type, uint32_t mask) 738 { 739 740 int ret = 0 ; 741 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 742 743 soft_min_level = mask ? (ffs(mask) - 1) : 0; 744 soft_max_level = mask ? (fls(mask) - 1) : 0; 745 746 switch (clk_type) { 747 case SMU_GFXCLK: 748 case SMU_SCLK: 749 if (soft_min_level > 2 || soft_max_level > 2) { 750 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n"); 751 return -EINVAL; 752 } 753 754 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq); 755 if (ret) 756 return ret; 757 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 758 soft_max_level == 0 ? min_freq : 759 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq, 760 NULL); 761 if (ret) 762 return ret; 763 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 764 soft_min_level == 2 ? max_freq : 765 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq, 766 NULL); 767 if (ret) 768 return ret; 769 break; 770 case SMU_SOCCLK: 771 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 772 if (ret) 773 return ret; 774 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 775 if (ret) 776 return ret; 777 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); 778 if (ret) 779 return ret; 780 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); 781 if (ret) 782 return ret; 783 break; 784 case SMU_MCLK: 785 case SMU_FCLK: 786 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 787 if (ret) 788 return ret; 789 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 790 if (ret) 791 return ret; 792 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); 793 if (ret) 794 return ret; 795 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); 796 if (ret) 797 return ret; 798 break; 799 default: 800 break; 801 } 802 803 return ret; 804 } 805 806 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 807 { 808 int workload_type, ret; 809 uint32_t profile_mode = input[size]; 810 811 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 812 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 813 return -EINVAL; 814 } 815 816 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 817 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 818 return 0; 819 820 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 821 workload_type = smu_cmn_to_asic_specific_index(smu, 822 CMN2ASIC_MAPPING_WORKLOAD, 823 profile_mode); 824 if (workload_type < 0) { 825 /* 826 * TODO: If some case need switch to powersave/default power mode 827 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving. 828 */ 829 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode); 830 return -EINVAL; 831 } 832 833 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 834 1 << workload_type, 835 NULL); 836 if (ret) { 837 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 838 return ret; 839 } 840 841 smu->power_profile_mode = profile_mode; 842 843 return 0; 844 } 845 846 static int renoir_set_peak_clock_by_device(struct smu_context *smu) 847 { 848 int ret = 0; 849 uint32_t sclk_freq = 0, uclk_freq = 0; 850 851 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq); 852 if (ret) 853 return ret; 854 855 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq); 856 if (ret) 857 return ret; 858 859 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq); 860 if (ret) 861 return ret; 862 863 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq); 864 if (ret) 865 return ret; 866 867 return ret; 868 } 869 870 static int renoir_set_performance_level(struct smu_context *smu, 871 enum amd_dpm_forced_level level) 872 { 873 int ret = 0; 874 uint32_t sclk_mask, mclk_mask, soc_mask; 875 876 switch (level) { 877 case AMD_DPM_FORCED_LEVEL_HIGH: 878 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 879 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 880 881 ret = renoir_force_dpm_limit_value(smu, true); 882 break; 883 case AMD_DPM_FORCED_LEVEL_LOW: 884 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 885 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 886 887 ret = renoir_force_dpm_limit_value(smu, false); 888 break; 889 case AMD_DPM_FORCED_LEVEL_AUTO: 890 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 891 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 892 893 ret = renoir_unforce_dpm_levels(smu); 894 break; 895 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 896 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 897 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 898 899 ret = smu_cmn_send_smc_msg_with_param(smu, 900 SMU_MSG_SetHardMinGfxClk, 901 RENOIR_UMD_PSTATE_GFXCLK, 902 NULL); 903 if (ret) 904 return ret; 905 ret = smu_cmn_send_smc_msg_with_param(smu, 906 SMU_MSG_SetHardMinFclkByFreq, 907 RENOIR_UMD_PSTATE_FCLK, 908 NULL); 909 if (ret) 910 return ret; 911 ret = smu_cmn_send_smc_msg_with_param(smu, 912 SMU_MSG_SetHardMinSocclkByFreq, 913 RENOIR_UMD_PSTATE_SOCCLK, 914 NULL); 915 if (ret) 916 return ret; 917 ret = smu_cmn_send_smc_msg_with_param(smu, 918 SMU_MSG_SetHardMinVcn, 919 RENOIR_UMD_PSTATE_VCNCLK, 920 NULL); 921 if (ret) 922 return ret; 923 924 ret = smu_cmn_send_smc_msg_with_param(smu, 925 SMU_MSG_SetSoftMaxGfxClk, 926 RENOIR_UMD_PSTATE_GFXCLK, 927 NULL); 928 if (ret) 929 return ret; 930 ret = smu_cmn_send_smc_msg_with_param(smu, 931 SMU_MSG_SetSoftMaxFclkByFreq, 932 RENOIR_UMD_PSTATE_FCLK, 933 NULL); 934 if (ret) 935 return ret; 936 ret = smu_cmn_send_smc_msg_with_param(smu, 937 SMU_MSG_SetSoftMaxSocclkByFreq, 938 RENOIR_UMD_PSTATE_SOCCLK, 939 NULL); 940 if (ret) 941 return ret; 942 ret = smu_cmn_send_smc_msg_with_param(smu, 943 SMU_MSG_SetSoftMaxVcn, 944 RENOIR_UMD_PSTATE_VCNCLK, 945 NULL); 946 if (ret) 947 return ret; 948 break; 949 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 950 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 951 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 952 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 953 954 ret = renoir_get_profiling_clk_mask(smu, level, 955 &sclk_mask, 956 &mclk_mask, 957 &soc_mask); 958 if (ret) 959 return ret; 960 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); 961 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 962 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 963 break; 964 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 965 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 966 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 967 968 ret = renoir_set_peak_clock_by_device(smu); 969 break; 970 case AMD_DPM_FORCED_LEVEL_MANUAL: 971 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 972 default: 973 break; 974 } 975 return ret; 976 } 977 978 /* save watermark settings into pplib smu structure, 979 * also pass data to smu controller 980 */ 981 static int renoir_set_watermarks_table( 982 struct smu_context *smu, 983 struct pp_smu_wm_range_sets *clock_ranges) 984 { 985 Watermarks_t *table = smu->smu_table.watermarks_table; 986 int ret = 0; 987 int i; 988 989 if (clock_ranges) { 990 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 991 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 992 return -EINVAL; 993 994 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/ 995 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 996 table->WatermarkRow[WM_DCFCLK][i].MinClock = 997 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 998 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 999 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1000 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1001 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1002 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1003 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1004 1005 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1006 clock_ranges->reader_wm_sets[i].wm_inst; 1007 table->WatermarkRow[WM_DCFCLK][i].WmType = 1008 clock_ranges->reader_wm_sets[i].wm_type; 1009 } 1010 1011 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1012 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1013 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1014 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1015 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1016 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1017 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1018 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1019 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1020 1021 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1022 clock_ranges->writer_wm_sets[i].wm_inst; 1023 table->WatermarkRow[WM_SOCCLK][i].WmType = 1024 clock_ranges->writer_wm_sets[i].wm_type; 1025 } 1026 1027 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1028 } 1029 1030 /* pass data to smu controller */ 1031 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1032 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1033 ret = smu_cmn_write_watermarks_table(smu); 1034 if (ret) { 1035 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1036 return ret; 1037 } 1038 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1039 } 1040 1041 return 0; 1042 } 1043 1044 static int renoir_get_power_profile_mode(struct smu_context *smu, 1045 char *buf) 1046 { 1047 static const char *profile_name[] = { 1048 "BOOTUP_DEFAULT", 1049 "3D_FULL_SCREEN", 1050 "POWER_SAVING", 1051 "VIDEO", 1052 "VR", 1053 "COMPUTE", 1054 "CUSTOM"}; 1055 uint32_t i, size = 0; 1056 int16_t workload_type = 0; 1057 1058 if (!buf) 1059 return -EINVAL; 1060 1061 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1062 /* 1063 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1064 * Not all profile modes are supported on arcturus. 1065 */ 1066 workload_type = smu_cmn_to_asic_specific_index(smu, 1067 CMN2ASIC_MAPPING_WORKLOAD, 1068 i); 1069 if (workload_type < 0) 1070 continue; 1071 1072 size += sprintf(buf + size, "%2d %14s%s\n", 1073 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1074 } 1075 1076 return size; 1077 } 1078 1079 static int renoir_get_smu_metrics_data(struct smu_context *smu, 1080 MetricsMember_t member, 1081 uint32_t *value) 1082 { 1083 struct smu_table_context *smu_table = &smu->smu_table; 1084 1085 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 1086 int ret = 0; 1087 1088 mutex_lock(&smu->metrics_lock); 1089 1090 ret = smu_cmn_get_metrics_table_locked(smu, 1091 NULL, 1092 false); 1093 if (ret) { 1094 mutex_unlock(&smu->metrics_lock); 1095 return ret; 1096 } 1097 1098 switch (member) { 1099 case METRICS_AVERAGE_GFXCLK: 1100 *value = metrics->ClockFrequency[CLOCK_GFXCLK]; 1101 break; 1102 case METRICS_AVERAGE_SOCCLK: 1103 *value = metrics->ClockFrequency[CLOCK_SOCCLK]; 1104 break; 1105 case METRICS_AVERAGE_UCLK: 1106 *value = metrics->ClockFrequency[CLOCK_FCLK]; 1107 break; 1108 case METRICS_AVERAGE_GFXACTIVITY: 1109 *value = metrics->AverageGfxActivity / 100; 1110 break; 1111 case METRICS_AVERAGE_VCNACTIVITY: 1112 *value = metrics->AverageUvdActivity / 100; 1113 break; 1114 case METRICS_AVERAGE_SOCKETPOWER: 1115 *value = (metrics->CurrentSocketPower << 8) / 1000; 1116 break; 1117 case METRICS_TEMPERATURE_EDGE: 1118 *value = (metrics->GfxTemperature / 100) * 1119 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1120 break; 1121 case METRICS_TEMPERATURE_HOTSPOT: 1122 *value = (metrics->SocTemperature / 100) * 1123 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1124 break; 1125 case METRICS_THROTTLER_STATUS: 1126 *value = metrics->ThrottlerStatus; 1127 break; 1128 case METRICS_VOLTAGE_VDDGFX: 1129 *value = metrics->Voltage[0]; 1130 break; 1131 case METRICS_VOLTAGE_VDDSOC: 1132 *value = metrics->Voltage[1]; 1133 break; 1134 default: 1135 *value = UINT_MAX; 1136 break; 1137 } 1138 1139 mutex_unlock(&smu->metrics_lock); 1140 1141 return ret; 1142 } 1143 1144 static int renoir_read_sensor(struct smu_context *smu, 1145 enum amd_pp_sensors sensor, 1146 void *data, uint32_t *size) 1147 { 1148 int ret = 0; 1149 1150 if (!data || !size) 1151 return -EINVAL; 1152 1153 mutex_lock(&smu->sensor_lock); 1154 switch (sensor) { 1155 case AMDGPU_PP_SENSOR_GPU_LOAD: 1156 ret = renoir_get_smu_metrics_data(smu, 1157 METRICS_AVERAGE_GFXACTIVITY, 1158 (uint32_t *)data); 1159 *size = 4; 1160 break; 1161 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1162 ret = renoir_get_smu_metrics_data(smu, 1163 METRICS_TEMPERATURE_EDGE, 1164 (uint32_t *)data); 1165 *size = 4; 1166 break; 1167 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1168 ret = renoir_get_smu_metrics_data(smu, 1169 METRICS_TEMPERATURE_HOTSPOT, 1170 (uint32_t *)data); 1171 *size = 4; 1172 break; 1173 case AMDGPU_PP_SENSOR_GFX_MCLK: 1174 ret = renoir_get_smu_metrics_data(smu, 1175 METRICS_AVERAGE_UCLK, 1176 (uint32_t *)data); 1177 *(uint32_t *)data *= 100; 1178 *size = 4; 1179 break; 1180 case AMDGPU_PP_SENSOR_GFX_SCLK: 1181 ret = renoir_get_smu_metrics_data(smu, 1182 METRICS_AVERAGE_GFXCLK, 1183 (uint32_t *)data); 1184 *(uint32_t *)data *= 100; 1185 *size = 4; 1186 break; 1187 case AMDGPU_PP_SENSOR_VDDGFX: 1188 ret = renoir_get_smu_metrics_data(smu, 1189 METRICS_VOLTAGE_VDDGFX, 1190 (uint32_t *)data); 1191 *size = 4; 1192 break; 1193 case AMDGPU_PP_SENSOR_VDDNB: 1194 ret = renoir_get_smu_metrics_data(smu, 1195 METRICS_VOLTAGE_VDDSOC, 1196 (uint32_t *)data); 1197 *size = 4; 1198 break; 1199 case AMDGPU_PP_SENSOR_GPU_POWER: 1200 ret = renoir_get_smu_metrics_data(smu, 1201 METRICS_AVERAGE_SOCKETPOWER, 1202 (uint32_t *)data); 1203 *size = 4; 1204 break; 1205 default: 1206 ret = -EOPNOTSUPP; 1207 break; 1208 } 1209 mutex_unlock(&smu->sensor_lock); 1210 1211 return ret; 1212 } 1213 1214 static bool renoir_is_dpm_running(struct smu_context *smu) 1215 { 1216 struct amdgpu_device *adev = smu->adev; 1217 1218 /* 1219 * Until now, the pmfw hasn't exported the interface of SMU 1220 * feature mask to APU SKU so just force on all the feature 1221 * at early initial stage. 1222 */ 1223 if (adev->in_suspend) 1224 return false; 1225 else 1226 return true; 1227 1228 } 1229 1230 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, 1231 void **table) 1232 { 1233 struct smu_table_context *smu_table = &smu->smu_table; 1234 struct gpu_metrics_v2_1 *gpu_metrics = 1235 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; 1236 SmuMetrics_t metrics; 1237 int ret = 0; 1238 1239 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1240 if (ret) 1241 return ret; 1242 1243 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); 1244 1245 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1246 gpu_metrics->temperature_soc = metrics.SocTemperature; 1247 memcpy(&gpu_metrics->temperature_core[0], 1248 &metrics.CoreTemperature[0], 1249 sizeof(uint16_t) * 8); 1250 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1251 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1252 1253 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1254 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity; 1255 1256 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1257 gpu_metrics->average_cpu_power = metrics.Power[0]; 1258 gpu_metrics->average_soc_power = metrics.Power[1]; 1259 memcpy(&gpu_metrics->average_core_power[0], 1260 &metrics.CorePower[0], 1261 sizeof(uint16_t) * 8); 1262 1263 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1264 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1265 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency; 1266 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency; 1267 1268 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK]; 1269 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK]; 1270 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK]; 1271 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK]; 1272 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK]; 1273 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK]; 1274 memcpy(&gpu_metrics->current_coreclk[0], 1275 &metrics.CoreFrequency[0], 1276 sizeof(uint16_t) * 8); 1277 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1278 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1279 1280 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1281 1282 gpu_metrics->fan_pwm = metrics.FanPwm; 1283 1284 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1285 1286 *table = (void *)gpu_metrics; 1287 1288 return sizeof(struct gpu_metrics_v2_1); 1289 } 1290 1291 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) 1292 { 1293 1294 return 0; 1295 } 1296 1297 static const struct pptable_funcs renoir_ppt_funcs = { 1298 .set_power_state = NULL, 1299 .print_clk_levels = renoir_print_clk_levels, 1300 .get_current_power_state = renoir_get_current_power_state, 1301 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable, 1302 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable, 1303 .force_clk_levels = renoir_force_clk_levels, 1304 .set_power_profile_mode = renoir_set_power_profile_mode, 1305 .set_performance_level = renoir_set_performance_level, 1306 .get_dpm_clock_table = renoir_get_dpm_clock_table, 1307 .set_watermarks_table = renoir_set_watermarks_table, 1308 .get_power_profile_mode = renoir_get_power_profile_mode, 1309 .read_sensor = renoir_read_sensor, 1310 .check_fw_status = smu_v12_0_check_fw_status, 1311 .check_fw_version = smu_v12_0_check_fw_version, 1312 .powergate_sdma = smu_v12_0_powergate_sdma, 1313 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1314 .send_smc_msg = smu_cmn_send_smc_msg, 1315 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, 1316 .gfx_off_control = smu_v12_0_gfx_off_control, 1317 .get_gfx_off_status = smu_v12_0_get_gfxoff_status, 1318 .init_smc_tables = renoir_init_smc_tables, 1319 .fini_smc_tables = smu_v12_0_fini_smc_tables, 1320 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables, 1321 .get_enabled_mask = smu_cmn_get_enabled_mask, 1322 .feature_is_enabled = smu_cmn_feature_is_enabled, 1323 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1324 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq, 1325 .mode2_reset = smu_v12_0_mode2_reset, 1326 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, 1327 .set_driver_table_location = smu_v12_0_set_driver_table_location, 1328 .is_dpm_running = renoir_is_dpm_running, 1329 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1330 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1331 .get_gpu_metrics = renoir_get_gpu_metrics, 1332 .gfx_state_change_set = renoir_gfx_state_change_set, 1333 .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters, 1334 .od_edit_dpm_table = renoir_od_edit_dpm_table, 1335 .get_vbios_bootup_values = smu_v12_0_get_vbios_bootup_values, 1336 }; 1337 1338 void renoir_set_ppt_funcs(struct smu_context *smu) 1339 { 1340 smu->ppt_funcs = &renoir_ppt_funcs; 1341 smu->message_map = renoir_message_map; 1342 smu->clock_map = renoir_clk_map; 1343 smu->table_map = renoir_table_map; 1344 smu->workload_map = renoir_workload_map; 1345 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; 1346 smu->is_apu = true; 1347 } 1348