1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v12_0_ppsmc.h" 29 #include "smu12_driver_if.h" 30 #include "smu_v12_0.h" 31 #include "renoir_ppt.h" 32 #include "smu_cmn.h" 33 34 /* 35 * DO NOT use these for err/warn/info/debug messages. 36 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 37 * They are more MGPU friendly. 38 */ 39 #undef pr_err 40 #undef pr_warn 41 #undef pr_info 42 #undef pr_debug 43 44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { 45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1), 49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1), 50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1), 51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1), 56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1), 57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1), 58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 59 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1), 60 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1), 61 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1), 62 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1), 63 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1), 64 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1), 65 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1), 66 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 67 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 68 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 69 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 70 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 71 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1), 72 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1), 73 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 74 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1), 75 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1), 76 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1), 77 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1), 78 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1), 79 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1), 80 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 81 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1), 82 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 83 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 84 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1), 85 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1), 86 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1), 87 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1), 88 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 89 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 90 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 91 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 92 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 93 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1), 94 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1), 95 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1), 96 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 97 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1), 98 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1), 99 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 100 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 101 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1), 102 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1), 103 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 104 }; 105 106 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { 107 CLK_MAP(GFXCLK, CLOCK_GFXCLK), 108 CLK_MAP(SCLK, CLOCK_GFXCLK), 109 CLK_MAP(SOCCLK, CLOCK_SOCCLK), 110 CLK_MAP(UCLK, CLOCK_FCLK), 111 CLK_MAP(MCLK, CLOCK_FCLK), 112 }; 113 114 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { 115 TAB_MAP_VALID(WATERMARKS), 116 TAB_MAP_INVALID(CUSTOM_DPM), 117 TAB_MAP_VALID(DPMCLOCKS), 118 TAB_MAP_VALID(SMU_METRICS), 119 }; 120 121 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 122 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 123 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 127 }; 128 129 static int renoir_init_smc_tables(struct smu_context *smu) 130 { 131 struct smu_table_context *smu_table = &smu->smu_table; 132 struct smu_table *tables = smu_table->tables; 133 134 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 135 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 136 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 137 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 138 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 139 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 140 141 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 142 if (!smu_table->clocks_table) 143 goto err0_out; 144 145 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 146 if (!smu_table->metrics_table) 147 goto err1_out; 148 smu_table->metrics_time = 0; 149 150 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 151 if (!smu_table->watermarks_table) 152 goto err2_out; 153 154 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); 155 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 156 if (!smu_table->gpu_metrics_table) 157 goto err3_out; 158 159 return 0; 160 161 err3_out: 162 kfree(smu_table->watermarks_table); 163 err2_out: 164 kfree(smu_table->metrics_table); 165 err1_out: 166 kfree(smu_table->clocks_table); 167 err0_out: 168 return -ENOMEM; 169 } 170 171 /* 172 * This interface just for getting uclk ultimate freq and should't introduce 173 * other likewise function result in overmuch callback. 174 */ 175 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 176 uint32_t dpm_level, uint32_t *freq) 177 { 178 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 179 180 if (!clk_table || clk_type >= SMU_CLK_COUNT) 181 return -EINVAL; 182 183 switch (clk_type) { 184 case SMU_SOCCLK: 185 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) 186 return -EINVAL; 187 *freq = clk_table->SocClocks[dpm_level].Freq; 188 break; 189 case SMU_UCLK: 190 case SMU_MCLK: 191 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 192 return -EINVAL; 193 *freq = clk_table->FClocks[dpm_level].Freq; 194 break; 195 case SMU_DCEFCLK: 196 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) 197 return -EINVAL; 198 *freq = clk_table->DcfClocks[dpm_level].Freq; 199 break; 200 case SMU_FCLK: 201 if (dpm_level >= NUM_FCLK_DPM_LEVELS) 202 return -EINVAL; 203 *freq = clk_table->FClocks[dpm_level].Freq; 204 break; 205 default: 206 return -EINVAL; 207 } 208 209 return 0; 210 } 211 212 static int renoir_get_profiling_clk_mask(struct smu_context *smu, 213 enum amd_dpm_forced_level level, 214 uint32_t *sclk_mask, 215 uint32_t *mclk_mask, 216 uint32_t *soc_mask) 217 { 218 219 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 220 if (sclk_mask) 221 *sclk_mask = 0; 222 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 223 if (mclk_mask) 224 /* mclk levels are in reverse order */ 225 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; 226 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 227 if(sclk_mask) 228 /* The sclk as gfxclk and has three level about max/min/current */ 229 *sclk_mask = 3 - 1; 230 231 if(mclk_mask) 232 /* mclk levels are in reverse order */ 233 *mclk_mask = 0; 234 235 if(soc_mask) 236 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; 237 } 238 239 return 0; 240 } 241 242 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu, 243 enum smu_clk_type clk_type, 244 uint32_t *min, 245 uint32_t *max) 246 { 247 int ret = 0; 248 uint32_t mclk_mask, soc_mask; 249 uint32_t clock_limit; 250 251 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 252 switch (clk_type) { 253 case SMU_MCLK: 254 case SMU_UCLK: 255 clock_limit = smu->smu_table.boot_values.uclk; 256 break; 257 case SMU_GFXCLK: 258 case SMU_SCLK: 259 clock_limit = smu->smu_table.boot_values.gfxclk; 260 break; 261 case SMU_SOCCLK: 262 clock_limit = smu->smu_table.boot_values.socclk; 263 break; 264 default: 265 clock_limit = 0; 266 break; 267 } 268 269 /* clock in Mhz unit */ 270 if (min) 271 *min = clock_limit / 100; 272 if (max) 273 *max = clock_limit / 100; 274 275 return 0; 276 } 277 278 if (max) { 279 ret = renoir_get_profiling_clk_mask(smu, 280 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 281 NULL, 282 &mclk_mask, 283 &soc_mask); 284 if (ret) 285 goto failed; 286 287 switch (clk_type) { 288 case SMU_GFXCLK: 289 case SMU_SCLK: 290 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max); 291 if (ret) { 292 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n"); 293 goto failed; 294 } 295 break; 296 case SMU_UCLK: 297 case SMU_FCLK: 298 case SMU_MCLK: 299 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 300 if (ret) 301 goto failed; 302 break; 303 case SMU_SOCCLK: 304 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 305 if (ret) 306 goto failed; 307 break; 308 default: 309 ret = -EINVAL; 310 goto failed; 311 } 312 } 313 314 if (min) { 315 switch (clk_type) { 316 case SMU_GFXCLK: 317 case SMU_SCLK: 318 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min); 319 if (ret) { 320 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n"); 321 goto failed; 322 } 323 break; 324 case SMU_UCLK: 325 case SMU_FCLK: 326 case SMU_MCLK: 327 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min); 328 if (ret) 329 goto failed; 330 break; 331 case SMU_SOCCLK: 332 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min); 333 if (ret) 334 goto failed; 335 break; 336 default: 337 ret = -EINVAL; 338 goto failed; 339 } 340 } 341 failed: 342 return ret; 343 } 344 345 static int renoir_od_edit_dpm_table(struct smu_context *smu, 346 enum PP_OD_DPM_TABLE_COMMAND type, 347 long input[], uint32_t size) 348 { 349 int ret = 0; 350 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 351 352 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 353 dev_warn(smu->adev->dev, "Fine grain is not enabled!\n"); 354 return -EINVAL; 355 } 356 357 switch (type) { 358 case PP_OD_EDIT_SCLK_VDDC_TABLE: 359 if (size != 2) { 360 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 361 return -EINVAL; 362 } 363 364 if (input[0] == 0) { 365 if (input[1] < smu->gfx_default_hard_min_freq) { 366 dev_warn(smu->adev->dev, 367 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 368 input[1], smu->gfx_default_hard_min_freq); 369 return -EINVAL; 370 } 371 smu->gfx_actual_hard_min_freq = input[1]; 372 } else if (input[0] == 1) { 373 if (input[1] > smu->gfx_default_soft_max_freq) { 374 dev_warn(smu->adev->dev, 375 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 376 input[1], smu->gfx_default_soft_max_freq); 377 return -EINVAL; 378 } 379 smu->gfx_actual_soft_max_freq = input[1]; 380 } else { 381 return -EINVAL; 382 } 383 break; 384 case PP_OD_RESTORE_DEFAULT_TABLE: 385 if (size != 0) { 386 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 387 return -EINVAL; 388 } 389 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 390 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 391 392 ret = smu_cmn_send_smc_msg_with_param(smu, 393 SMU_MSG_SetHardMinGfxClk, 394 smu->gfx_actual_hard_min_freq, 395 NULL); 396 if (ret) { 397 dev_err(smu->adev->dev, "Restore the default hard min sclk failed!"); 398 return ret; 399 } 400 401 ret = smu_cmn_send_smc_msg_with_param(smu, 402 SMU_MSG_SetSoftMaxGfxClk, 403 smu->gfx_actual_soft_max_freq, 404 NULL); 405 if (ret) { 406 dev_err(smu->adev->dev, "Restore the default soft max sclk failed!"); 407 return ret; 408 } 409 break; 410 case PP_OD_COMMIT_DPM_TABLE: 411 if (size != 0) { 412 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 413 return -EINVAL; 414 } else { 415 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 416 dev_err(smu->adev->dev, 417 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 418 smu->gfx_actual_hard_min_freq, 419 smu->gfx_actual_soft_max_freq); 420 return -EINVAL; 421 } 422 423 ret = smu_cmn_send_smc_msg_with_param(smu, 424 SMU_MSG_SetHardMinGfxClk, 425 smu->gfx_actual_hard_min_freq, 426 NULL); 427 if (ret) { 428 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 429 return ret; 430 } 431 432 ret = smu_cmn_send_smc_msg_with_param(smu, 433 SMU_MSG_SetSoftMaxGfxClk, 434 smu->gfx_actual_soft_max_freq, 435 NULL); 436 if (ret) { 437 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 438 return ret; 439 } 440 } 441 break; 442 default: 443 return -ENOSYS; 444 } 445 446 return ret; 447 } 448 449 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 450 { 451 uint32_t min = 0, max = 0; 452 uint32_t ret = 0; 453 454 ret = smu_cmn_send_smc_msg_with_param(smu, 455 SMU_MSG_GetMinGfxclkFrequency, 456 0, &min); 457 if (ret) 458 return ret; 459 ret = smu_cmn_send_smc_msg_with_param(smu, 460 SMU_MSG_GetMaxGfxclkFrequency, 461 0, &max); 462 if (ret) 463 return ret; 464 465 smu->gfx_default_hard_min_freq = min; 466 smu->gfx_default_soft_max_freq = max; 467 smu->gfx_actual_hard_min_freq = 0; 468 smu->gfx_actual_soft_max_freq = 0; 469 470 return 0; 471 } 472 473 static int renoir_print_clk_levels(struct smu_context *smu, 474 enum smu_clk_type clk_type, char *buf) 475 { 476 int i, size = 0, ret = 0; 477 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; 478 SmuMetrics_t metrics; 479 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 480 bool cur_value_match_level = false; 481 482 memset(&metrics, 0, sizeof(metrics)); 483 484 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 485 if (ret) 486 return ret; 487 488 switch (clk_type) { 489 case SMU_OD_RANGE: 490 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 491 ret = smu_cmn_send_smc_msg_with_param(smu, 492 SMU_MSG_GetMinGfxclkFrequency, 493 0, &min); 494 if (ret) 495 return ret; 496 ret = smu_cmn_send_smc_msg_with_param(smu, 497 SMU_MSG_GetMaxGfxclkFrequency, 498 0, &max); 499 if (ret) 500 return ret; 501 size += sprintf(buf + size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max); 502 } 503 break; 504 case SMU_OD_SCLK: 505 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 506 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 507 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 508 size += sprintf(buf + size, "OD_SCLK\n"); 509 size += sprintf(buf + size, "0:%10uMhz\n", min); 510 size += sprintf(buf + size, "1:%10uMhz\n", max); 511 } 512 break; 513 case SMU_GFXCLK: 514 case SMU_SCLK: 515 /* retirve table returned paramters unit is MHz */ 516 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; 517 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max); 518 if (!ret) { 519 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 520 if (cur_value == max) 521 i = 2; 522 else if (cur_value == min) 523 i = 0; 524 else 525 i = 1; 526 527 size += sprintf(buf + size, "0: %uMhz %s\n", min, 528 i == 0 ? "*" : ""); 529 size += sprintf(buf + size, "1: %uMhz %s\n", 530 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, 531 i == 1 ? "*" : ""); 532 size += sprintf(buf + size, "2: %uMhz %s\n", max, 533 i == 2 ? "*" : ""); 534 } 535 return size; 536 case SMU_SOCCLK: 537 count = NUM_SOCCLK_DPM_LEVELS; 538 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; 539 break; 540 case SMU_MCLK: 541 count = NUM_MEMCLK_DPM_LEVELS; 542 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 543 break; 544 case SMU_DCEFCLK: 545 count = NUM_DCFCLK_DPM_LEVELS; 546 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK]; 547 break; 548 case SMU_FCLK: 549 count = NUM_FCLK_DPM_LEVELS; 550 cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 551 break; 552 default: 553 break; 554 } 555 556 switch (clk_type) { 557 case SMU_GFXCLK: 558 case SMU_SCLK: 559 case SMU_SOCCLK: 560 case SMU_MCLK: 561 case SMU_DCEFCLK: 562 case SMU_FCLK: 563 for (i = 0; i < count; i++) { 564 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); 565 if (ret) 566 return ret; 567 if (!value) 568 continue; 569 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 570 cur_value == value ? "*" : ""); 571 if (cur_value == value) 572 cur_value_match_level = true; 573 } 574 575 if (!cur_value_match_level) 576 size += sprintf(buf + size, " %uMhz *\n", cur_value); 577 578 break; 579 default: 580 break; 581 } 582 583 return size; 584 } 585 586 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) 587 { 588 enum amd_pm_state_type pm_type; 589 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 590 591 if (!smu_dpm_ctx->dpm_context || 592 !smu_dpm_ctx->dpm_current_power_state) 593 return -EINVAL; 594 595 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) { 596 case SMU_STATE_UI_LABEL_BATTERY: 597 pm_type = POWER_STATE_TYPE_BATTERY; 598 break; 599 case SMU_STATE_UI_LABEL_BALLANCED: 600 pm_type = POWER_STATE_TYPE_BALANCED; 601 break; 602 case SMU_STATE_UI_LABEL_PERFORMANCE: 603 pm_type = POWER_STATE_TYPE_PERFORMANCE; 604 break; 605 default: 606 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT) 607 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 608 else 609 pm_type = POWER_STATE_TYPE_DEFAULT; 610 break; 611 } 612 613 return pm_type; 614 } 615 616 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 617 { 618 int ret = 0; 619 620 if (enable) { 621 /* vcn dpm on is a prerequisite for vcn power gate messages */ 622 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 623 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 624 if (ret) 625 return ret; 626 } 627 } else { 628 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 629 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 630 if (ret) 631 return ret; 632 } 633 } 634 635 return ret; 636 } 637 638 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 639 { 640 int ret = 0; 641 642 if (enable) { 643 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 644 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 645 if (ret) 646 return ret; 647 } 648 } else { 649 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 650 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 651 if (ret) 652 return ret; 653 } 654 } 655 656 return ret; 657 } 658 659 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest) 660 { 661 int ret = 0, i = 0; 662 uint32_t min_freq, max_freq, force_freq; 663 enum smu_clk_type clk_type; 664 665 enum smu_clk_type clks[] = { 666 SMU_GFXCLK, 667 SMU_MCLK, 668 SMU_SOCCLK, 669 }; 670 671 for (i = 0; i < ARRAY_SIZE(clks); i++) { 672 clk_type = clks[i]; 673 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 674 if (ret) 675 return ret; 676 677 force_freq = highest ? max_freq : min_freq; 678 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 679 if (ret) 680 return ret; 681 } 682 683 return ret; 684 } 685 686 static int renoir_unforce_dpm_levels(struct smu_context *smu) { 687 688 int ret = 0, i = 0; 689 uint32_t min_freq, max_freq; 690 enum smu_clk_type clk_type; 691 692 struct clk_feature_map { 693 enum smu_clk_type clk_type; 694 uint32_t feature; 695 } clk_feature_map[] = { 696 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, 697 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, 698 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 699 }; 700 701 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 702 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 703 continue; 704 705 clk_type = clk_feature_map[i].clk_type; 706 707 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 708 if (ret) 709 return ret; 710 711 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 712 if (ret) 713 return ret; 714 } 715 716 return ret; 717 } 718 719 /* 720 * This interface get dpm clock table for dc 721 */ 722 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 723 { 724 DpmClocks_t *table = smu->smu_table.clocks_table; 725 int i; 726 727 if (!clock_table || !table) 728 return -EINVAL; 729 730 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { 731 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; 732 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; 733 } 734 735 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 736 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq; 737 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; 738 } 739 740 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 741 clock_table->FClocks[i].Freq = table->FClocks[i].Freq; 742 clock_table->FClocks[i].Vol = table->FClocks[i].Vol; 743 } 744 745 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) { 746 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq; 747 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; 748 } 749 750 return 0; 751 } 752 753 static int renoir_force_clk_levels(struct smu_context *smu, 754 enum smu_clk_type clk_type, uint32_t mask) 755 { 756 757 int ret = 0 ; 758 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 759 760 soft_min_level = mask ? (ffs(mask) - 1) : 0; 761 soft_max_level = mask ? (fls(mask) - 1) : 0; 762 763 switch (clk_type) { 764 case SMU_GFXCLK: 765 case SMU_SCLK: 766 if (soft_min_level > 2 || soft_max_level > 2) { 767 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n"); 768 return -EINVAL; 769 } 770 771 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq); 772 if (ret) 773 return ret; 774 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 775 soft_max_level == 0 ? min_freq : 776 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq, 777 NULL); 778 if (ret) 779 return ret; 780 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 781 soft_min_level == 2 ? max_freq : 782 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq, 783 NULL); 784 if (ret) 785 return ret; 786 break; 787 case SMU_SOCCLK: 788 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 789 if (ret) 790 return ret; 791 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 792 if (ret) 793 return ret; 794 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); 795 if (ret) 796 return ret; 797 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); 798 if (ret) 799 return ret; 800 break; 801 case SMU_MCLK: 802 case SMU_FCLK: 803 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 804 if (ret) 805 return ret; 806 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 807 if (ret) 808 return ret; 809 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); 810 if (ret) 811 return ret; 812 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); 813 if (ret) 814 return ret; 815 break; 816 default: 817 break; 818 } 819 820 return ret; 821 } 822 823 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 824 { 825 int workload_type, ret; 826 uint32_t profile_mode = input[size]; 827 828 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 829 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 830 return -EINVAL; 831 } 832 833 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 834 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 835 return 0; 836 837 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 838 workload_type = smu_cmn_to_asic_specific_index(smu, 839 CMN2ASIC_MAPPING_WORKLOAD, 840 profile_mode); 841 if (workload_type < 0) { 842 /* 843 * TODO: If some case need switch to powersave/default power mode 844 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving. 845 */ 846 dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode); 847 return -EINVAL; 848 } 849 850 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 851 1 << workload_type, 852 NULL); 853 if (ret) { 854 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 855 return ret; 856 } 857 858 smu->power_profile_mode = profile_mode; 859 860 return 0; 861 } 862 863 static int renoir_set_peak_clock_by_device(struct smu_context *smu) 864 { 865 int ret = 0; 866 uint32_t sclk_freq = 0, uclk_freq = 0; 867 868 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq); 869 if (ret) 870 return ret; 871 872 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq); 873 if (ret) 874 return ret; 875 876 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq); 877 if (ret) 878 return ret; 879 880 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq); 881 if (ret) 882 return ret; 883 884 return ret; 885 } 886 887 static int renoir_set_performance_level(struct smu_context *smu, 888 enum amd_dpm_forced_level level) 889 { 890 int ret = 0; 891 uint32_t sclk_mask, mclk_mask, soc_mask; 892 893 switch (level) { 894 case AMD_DPM_FORCED_LEVEL_HIGH: 895 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 896 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 897 898 ret = renoir_force_dpm_limit_value(smu, true); 899 break; 900 case AMD_DPM_FORCED_LEVEL_LOW: 901 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 902 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 903 904 ret = renoir_force_dpm_limit_value(smu, false); 905 break; 906 case AMD_DPM_FORCED_LEVEL_AUTO: 907 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 908 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 909 910 ret = renoir_unforce_dpm_levels(smu); 911 break; 912 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 913 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 914 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 915 916 ret = smu_cmn_send_smc_msg_with_param(smu, 917 SMU_MSG_SetHardMinGfxClk, 918 RENOIR_UMD_PSTATE_GFXCLK, 919 NULL); 920 if (ret) 921 return ret; 922 ret = smu_cmn_send_smc_msg_with_param(smu, 923 SMU_MSG_SetHardMinFclkByFreq, 924 RENOIR_UMD_PSTATE_FCLK, 925 NULL); 926 if (ret) 927 return ret; 928 ret = smu_cmn_send_smc_msg_with_param(smu, 929 SMU_MSG_SetHardMinSocclkByFreq, 930 RENOIR_UMD_PSTATE_SOCCLK, 931 NULL); 932 if (ret) 933 return ret; 934 ret = smu_cmn_send_smc_msg_with_param(smu, 935 SMU_MSG_SetHardMinVcn, 936 RENOIR_UMD_PSTATE_VCNCLK, 937 NULL); 938 if (ret) 939 return ret; 940 941 ret = smu_cmn_send_smc_msg_with_param(smu, 942 SMU_MSG_SetSoftMaxGfxClk, 943 RENOIR_UMD_PSTATE_GFXCLK, 944 NULL); 945 if (ret) 946 return ret; 947 ret = smu_cmn_send_smc_msg_with_param(smu, 948 SMU_MSG_SetSoftMaxFclkByFreq, 949 RENOIR_UMD_PSTATE_FCLK, 950 NULL); 951 if (ret) 952 return ret; 953 ret = smu_cmn_send_smc_msg_with_param(smu, 954 SMU_MSG_SetSoftMaxSocclkByFreq, 955 RENOIR_UMD_PSTATE_SOCCLK, 956 NULL); 957 if (ret) 958 return ret; 959 ret = smu_cmn_send_smc_msg_with_param(smu, 960 SMU_MSG_SetSoftMaxVcn, 961 RENOIR_UMD_PSTATE_VCNCLK, 962 NULL); 963 if (ret) 964 return ret; 965 break; 966 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 967 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 968 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 969 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 970 971 ret = renoir_get_profiling_clk_mask(smu, level, 972 &sclk_mask, 973 &mclk_mask, 974 &soc_mask); 975 if (ret) 976 return ret; 977 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); 978 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 979 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 980 break; 981 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 982 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 983 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 984 985 ret = renoir_set_peak_clock_by_device(smu); 986 break; 987 case AMD_DPM_FORCED_LEVEL_MANUAL: 988 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 989 default: 990 break; 991 } 992 return ret; 993 } 994 995 /* save watermark settings into pplib smu structure, 996 * also pass data to smu controller 997 */ 998 static int renoir_set_watermarks_table( 999 struct smu_context *smu, 1000 struct pp_smu_wm_range_sets *clock_ranges) 1001 { 1002 Watermarks_t *table = smu->smu_table.watermarks_table; 1003 int ret = 0; 1004 int i; 1005 1006 if (clock_ranges) { 1007 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1008 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1009 return -EINVAL; 1010 1011 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/ 1012 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1013 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1014 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1015 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1016 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1017 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1018 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1019 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1020 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1021 1022 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1023 clock_ranges->reader_wm_sets[i].wm_inst; 1024 table->WatermarkRow[WM_DCFCLK][i].WmType = 1025 clock_ranges->reader_wm_sets[i].wm_type; 1026 } 1027 1028 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1029 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1030 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1031 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1032 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1033 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1034 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1035 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1036 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1037 1038 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1039 clock_ranges->writer_wm_sets[i].wm_inst; 1040 table->WatermarkRow[WM_SOCCLK][i].WmType = 1041 clock_ranges->writer_wm_sets[i].wm_type; 1042 } 1043 1044 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1045 } 1046 1047 /* pass data to smu controller */ 1048 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1049 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1050 ret = smu_cmn_write_watermarks_table(smu); 1051 if (ret) { 1052 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1053 return ret; 1054 } 1055 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1056 } 1057 1058 return 0; 1059 } 1060 1061 static int renoir_get_power_profile_mode(struct smu_context *smu, 1062 char *buf) 1063 { 1064 static const char *profile_name[] = { 1065 "BOOTUP_DEFAULT", 1066 "3D_FULL_SCREEN", 1067 "POWER_SAVING", 1068 "VIDEO", 1069 "VR", 1070 "COMPUTE", 1071 "CUSTOM"}; 1072 uint32_t i, size = 0; 1073 int16_t workload_type = 0; 1074 1075 if (!buf) 1076 return -EINVAL; 1077 1078 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1079 /* 1080 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1081 * Not all profile modes are supported on arcturus. 1082 */ 1083 workload_type = smu_cmn_to_asic_specific_index(smu, 1084 CMN2ASIC_MAPPING_WORKLOAD, 1085 i); 1086 if (workload_type < 0) 1087 continue; 1088 1089 size += sprintf(buf + size, "%2d %14s%s\n", 1090 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1091 } 1092 1093 return size; 1094 } 1095 1096 static int renoir_get_smu_metrics_data(struct smu_context *smu, 1097 MetricsMember_t member, 1098 uint32_t *value) 1099 { 1100 struct smu_table_context *smu_table = &smu->smu_table; 1101 1102 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 1103 int ret = 0; 1104 1105 mutex_lock(&smu->metrics_lock); 1106 1107 ret = smu_cmn_get_metrics_table_locked(smu, 1108 NULL, 1109 false); 1110 if (ret) { 1111 mutex_unlock(&smu->metrics_lock); 1112 return ret; 1113 } 1114 1115 switch (member) { 1116 case METRICS_AVERAGE_GFXCLK: 1117 *value = metrics->ClockFrequency[CLOCK_GFXCLK]; 1118 break; 1119 case METRICS_AVERAGE_SOCCLK: 1120 *value = metrics->ClockFrequency[CLOCK_SOCCLK]; 1121 break; 1122 case METRICS_AVERAGE_UCLK: 1123 *value = metrics->ClockFrequency[CLOCK_FCLK]; 1124 break; 1125 case METRICS_AVERAGE_GFXACTIVITY: 1126 *value = metrics->AverageGfxActivity / 100; 1127 break; 1128 case METRICS_AVERAGE_VCNACTIVITY: 1129 *value = metrics->AverageUvdActivity / 100; 1130 break; 1131 case METRICS_AVERAGE_SOCKETPOWER: 1132 *value = metrics->CurrentSocketPower << 8; 1133 break; 1134 case METRICS_TEMPERATURE_EDGE: 1135 *value = (metrics->GfxTemperature / 100) * 1136 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1137 break; 1138 case METRICS_TEMPERATURE_HOTSPOT: 1139 *value = (metrics->SocTemperature / 100) * 1140 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1141 break; 1142 case METRICS_THROTTLER_STATUS: 1143 *value = metrics->ThrottlerStatus; 1144 break; 1145 case METRICS_VOLTAGE_VDDGFX: 1146 *value = metrics->Voltage[0]; 1147 break; 1148 case METRICS_VOLTAGE_VDDSOC: 1149 *value = metrics->Voltage[1]; 1150 break; 1151 default: 1152 *value = UINT_MAX; 1153 break; 1154 } 1155 1156 mutex_unlock(&smu->metrics_lock); 1157 1158 return ret; 1159 } 1160 1161 static int renoir_read_sensor(struct smu_context *smu, 1162 enum amd_pp_sensors sensor, 1163 void *data, uint32_t *size) 1164 { 1165 int ret = 0; 1166 1167 if (!data || !size) 1168 return -EINVAL; 1169 1170 mutex_lock(&smu->sensor_lock); 1171 switch (sensor) { 1172 case AMDGPU_PP_SENSOR_GPU_LOAD: 1173 ret = renoir_get_smu_metrics_data(smu, 1174 METRICS_AVERAGE_GFXACTIVITY, 1175 (uint32_t *)data); 1176 *size = 4; 1177 break; 1178 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1179 ret = renoir_get_smu_metrics_data(smu, 1180 METRICS_TEMPERATURE_EDGE, 1181 (uint32_t *)data); 1182 *size = 4; 1183 break; 1184 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1185 ret = renoir_get_smu_metrics_data(smu, 1186 METRICS_TEMPERATURE_HOTSPOT, 1187 (uint32_t *)data); 1188 *size = 4; 1189 break; 1190 case AMDGPU_PP_SENSOR_GFX_MCLK: 1191 ret = renoir_get_smu_metrics_data(smu, 1192 METRICS_AVERAGE_UCLK, 1193 (uint32_t *)data); 1194 *(uint32_t *)data *= 100; 1195 *size = 4; 1196 break; 1197 case AMDGPU_PP_SENSOR_GFX_SCLK: 1198 ret = renoir_get_smu_metrics_data(smu, 1199 METRICS_AVERAGE_GFXCLK, 1200 (uint32_t *)data); 1201 *(uint32_t *)data *= 100; 1202 *size = 4; 1203 break; 1204 case AMDGPU_PP_SENSOR_VDDGFX: 1205 ret = renoir_get_smu_metrics_data(smu, 1206 METRICS_VOLTAGE_VDDGFX, 1207 (uint32_t *)data); 1208 *size = 4; 1209 break; 1210 case AMDGPU_PP_SENSOR_VDDNB: 1211 ret = renoir_get_smu_metrics_data(smu, 1212 METRICS_VOLTAGE_VDDSOC, 1213 (uint32_t *)data); 1214 *size = 4; 1215 break; 1216 case AMDGPU_PP_SENSOR_GPU_POWER: 1217 ret = renoir_get_smu_metrics_data(smu, 1218 METRICS_AVERAGE_SOCKETPOWER, 1219 (uint32_t *)data); 1220 *size = 4; 1221 break; 1222 default: 1223 ret = -EOPNOTSUPP; 1224 break; 1225 } 1226 mutex_unlock(&smu->sensor_lock); 1227 1228 return ret; 1229 } 1230 1231 static bool renoir_is_dpm_running(struct smu_context *smu) 1232 { 1233 struct amdgpu_device *adev = smu->adev; 1234 1235 /* 1236 * Until now, the pmfw hasn't exported the interface of SMU 1237 * feature mask to APU SKU so just force on all the feature 1238 * at early initial stage. 1239 */ 1240 if (adev->in_suspend) 1241 return false; 1242 else 1243 return true; 1244 1245 } 1246 1247 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, 1248 void **table) 1249 { 1250 struct smu_table_context *smu_table = &smu->smu_table; 1251 struct gpu_metrics_v2_0 *gpu_metrics = 1252 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; 1253 SmuMetrics_t metrics; 1254 int ret = 0; 1255 1256 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1257 if (ret) 1258 return ret; 1259 1260 smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics); 1261 1262 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1263 gpu_metrics->temperature_soc = metrics.SocTemperature; 1264 memcpy(&gpu_metrics->temperature_core[0], 1265 &metrics.CoreTemperature[0], 1266 sizeof(uint16_t) * 8); 1267 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1268 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1269 1270 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1271 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity; 1272 1273 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1274 gpu_metrics->average_cpu_power = metrics.Power[0]; 1275 gpu_metrics->average_soc_power = metrics.Power[1]; 1276 memcpy(&gpu_metrics->average_core_power[0], 1277 &metrics.CorePower[0], 1278 sizeof(uint16_t) * 8); 1279 1280 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1281 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1282 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency; 1283 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency; 1284 1285 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK]; 1286 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK]; 1287 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK]; 1288 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK]; 1289 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK]; 1290 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK]; 1291 memcpy(&gpu_metrics->current_coreclk[0], 1292 &metrics.CoreFrequency[0], 1293 sizeof(uint16_t) * 8); 1294 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1295 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1296 1297 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1298 1299 gpu_metrics->fan_pwm = metrics.FanPwm; 1300 1301 *table = (void *)gpu_metrics; 1302 1303 return sizeof(struct gpu_metrics_v2_0); 1304 } 1305 1306 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) 1307 { 1308 1309 return 0; 1310 } 1311 1312 static const struct pptable_funcs renoir_ppt_funcs = { 1313 .set_power_state = NULL, 1314 .print_clk_levels = renoir_print_clk_levels, 1315 .get_current_power_state = renoir_get_current_power_state, 1316 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable, 1317 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable, 1318 .force_clk_levels = renoir_force_clk_levels, 1319 .set_power_profile_mode = renoir_set_power_profile_mode, 1320 .set_performance_level = renoir_set_performance_level, 1321 .get_dpm_clock_table = renoir_get_dpm_clock_table, 1322 .set_watermarks_table = renoir_set_watermarks_table, 1323 .get_power_profile_mode = renoir_get_power_profile_mode, 1324 .read_sensor = renoir_read_sensor, 1325 .check_fw_status = smu_v12_0_check_fw_status, 1326 .check_fw_version = smu_v12_0_check_fw_version, 1327 .powergate_sdma = smu_v12_0_powergate_sdma, 1328 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1329 .send_smc_msg = smu_cmn_send_smc_msg, 1330 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, 1331 .gfx_off_control = smu_v12_0_gfx_off_control, 1332 .get_gfx_off_status = smu_v12_0_get_gfxoff_status, 1333 .init_smc_tables = renoir_init_smc_tables, 1334 .fini_smc_tables = smu_v12_0_fini_smc_tables, 1335 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables, 1336 .get_enabled_mask = smu_cmn_get_enabled_mask, 1337 .feature_is_enabled = smu_cmn_feature_is_enabled, 1338 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1339 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq, 1340 .mode2_reset = smu_v12_0_mode2_reset, 1341 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, 1342 .set_driver_table_location = smu_v12_0_set_driver_table_location, 1343 .is_dpm_running = renoir_is_dpm_running, 1344 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1345 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1346 .get_gpu_metrics = renoir_get_gpu_metrics, 1347 .gfx_state_change_set = renoir_gfx_state_change_set, 1348 .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters, 1349 .od_edit_dpm_table = renoir_od_edit_dpm_table, 1350 }; 1351 1352 void renoir_set_ppt_funcs(struct smu_context *smu) 1353 { 1354 smu->ppt_funcs = &renoir_ppt_funcs; 1355 smu->message_map = renoir_message_map; 1356 smu->clock_map = renoir_clk_map; 1357 smu->table_map = renoir_table_map; 1358 smu->workload_map = renoir_workload_map; 1359 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; 1360 smu->is_apu = true; 1361 } 1362