1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2019 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan */ 23e098bc96SEvan Quan 24e098bc96SEvan Quan #define SWSMU_CODE_LAYER_L2 25e098bc96SEvan Quan 26e098bc96SEvan Quan #include "amdgpu.h" 27e098bc96SEvan Quan #include "amdgpu_smu.h" 28e098bc96SEvan Quan #include "smu_v12_0_ppsmc.h" 29e098bc96SEvan Quan #include "smu12_driver_if.h" 30e098bc96SEvan Quan #include "smu_v12_0.h" 31e098bc96SEvan Quan #include "renoir_ppt.h" 32e098bc96SEvan Quan #include "smu_cmn.h" 33e098bc96SEvan Quan 34e098bc96SEvan Quan /* 35e098bc96SEvan Quan * DO NOT use these for err/warn/info/debug messages. 36e098bc96SEvan Quan * Use dev_err, dev_warn, dev_info and dev_dbg instead. 37e098bc96SEvan Quan * They are more MGPU friendly. 38e098bc96SEvan Quan */ 39e098bc96SEvan Quan #undef pr_err 40e098bc96SEvan Quan #undef pr_warn 41e098bc96SEvan Quan #undef pr_info 42e098bc96SEvan Quan #undef pr_debug 43e098bc96SEvan Quan 44e098bc96SEvan Quan static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { 45e098bc96SEvan Quan MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 46e098bc96SEvan Quan MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 47e098bc96SEvan Quan MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 48e098bc96SEvan Quan MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1), 49e098bc96SEvan Quan MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1), 50e098bc96SEvan Quan MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1), 51e098bc96SEvan Quan MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 52e098bc96SEvan Quan MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 53e098bc96SEvan Quan MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 54e098bc96SEvan Quan MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 55e098bc96SEvan Quan MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1), 56e098bc96SEvan Quan MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1), 57e098bc96SEvan Quan MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1), 58e098bc96SEvan Quan MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 59e098bc96SEvan Quan MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1), 60e098bc96SEvan Quan MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1), 61e098bc96SEvan Quan MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1), 62e098bc96SEvan Quan MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1), 63e098bc96SEvan Quan MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1), 64e098bc96SEvan Quan MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1), 65e098bc96SEvan Quan MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1), 66e098bc96SEvan Quan MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 67e098bc96SEvan Quan MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 68e098bc96SEvan Quan MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 69e098bc96SEvan Quan MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 70e098bc96SEvan Quan MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 71e098bc96SEvan Quan MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1), 72e098bc96SEvan Quan MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1), 73e098bc96SEvan Quan MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 74e098bc96SEvan Quan MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1), 75e098bc96SEvan Quan MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1), 76e098bc96SEvan Quan MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1), 77e098bc96SEvan Quan MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1), 78e098bc96SEvan Quan MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1), 79e098bc96SEvan Quan MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1), 80e098bc96SEvan Quan MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 81e098bc96SEvan Quan MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1), 82e098bc96SEvan Quan MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 83e098bc96SEvan Quan MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 84e098bc96SEvan Quan MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1), 85e098bc96SEvan Quan MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1), 86e098bc96SEvan Quan MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1), 87e098bc96SEvan Quan MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1), 88e098bc96SEvan Quan MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 89e098bc96SEvan Quan MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 90e098bc96SEvan Quan MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 91e098bc96SEvan Quan MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 92e098bc96SEvan Quan MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 93e098bc96SEvan Quan MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1), 94e098bc96SEvan Quan MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1), 95e098bc96SEvan Quan MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1), 96e098bc96SEvan Quan MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 97e098bc96SEvan Quan MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1), 98e098bc96SEvan Quan MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1), 99e098bc96SEvan Quan MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 100e098bc96SEvan Quan MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 101e098bc96SEvan Quan MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1), 102e098bc96SEvan Quan MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1), 103e098bc96SEvan Quan MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 104e098bc96SEvan Quan }; 105e098bc96SEvan Quan 106e098bc96SEvan Quan static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { 107e098bc96SEvan Quan CLK_MAP(GFXCLK, CLOCK_GFXCLK), 108e098bc96SEvan Quan CLK_MAP(SCLK, CLOCK_GFXCLK), 109e098bc96SEvan Quan CLK_MAP(SOCCLK, CLOCK_SOCCLK), 110e098bc96SEvan Quan CLK_MAP(UCLK, CLOCK_FCLK), 111e098bc96SEvan Quan CLK_MAP(MCLK, CLOCK_FCLK), 11278842457SDavid M Nieto CLK_MAP(VCLK, CLOCK_VCLK), 11378842457SDavid M Nieto CLK_MAP(DCLK, CLOCK_DCLK), 114e098bc96SEvan Quan }; 115e098bc96SEvan Quan 116e098bc96SEvan Quan static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { 117e098bc96SEvan Quan TAB_MAP_VALID(WATERMARKS), 118e098bc96SEvan Quan TAB_MAP_INVALID(CUSTOM_DPM), 119e098bc96SEvan Quan TAB_MAP_VALID(DPMCLOCKS), 120e098bc96SEvan Quan TAB_MAP_VALID(SMU_METRICS), 121e098bc96SEvan Quan }; 122e098bc96SEvan Quan 123e098bc96SEvan Quan static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 124e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 125e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 126e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 127e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 128e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 129e098bc96SEvan Quan }; 130e098bc96SEvan Quan 131d4c9b03fSGraham Sider static const uint8_t renoir_throttler_map[] = { 132d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), 133d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), 134d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), 135d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), 136d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), 137d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), 138d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), 139d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), 140d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), 141d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_PROCHOT_CPU] = (SMU_THROTTLER_PROCHOT_CPU_BIT), 142d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_PROCHOT_GFX] = (SMU_THROTTLER_PROCHOT_GFX_BIT), 143d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_EDC_CPU] = (SMU_THROTTLER_EDC_CPU_BIT), 144d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_EDC_GFX] = (SMU_THROTTLER_EDC_GFX_BIT), 145d4c9b03fSGraham Sider }; 146d4c9b03fSGraham Sider 147e098bc96SEvan Quan static int renoir_init_smc_tables(struct smu_context *smu) 148e098bc96SEvan Quan { 149e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 150e098bc96SEvan Quan struct smu_table *tables = smu_table->tables; 151e098bc96SEvan Quan 152e098bc96SEvan Quan SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 153e098bc96SEvan Quan PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 154e098bc96SEvan Quan SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 155e098bc96SEvan Quan PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 156e098bc96SEvan Quan SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 157e098bc96SEvan Quan PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 158e098bc96SEvan Quan 159e098bc96SEvan Quan smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 160e098bc96SEvan Quan if (!smu_table->clocks_table) 161e098bc96SEvan Quan goto err0_out; 162e098bc96SEvan Quan 163e098bc96SEvan Quan smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 164e098bc96SEvan Quan if (!smu_table->metrics_table) 165e098bc96SEvan Quan goto err1_out; 166e098bc96SEvan Quan smu_table->metrics_time = 0; 167e098bc96SEvan Quan 168e098bc96SEvan Quan smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 169e098bc96SEvan Quan if (!smu_table->watermarks_table) 170e098bc96SEvan Quan goto err2_out; 171e098bc96SEvan Quan 172d4c9b03fSGraham Sider smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); 173e098bc96SEvan Quan smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 174e098bc96SEvan Quan if (!smu_table->gpu_metrics_table) 175e098bc96SEvan Quan goto err3_out; 176e098bc96SEvan Quan 177e098bc96SEvan Quan return 0; 178e098bc96SEvan Quan 179e098bc96SEvan Quan err3_out: 180e098bc96SEvan Quan kfree(smu_table->watermarks_table); 181e098bc96SEvan Quan err2_out: 182e098bc96SEvan Quan kfree(smu_table->metrics_table); 183e098bc96SEvan Quan err1_out: 184e098bc96SEvan Quan kfree(smu_table->clocks_table); 185e098bc96SEvan Quan err0_out: 186e098bc96SEvan Quan return -ENOMEM; 187e098bc96SEvan Quan } 188e098bc96SEvan Quan 189fecc72f1SLee Jones /* 190e098bc96SEvan Quan * This interface just for getting uclk ultimate freq and should't introduce 191e098bc96SEvan Quan * other likewise function result in overmuch callback. 192e098bc96SEvan Quan */ 193e098bc96SEvan Quan static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 194e098bc96SEvan Quan uint32_t dpm_level, uint32_t *freq) 195e098bc96SEvan Quan { 196e098bc96SEvan Quan DpmClocks_t *clk_table = smu->smu_table.clocks_table; 197e098bc96SEvan Quan 198e098bc96SEvan Quan if (!clk_table || clk_type >= SMU_CLK_COUNT) 199e098bc96SEvan Quan return -EINVAL; 200e098bc96SEvan Quan 201e098bc96SEvan Quan switch (clk_type) { 202e098bc96SEvan Quan case SMU_SOCCLK: 203e098bc96SEvan Quan if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) 204e098bc96SEvan Quan return -EINVAL; 205e098bc96SEvan Quan *freq = clk_table->SocClocks[dpm_level].Freq; 206e098bc96SEvan Quan break; 207d45af863SXiaojian Du case SMU_UCLK: 208e098bc96SEvan Quan case SMU_MCLK: 209e098bc96SEvan Quan if (dpm_level >= NUM_FCLK_DPM_LEVELS) 210e098bc96SEvan Quan return -EINVAL; 211e098bc96SEvan Quan *freq = clk_table->FClocks[dpm_level].Freq; 212e098bc96SEvan Quan break; 213e098bc96SEvan Quan case SMU_DCEFCLK: 214e098bc96SEvan Quan if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) 215e098bc96SEvan Quan return -EINVAL; 216e098bc96SEvan Quan *freq = clk_table->DcfClocks[dpm_level].Freq; 217e098bc96SEvan Quan break; 218e098bc96SEvan Quan case SMU_FCLK: 219e098bc96SEvan Quan if (dpm_level >= NUM_FCLK_DPM_LEVELS) 220e098bc96SEvan Quan return -EINVAL; 221e098bc96SEvan Quan *freq = clk_table->FClocks[dpm_level].Freq; 222e098bc96SEvan Quan break; 22378842457SDavid M Nieto case SMU_VCLK: 22478842457SDavid M Nieto if (dpm_level >= NUM_VCN_DPM_LEVELS) 22578842457SDavid M Nieto return -EINVAL; 22678842457SDavid M Nieto *freq = clk_table->VClocks[dpm_level].Freq; 22778842457SDavid M Nieto break; 22878842457SDavid M Nieto case SMU_DCLK: 22978842457SDavid M Nieto if (dpm_level >= NUM_VCN_DPM_LEVELS) 23078842457SDavid M Nieto return -EINVAL; 23178842457SDavid M Nieto *freq = clk_table->DClocks[dpm_level].Freq; 23278842457SDavid M Nieto break; 23378842457SDavid M Nieto 234e098bc96SEvan Quan default: 235e098bc96SEvan Quan return -EINVAL; 236e098bc96SEvan Quan } 237e098bc96SEvan Quan 238e098bc96SEvan Quan return 0; 239e098bc96SEvan Quan } 240e098bc96SEvan Quan 241e098bc96SEvan Quan static int renoir_get_profiling_clk_mask(struct smu_context *smu, 242e098bc96SEvan Quan enum amd_dpm_forced_level level, 243e098bc96SEvan Quan uint32_t *sclk_mask, 244e098bc96SEvan Quan uint32_t *mclk_mask, 245e098bc96SEvan Quan uint32_t *soc_mask) 246e098bc96SEvan Quan { 247e098bc96SEvan Quan 248e098bc96SEvan Quan if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 249e098bc96SEvan Quan if (sclk_mask) 250e098bc96SEvan Quan *sclk_mask = 0; 251e098bc96SEvan Quan } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 252e098bc96SEvan Quan if (mclk_mask) 253485d531cSAlex Deucher /* mclk levels are in reverse order */ 254485d531cSAlex Deucher *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; 255e098bc96SEvan Quan } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 256e098bc96SEvan Quan if(sclk_mask) 257e098bc96SEvan Quan /* The sclk as gfxclk and has three level about max/min/current */ 258e098bc96SEvan Quan *sclk_mask = 3 - 1; 259e098bc96SEvan Quan 260e098bc96SEvan Quan if(mclk_mask) 261485d531cSAlex Deucher /* mclk levels are in reverse order */ 262485d531cSAlex Deucher *mclk_mask = 0; 263e098bc96SEvan Quan 264e098bc96SEvan Quan if(soc_mask) 265e098bc96SEvan Quan *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; 266e098bc96SEvan Quan } 267e098bc96SEvan Quan 268e098bc96SEvan Quan return 0; 269e098bc96SEvan Quan } 270e098bc96SEvan Quan 271e098bc96SEvan Quan static int renoir_get_dpm_ultimate_freq(struct smu_context *smu, 272e098bc96SEvan Quan enum smu_clk_type clk_type, 273e098bc96SEvan Quan uint32_t *min, 274e098bc96SEvan Quan uint32_t *max) 275e098bc96SEvan Quan { 276e098bc96SEvan Quan int ret = 0; 277e098bc96SEvan Quan uint32_t mclk_mask, soc_mask; 278e098bc96SEvan Quan uint32_t clock_limit; 279e098bc96SEvan Quan 280e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 281e098bc96SEvan Quan switch (clk_type) { 282e098bc96SEvan Quan case SMU_MCLK: 283e098bc96SEvan Quan case SMU_UCLK: 284e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.uclk; 285e098bc96SEvan Quan break; 286e098bc96SEvan Quan case SMU_GFXCLK: 287e098bc96SEvan Quan case SMU_SCLK: 288e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.gfxclk; 289e098bc96SEvan Quan break; 290e098bc96SEvan Quan case SMU_SOCCLK: 291e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.socclk; 292e098bc96SEvan Quan break; 293e098bc96SEvan Quan default: 294e098bc96SEvan Quan clock_limit = 0; 295e098bc96SEvan Quan break; 296e098bc96SEvan Quan } 297e098bc96SEvan Quan 298e098bc96SEvan Quan /* clock in Mhz unit */ 299e098bc96SEvan Quan if (min) 300e098bc96SEvan Quan *min = clock_limit / 100; 301e098bc96SEvan Quan if (max) 302e098bc96SEvan Quan *max = clock_limit / 100; 303e098bc96SEvan Quan 304e098bc96SEvan Quan return 0; 305e098bc96SEvan Quan } 306e098bc96SEvan Quan 307e098bc96SEvan Quan if (max) { 308e098bc96SEvan Quan ret = renoir_get_profiling_clk_mask(smu, 309e098bc96SEvan Quan AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 310e098bc96SEvan Quan NULL, 311e098bc96SEvan Quan &mclk_mask, 312e098bc96SEvan Quan &soc_mask); 313e098bc96SEvan Quan if (ret) 314e098bc96SEvan Quan goto failed; 315e098bc96SEvan Quan 316e098bc96SEvan Quan switch (clk_type) { 317e098bc96SEvan Quan case SMU_GFXCLK: 318e098bc96SEvan Quan case SMU_SCLK: 319e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max); 320e098bc96SEvan Quan if (ret) { 321e098bc96SEvan Quan dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n"); 322e098bc96SEvan Quan goto failed; 323e098bc96SEvan Quan } 324e098bc96SEvan Quan break; 325e098bc96SEvan Quan case SMU_UCLK: 326e098bc96SEvan Quan case SMU_FCLK: 327e098bc96SEvan Quan case SMU_MCLK: 328e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 329e098bc96SEvan Quan if (ret) 330e098bc96SEvan Quan goto failed; 331e098bc96SEvan Quan break; 332e098bc96SEvan Quan case SMU_SOCCLK: 333e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 334e098bc96SEvan Quan if (ret) 335e098bc96SEvan Quan goto failed; 336e098bc96SEvan Quan break; 337e098bc96SEvan Quan default: 338e098bc96SEvan Quan ret = -EINVAL; 339e098bc96SEvan Quan goto failed; 340e098bc96SEvan Quan } 341e098bc96SEvan Quan } 342e098bc96SEvan Quan 343e098bc96SEvan Quan if (min) { 344e098bc96SEvan Quan switch (clk_type) { 345e098bc96SEvan Quan case SMU_GFXCLK: 346e098bc96SEvan Quan case SMU_SCLK: 347e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min); 348e098bc96SEvan Quan if (ret) { 349e098bc96SEvan Quan dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n"); 350e098bc96SEvan Quan goto failed; 351e098bc96SEvan Quan } 352e098bc96SEvan Quan break; 353e098bc96SEvan Quan case SMU_UCLK: 354e098bc96SEvan Quan case SMU_FCLK: 355e098bc96SEvan Quan case SMU_MCLK: 356485d531cSAlex Deucher ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min); 357e098bc96SEvan Quan if (ret) 358e098bc96SEvan Quan goto failed; 359e098bc96SEvan Quan break; 360e098bc96SEvan Quan case SMU_SOCCLK: 361e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min); 362e098bc96SEvan Quan if (ret) 363e098bc96SEvan Quan goto failed; 364e098bc96SEvan Quan break; 365e098bc96SEvan Quan default: 366e098bc96SEvan Quan ret = -EINVAL; 367e098bc96SEvan Quan goto failed; 368e098bc96SEvan Quan } 369e098bc96SEvan Quan } 370e098bc96SEvan Quan failed: 371e098bc96SEvan Quan return ret; 372e098bc96SEvan Quan } 373e098bc96SEvan Quan 374ca55f459SXiaojian Du static int renoir_od_edit_dpm_table(struct smu_context *smu, 375ca55f459SXiaojian Du enum PP_OD_DPM_TABLE_COMMAND type, 376ca55f459SXiaojian Du long input[], uint32_t size) 377ca55f459SXiaojian Du { 378ca55f459SXiaojian Du int ret = 0; 379e017fb66SXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 380ca55f459SXiaojian Du 381e017fb66SXiaojian Du if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 382d7ef887fSXiaojian Du dev_warn(smu->adev->dev, 383ce7c670dSColin Ian King "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 384ca55f459SXiaojian Du return -EINVAL; 385ca55f459SXiaojian Du } 386ca55f459SXiaojian Du 387ca55f459SXiaojian Du switch (type) { 388ca55f459SXiaojian Du case PP_OD_EDIT_SCLK_VDDC_TABLE: 389ca55f459SXiaojian Du if (size != 2) { 390ca55f459SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n"); 391ca55f459SXiaojian Du return -EINVAL; 392ca55f459SXiaojian Du } 393ca55f459SXiaojian Du 394ca55f459SXiaojian Du if (input[0] == 0) { 395ca55f459SXiaojian Du if (input[1] < smu->gfx_default_hard_min_freq) { 39608da4fcdSXiaojian Du dev_warn(smu->adev->dev, 39708da4fcdSXiaojian Du "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 398ca55f459SXiaojian Du input[1], smu->gfx_default_hard_min_freq); 399ca55f459SXiaojian Du return -EINVAL; 400ca55f459SXiaojian Du } 401ca55f459SXiaojian Du smu->gfx_actual_hard_min_freq = input[1]; 402ca55f459SXiaojian Du } else if (input[0] == 1) { 403ca55f459SXiaojian Du if (input[1] > smu->gfx_default_soft_max_freq) { 40408da4fcdSXiaojian Du dev_warn(smu->adev->dev, 40508da4fcdSXiaojian Du "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 406ca55f459SXiaojian Du input[1], smu->gfx_default_soft_max_freq); 407ca55f459SXiaojian Du return -EINVAL; 408ca55f459SXiaojian Du } 409ca55f459SXiaojian Du smu->gfx_actual_soft_max_freq = input[1]; 410ca55f459SXiaojian Du } else { 411ca55f459SXiaojian Du return -EINVAL; 412ca55f459SXiaojian Du } 413ca55f459SXiaojian Du break; 414ca55f459SXiaojian Du case PP_OD_RESTORE_DEFAULT_TABLE: 415ca55f459SXiaojian Du if (size != 0) { 416ca55f459SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n"); 417ca55f459SXiaojian Du return -EINVAL; 418ca55f459SXiaojian Du } 419ca55f459SXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 420ca55f459SXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 421ca55f459SXiaojian Du break; 422ca55f459SXiaojian Du case PP_OD_COMMIT_DPM_TABLE: 423ca55f459SXiaojian Du if (size != 0) { 424ca55f459SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n"); 425ca55f459SXiaojian Du return -EINVAL; 426ca55f459SXiaojian Du } else { 427ca55f459SXiaojian Du if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 42808da4fcdSXiaojian Du dev_err(smu->adev->dev, 429*f5d8e164SColin Ian King "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 43008da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq, 43108da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq); 432ca55f459SXiaojian Du return -EINVAL; 433ca55f459SXiaojian Du } 434ca55f459SXiaojian Du 435ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 436ca55f459SXiaojian Du SMU_MSG_SetHardMinGfxClk, 437ca55f459SXiaojian Du smu->gfx_actual_hard_min_freq, 438ca55f459SXiaojian Du NULL); 439ca55f459SXiaojian Du if (ret) { 440ca55f459SXiaojian Du dev_err(smu->adev->dev, "Set hard min sclk failed!"); 441ca55f459SXiaojian Du return ret; 442ca55f459SXiaojian Du } 443ca55f459SXiaojian Du 444ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 445ca55f459SXiaojian Du SMU_MSG_SetSoftMaxGfxClk, 446ca55f459SXiaojian Du smu->gfx_actual_soft_max_freq, 447ca55f459SXiaojian Du NULL); 448ca55f459SXiaojian Du if (ret) { 449ca55f459SXiaojian Du dev_err(smu->adev->dev, "Set soft max sclk failed!"); 450ca55f459SXiaojian Du return ret; 451ca55f459SXiaojian Du } 452ca55f459SXiaojian Du } 453ca55f459SXiaojian Du break; 454ca55f459SXiaojian Du default: 455ca55f459SXiaojian Du return -ENOSYS; 456ca55f459SXiaojian Du } 457ca55f459SXiaojian Du 458ca55f459SXiaojian Du return ret; 459ca55f459SXiaojian Du } 460ca55f459SXiaojian Du 461ca55f459SXiaojian Du static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 462ca55f459SXiaojian Du { 463ca55f459SXiaojian Du uint32_t min = 0, max = 0; 464ca55f459SXiaojian Du uint32_t ret = 0; 465ca55f459SXiaojian Du 466ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 467ca55f459SXiaojian Du SMU_MSG_GetMinGfxclkFrequency, 468ca55f459SXiaojian Du 0, &min); 469ca55f459SXiaojian Du if (ret) 470ca55f459SXiaojian Du return ret; 471ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 472ca55f459SXiaojian Du SMU_MSG_GetMaxGfxclkFrequency, 473ca55f459SXiaojian Du 0, &max); 474ca55f459SXiaojian Du if (ret) 475ca55f459SXiaojian Du return ret; 476ca55f459SXiaojian Du 477ca55f459SXiaojian Du smu->gfx_default_hard_min_freq = min; 478ca55f459SXiaojian Du smu->gfx_default_soft_max_freq = max; 479ca55f459SXiaojian Du smu->gfx_actual_hard_min_freq = 0; 480ca55f459SXiaojian Du smu->gfx_actual_soft_max_freq = 0; 481ca55f459SXiaojian Du 482ca55f459SXiaojian Du return 0; 483ca55f459SXiaojian Du } 484ca55f459SXiaojian Du 485e098bc96SEvan Quan static int renoir_print_clk_levels(struct smu_context *smu, 486e098bc96SEvan Quan enum smu_clk_type clk_type, char *buf) 487e098bc96SEvan Quan { 488e098bc96SEvan Quan int i, size = 0, ret = 0; 489e098bc96SEvan Quan uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; 490e098bc96SEvan Quan SmuMetrics_t metrics; 491e017fb66SXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 492e098bc96SEvan Quan bool cur_value_match_level = false; 493e098bc96SEvan Quan 494e098bc96SEvan Quan memset(&metrics, 0, sizeof(metrics)); 495e098bc96SEvan Quan 496e098bc96SEvan Quan ret = smu_cmn_get_metrics_table(smu, &metrics, false); 497e098bc96SEvan Quan if (ret) 498e098bc96SEvan Quan return ret; 499e098bc96SEvan Quan 500e098bc96SEvan Quan switch (clk_type) { 501ca55f459SXiaojian Du case SMU_OD_RANGE: 502e017fb66SXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 503ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 504ca55f459SXiaojian Du SMU_MSG_GetMinGfxclkFrequency, 505ca55f459SXiaojian Du 0, &min); 506ca55f459SXiaojian Du if (ret) 507ca55f459SXiaojian Du return ret; 508ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 509ca55f459SXiaojian Du SMU_MSG_GetMaxGfxclkFrequency, 510ca55f459SXiaojian Du 0, &max); 511ca55f459SXiaojian Du if (ret) 512ca55f459SXiaojian Du return ret; 513e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max); 514ca55f459SXiaojian Du } 515ca55f459SXiaojian Du break; 516ca55f459SXiaojian Du case SMU_OD_SCLK: 517e017fb66SXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 518ca55f459SXiaojian Du min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 519ca55f459SXiaojian Du max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 520e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "OD_SCLK\n"); 521e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "0:%10uMhz\n", min); 522e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "1:%10uMhz\n", max); 52308da4fcdSXiaojian Du } 524ca55f459SXiaojian Du break; 525e098bc96SEvan Quan case SMU_GFXCLK: 526e098bc96SEvan Quan case SMU_SCLK: 527e098bc96SEvan Quan /* retirve table returned paramters unit is MHz */ 528e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; 529e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max); 530e098bc96SEvan Quan if (!ret) { 531e098bc96SEvan Quan /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 532e098bc96SEvan Quan if (cur_value == max) 533e098bc96SEvan Quan i = 2; 534e098bc96SEvan Quan else if (cur_value == min) 535e098bc96SEvan Quan i = 0; 536e098bc96SEvan Quan else 537e098bc96SEvan Quan i = 1; 538e098bc96SEvan Quan 539e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 540e098bc96SEvan Quan i == 0 ? "*" : ""); 541e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 542e098bc96SEvan Quan i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, 543e098bc96SEvan Quan i == 1 ? "*" : ""); 544e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 545e098bc96SEvan Quan i == 2 ? "*" : ""); 546e098bc96SEvan Quan } 547e098bc96SEvan Quan return size; 548e098bc96SEvan Quan case SMU_SOCCLK: 549e098bc96SEvan Quan count = NUM_SOCCLK_DPM_LEVELS; 550e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; 551e098bc96SEvan Quan break; 552e098bc96SEvan Quan case SMU_MCLK: 553e098bc96SEvan Quan count = NUM_MEMCLK_DPM_LEVELS; 554e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 555e098bc96SEvan Quan break; 556e098bc96SEvan Quan case SMU_DCEFCLK: 557e098bc96SEvan Quan count = NUM_DCFCLK_DPM_LEVELS; 558e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_DCFCLK]; 559e098bc96SEvan Quan break; 560e098bc96SEvan Quan case SMU_FCLK: 561e098bc96SEvan Quan count = NUM_FCLK_DPM_LEVELS; 562e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 563e098bc96SEvan Quan break; 56478842457SDavid M Nieto case SMU_VCLK: 56578842457SDavid M Nieto count = NUM_VCN_DPM_LEVELS; 56678842457SDavid M Nieto cur_value = metrics.ClockFrequency[CLOCK_VCLK]; 56778842457SDavid M Nieto break; 56878842457SDavid M Nieto case SMU_DCLK: 56978842457SDavid M Nieto count = NUM_VCN_DPM_LEVELS; 57078842457SDavid M Nieto cur_value = metrics.ClockFrequency[CLOCK_DCLK]; 57178842457SDavid M Nieto break; 572e098bc96SEvan Quan default: 573ca55f459SXiaojian Du break; 574e098bc96SEvan Quan } 575e098bc96SEvan Quan 576ca55f459SXiaojian Du switch (clk_type) { 577ca55f459SXiaojian Du case SMU_GFXCLK: 578ca55f459SXiaojian Du case SMU_SCLK: 579ca55f459SXiaojian Du case SMU_SOCCLK: 580ca55f459SXiaojian Du case SMU_MCLK: 581ca55f459SXiaojian Du case SMU_DCEFCLK: 582ca55f459SXiaojian Du case SMU_FCLK: 58378842457SDavid M Nieto case SMU_VCLK: 58478842457SDavid M Nieto case SMU_DCLK: 585e098bc96SEvan Quan for (i = 0; i < count; i++) { 586e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); 587e098bc96SEvan Quan if (ret) 588e098bc96SEvan Quan return ret; 589e098bc96SEvan Quan if (!value) 590e098bc96SEvan Quan continue; 591e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 592e098bc96SEvan Quan cur_value == value ? "*" : ""); 593e098bc96SEvan Quan if (cur_value == value) 594e098bc96SEvan Quan cur_value_match_level = true; 595e098bc96SEvan Quan } 596e098bc96SEvan Quan 597e098bc96SEvan Quan if (!cur_value_match_level) 598e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 599e098bc96SEvan Quan 600ca55f459SXiaojian Du break; 601ca55f459SXiaojian Du default: 602ca55f459SXiaojian Du break; 603ca55f459SXiaojian Du } 604ca55f459SXiaojian Du 605e098bc96SEvan Quan return size; 606e098bc96SEvan Quan } 607e098bc96SEvan Quan 608e098bc96SEvan Quan static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) 609e098bc96SEvan Quan { 610e098bc96SEvan Quan enum amd_pm_state_type pm_type; 611e098bc96SEvan Quan struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 612e098bc96SEvan Quan 613e098bc96SEvan Quan if (!smu_dpm_ctx->dpm_context || 614e098bc96SEvan Quan !smu_dpm_ctx->dpm_current_power_state) 615e098bc96SEvan Quan return -EINVAL; 616e098bc96SEvan Quan 617e098bc96SEvan Quan switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) { 618e098bc96SEvan Quan case SMU_STATE_UI_LABEL_BATTERY: 619e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_BATTERY; 620e098bc96SEvan Quan break; 621e098bc96SEvan Quan case SMU_STATE_UI_LABEL_BALLANCED: 622e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_BALANCED; 623e098bc96SEvan Quan break; 624e098bc96SEvan Quan case SMU_STATE_UI_LABEL_PERFORMANCE: 625e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_PERFORMANCE; 626e098bc96SEvan Quan break; 627e098bc96SEvan Quan default: 628e098bc96SEvan Quan if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT) 629e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 630e098bc96SEvan Quan else 631e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_DEFAULT; 632e098bc96SEvan Quan break; 633e098bc96SEvan Quan } 634e098bc96SEvan Quan 635e098bc96SEvan Quan return pm_type; 636e098bc96SEvan Quan } 637e098bc96SEvan Quan 638e098bc96SEvan Quan static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 639e098bc96SEvan Quan { 640e098bc96SEvan Quan int ret = 0; 641e098bc96SEvan Quan 642e098bc96SEvan Quan if (enable) { 643e098bc96SEvan Quan /* vcn dpm on is a prerequisite for vcn power gate messages */ 644e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 645e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 646e098bc96SEvan Quan if (ret) 647e098bc96SEvan Quan return ret; 648e098bc96SEvan Quan } 649e098bc96SEvan Quan } else { 650e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 651e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 652e098bc96SEvan Quan if (ret) 653e098bc96SEvan Quan return ret; 654e098bc96SEvan Quan } 655e098bc96SEvan Quan } 656e098bc96SEvan Quan 657e098bc96SEvan Quan return ret; 658e098bc96SEvan Quan } 659e098bc96SEvan Quan 660e098bc96SEvan Quan static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 661e098bc96SEvan Quan { 662e098bc96SEvan Quan int ret = 0; 663e098bc96SEvan Quan 664e098bc96SEvan Quan if (enable) { 665e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 666e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 667e098bc96SEvan Quan if (ret) 668e098bc96SEvan Quan return ret; 669e098bc96SEvan Quan } 670e098bc96SEvan Quan } else { 671e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 672e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 673e098bc96SEvan Quan if (ret) 674e098bc96SEvan Quan return ret; 675e098bc96SEvan Quan } 676e098bc96SEvan Quan } 677e098bc96SEvan Quan 678e098bc96SEvan Quan return ret; 679e098bc96SEvan Quan } 680e098bc96SEvan Quan 681e098bc96SEvan Quan static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest) 682e098bc96SEvan Quan { 683e098bc96SEvan Quan int ret = 0, i = 0; 684e098bc96SEvan Quan uint32_t min_freq, max_freq, force_freq; 685e098bc96SEvan Quan enum smu_clk_type clk_type; 686e098bc96SEvan Quan 687e098bc96SEvan Quan enum smu_clk_type clks[] = { 688e098bc96SEvan Quan SMU_GFXCLK, 689e098bc96SEvan Quan SMU_MCLK, 690e098bc96SEvan Quan SMU_SOCCLK, 691e098bc96SEvan Quan }; 692e098bc96SEvan Quan 693e098bc96SEvan Quan for (i = 0; i < ARRAY_SIZE(clks); i++) { 694e098bc96SEvan Quan clk_type = clks[i]; 695e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 696e098bc96SEvan Quan if (ret) 697e098bc96SEvan Quan return ret; 698e098bc96SEvan Quan 699e098bc96SEvan Quan force_freq = highest ? max_freq : min_freq; 700e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 701e098bc96SEvan Quan if (ret) 702e098bc96SEvan Quan return ret; 703e098bc96SEvan Quan } 704e098bc96SEvan Quan 705e098bc96SEvan Quan return ret; 706e098bc96SEvan Quan } 707e098bc96SEvan Quan 708e098bc96SEvan Quan static int renoir_unforce_dpm_levels(struct smu_context *smu) { 709e098bc96SEvan Quan 710e098bc96SEvan Quan int ret = 0, i = 0; 711e098bc96SEvan Quan uint32_t min_freq, max_freq; 712e098bc96SEvan Quan enum smu_clk_type clk_type; 713e098bc96SEvan Quan 714e098bc96SEvan Quan struct clk_feature_map { 715e098bc96SEvan Quan enum smu_clk_type clk_type; 716e098bc96SEvan Quan uint32_t feature; 717e098bc96SEvan Quan } clk_feature_map[] = { 718e098bc96SEvan Quan {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, 719e098bc96SEvan Quan {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, 720e098bc96SEvan Quan {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 721e098bc96SEvan Quan }; 722e098bc96SEvan Quan 723e098bc96SEvan Quan for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 724e098bc96SEvan Quan if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 725e098bc96SEvan Quan continue; 726e098bc96SEvan Quan 727e098bc96SEvan Quan clk_type = clk_feature_map[i].clk_type; 728e098bc96SEvan Quan 729e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 730e098bc96SEvan Quan if (ret) 731e098bc96SEvan Quan return ret; 732e098bc96SEvan Quan 733e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 734e098bc96SEvan Quan if (ret) 735e098bc96SEvan Quan return ret; 736e098bc96SEvan Quan } 737e098bc96SEvan Quan 738e098bc96SEvan Quan return ret; 739e098bc96SEvan Quan } 740e098bc96SEvan Quan 741fecc72f1SLee Jones /* 742e098bc96SEvan Quan * This interface get dpm clock table for dc 743e098bc96SEvan Quan */ 744e098bc96SEvan Quan static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 745e098bc96SEvan Quan { 746e098bc96SEvan Quan DpmClocks_t *table = smu->smu_table.clocks_table; 747e098bc96SEvan Quan int i; 748e098bc96SEvan Quan 749e098bc96SEvan Quan if (!clock_table || !table) 750e098bc96SEvan Quan return -EINVAL; 751e098bc96SEvan Quan 752e098bc96SEvan Quan for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { 753e098bc96SEvan Quan clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; 754e098bc96SEvan Quan clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; 755e098bc96SEvan Quan } 756e098bc96SEvan Quan 757e098bc96SEvan Quan for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 758e098bc96SEvan Quan clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq; 759e098bc96SEvan Quan clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; 760e098bc96SEvan Quan } 761e098bc96SEvan Quan 762e098bc96SEvan Quan for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 763e098bc96SEvan Quan clock_table->FClocks[i].Freq = table->FClocks[i].Freq; 764e098bc96SEvan Quan clock_table->FClocks[i].Vol = table->FClocks[i].Vol; 765e098bc96SEvan Quan } 766e098bc96SEvan Quan 767e098bc96SEvan Quan for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) { 768e098bc96SEvan Quan clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq; 769e098bc96SEvan Quan clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; 770e098bc96SEvan Quan } 771e098bc96SEvan Quan 77278842457SDavid M Nieto for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { 77378842457SDavid M Nieto clock_table->VClocks[i].Freq = table->VClocks[i].Freq; 77478842457SDavid M Nieto clock_table->VClocks[i].Vol = table->VClocks[i].Vol; 77578842457SDavid M Nieto } 77678842457SDavid M Nieto 77778842457SDavid M Nieto for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { 77878842457SDavid M Nieto clock_table->DClocks[i].Freq = table->DClocks[i].Freq; 77978842457SDavid M Nieto clock_table->DClocks[i].Vol = table->DClocks[i].Vol; 78078842457SDavid M Nieto } 78178842457SDavid M Nieto 782e098bc96SEvan Quan return 0; 783e098bc96SEvan Quan } 784e098bc96SEvan Quan 785e098bc96SEvan Quan static int renoir_force_clk_levels(struct smu_context *smu, 786e098bc96SEvan Quan enum smu_clk_type clk_type, uint32_t mask) 787e098bc96SEvan Quan { 788e098bc96SEvan Quan 789e098bc96SEvan Quan int ret = 0 ; 790e098bc96SEvan Quan uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 791e098bc96SEvan Quan 792e098bc96SEvan Quan soft_min_level = mask ? (ffs(mask) - 1) : 0; 793e098bc96SEvan Quan soft_max_level = mask ? (fls(mask) - 1) : 0; 794e098bc96SEvan Quan 795e098bc96SEvan Quan switch (clk_type) { 796e098bc96SEvan Quan case SMU_GFXCLK: 797e098bc96SEvan Quan case SMU_SCLK: 798e098bc96SEvan Quan if (soft_min_level > 2 || soft_max_level > 2) { 799e098bc96SEvan Quan dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n"); 800e098bc96SEvan Quan return -EINVAL; 801e098bc96SEvan Quan } 802e098bc96SEvan Quan 803e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq); 804e098bc96SEvan Quan if (ret) 805e098bc96SEvan Quan return ret; 806e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 807e098bc96SEvan Quan soft_max_level == 0 ? min_freq : 808e098bc96SEvan Quan soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq, 809e098bc96SEvan Quan NULL); 810e098bc96SEvan Quan if (ret) 811e098bc96SEvan Quan return ret; 812e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 813e098bc96SEvan Quan soft_min_level == 2 ? max_freq : 814e098bc96SEvan Quan soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq, 815e098bc96SEvan Quan NULL); 816e098bc96SEvan Quan if (ret) 817e098bc96SEvan Quan return ret; 818e098bc96SEvan Quan break; 819e098bc96SEvan Quan case SMU_SOCCLK: 820e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 821e098bc96SEvan Quan if (ret) 822e098bc96SEvan Quan return ret; 823e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 824e098bc96SEvan Quan if (ret) 825e098bc96SEvan Quan return ret; 826e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); 827e098bc96SEvan Quan if (ret) 828e098bc96SEvan Quan return ret; 829e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); 830e098bc96SEvan Quan if (ret) 831e098bc96SEvan Quan return ret; 832e098bc96SEvan Quan break; 833e098bc96SEvan Quan case SMU_MCLK: 834e098bc96SEvan Quan case SMU_FCLK: 835e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 836e098bc96SEvan Quan if (ret) 837e098bc96SEvan Quan return ret; 838e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 839e098bc96SEvan Quan if (ret) 840e098bc96SEvan Quan return ret; 841e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); 842e098bc96SEvan Quan if (ret) 843e098bc96SEvan Quan return ret; 844e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); 845e098bc96SEvan Quan if (ret) 846e098bc96SEvan Quan return ret; 847e098bc96SEvan Quan break; 848e098bc96SEvan Quan default: 849e098bc96SEvan Quan break; 850e098bc96SEvan Quan } 851e098bc96SEvan Quan 852e098bc96SEvan Quan return ret; 853e098bc96SEvan Quan } 854e098bc96SEvan Quan 855e098bc96SEvan Quan static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 856e098bc96SEvan Quan { 857e098bc96SEvan Quan int workload_type, ret; 858e098bc96SEvan Quan uint32_t profile_mode = input[size]; 859e098bc96SEvan Quan 860e098bc96SEvan Quan if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 861e098bc96SEvan Quan dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 862e098bc96SEvan Quan return -EINVAL; 863e098bc96SEvan Quan } 864e098bc96SEvan Quan 86579af0681SXiaojian Du if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 86679af0681SXiaojian Du profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 86779af0681SXiaojian Du return 0; 86879af0681SXiaojian Du 869e098bc96SEvan Quan /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 870e098bc96SEvan Quan workload_type = smu_cmn_to_asic_specific_index(smu, 871e098bc96SEvan Quan CMN2ASIC_MAPPING_WORKLOAD, 872e098bc96SEvan Quan profile_mode); 873e098bc96SEvan Quan if (workload_type < 0) { 874e098bc96SEvan Quan /* 875e098bc96SEvan Quan * TODO: If some case need switch to powersave/default power mode 876e098bc96SEvan Quan * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving. 877e098bc96SEvan Quan */ 8789d489afdSAlex Deucher dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode); 879e098bc96SEvan Quan return -EINVAL; 880e098bc96SEvan Quan } 881e098bc96SEvan Quan 882e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 883e098bc96SEvan Quan 1 << workload_type, 884e098bc96SEvan Quan NULL); 885e098bc96SEvan Quan if (ret) { 886e098bc96SEvan Quan dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 887e098bc96SEvan Quan return ret; 888e098bc96SEvan Quan } 889e098bc96SEvan Quan 890e098bc96SEvan Quan smu->power_profile_mode = profile_mode; 891e098bc96SEvan Quan 892e098bc96SEvan Quan return 0; 893e098bc96SEvan Quan } 894e098bc96SEvan Quan 895e098bc96SEvan Quan static int renoir_set_peak_clock_by_device(struct smu_context *smu) 896e098bc96SEvan Quan { 897e098bc96SEvan Quan int ret = 0; 898e098bc96SEvan Quan uint32_t sclk_freq = 0, uclk_freq = 0; 899e098bc96SEvan Quan 900e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq); 901e098bc96SEvan Quan if (ret) 902e098bc96SEvan Quan return ret; 903e098bc96SEvan Quan 904e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq); 905e098bc96SEvan Quan if (ret) 906e098bc96SEvan Quan return ret; 907e098bc96SEvan Quan 908e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq); 909e098bc96SEvan Quan if (ret) 910e098bc96SEvan Quan return ret; 911e098bc96SEvan Quan 912e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq); 913e098bc96SEvan Quan if (ret) 914e098bc96SEvan Quan return ret; 915e098bc96SEvan Quan 916e098bc96SEvan Quan return ret; 917e098bc96SEvan Quan } 918e098bc96SEvan Quan 919e098bc96SEvan Quan static int renoir_set_performance_level(struct smu_context *smu, 920e098bc96SEvan Quan enum amd_dpm_forced_level level) 921e098bc96SEvan Quan { 922e098bc96SEvan Quan int ret = 0; 923e098bc96SEvan Quan uint32_t sclk_mask, mclk_mask, soc_mask; 924e098bc96SEvan Quan 925e098bc96SEvan Quan switch (level) { 926e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_HIGH: 92708da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 92808da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 92908da4fcdSXiaojian Du 930e098bc96SEvan Quan ret = renoir_force_dpm_limit_value(smu, true); 931e098bc96SEvan Quan break; 932e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_LOW: 93308da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 93408da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 93508da4fcdSXiaojian Du 936e098bc96SEvan Quan ret = renoir_force_dpm_limit_value(smu, false); 937e098bc96SEvan Quan break; 938e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_AUTO: 93908da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 94008da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 94108da4fcdSXiaojian Du 942e098bc96SEvan Quan ret = renoir_unforce_dpm_levels(smu); 943e098bc96SEvan Quan break; 94492e00593SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 94508da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 94608da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 94708da4fcdSXiaojian Du 94892e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 94992e00593SEvan Quan SMU_MSG_SetHardMinGfxClk, 95092e00593SEvan Quan RENOIR_UMD_PSTATE_GFXCLK, 95192e00593SEvan Quan NULL); 95292e00593SEvan Quan if (ret) 95392e00593SEvan Quan return ret; 95492e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 95592e00593SEvan Quan SMU_MSG_SetHardMinFclkByFreq, 95692e00593SEvan Quan RENOIR_UMD_PSTATE_FCLK, 95792e00593SEvan Quan NULL); 95892e00593SEvan Quan if (ret) 95992e00593SEvan Quan return ret; 96092e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 96192e00593SEvan Quan SMU_MSG_SetHardMinSocclkByFreq, 96292e00593SEvan Quan RENOIR_UMD_PSTATE_SOCCLK, 96392e00593SEvan Quan NULL); 96492e00593SEvan Quan if (ret) 96592e00593SEvan Quan return ret; 96692e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 96792e00593SEvan Quan SMU_MSG_SetHardMinVcn, 96892e00593SEvan Quan RENOIR_UMD_PSTATE_VCNCLK, 96992e00593SEvan Quan NULL); 97092e00593SEvan Quan if (ret) 97192e00593SEvan Quan return ret; 97292e00593SEvan Quan 97392e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 97492e00593SEvan Quan SMU_MSG_SetSoftMaxGfxClk, 97592e00593SEvan Quan RENOIR_UMD_PSTATE_GFXCLK, 97692e00593SEvan Quan NULL); 97792e00593SEvan Quan if (ret) 97892e00593SEvan Quan return ret; 97992e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 98092e00593SEvan Quan SMU_MSG_SetSoftMaxFclkByFreq, 98192e00593SEvan Quan RENOIR_UMD_PSTATE_FCLK, 98292e00593SEvan Quan NULL); 98392e00593SEvan Quan if (ret) 98492e00593SEvan Quan return ret; 98592e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 98692e00593SEvan Quan SMU_MSG_SetSoftMaxSocclkByFreq, 98792e00593SEvan Quan RENOIR_UMD_PSTATE_SOCCLK, 98892e00593SEvan Quan NULL); 98992e00593SEvan Quan if (ret) 99092e00593SEvan Quan return ret; 99192e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 99292e00593SEvan Quan SMU_MSG_SetSoftMaxVcn, 99392e00593SEvan Quan RENOIR_UMD_PSTATE_VCNCLK, 99492e00593SEvan Quan NULL); 99592e00593SEvan Quan if (ret) 99692e00593SEvan Quan return ret; 99792e00593SEvan Quan break; 998e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 999e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 100008da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 100108da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 100208da4fcdSXiaojian Du 1003e098bc96SEvan Quan ret = renoir_get_profiling_clk_mask(smu, level, 1004e098bc96SEvan Quan &sclk_mask, 1005e098bc96SEvan Quan &mclk_mask, 1006e098bc96SEvan Quan &soc_mask); 1007e098bc96SEvan Quan if (ret) 1008e098bc96SEvan Quan return ret; 1009e098bc96SEvan Quan renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); 1010e098bc96SEvan Quan renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 1011e098bc96SEvan Quan renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1012e098bc96SEvan Quan break; 1013e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 101408da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 101508da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 101608da4fcdSXiaojian Du 1017e098bc96SEvan Quan ret = renoir_set_peak_clock_by_device(smu); 1018e098bc96SEvan Quan break; 1019e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_MANUAL: 1020e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1021e098bc96SEvan Quan default: 1022e098bc96SEvan Quan break; 1023e098bc96SEvan Quan } 1024e098bc96SEvan Quan return ret; 1025e098bc96SEvan Quan } 1026e098bc96SEvan Quan 1027e098bc96SEvan Quan /* save watermark settings into pplib smu structure, 1028e098bc96SEvan Quan * also pass data to smu controller 1029e098bc96SEvan Quan */ 1030e098bc96SEvan Quan static int renoir_set_watermarks_table( 1031e098bc96SEvan Quan struct smu_context *smu, 10327b9c7e30SEvan Quan struct pp_smu_wm_range_sets *clock_ranges) 1033e098bc96SEvan Quan { 1034e098bc96SEvan Quan Watermarks_t *table = smu->smu_table.watermarks_table; 1035e098bc96SEvan Quan int ret = 0; 1036e098bc96SEvan Quan int i; 1037e098bc96SEvan Quan 1038e098bc96SEvan Quan if (clock_ranges) { 10397b9c7e30SEvan Quan if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 10407b9c7e30SEvan Quan clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1041e098bc96SEvan Quan return -EINVAL; 1042e098bc96SEvan Quan 1043e098bc96SEvan Quan /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/ 10447b9c7e30SEvan Quan for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1045e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MinClock = 10467b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1047e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MaxClock = 10487b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1049e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MinMclk = 10507b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1051e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 10527b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 10537b9c7e30SEvan Quan 10547b9c7e30SEvan Quan table->WatermarkRow[WM_DCFCLK][i].WmSetting = 10557b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].wm_inst; 1056ce2c0006SEvan Quan table->WatermarkRow[WM_DCFCLK][i].WmType = 1057ce2c0006SEvan Quan clock_ranges->reader_wm_sets[i].wm_type; 1058e098bc96SEvan Quan } 1059e098bc96SEvan Quan 10607b9c7e30SEvan Quan for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1061e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MinClock = 10627b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1063e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MaxClock = 10647b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1065e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MinMclk = 10667b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1067e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 10687b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 10697b9c7e30SEvan Quan 10707b9c7e30SEvan Quan table->WatermarkRow[WM_SOCCLK][i].WmSetting = 10717b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].wm_inst; 1072ce2c0006SEvan Quan table->WatermarkRow[WM_SOCCLK][i].WmType = 1073ce2c0006SEvan Quan clock_ranges->writer_wm_sets[i].wm_type; 1074e098bc96SEvan Quan } 1075e098bc96SEvan Quan 1076e098bc96SEvan Quan smu->watermarks_bitmap |= WATERMARKS_EXIST; 1077e098bc96SEvan Quan } 1078e098bc96SEvan Quan 1079e098bc96SEvan Quan /* pass data to smu controller */ 1080e098bc96SEvan Quan if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1081e098bc96SEvan Quan !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1082e098bc96SEvan Quan ret = smu_cmn_write_watermarks_table(smu); 1083e098bc96SEvan Quan if (ret) { 1084e098bc96SEvan Quan dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1085e098bc96SEvan Quan return ret; 1086e098bc96SEvan Quan } 1087e098bc96SEvan Quan smu->watermarks_bitmap |= WATERMARKS_LOADED; 1088e098bc96SEvan Quan } 1089e098bc96SEvan Quan 1090e098bc96SEvan Quan return 0; 1091e098bc96SEvan Quan } 1092e098bc96SEvan Quan 1093e098bc96SEvan Quan static int renoir_get_power_profile_mode(struct smu_context *smu, 1094e098bc96SEvan Quan char *buf) 1095e098bc96SEvan Quan { 1096e098bc96SEvan Quan static const char *profile_name[] = { 1097e098bc96SEvan Quan "BOOTUP_DEFAULT", 1098e098bc96SEvan Quan "3D_FULL_SCREEN", 1099e098bc96SEvan Quan "POWER_SAVING", 1100e098bc96SEvan Quan "VIDEO", 1101e098bc96SEvan Quan "VR", 1102e098bc96SEvan Quan "COMPUTE", 1103e098bc96SEvan Quan "CUSTOM"}; 1104e098bc96SEvan Quan uint32_t i, size = 0; 1105e098bc96SEvan Quan int16_t workload_type = 0; 1106e098bc96SEvan Quan 1107e098bc96SEvan Quan if (!buf) 1108e098bc96SEvan Quan return -EINVAL; 1109e098bc96SEvan Quan 1110e098bc96SEvan Quan for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1111e098bc96SEvan Quan /* 1112e098bc96SEvan Quan * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1113e098bc96SEvan Quan * Not all profile modes are supported on arcturus. 1114e098bc96SEvan Quan */ 1115e098bc96SEvan Quan workload_type = smu_cmn_to_asic_specific_index(smu, 1116e098bc96SEvan Quan CMN2ASIC_MAPPING_WORKLOAD, 1117e098bc96SEvan Quan i); 1118e098bc96SEvan Quan if (workload_type < 0) 1119e098bc96SEvan Quan continue; 1120e098bc96SEvan Quan 1121e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 1122e098bc96SEvan Quan i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1123e098bc96SEvan Quan } 1124e098bc96SEvan Quan 1125e098bc96SEvan Quan return size; 1126e098bc96SEvan Quan } 1127e098bc96SEvan Quan 112822ca75eaSAlex Deucher static int renoir_get_smu_metrics_data(struct smu_context *smu, 112922ca75eaSAlex Deucher MetricsMember_t member, 113022ca75eaSAlex Deucher uint32_t *value) 113122ca75eaSAlex Deucher { 113222ca75eaSAlex Deucher struct smu_table_context *smu_table = &smu->smu_table; 113322ca75eaSAlex Deucher 113422ca75eaSAlex Deucher SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 113522ca75eaSAlex Deucher int ret = 0; 113622ca75eaSAlex Deucher 113722ca75eaSAlex Deucher mutex_lock(&smu->metrics_lock); 113822ca75eaSAlex Deucher 113922ca75eaSAlex Deucher ret = smu_cmn_get_metrics_table_locked(smu, 114022ca75eaSAlex Deucher NULL, 114122ca75eaSAlex Deucher false); 114222ca75eaSAlex Deucher if (ret) { 114322ca75eaSAlex Deucher mutex_unlock(&smu->metrics_lock); 114422ca75eaSAlex Deucher return ret; 114522ca75eaSAlex Deucher } 114622ca75eaSAlex Deucher 114722ca75eaSAlex Deucher switch (member) { 114822ca75eaSAlex Deucher case METRICS_AVERAGE_GFXCLK: 114922ca75eaSAlex Deucher *value = metrics->ClockFrequency[CLOCK_GFXCLK]; 115022ca75eaSAlex Deucher break; 115122ca75eaSAlex Deucher case METRICS_AVERAGE_SOCCLK: 115222ca75eaSAlex Deucher *value = metrics->ClockFrequency[CLOCK_SOCCLK]; 115322ca75eaSAlex Deucher break; 115422ca75eaSAlex Deucher case METRICS_AVERAGE_UCLK: 115522ca75eaSAlex Deucher *value = metrics->ClockFrequency[CLOCK_FCLK]; 115622ca75eaSAlex Deucher break; 115722ca75eaSAlex Deucher case METRICS_AVERAGE_GFXACTIVITY: 115822ca75eaSAlex Deucher *value = metrics->AverageGfxActivity / 100; 115922ca75eaSAlex Deucher break; 116022ca75eaSAlex Deucher case METRICS_AVERAGE_VCNACTIVITY: 116122ca75eaSAlex Deucher *value = metrics->AverageUvdActivity / 100; 116222ca75eaSAlex Deucher break; 116322ca75eaSAlex Deucher case METRICS_AVERAGE_SOCKETPOWER: 1164137aac26SAlex Deucher *value = (metrics->CurrentSocketPower << 8) / 1000; 116522ca75eaSAlex Deucher break; 116622ca75eaSAlex Deucher case METRICS_TEMPERATURE_EDGE: 116722ca75eaSAlex Deucher *value = (metrics->GfxTemperature / 100) * 116822ca75eaSAlex Deucher SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 116922ca75eaSAlex Deucher break; 117022ca75eaSAlex Deucher case METRICS_TEMPERATURE_HOTSPOT: 117122ca75eaSAlex Deucher *value = (metrics->SocTemperature / 100) * 117222ca75eaSAlex Deucher SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 117322ca75eaSAlex Deucher break; 117422ca75eaSAlex Deucher case METRICS_THROTTLER_STATUS: 117522ca75eaSAlex Deucher *value = metrics->ThrottlerStatus; 117622ca75eaSAlex Deucher break; 117722ca75eaSAlex Deucher case METRICS_VOLTAGE_VDDGFX: 117822ca75eaSAlex Deucher *value = metrics->Voltage[0]; 117922ca75eaSAlex Deucher break; 118022ca75eaSAlex Deucher case METRICS_VOLTAGE_VDDSOC: 118122ca75eaSAlex Deucher *value = metrics->Voltage[1]; 118222ca75eaSAlex Deucher break; 11837b32dd0bSSathishkumar S case METRICS_SS_APU_SHARE: 11847b32dd0bSSathishkumar S /* return the percentage of APU power with respect to APU's power limit. 11857b32dd0bSSathishkumar S * percentage is reported, this isn't boost value. Smartshift power 11867b32dd0bSSathishkumar S * boost/shift is only when the percentage is more than 100. 11877b32dd0bSSathishkumar S */ 11887b32dd0bSSathishkumar S if (metrics->StapmOriginalLimit > 0) 11897b32dd0bSSathishkumar S *value = (metrics->ApuPower * 100) / metrics->StapmOriginalLimit; 11907b32dd0bSSathishkumar S else 11917b32dd0bSSathishkumar S *value = 0; 11927b32dd0bSSathishkumar S break; 11937b32dd0bSSathishkumar S case METRICS_SS_DGPU_SHARE: 11947b32dd0bSSathishkumar S /* return the percentage of dGPU power with respect to dGPU's power limit. 11957b32dd0bSSathishkumar S * percentage is reported, this isn't boost value. Smartshift power 11967b32dd0bSSathishkumar S * boost/shift is only when the percentage is more than 100. 11977b32dd0bSSathishkumar S */ 11987b32dd0bSSathishkumar S if ((metrics->dGpuPower > 0) && 11997b32dd0bSSathishkumar S (metrics->StapmCurrentLimit > metrics->StapmOriginalLimit)) 12007b32dd0bSSathishkumar S *value = (metrics->dGpuPower * 100) / 12017b32dd0bSSathishkumar S (metrics->StapmCurrentLimit - metrics->StapmOriginalLimit); 12027b32dd0bSSathishkumar S else 12037b32dd0bSSathishkumar S *value = 0; 12047b32dd0bSSathishkumar S break; 120522ca75eaSAlex Deucher default: 120622ca75eaSAlex Deucher *value = UINT_MAX; 120722ca75eaSAlex Deucher break; 120822ca75eaSAlex Deucher } 120922ca75eaSAlex Deucher 121022ca75eaSAlex Deucher mutex_unlock(&smu->metrics_lock); 121122ca75eaSAlex Deucher 121222ca75eaSAlex Deucher return ret; 121322ca75eaSAlex Deucher } 121422ca75eaSAlex Deucher 1215e098bc96SEvan Quan static int renoir_read_sensor(struct smu_context *smu, 1216e098bc96SEvan Quan enum amd_pp_sensors sensor, 1217e098bc96SEvan Quan void *data, uint32_t *size) 1218e098bc96SEvan Quan { 1219e098bc96SEvan Quan int ret = 0; 1220e098bc96SEvan Quan 1221e098bc96SEvan Quan if (!data || !size) 1222e098bc96SEvan Quan return -EINVAL; 1223e098bc96SEvan Quan 1224e098bc96SEvan Quan mutex_lock(&smu->sensor_lock); 1225e098bc96SEvan Quan switch (sensor) { 1226e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GPU_LOAD: 122722ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu, 122822ca75eaSAlex Deucher METRICS_AVERAGE_GFXACTIVITY, 122922ca75eaSAlex Deucher (uint32_t *)data); 1230e098bc96SEvan Quan *size = 4; 1231e098bc96SEvan Quan break; 123222ca75eaSAlex Deucher case AMDGPU_PP_SENSOR_EDGE_TEMP: 123322ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu, 123422ca75eaSAlex Deucher METRICS_TEMPERATURE_EDGE, 123522ca75eaSAlex Deucher (uint32_t *)data); 123622ca75eaSAlex Deucher *size = 4; 123722ca75eaSAlex Deucher break; 123822ca75eaSAlex Deucher case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 123922ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu, 124022ca75eaSAlex Deucher METRICS_TEMPERATURE_HOTSPOT, 124122ca75eaSAlex Deucher (uint32_t *)data); 1242e098bc96SEvan Quan *size = 4; 1243e098bc96SEvan Quan break; 1244e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GFX_MCLK: 124522ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu, 124622ca75eaSAlex Deucher METRICS_AVERAGE_UCLK, 124722ca75eaSAlex Deucher (uint32_t *)data); 1248e098bc96SEvan Quan *(uint32_t *)data *= 100; 1249e098bc96SEvan Quan *size = 4; 1250e098bc96SEvan Quan break; 1251e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GFX_SCLK: 125222ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu, 125322ca75eaSAlex Deucher METRICS_AVERAGE_GFXCLK, 125422ca75eaSAlex Deucher (uint32_t *)data); 1255e098bc96SEvan Quan *(uint32_t *)data *= 100; 1256e098bc96SEvan Quan *size = 4; 1257e098bc96SEvan Quan break; 125861426114SAlex Deucher case AMDGPU_PP_SENSOR_VDDGFX: 125922ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu, 126022ca75eaSAlex Deucher METRICS_VOLTAGE_VDDGFX, 126122ca75eaSAlex Deucher (uint32_t *)data); 126261426114SAlex Deucher *size = 4; 126361426114SAlex Deucher break; 126461426114SAlex Deucher case AMDGPU_PP_SENSOR_VDDNB: 126522ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu, 126622ca75eaSAlex Deucher METRICS_VOLTAGE_VDDSOC, 126722ca75eaSAlex Deucher (uint32_t *)data); 126861426114SAlex Deucher *size = 4; 126961426114SAlex Deucher break; 1270b49dc928SAlex Deucher case AMDGPU_PP_SENSOR_GPU_POWER: 127122ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu, 127222ca75eaSAlex Deucher METRICS_AVERAGE_SOCKETPOWER, 127322ca75eaSAlex Deucher (uint32_t *)data); 1274b49dc928SAlex Deucher *size = 4; 1275b49dc928SAlex Deucher break; 12767b32dd0bSSathishkumar S case AMDGPU_PP_SENSOR_SS_APU_SHARE: 12777b32dd0bSSathishkumar S ret = renoir_get_smu_metrics_data(smu, 12787b32dd0bSSathishkumar S METRICS_SS_APU_SHARE, 12797b32dd0bSSathishkumar S (uint32_t *)data); 12807b32dd0bSSathishkumar S *size = 4; 12817b32dd0bSSathishkumar S break; 12827b32dd0bSSathishkumar S case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 12837b32dd0bSSathishkumar S ret = renoir_get_smu_metrics_data(smu, 12847b32dd0bSSathishkumar S METRICS_SS_DGPU_SHARE, 12857b32dd0bSSathishkumar S (uint32_t *)data); 12867b32dd0bSSathishkumar S *size = 4; 12877b32dd0bSSathishkumar S break; 1288e098bc96SEvan Quan default: 1289e098bc96SEvan Quan ret = -EOPNOTSUPP; 1290e098bc96SEvan Quan break; 1291e098bc96SEvan Quan } 1292e098bc96SEvan Quan mutex_unlock(&smu->sensor_lock); 1293e098bc96SEvan Quan 1294e098bc96SEvan Quan return ret; 1295e098bc96SEvan Quan } 1296e098bc96SEvan Quan 1297e098bc96SEvan Quan static bool renoir_is_dpm_running(struct smu_context *smu) 1298e098bc96SEvan Quan { 1299e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1300e098bc96SEvan Quan 1301e098bc96SEvan Quan /* 1302e098bc96SEvan Quan * Until now, the pmfw hasn't exported the interface of SMU 1303e098bc96SEvan Quan * feature mask to APU SKU so just force on all the feature 1304e098bc96SEvan Quan * at early initial stage. 1305e098bc96SEvan Quan */ 1306e098bc96SEvan Quan if (adev->in_suspend) 1307e098bc96SEvan Quan return false; 1308e098bc96SEvan Quan else 1309e098bc96SEvan Quan return true; 1310e098bc96SEvan Quan 1311e098bc96SEvan Quan } 1312e098bc96SEvan Quan 1313e098bc96SEvan Quan static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, 1314e098bc96SEvan Quan void **table) 1315e098bc96SEvan Quan { 1316e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 1317d4c9b03fSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics = 1318d4c9b03fSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1319e098bc96SEvan Quan SmuMetrics_t metrics; 1320e098bc96SEvan Quan int ret = 0; 1321e098bc96SEvan Quan 1322e098bc96SEvan Quan ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1323e098bc96SEvan Quan if (ret) 1324e098bc96SEvan Quan return ret; 1325e098bc96SEvan Quan 1326d4c9b03fSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1327e098bc96SEvan Quan 1328e098bc96SEvan Quan gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1329e098bc96SEvan Quan gpu_metrics->temperature_soc = metrics.SocTemperature; 1330e098bc96SEvan Quan memcpy(&gpu_metrics->temperature_core[0], 1331e098bc96SEvan Quan &metrics.CoreTemperature[0], 1332e098bc96SEvan Quan sizeof(uint16_t) * 8); 1333e098bc96SEvan Quan gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1334e098bc96SEvan Quan gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1335e098bc96SEvan Quan 1336e098bc96SEvan Quan gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1337e098bc96SEvan Quan gpu_metrics->average_mm_activity = metrics.AverageUvdActivity; 1338e098bc96SEvan Quan 1339e098bc96SEvan Quan gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1340e098bc96SEvan Quan gpu_metrics->average_cpu_power = metrics.Power[0]; 1341e098bc96SEvan Quan gpu_metrics->average_soc_power = metrics.Power[1]; 1342e098bc96SEvan Quan memcpy(&gpu_metrics->average_core_power[0], 1343e098bc96SEvan Quan &metrics.CorePower[0], 1344e098bc96SEvan Quan sizeof(uint16_t) * 8); 1345e098bc96SEvan Quan 1346e098bc96SEvan Quan gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1347e098bc96SEvan Quan gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1348e098bc96SEvan Quan gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency; 1349e098bc96SEvan Quan gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency; 1350e098bc96SEvan Quan 1351e098bc96SEvan Quan gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK]; 1352e098bc96SEvan Quan gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK]; 1353e098bc96SEvan Quan gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK]; 1354e098bc96SEvan Quan gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK]; 1355e098bc96SEvan Quan gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK]; 1356e098bc96SEvan Quan gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK]; 1357e098bc96SEvan Quan memcpy(&gpu_metrics->current_coreclk[0], 1358e098bc96SEvan Quan &metrics.CoreFrequency[0], 1359e098bc96SEvan Quan sizeof(uint16_t) * 8); 1360e098bc96SEvan Quan gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1361e098bc96SEvan Quan gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1362e098bc96SEvan Quan 1363e098bc96SEvan Quan gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1364d4c9b03fSGraham Sider gpu_metrics->indep_throttle_status = 1365d4c9b03fSGraham Sider smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1366d4c9b03fSGraham Sider renoir_throttler_map); 1367e098bc96SEvan Quan 1368e098bc96SEvan Quan gpu_metrics->fan_pwm = metrics.FanPwm; 1369e098bc96SEvan Quan 1370de4b7cd8SKevin Wang gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1371de4b7cd8SKevin Wang 1372e098bc96SEvan Quan *table = (void *)gpu_metrics; 1373e098bc96SEvan Quan 1374d4c9b03fSGraham Sider return sizeof(struct gpu_metrics_v2_2); 1375e098bc96SEvan Quan } 1376e098bc96SEvan Quan 13778279bb4eSPrike Liang static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) 13788279bb4eSPrike Liang { 13798279bb4eSPrike Liang 1380d96dd7efSPrike Liang return 0; 13818279bb4eSPrike Liang } 13828279bb4eSPrike Liang 1383e098bc96SEvan Quan static const struct pptable_funcs renoir_ppt_funcs = { 1384e098bc96SEvan Quan .set_power_state = NULL, 1385e098bc96SEvan Quan .print_clk_levels = renoir_print_clk_levels, 1386e098bc96SEvan Quan .get_current_power_state = renoir_get_current_power_state, 1387e098bc96SEvan Quan .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable, 1388e098bc96SEvan Quan .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable, 1389e098bc96SEvan Quan .force_clk_levels = renoir_force_clk_levels, 1390e098bc96SEvan Quan .set_power_profile_mode = renoir_set_power_profile_mode, 1391e098bc96SEvan Quan .set_performance_level = renoir_set_performance_level, 1392e098bc96SEvan Quan .get_dpm_clock_table = renoir_get_dpm_clock_table, 1393e098bc96SEvan Quan .set_watermarks_table = renoir_set_watermarks_table, 1394e098bc96SEvan Quan .get_power_profile_mode = renoir_get_power_profile_mode, 1395e098bc96SEvan Quan .read_sensor = renoir_read_sensor, 1396e098bc96SEvan Quan .check_fw_status = smu_v12_0_check_fw_status, 1397e098bc96SEvan Quan .check_fw_version = smu_v12_0_check_fw_version, 1398e098bc96SEvan Quan .powergate_sdma = smu_v12_0_powergate_sdma, 1399e098bc96SEvan Quan .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1400e098bc96SEvan Quan .send_smc_msg = smu_cmn_send_smc_msg, 1401e098bc96SEvan Quan .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, 1402e098bc96SEvan Quan .gfx_off_control = smu_v12_0_gfx_off_control, 1403e098bc96SEvan Quan .get_gfx_off_status = smu_v12_0_get_gfxoff_status, 1404e098bc96SEvan Quan .init_smc_tables = renoir_init_smc_tables, 1405e098bc96SEvan Quan .fini_smc_tables = smu_v12_0_fini_smc_tables, 1406e098bc96SEvan Quan .set_default_dpm_table = smu_v12_0_set_default_dpm_tables, 1407e098bc96SEvan Quan .get_enabled_mask = smu_cmn_get_enabled_mask, 1408e098bc96SEvan Quan .feature_is_enabled = smu_cmn_feature_is_enabled, 1409e098bc96SEvan Quan .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1410e098bc96SEvan Quan .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq, 1411e098bc96SEvan Quan .mode2_reset = smu_v12_0_mode2_reset, 1412e098bc96SEvan Quan .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, 1413e098bc96SEvan Quan .set_driver_table_location = smu_v12_0_set_driver_table_location, 1414e098bc96SEvan Quan .is_dpm_running = renoir_is_dpm_running, 1415e098bc96SEvan Quan .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1416e098bc96SEvan Quan .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1417e098bc96SEvan Quan .get_gpu_metrics = renoir_get_gpu_metrics, 14188279bb4eSPrike Liang .gfx_state_change_set = renoir_gfx_state_change_set, 1419ca55f459SXiaojian Du .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters, 1420ca55f459SXiaojian Du .od_edit_dpm_table = renoir_od_edit_dpm_table, 1421eb607a00SXiaojian Du .get_vbios_bootup_values = smu_v12_0_get_vbios_bootup_values, 1422e098bc96SEvan Quan }; 1423e098bc96SEvan Quan 1424e098bc96SEvan Quan void renoir_set_ppt_funcs(struct smu_context *smu) 1425e098bc96SEvan Quan { 1426e098bc96SEvan Quan smu->ppt_funcs = &renoir_ppt_funcs; 1427e098bc96SEvan Quan smu->message_map = renoir_message_map; 1428e098bc96SEvan Quan smu->clock_map = renoir_clk_map; 1429e098bc96SEvan Quan smu->table_map = renoir_table_map; 1430e098bc96SEvan Quan smu->workload_map = renoir_workload_map; 1431e098bc96SEvan Quan smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; 1432e098bc96SEvan Quan smu->is_apu = true; 1433e098bc96SEvan Quan } 1434