1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2019 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan */ 23e098bc96SEvan Quan 24e098bc96SEvan Quan #define SWSMU_CODE_LAYER_L2 25e098bc96SEvan Quan 26e098bc96SEvan Quan #include "amdgpu.h" 27e098bc96SEvan Quan #include "amdgpu_smu.h" 28e098bc96SEvan Quan #include "smu_v12_0_ppsmc.h" 29e098bc96SEvan Quan #include "smu12_driver_if.h" 30e098bc96SEvan Quan #include "smu_v12_0.h" 31e098bc96SEvan Quan #include "renoir_ppt.h" 32e098bc96SEvan Quan #include "smu_cmn.h" 33e098bc96SEvan Quan 34e098bc96SEvan Quan /* 35e098bc96SEvan Quan * DO NOT use these for err/warn/info/debug messages. 36e098bc96SEvan Quan * Use dev_err, dev_warn, dev_info and dev_dbg instead. 37e098bc96SEvan Quan * They are more MGPU friendly. 38e098bc96SEvan Quan */ 39e098bc96SEvan Quan #undef pr_err 40e098bc96SEvan Quan #undef pr_warn 41e098bc96SEvan Quan #undef pr_info 42e098bc96SEvan Quan #undef pr_debug 43e098bc96SEvan Quan 44e098bc96SEvan Quan static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { 45e098bc96SEvan Quan MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 46e098bc96SEvan Quan MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 47e098bc96SEvan Quan MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 48e098bc96SEvan Quan MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1), 49e098bc96SEvan Quan MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1), 50e098bc96SEvan Quan MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1), 51e098bc96SEvan Quan MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 52e098bc96SEvan Quan MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 53e098bc96SEvan Quan MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 54e098bc96SEvan Quan MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 55e098bc96SEvan Quan MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1), 56e098bc96SEvan Quan MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1), 57e098bc96SEvan Quan MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1), 58e098bc96SEvan Quan MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 59e098bc96SEvan Quan MSG_MAP(Spare1, PPSMC_MSG_spare1, 1), 60e098bc96SEvan Quan MSG_MAP(Spare2, PPSMC_MSG_spare2, 1), 61e098bc96SEvan Quan MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1), 62e098bc96SEvan Quan MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1), 63e098bc96SEvan Quan MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1), 64e098bc96SEvan Quan MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1), 65e098bc96SEvan Quan MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1), 66e098bc96SEvan Quan MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1), 67e098bc96SEvan Quan MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1), 68e098bc96SEvan Quan MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 69e098bc96SEvan Quan MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 70e098bc96SEvan Quan MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 71e098bc96SEvan Quan MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 72e098bc96SEvan Quan MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 73e098bc96SEvan Quan MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1), 74e098bc96SEvan Quan MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1), 75e098bc96SEvan Quan MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 76e098bc96SEvan Quan MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1), 77e098bc96SEvan Quan MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1), 78e098bc96SEvan Quan MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1), 79e098bc96SEvan Quan MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1), 80e098bc96SEvan Quan MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1), 81e098bc96SEvan Quan MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1), 82e098bc96SEvan Quan MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 83e098bc96SEvan Quan MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1), 84e098bc96SEvan Quan MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 85e098bc96SEvan Quan MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 86e098bc96SEvan Quan MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1), 87e098bc96SEvan Quan MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1), 88e098bc96SEvan Quan MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1), 89e098bc96SEvan Quan MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1), 90e098bc96SEvan Quan MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 91e098bc96SEvan Quan MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 92e098bc96SEvan Quan MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 93e098bc96SEvan Quan MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 94e098bc96SEvan Quan MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 95e098bc96SEvan Quan MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1), 96e098bc96SEvan Quan MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1), 97e098bc96SEvan Quan MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1), 98e098bc96SEvan Quan MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 99e098bc96SEvan Quan MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1), 100e098bc96SEvan Quan MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1), 101e098bc96SEvan Quan MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 102e098bc96SEvan Quan MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 103e098bc96SEvan Quan MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1), 104e098bc96SEvan Quan MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1), 105e098bc96SEvan Quan MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 106e098bc96SEvan Quan }; 107e098bc96SEvan Quan 108e098bc96SEvan Quan static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { 109e098bc96SEvan Quan CLK_MAP(GFXCLK, CLOCK_GFXCLK), 110e098bc96SEvan Quan CLK_MAP(SCLK, CLOCK_GFXCLK), 111e098bc96SEvan Quan CLK_MAP(SOCCLK, CLOCK_SOCCLK), 112e098bc96SEvan Quan CLK_MAP(UCLK, CLOCK_FCLK), 113e098bc96SEvan Quan CLK_MAP(MCLK, CLOCK_FCLK), 114e098bc96SEvan Quan }; 115e098bc96SEvan Quan 116e098bc96SEvan Quan static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { 117e098bc96SEvan Quan TAB_MAP_VALID(WATERMARKS), 118e098bc96SEvan Quan TAB_MAP_INVALID(CUSTOM_DPM), 119e098bc96SEvan Quan TAB_MAP_VALID(DPMCLOCKS), 120e098bc96SEvan Quan TAB_MAP_VALID(SMU_METRICS), 121e098bc96SEvan Quan }; 122e098bc96SEvan Quan 123e098bc96SEvan Quan static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 124e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 125e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 126e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 127e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 128e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 129e098bc96SEvan Quan }; 130e098bc96SEvan Quan 131e098bc96SEvan Quan static int renoir_init_smc_tables(struct smu_context *smu) 132e098bc96SEvan Quan { 133e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 134e098bc96SEvan Quan struct smu_table *tables = smu_table->tables; 135e098bc96SEvan Quan 136e098bc96SEvan Quan SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 137e098bc96SEvan Quan PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 138e098bc96SEvan Quan SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 139e098bc96SEvan Quan PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 140e098bc96SEvan Quan SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 141e098bc96SEvan Quan PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 142e098bc96SEvan Quan 143e098bc96SEvan Quan smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 144e098bc96SEvan Quan if (!smu_table->clocks_table) 145e098bc96SEvan Quan goto err0_out; 146e098bc96SEvan Quan 147e098bc96SEvan Quan smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 148e098bc96SEvan Quan if (!smu_table->metrics_table) 149e098bc96SEvan Quan goto err1_out; 150e098bc96SEvan Quan smu_table->metrics_time = 0; 151e098bc96SEvan Quan 152e098bc96SEvan Quan smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 153e098bc96SEvan Quan if (!smu_table->watermarks_table) 154e098bc96SEvan Quan goto err2_out; 155e098bc96SEvan Quan 156e098bc96SEvan Quan smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); 157e098bc96SEvan Quan smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 158e098bc96SEvan Quan if (!smu_table->gpu_metrics_table) 159e098bc96SEvan Quan goto err3_out; 160e098bc96SEvan Quan 161e098bc96SEvan Quan return 0; 162e098bc96SEvan Quan 163e098bc96SEvan Quan err3_out: 164e098bc96SEvan Quan kfree(smu_table->watermarks_table); 165e098bc96SEvan Quan err2_out: 166e098bc96SEvan Quan kfree(smu_table->metrics_table); 167e098bc96SEvan Quan err1_out: 168e098bc96SEvan Quan kfree(smu_table->clocks_table); 169e098bc96SEvan Quan err0_out: 170e098bc96SEvan Quan return -ENOMEM; 171e098bc96SEvan Quan } 172e098bc96SEvan Quan 173e098bc96SEvan Quan /** 174e098bc96SEvan Quan * This interface just for getting uclk ultimate freq and should't introduce 175e098bc96SEvan Quan * other likewise function result in overmuch callback. 176e098bc96SEvan Quan */ 177e098bc96SEvan Quan static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 178e098bc96SEvan Quan uint32_t dpm_level, uint32_t *freq) 179e098bc96SEvan Quan { 180e098bc96SEvan Quan DpmClocks_t *clk_table = smu->smu_table.clocks_table; 181e098bc96SEvan Quan 182e098bc96SEvan Quan if (!clk_table || clk_type >= SMU_CLK_COUNT) 183e098bc96SEvan Quan return -EINVAL; 184e098bc96SEvan Quan 185e098bc96SEvan Quan switch (clk_type) { 186e098bc96SEvan Quan case SMU_SOCCLK: 187e098bc96SEvan Quan if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) 188e098bc96SEvan Quan return -EINVAL; 189e098bc96SEvan Quan *freq = clk_table->SocClocks[dpm_level].Freq; 190e098bc96SEvan Quan break; 191e098bc96SEvan Quan case SMU_MCLK: 192e098bc96SEvan Quan if (dpm_level >= NUM_FCLK_DPM_LEVELS) 193e098bc96SEvan Quan return -EINVAL; 194e098bc96SEvan Quan *freq = clk_table->FClocks[dpm_level].Freq; 195e098bc96SEvan Quan break; 196e098bc96SEvan Quan case SMU_DCEFCLK: 197e098bc96SEvan Quan if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) 198e098bc96SEvan Quan return -EINVAL; 199e098bc96SEvan Quan *freq = clk_table->DcfClocks[dpm_level].Freq; 200e098bc96SEvan Quan break; 201e098bc96SEvan Quan case SMU_FCLK: 202e098bc96SEvan Quan if (dpm_level >= NUM_FCLK_DPM_LEVELS) 203e098bc96SEvan Quan return -EINVAL; 204e098bc96SEvan Quan *freq = clk_table->FClocks[dpm_level].Freq; 205e098bc96SEvan Quan break; 206e098bc96SEvan Quan default: 207e098bc96SEvan Quan return -EINVAL; 208e098bc96SEvan Quan } 209e098bc96SEvan Quan 210e098bc96SEvan Quan return 0; 211e098bc96SEvan Quan } 212e098bc96SEvan Quan 213e098bc96SEvan Quan static int renoir_get_profiling_clk_mask(struct smu_context *smu, 214e098bc96SEvan Quan enum amd_dpm_forced_level level, 215e098bc96SEvan Quan uint32_t *sclk_mask, 216e098bc96SEvan Quan uint32_t *mclk_mask, 217e098bc96SEvan Quan uint32_t *soc_mask) 218e098bc96SEvan Quan { 219e098bc96SEvan Quan 220e098bc96SEvan Quan if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 221e098bc96SEvan Quan if (sclk_mask) 222e098bc96SEvan Quan *sclk_mask = 0; 223e098bc96SEvan Quan } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 224e098bc96SEvan Quan if (mclk_mask) 225e098bc96SEvan Quan *mclk_mask = 0; 226e098bc96SEvan Quan } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 227e098bc96SEvan Quan if(sclk_mask) 228e098bc96SEvan Quan /* The sclk as gfxclk and has three level about max/min/current */ 229e098bc96SEvan Quan *sclk_mask = 3 - 1; 230e098bc96SEvan Quan 231e098bc96SEvan Quan if(mclk_mask) 232e098bc96SEvan Quan *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; 233e098bc96SEvan Quan 234e098bc96SEvan Quan if(soc_mask) 235e098bc96SEvan Quan *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; 236e098bc96SEvan Quan } 237e098bc96SEvan Quan 238e098bc96SEvan Quan return 0; 239e098bc96SEvan Quan } 240e098bc96SEvan Quan 241e098bc96SEvan Quan static int renoir_get_dpm_ultimate_freq(struct smu_context *smu, 242e098bc96SEvan Quan enum smu_clk_type clk_type, 243e098bc96SEvan Quan uint32_t *min, 244e098bc96SEvan Quan uint32_t *max) 245e098bc96SEvan Quan { 246e098bc96SEvan Quan int ret = 0; 247e098bc96SEvan Quan uint32_t mclk_mask, soc_mask; 248e098bc96SEvan Quan uint32_t clock_limit; 249e098bc96SEvan Quan 250e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 251e098bc96SEvan Quan switch (clk_type) { 252e098bc96SEvan Quan case SMU_MCLK: 253e098bc96SEvan Quan case SMU_UCLK: 254e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.uclk; 255e098bc96SEvan Quan break; 256e098bc96SEvan Quan case SMU_GFXCLK: 257e098bc96SEvan Quan case SMU_SCLK: 258e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.gfxclk; 259e098bc96SEvan Quan break; 260e098bc96SEvan Quan case SMU_SOCCLK: 261e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.socclk; 262e098bc96SEvan Quan break; 263e098bc96SEvan Quan default: 264e098bc96SEvan Quan clock_limit = 0; 265e098bc96SEvan Quan break; 266e098bc96SEvan Quan } 267e098bc96SEvan Quan 268e098bc96SEvan Quan /* clock in Mhz unit */ 269e098bc96SEvan Quan if (min) 270e098bc96SEvan Quan *min = clock_limit / 100; 271e098bc96SEvan Quan if (max) 272e098bc96SEvan Quan *max = clock_limit / 100; 273e098bc96SEvan Quan 274e098bc96SEvan Quan return 0; 275e098bc96SEvan Quan } 276e098bc96SEvan Quan 277e098bc96SEvan Quan if (max) { 278e098bc96SEvan Quan ret = renoir_get_profiling_clk_mask(smu, 279e098bc96SEvan Quan AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 280e098bc96SEvan Quan NULL, 281e098bc96SEvan Quan &mclk_mask, 282e098bc96SEvan Quan &soc_mask); 283e098bc96SEvan Quan if (ret) 284e098bc96SEvan Quan goto failed; 285e098bc96SEvan Quan 286e098bc96SEvan Quan switch (clk_type) { 287e098bc96SEvan Quan case SMU_GFXCLK: 288e098bc96SEvan Quan case SMU_SCLK: 289e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max); 290e098bc96SEvan Quan if (ret) { 291e098bc96SEvan Quan dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n"); 292e098bc96SEvan Quan goto failed; 293e098bc96SEvan Quan } 294e098bc96SEvan Quan break; 295e098bc96SEvan Quan case SMU_UCLK: 296e098bc96SEvan Quan case SMU_FCLK: 297e098bc96SEvan Quan case SMU_MCLK: 298e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 299e098bc96SEvan Quan if (ret) 300e098bc96SEvan Quan goto failed; 301e098bc96SEvan Quan break; 302e098bc96SEvan Quan case SMU_SOCCLK: 303e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 304e098bc96SEvan Quan if (ret) 305e098bc96SEvan Quan goto failed; 306e098bc96SEvan Quan break; 307e098bc96SEvan Quan default: 308e098bc96SEvan Quan ret = -EINVAL; 309e098bc96SEvan Quan goto failed; 310e098bc96SEvan Quan } 311e098bc96SEvan Quan } 312e098bc96SEvan Quan 313e098bc96SEvan Quan if (min) { 314e098bc96SEvan Quan switch (clk_type) { 315e098bc96SEvan Quan case SMU_GFXCLK: 316e098bc96SEvan Quan case SMU_SCLK: 317e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min); 318e098bc96SEvan Quan if (ret) { 319e098bc96SEvan Quan dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n"); 320e098bc96SEvan Quan goto failed; 321e098bc96SEvan Quan } 322e098bc96SEvan Quan break; 323e098bc96SEvan Quan case SMU_UCLK: 324e098bc96SEvan Quan case SMU_FCLK: 325e098bc96SEvan Quan case SMU_MCLK: 326e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min); 327e098bc96SEvan Quan if (ret) 328e098bc96SEvan Quan goto failed; 329e098bc96SEvan Quan break; 330e098bc96SEvan Quan case SMU_SOCCLK: 331e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min); 332e098bc96SEvan Quan if (ret) 333e098bc96SEvan Quan goto failed; 334e098bc96SEvan Quan break; 335e098bc96SEvan Quan default: 336e098bc96SEvan Quan ret = -EINVAL; 337e098bc96SEvan Quan goto failed; 338e098bc96SEvan Quan } 339e098bc96SEvan Quan } 340e098bc96SEvan Quan failed: 341e098bc96SEvan Quan return ret; 342e098bc96SEvan Quan } 343e098bc96SEvan Quan 344e098bc96SEvan Quan static int renoir_print_clk_levels(struct smu_context *smu, 345e098bc96SEvan Quan enum smu_clk_type clk_type, char *buf) 346e098bc96SEvan Quan { 347e098bc96SEvan Quan int i, size = 0, ret = 0; 348e098bc96SEvan Quan uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; 349e098bc96SEvan Quan SmuMetrics_t metrics; 350e098bc96SEvan Quan bool cur_value_match_level = false; 351e098bc96SEvan Quan 352e098bc96SEvan Quan memset(&metrics, 0, sizeof(metrics)); 353e098bc96SEvan Quan 354e098bc96SEvan Quan ret = smu_cmn_get_metrics_table(smu, &metrics, false); 355e098bc96SEvan Quan if (ret) 356e098bc96SEvan Quan return ret; 357e098bc96SEvan Quan 358e098bc96SEvan Quan switch (clk_type) { 359e098bc96SEvan Quan case SMU_GFXCLK: 360e098bc96SEvan Quan case SMU_SCLK: 361e098bc96SEvan Quan /* retirve table returned paramters unit is MHz */ 362e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; 363e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max); 364e098bc96SEvan Quan if (!ret) { 365e098bc96SEvan Quan /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 366e098bc96SEvan Quan if (cur_value == max) 367e098bc96SEvan Quan i = 2; 368e098bc96SEvan Quan else if (cur_value == min) 369e098bc96SEvan Quan i = 0; 370e098bc96SEvan Quan else 371e098bc96SEvan Quan i = 1; 372e098bc96SEvan Quan 373e098bc96SEvan Quan size += sprintf(buf + size, "0: %uMhz %s\n", min, 374e098bc96SEvan Quan i == 0 ? "*" : ""); 375e098bc96SEvan Quan size += sprintf(buf + size, "1: %uMhz %s\n", 376e098bc96SEvan Quan i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, 377e098bc96SEvan Quan i == 1 ? "*" : ""); 378e098bc96SEvan Quan size += sprintf(buf + size, "2: %uMhz %s\n", max, 379e098bc96SEvan Quan i == 2 ? "*" : ""); 380e098bc96SEvan Quan } 381e098bc96SEvan Quan return size; 382e098bc96SEvan Quan case SMU_SOCCLK: 383e098bc96SEvan Quan count = NUM_SOCCLK_DPM_LEVELS; 384e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; 385e098bc96SEvan Quan break; 386e098bc96SEvan Quan case SMU_MCLK: 387e098bc96SEvan Quan count = NUM_MEMCLK_DPM_LEVELS; 388e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 389e098bc96SEvan Quan break; 390e098bc96SEvan Quan case SMU_DCEFCLK: 391e098bc96SEvan Quan count = NUM_DCFCLK_DPM_LEVELS; 392e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_DCFCLK]; 393e098bc96SEvan Quan break; 394e098bc96SEvan Quan case SMU_FCLK: 395e098bc96SEvan Quan count = NUM_FCLK_DPM_LEVELS; 396e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_FCLK]; 397e098bc96SEvan Quan break; 398e098bc96SEvan Quan default: 399e098bc96SEvan Quan return -EINVAL; 400e098bc96SEvan Quan } 401e098bc96SEvan Quan 402e098bc96SEvan Quan for (i = 0; i < count; i++) { 403e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); 404e098bc96SEvan Quan if (ret) 405e098bc96SEvan Quan return ret; 406e098bc96SEvan Quan if (!value) 407e098bc96SEvan Quan continue; 408e098bc96SEvan Quan size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 409e098bc96SEvan Quan cur_value == value ? "*" : ""); 410e098bc96SEvan Quan if (cur_value == value) 411e098bc96SEvan Quan cur_value_match_level = true; 412e098bc96SEvan Quan } 413e098bc96SEvan Quan 414e098bc96SEvan Quan if (!cur_value_match_level) 415e098bc96SEvan Quan size += sprintf(buf + size, " %uMhz *\n", cur_value); 416e098bc96SEvan Quan 417e098bc96SEvan Quan return size; 418e098bc96SEvan Quan } 419e098bc96SEvan Quan 420e098bc96SEvan Quan static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) 421e098bc96SEvan Quan { 422e098bc96SEvan Quan enum amd_pm_state_type pm_type; 423e098bc96SEvan Quan struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 424e098bc96SEvan Quan 425e098bc96SEvan Quan if (!smu_dpm_ctx->dpm_context || 426e098bc96SEvan Quan !smu_dpm_ctx->dpm_current_power_state) 427e098bc96SEvan Quan return -EINVAL; 428e098bc96SEvan Quan 429e098bc96SEvan Quan switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) { 430e098bc96SEvan Quan case SMU_STATE_UI_LABEL_BATTERY: 431e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_BATTERY; 432e098bc96SEvan Quan break; 433e098bc96SEvan Quan case SMU_STATE_UI_LABEL_BALLANCED: 434e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_BALANCED; 435e098bc96SEvan Quan break; 436e098bc96SEvan Quan case SMU_STATE_UI_LABEL_PERFORMANCE: 437e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_PERFORMANCE; 438e098bc96SEvan Quan break; 439e098bc96SEvan Quan default: 440e098bc96SEvan Quan if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT) 441e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 442e098bc96SEvan Quan else 443e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_DEFAULT; 444e098bc96SEvan Quan break; 445e098bc96SEvan Quan } 446e098bc96SEvan Quan 447e098bc96SEvan Quan return pm_type; 448e098bc96SEvan Quan } 449e098bc96SEvan Quan 450e098bc96SEvan Quan static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 451e098bc96SEvan Quan { 452e098bc96SEvan Quan int ret = 0; 453e098bc96SEvan Quan 454e098bc96SEvan Quan if (enable) { 455e098bc96SEvan Quan /* vcn dpm on is a prerequisite for vcn power gate messages */ 456e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 457e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 458e098bc96SEvan Quan if (ret) 459e098bc96SEvan Quan return ret; 460e098bc96SEvan Quan } 461e098bc96SEvan Quan } else { 462e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 463e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 464e098bc96SEvan Quan if (ret) 465e098bc96SEvan Quan return ret; 466e098bc96SEvan Quan } 467e098bc96SEvan Quan } 468e098bc96SEvan Quan 469e098bc96SEvan Quan return ret; 470e098bc96SEvan Quan } 471e098bc96SEvan Quan 472e098bc96SEvan Quan static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 473e098bc96SEvan Quan { 474e098bc96SEvan Quan int ret = 0; 475e098bc96SEvan Quan 476e098bc96SEvan Quan if (enable) { 477e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 478e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 479e098bc96SEvan Quan if (ret) 480e098bc96SEvan Quan return ret; 481e098bc96SEvan Quan } 482e098bc96SEvan Quan } else { 483e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 484e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 485e098bc96SEvan Quan if (ret) 486e098bc96SEvan Quan return ret; 487e098bc96SEvan Quan } 488e098bc96SEvan Quan } 489e098bc96SEvan Quan 490e098bc96SEvan Quan return ret; 491e098bc96SEvan Quan } 492e098bc96SEvan Quan 493e098bc96SEvan Quan static int renoir_get_current_clk_freq_by_table(struct smu_context *smu, 494e098bc96SEvan Quan enum smu_clk_type clk_type, 495e098bc96SEvan Quan uint32_t *value) 496e098bc96SEvan Quan { 497e098bc96SEvan Quan int ret = 0, clk_id = 0; 498e098bc96SEvan Quan SmuMetrics_t metrics; 499e098bc96SEvan Quan 500e098bc96SEvan Quan ret = smu_cmn_get_metrics_table(smu, &metrics, false); 501e098bc96SEvan Quan if (ret) 502e098bc96SEvan Quan return ret; 503e098bc96SEvan Quan 504e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 505e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 506e098bc96SEvan Quan clk_type); 507e098bc96SEvan Quan if (clk_id < 0) 508e098bc96SEvan Quan return clk_id; 509e098bc96SEvan Quan 510e098bc96SEvan Quan *value = metrics.ClockFrequency[clk_id]; 511e098bc96SEvan Quan 512e098bc96SEvan Quan return ret; 513e098bc96SEvan Quan } 514e098bc96SEvan Quan 515e098bc96SEvan Quan static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest) 516e098bc96SEvan Quan { 517e098bc96SEvan Quan int ret = 0, i = 0; 518e098bc96SEvan Quan uint32_t min_freq, max_freq, force_freq; 519e098bc96SEvan Quan enum smu_clk_type clk_type; 520e098bc96SEvan Quan 521e098bc96SEvan Quan enum smu_clk_type clks[] = { 522e098bc96SEvan Quan SMU_GFXCLK, 523e098bc96SEvan Quan SMU_MCLK, 524e098bc96SEvan Quan SMU_SOCCLK, 525e098bc96SEvan Quan }; 526e098bc96SEvan Quan 527e098bc96SEvan Quan for (i = 0; i < ARRAY_SIZE(clks); i++) { 528e098bc96SEvan Quan clk_type = clks[i]; 529e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 530e098bc96SEvan Quan if (ret) 531e098bc96SEvan Quan return ret; 532e098bc96SEvan Quan 533e098bc96SEvan Quan force_freq = highest ? max_freq : min_freq; 534e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 535e098bc96SEvan Quan if (ret) 536e098bc96SEvan Quan return ret; 537e098bc96SEvan Quan } 538e098bc96SEvan Quan 539e098bc96SEvan Quan return ret; 540e098bc96SEvan Quan } 541e098bc96SEvan Quan 542e098bc96SEvan Quan static int renoir_unforce_dpm_levels(struct smu_context *smu) { 543e098bc96SEvan Quan 544e098bc96SEvan Quan int ret = 0, i = 0; 545e098bc96SEvan Quan uint32_t min_freq, max_freq; 546e098bc96SEvan Quan enum smu_clk_type clk_type; 547e098bc96SEvan Quan 548e098bc96SEvan Quan struct clk_feature_map { 549e098bc96SEvan Quan enum smu_clk_type clk_type; 550e098bc96SEvan Quan uint32_t feature; 551e098bc96SEvan Quan } clk_feature_map[] = { 552e098bc96SEvan Quan {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, 553e098bc96SEvan Quan {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, 554e098bc96SEvan Quan {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 555e098bc96SEvan Quan }; 556e098bc96SEvan Quan 557e098bc96SEvan Quan for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 558e098bc96SEvan Quan if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 559e098bc96SEvan Quan continue; 560e098bc96SEvan Quan 561e098bc96SEvan Quan clk_type = clk_feature_map[i].clk_type; 562e098bc96SEvan Quan 563e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 564e098bc96SEvan Quan if (ret) 565e098bc96SEvan Quan return ret; 566e098bc96SEvan Quan 567e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 568e098bc96SEvan Quan if (ret) 569e098bc96SEvan Quan return ret; 570e098bc96SEvan Quan } 571e098bc96SEvan Quan 572e098bc96SEvan Quan return ret; 573e098bc96SEvan Quan } 574e098bc96SEvan Quan 575e098bc96SEvan Quan static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value) 576e098bc96SEvan Quan { 577e098bc96SEvan Quan int ret = 0; 578e098bc96SEvan Quan SmuMetrics_t metrics; 579e098bc96SEvan Quan 580e098bc96SEvan Quan if (!value) 581e098bc96SEvan Quan return -EINVAL; 582e098bc96SEvan Quan 583e098bc96SEvan Quan ret = smu_cmn_get_metrics_table(smu, &metrics, false); 584e098bc96SEvan Quan if (ret) 585e098bc96SEvan Quan return ret; 586e098bc96SEvan Quan 587e098bc96SEvan Quan *value = (metrics.GfxTemperature / 100) * 588e098bc96SEvan Quan SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 589e098bc96SEvan Quan 590e098bc96SEvan Quan return 0; 591e098bc96SEvan Quan } 592e098bc96SEvan Quan 593e098bc96SEvan Quan static int renoir_get_current_activity_percent(struct smu_context *smu, 594e098bc96SEvan Quan enum amd_pp_sensors sensor, 595e098bc96SEvan Quan uint32_t *value) 596e098bc96SEvan Quan { 597e098bc96SEvan Quan int ret = 0; 598e098bc96SEvan Quan SmuMetrics_t metrics; 599e098bc96SEvan Quan 600e098bc96SEvan Quan if (!value) 601e098bc96SEvan Quan return -EINVAL; 602e098bc96SEvan Quan 603e098bc96SEvan Quan ret = smu_cmn_get_metrics_table(smu, &metrics, false); 604e098bc96SEvan Quan if (ret) 605e098bc96SEvan Quan return ret; 606e098bc96SEvan Quan 607e098bc96SEvan Quan switch (sensor) { 608e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GPU_LOAD: 609e098bc96SEvan Quan *value = metrics.AverageGfxActivity / 100; 610e098bc96SEvan Quan break; 611e098bc96SEvan Quan default: 612e098bc96SEvan Quan dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 613e098bc96SEvan Quan return -EINVAL; 614e098bc96SEvan Quan } 615e098bc96SEvan Quan 616e098bc96SEvan Quan return 0; 617e098bc96SEvan Quan } 618e098bc96SEvan Quan 61961426114SAlex Deucher static int renoir_get_vddc(struct smu_context *smu, uint32_t *value, 62061426114SAlex Deucher unsigned int index) 62161426114SAlex Deucher { 62261426114SAlex Deucher int ret = 0; 62361426114SAlex Deucher SmuMetrics_t metrics; 62461426114SAlex Deucher 62561426114SAlex Deucher if (index >= 2) 62661426114SAlex Deucher return -EINVAL; 62761426114SAlex Deucher 62861426114SAlex Deucher if (!value) 62961426114SAlex Deucher return -EINVAL; 63061426114SAlex Deucher 63161426114SAlex Deucher ret = smu_cmn_get_metrics_table(smu, &metrics, false); 63261426114SAlex Deucher if (ret) 63361426114SAlex Deucher return ret; 63461426114SAlex Deucher 63561426114SAlex Deucher *value = metrics.Voltage[index]; 63661426114SAlex Deucher 63761426114SAlex Deucher return 0; 63861426114SAlex Deucher } 63961426114SAlex Deucher 640b49dc928SAlex Deucher static int renoir_get_power(struct smu_context *smu, uint32_t *value) 641b49dc928SAlex Deucher { 642b49dc928SAlex Deucher int ret = 0; 643b49dc928SAlex Deucher SmuMetrics_t metrics; 644b49dc928SAlex Deucher 645b49dc928SAlex Deucher if (!value) 646b49dc928SAlex Deucher return -EINVAL; 647b49dc928SAlex Deucher 648b49dc928SAlex Deucher ret = smu_cmn_get_metrics_table(smu, &metrics, false); 649b49dc928SAlex Deucher if (ret) 650b49dc928SAlex Deucher return ret; 651b49dc928SAlex Deucher 652b49dc928SAlex Deucher *value = metrics.CurrentSocketPower << 8; 653b49dc928SAlex Deucher 654b49dc928SAlex Deucher return 0; 655b49dc928SAlex Deucher } 656b49dc928SAlex Deucher 657e098bc96SEvan Quan /** 658e098bc96SEvan Quan * This interface get dpm clock table for dc 659e098bc96SEvan Quan */ 660e098bc96SEvan Quan static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 661e098bc96SEvan Quan { 662e098bc96SEvan Quan DpmClocks_t *table = smu->smu_table.clocks_table; 663e098bc96SEvan Quan int i; 664e098bc96SEvan Quan 665e098bc96SEvan Quan if (!clock_table || !table) 666e098bc96SEvan Quan return -EINVAL; 667e098bc96SEvan Quan 668e098bc96SEvan Quan for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { 669e098bc96SEvan Quan clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; 670e098bc96SEvan Quan clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; 671e098bc96SEvan Quan } 672e098bc96SEvan Quan 673e098bc96SEvan Quan for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 674e098bc96SEvan Quan clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq; 675e098bc96SEvan Quan clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; 676e098bc96SEvan Quan } 677e098bc96SEvan Quan 678e098bc96SEvan Quan for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 679e098bc96SEvan Quan clock_table->FClocks[i].Freq = table->FClocks[i].Freq; 680e098bc96SEvan Quan clock_table->FClocks[i].Vol = table->FClocks[i].Vol; 681e098bc96SEvan Quan } 682e098bc96SEvan Quan 683e098bc96SEvan Quan for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) { 684e098bc96SEvan Quan clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq; 685e098bc96SEvan Quan clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; 686e098bc96SEvan Quan } 687e098bc96SEvan Quan 688e098bc96SEvan Quan return 0; 689e098bc96SEvan Quan } 690e098bc96SEvan Quan 691e098bc96SEvan Quan static int renoir_force_clk_levels(struct smu_context *smu, 692e098bc96SEvan Quan enum smu_clk_type clk_type, uint32_t mask) 693e098bc96SEvan Quan { 694e098bc96SEvan Quan 695e098bc96SEvan Quan int ret = 0 ; 696e098bc96SEvan Quan uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 697e098bc96SEvan Quan 698e098bc96SEvan Quan soft_min_level = mask ? (ffs(mask) - 1) : 0; 699e098bc96SEvan Quan soft_max_level = mask ? (fls(mask) - 1) : 0; 700e098bc96SEvan Quan 701e098bc96SEvan Quan switch (clk_type) { 702e098bc96SEvan Quan case SMU_GFXCLK: 703e098bc96SEvan Quan case SMU_SCLK: 704e098bc96SEvan Quan if (soft_min_level > 2 || soft_max_level > 2) { 705e098bc96SEvan Quan dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n"); 706e098bc96SEvan Quan return -EINVAL; 707e098bc96SEvan Quan } 708e098bc96SEvan Quan 709e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq); 710e098bc96SEvan Quan if (ret) 711e098bc96SEvan Quan return ret; 712e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 713e098bc96SEvan Quan soft_max_level == 0 ? min_freq : 714e098bc96SEvan Quan soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq, 715e098bc96SEvan Quan NULL); 716e098bc96SEvan Quan if (ret) 717e098bc96SEvan Quan return ret; 718e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 719e098bc96SEvan Quan soft_min_level == 2 ? max_freq : 720e098bc96SEvan Quan soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq, 721e098bc96SEvan Quan NULL); 722e098bc96SEvan Quan if (ret) 723e098bc96SEvan Quan return ret; 724e098bc96SEvan Quan break; 725e098bc96SEvan Quan case SMU_SOCCLK: 726e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 727e098bc96SEvan Quan if (ret) 728e098bc96SEvan Quan return ret; 729e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 730e098bc96SEvan Quan if (ret) 731e098bc96SEvan Quan return ret; 732e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); 733e098bc96SEvan Quan if (ret) 734e098bc96SEvan Quan return ret; 735e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); 736e098bc96SEvan Quan if (ret) 737e098bc96SEvan Quan return ret; 738e098bc96SEvan Quan break; 739e098bc96SEvan Quan case SMU_MCLK: 740e098bc96SEvan Quan case SMU_FCLK: 741e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq); 742e098bc96SEvan Quan if (ret) 743e098bc96SEvan Quan return ret; 744e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); 745e098bc96SEvan Quan if (ret) 746e098bc96SEvan Quan return ret; 747e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); 748e098bc96SEvan Quan if (ret) 749e098bc96SEvan Quan return ret; 750e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); 751e098bc96SEvan Quan if (ret) 752e098bc96SEvan Quan return ret; 753e098bc96SEvan Quan break; 754e098bc96SEvan Quan default: 755e098bc96SEvan Quan break; 756e098bc96SEvan Quan } 757e098bc96SEvan Quan 758e098bc96SEvan Quan return ret; 759e098bc96SEvan Quan } 760e098bc96SEvan Quan 761e098bc96SEvan Quan static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 762e098bc96SEvan Quan { 763e098bc96SEvan Quan int workload_type, ret; 764e098bc96SEvan Quan uint32_t profile_mode = input[size]; 765e098bc96SEvan Quan 766e098bc96SEvan Quan if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 767e098bc96SEvan Quan dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 768e098bc96SEvan Quan return -EINVAL; 769e098bc96SEvan Quan } 770e098bc96SEvan Quan 771e098bc96SEvan Quan /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 772e098bc96SEvan Quan workload_type = smu_cmn_to_asic_specific_index(smu, 773e098bc96SEvan Quan CMN2ASIC_MAPPING_WORKLOAD, 774e098bc96SEvan Quan profile_mode); 775e098bc96SEvan Quan if (workload_type < 0) { 776e098bc96SEvan Quan /* 777e098bc96SEvan Quan * TODO: If some case need switch to powersave/default power mode 778e098bc96SEvan Quan * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving. 779e098bc96SEvan Quan */ 780e098bc96SEvan Quan dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode); 781e098bc96SEvan Quan return -EINVAL; 782e098bc96SEvan Quan } 783e098bc96SEvan Quan 784e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 785e098bc96SEvan Quan 1 << workload_type, 786e098bc96SEvan Quan NULL); 787e098bc96SEvan Quan if (ret) { 788e098bc96SEvan Quan dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 789e098bc96SEvan Quan return ret; 790e098bc96SEvan Quan } 791e098bc96SEvan Quan 792e098bc96SEvan Quan smu->power_profile_mode = profile_mode; 793e098bc96SEvan Quan 794e098bc96SEvan Quan return 0; 795e098bc96SEvan Quan } 796e098bc96SEvan Quan 797e098bc96SEvan Quan static int renoir_set_peak_clock_by_device(struct smu_context *smu) 798e098bc96SEvan Quan { 799e098bc96SEvan Quan int ret = 0; 800e098bc96SEvan Quan uint32_t sclk_freq = 0, uclk_freq = 0; 801e098bc96SEvan Quan 802e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq); 803e098bc96SEvan Quan if (ret) 804e098bc96SEvan Quan return ret; 805e098bc96SEvan Quan 806e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq); 807e098bc96SEvan Quan if (ret) 808e098bc96SEvan Quan return ret; 809e098bc96SEvan Quan 810e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq); 811e098bc96SEvan Quan if (ret) 812e098bc96SEvan Quan return ret; 813e098bc96SEvan Quan 814e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq); 815e098bc96SEvan Quan if (ret) 816e098bc96SEvan Quan return ret; 817e098bc96SEvan Quan 818e098bc96SEvan Quan return ret; 819e098bc96SEvan Quan } 820e098bc96SEvan Quan 821e098bc96SEvan Quan static int renoir_set_performance_level(struct smu_context *smu, 822e098bc96SEvan Quan enum amd_dpm_forced_level level) 823e098bc96SEvan Quan { 824e098bc96SEvan Quan int ret = 0; 825e098bc96SEvan Quan uint32_t sclk_mask, mclk_mask, soc_mask; 826e098bc96SEvan Quan 827e098bc96SEvan Quan switch (level) { 828e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_HIGH: 829e098bc96SEvan Quan ret = renoir_force_dpm_limit_value(smu, true); 830e098bc96SEvan Quan break; 831e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_LOW: 832e098bc96SEvan Quan ret = renoir_force_dpm_limit_value(smu, false); 833e098bc96SEvan Quan break; 834e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_AUTO: 835e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 836e098bc96SEvan Quan ret = renoir_unforce_dpm_levels(smu); 837e098bc96SEvan Quan break; 838e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 839e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 840e098bc96SEvan Quan ret = renoir_get_profiling_clk_mask(smu, level, 841e098bc96SEvan Quan &sclk_mask, 842e098bc96SEvan Quan &mclk_mask, 843e098bc96SEvan Quan &soc_mask); 844e098bc96SEvan Quan if (ret) 845e098bc96SEvan Quan return ret; 846e098bc96SEvan Quan renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); 847e098bc96SEvan Quan renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 848e098bc96SEvan Quan renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 849e098bc96SEvan Quan break; 850e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 851e098bc96SEvan Quan ret = renoir_set_peak_clock_by_device(smu); 852e098bc96SEvan Quan break; 853e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_MANUAL: 854e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 855e098bc96SEvan Quan default: 856e098bc96SEvan Quan break; 857e098bc96SEvan Quan } 858e098bc96SEvan Quan return ret; 859e098bc96SEvan Quan } 860e098bc96SEvan Quan 861e098bc96SEvan Quan /* save watermark settings into pplib smu structure, 862e098bc96SEvan Quan * also pass data to smu controller 863e098bc96SEvan Quan */ 864e098bc96SEvan Quan static int renoir_set_watermarks_table( 865e098bc96SEvan Quan struct smu_context *smu, 866e098bc96SEvan Quan struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges) 867e098bc96SEvan Quan { 868e098bc96SEvan Quan Watermarks_t *table = smu->smu_table.watermarks_table; 869e098bc96SEvan Quan int ret = 0; 870e098bc96SEvan Quan int i; 871e098bc96SEvan Quan 872e098bc96SEvan Quan if (clock_ranges) { 873e098bc96SEvan Quan if (clock_ranges->num_wm_dmif_sets > 4 || 874e098bc96SEvan Quan clock_ranges->num_wm_mcif_sets > 4) 875e098bc96SEvan Quan return -EINVAL; 876e098bc96SEvan Quan 877e098bc96SEvan Quan /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/ 878e098bc96SEvan Quan for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { 879e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MinClock = 880e098bc96SEvan Quan cpu_to_le16((uint16_t) 881e098bc96SEvan Quan (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz)); 882e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MaxClock = 883e098bc96SEvan Quan cpu_to_le16((uint16_t) 884e098bc96SEvan Quan (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz)); 885e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MinMclk = 886e098bc96SEvan Quan cpu_to_le16((uint16_t) 887e098bc96SEvan Quan (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz)); 888e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 889e098bc96SEvan Quan cpu_to_le16((uint16_t) 890e098bc96SEvan Quan (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz)); 891e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t) 892e098bc96SEvan Quan clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; 893e098bc96SEvan Quan } 894e098bc96SEvan Quan 895e098bc96SEvan Quan for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) { 896e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MinClock = 897e098bc96SEvan Quan cpu_to_le16((uint16_t) 898e098bc96SEvan Quan (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz)); 899e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MaxClock = 900e098bc96SEvan Quan cpu_to_le16((uint16_t) 901e098bc96SEvan Quan (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz)); 902e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MinMclk = 903e098bc96SEvan Quan cpu_to_le16((uint16_t) 904e098bc96SEvan Quan (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz)); 905e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 906e098bc96SEvan Quan cpu_to_le16((uint16_t) 907e098bc96SEvan Quan (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz)); 908e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t) 909e098bc96SEvan Quan clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; 910e098bc96SEvan Quan } 911e098bc96SEvan Quan 912e098bc96SEvan Quan smu->watermarks_bitmap |= WATERMARKS_EXIST; 913e098bc96SEvan Quan } 914e098bc96SEvan Quan 915e098bc96SEvan Quan /* pass data to smu controller */ 916e098bc96SEvan Quan if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 917e098bc96SEvan Quan !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 918e098bc96SEvan Quan ret = smu_cmn_write_watermarks_table(smu); 919e098bc96SEvan Quan if (ret) { 920e098bc96SEvan Quan dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 921e098bc96SEvan Quan return ret; 922e098bc96SEvan Quan } 923e098bc96SEvan Quan smu->watermarks_bitmap |= WATERMARKS_LOADED; 924e098bc96SEvan Quan } 925e098bc96SEvan Quan 926e098bc96SEvan Quan return 0; 927e098bc96SEvan Quan } 928e098bc96SEvan Quan 929e098bc96SEvan Quan static int renoir_get_power_profile_mode(struct smu_context *smu, 930e098bc96SEvan Quan char *buf) 931e098bc96SEvan Quan { 932e098bc96SEvan Quan static const char *profile_name[] = { 933e098bc96SEvan Quan "BOOTUP_DEFAULT", 934e098bc96SEvan Quan "3D_FULL_SCREEN", 935e098bc96SEvan Quan "POWER_SAVING", 936e098bc96SEvan Quan "VIDEO", 937e098bc96SEvan Quan "VR", 938e098bc96SEvan Quan "COMPUTE", 939e098bc96SEvan Quan "CUSTOM"}; 940e098bc96SEvan Quan uint32_t i, size = 0; 941e098bc96SEvan Quan int16_t workload_type = 0; 942e098bc96SEvan Quan 943e098bc96SEvan Quan if (!buf) 944e098bc96SEvan Quan return -EINVAL; 945e098bc96SEvan Quan 946e098bc96SEvan Quan for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 947e098bc96SEvan Quan /* 948e098bc96SEvan Quan * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 949e098bc96SEvan Quan * Not all profile modes are supported on arcturus. 950e098bc96SEvan Quan */ 951e098bc96SEvan Quan workload_type = smu_cmn_to_asic_specific_index(smu, 952e098bc96SEvan Quan CMN2ASIC_MAPPING_WORKLOAD, 953e098bc96SEvan Quan i); 954e098bc96SEvan Quan if (workload_type < 0) 955e098bc96SEvan Quan continue; 956e098bc96SEvan Quan 957e098bc96SEvan Quan size += sprintf(buf + size, "%2d %14s%s\n", 958e098bc96SEvan Quan i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 959e098bc96SEvan Quan } 960e098bc96SEvan Quan 961e098bc96SEvan Quan return size; 962e098bc96SEvan Quan } 963e098bc96SEvan Quan 964e098bc96SEvan Quan static int renoir_read_sensor(struct smu_context *smu, 965e098bc96SEvan Quan enum amd_pp_sensors sensor, 966e098bc96SEvan Quan void *data, uint32_t *size) 967e098bc96SEvan Quan { 968e098bc96SEvan Quan int ret = 0; 969e098bc96SEvan Quan 970e098bc96SEvan Quan if (!data || !size) 971e098bc96SEvan Quan return -EINVAL; 972e098bc96SEvan Quan 973e098bc96SEvan Quan mutex_lock(&smu->sensor_lock); 974e098bc96SEvan Quan switch (sensor) { 975e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GPU_LOAD: 976e098bc96SEvan Quan ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data); 977e098bc96SEvan Quan *size = 4; 978e098bc96SEvan Quan break; 979e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GPU_TEMP: 980e098bc96SEvan Quan ret = renoir_get_gpu_temperature(smu, (uint32_t *)data); 981e098bc96SEvan Quan *size = 4; 982e098bc96SEvan Quan break; 983e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GFX_MCLK: 984e098bc96SEvan Quan ret = renoir_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 985e098bc96SEvan Quan *(uint32_t *)data *= 100; 986e098bc96SEvan Quan *size = 4; 987e098bc96SEvan Quan break; 988e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GFX_SCLK: 989e098bc96SEvan Quan ret = renoir_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 990e098bc96SEvan Quan *(uint32_t *)data *= 100; 991e098bc96SEvan Quan *size = 4; 992e098bc96SEvan Quan break; 99361426114SAlex Deucher case AMDGPU_PP_SENSOR_VDDGFX: 99461426114SAlex Deucher ret = renoir_get_vddc(smu, (uint32_t *)data, 0); 99561426114SAlex Deucher *size = 4; 99661426114SAlex Deucher break; 99761426114SAlex Deucher case AMDGPU_PP_SENSOR_VDDNB: 99861426114SAlex Deucher ret = renoir_get_vddc(smu, (uint32_t *)data, 1); 99961426114SAlex Deucher *size = 4; 100061426114SAlex Deucher break; 1001b49dc928SAlex Deucher case AMDGPU_PP_SENSOR_GPU_POWER: 1002b49dc928SAlex Deucher ret = renoir_get_power(smu, (uint32_t *)data); 1003b49dc928SAlex Deucher *size = 4; 1004b49dc928SAlex Deucher break; 1005e098bc96SEvan Quan default: 1006e098bc96SEvan Quan ret = -EOPNOTSUPP; 1007e098bc96SEvan Quan break; 1008e098bc96SEvan Quan } 1009e098bc96SEvan Quan mutex_unlock(&smu->sensor_lock); 1010e098bc96SEvan Quan 1011e098bc96SEvan Quan return ret; 1012e098bc96SEvan Quan } 1013e098bc96SEvan Quan 1014e098bc96SEvan Quan static bool renoir_is_dpm_running(struct smu_context *smu) 1015e098bc96SEvan Quan { 1016e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1017e098bc96SEvan Quan 1018e098bc96SEvan Quan /* 1019e098bc96SEvan Quan * Until now, the pmfw hasn't exported the interface of SMU 1020e098bc96SEvan Quan * feature mask to APU SKU so just force on all the feature 1021e098bc96SEvan Quan * at early initial stage. 1022e098bc96SEvan Quan */ 1023e098bc96SEvan Quan if (adev->in_suspend) 1024e098bc96SEvan Quan return false; 1025e098bc96SEvan Quan else 1026e098bc96SEvan Quan return true; 1027e098bc96SEvan Quan 1028e098bc96SEvan Quan } 1029e098bc96SEvan Quan 1030e098bc96SEvan Quan static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, 1031e098bc96SEvan Quan void **table) 1032e098bc96SEvan Quan { 1033e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 1034e098bc96SEvan Quan struct gpu_metrics_v2_0 *gpu_metrics = 1035e098bc96SEvan Quan (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; 1036e098bc96SEvan Quan SmuMetrics_t metrics; 1037e098bc96SEvan Quan int ret = 0; 1038e098bc96SEvan Quan 1039e098bc96SEvan Quan ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1040e098bc96SEvan Quan if (ret) 1041e098bc96SEvan Quan return ret; 1042e098bc96SEvan Quan 1043e098bc96SEvan Quan smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics); 1044e098bc96SEvan Quan 1045e098bc96SEvan Quan gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1046e098bc96SEvan Quan gpu_metrics->temperature_soc = metrics.SocTemperature; 1047e098bc96SEvan Quan memcpy(&gpu_metrics->temperature_core[0], 1048e098bc96SEvan Quan &metrics.CoreTemperature[0], 1049e098bc96SEvan Quan sizeof(uint16_t) * 8); 1050e098bc96SEvan Quan gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1051e098bc96SEvan Quan gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1052e098bc96SEvan Quan 1053e098bc96SEvan Quan gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1054e098bc96SEvan Quan gpu_metrics->average_mm_activity = metrics.AverageUvdActivity; 1055e098bc96SEvan Quan 1056e098bc96SEvan Quan gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1057e098bc96SEvan Quan gpu_metrics->average_cpu_power = metrics.Power[0]; 1058e098bc96SEvan Quan gpu_metrics->average_soc_power = metrics.Power[1]; 1059e098bc96SEvan Quan memcpy(&gpu_metrics->average_core_power[0], 1060e098bc96SEvan Quan &metrics.CorePower[0], 1061e098bc96SEvan Quan sizeof(uint16_t) * 8); 1062e098bc96SEvan Quan 1063e098bc96SEvan Quan gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1064e098bc96SEvan Quan gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1065e098bc96SEvan Quan gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency; 1066e098bc96SEvan Quan gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency; 1067e098bc96SEvan Quan 1068e098bc96SEvan Quan gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK]; 1069e098bc96SEvan Quan gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK]; 1070e098bc96SEvan Quan gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK]; 1071e098bc96SEvan Quan gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK]; 1072e098bc96SEvan Quan gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK]; 1073e098bc96SEvan Quan gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK]; 1074e098bc96SEvan Quan memcpy(&gpu_metrics->current_coreclk[0], 1075e098bc96SEvan Quan &metrics.CoreFrequency[0], 1076e098bc96SEvan Quan sizeof(uint16_t) * 8); 1077e098bc96SEvan Quan gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1078e098bc96SEvan Quan gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1079e098bc96SEvan Quan 1080e098bc96SEvan Quan gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1081e098bc96SEvan Quan 1082e098bc96SEvan Quan gpu_metrics->fan_pwm = metrics.FanPwm; 1083e098bc96SEvan Quan 1084e098bc96SEvan Quan *table = (void *)gpu_metrics; 1085e098bc96SEvan Quan 1086e098bc96SEvan Quan return sizeof(struct gpu_metrics_v2_0); 1087e098bc96SEvan Quan } 1088e098bc96SEvan Quan 1089e098bc96SEvan Quan static const struct pptable_funcs renoir_ppt_funcs = { 1090e098bc96SEvan Quan .set_power_state = NULL, 1091e098bc96SEvan Quan .print_clk_levels = renoir_print_clk_levels, 1092e098bc96SEvan Quan .get_current_power_state = renoir_get_current_power_state, 1093e098bc96SEvan Quan .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable, 1094e098bc96SEvan Quan .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable, 1095e098bc96SEvan Quan .force_clk_levels = renoir_force_clk_levels, 1096e098bc96SEvan Quan .set_power_profile_mode = renoir_set_power_profile_mode, 1097e098bc96SEvan Quan .set_performance_level = renoir_set_performance_level, 1098e098bc96SEvan Quan .get_dpm_clock_table = renoir_get_dpm_clock_table, 1099e098bc96SEvan Quan .set_watermarks_table = renoir_set_watermarks_table, 1100e098bc96SEvan Quan .get_power_profile_mode = renoir_get_power_profile_mode, 1101e098bc96SEvan Quan .read_sensor = renoir_read_sensor, 1102e098bc96SEvan Quan .check_fw_status = smu_v12_0_check_fw_status, 1103e098bc96SEvan Quan .check_fw_version = smu_v12_0_check_fw_version, 1104e098bc96SEvan Quan .powergate_sdma = smu_v12_0_powergate_sdma, 1105e098bc96SEvan Quan .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1106e098bc96SEvan Quan .send_smc_msg = smu_cmn_send_smc_msg, 1107e098bc96SEvan Quan .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, 1108e098bc96SEvan Quan .gfx_off_control = smu_v12_0_gfx_off_control, 1109e098bc96SEvan Quan .get_gfx_off_status = smu_v12_0_get_gfxoff_status, 1110e098bc96SEvan Quan .init_smc_tables = renoir_init_smc_tables, 1111e098bc96SEvan Quan .fini_smc_tables = smu_v12_0_fini_smc_tables, 1112e098bc96SEvan Quan .set_default_dpm_table = smu_v12_0_set_default_dpm_tables, 1113e098bc96SEvan Quan .get_enabled_mask = smu_cmn_get_enabled_mask, 1114e098bc96SEvan Quan .feature_is_enabled = smu_cmn_feature_is_enabled, 1115e098bc96SEvan Quan .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 1116e098bc96SEvan Quan .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq, 1117e098bc96SEvan Quan .mode2_reset = smu_v12_0_mode2_reset, 1118e098bc96SEvan Quan .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, 1119e098bc96SEvan Quan .set_driver_table_location = smu_v12_0_set_driver_table_location, 1120e098bc96SEvan Quan .is_dpm_running = renoir_is_dpm_running, 1121e098bc96SEvan Quan .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1122e098bc96SEvan Quan .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1123e098bc96SEvan Quan .get_gpu_metrics = renoir_get_gpu_metrics, 1124e098bc96SEvan Quan }; 1125e098bc96SEvan Quan 1126e098bc96SEvan Quan void renoir_set_ppt_funcs(struct smu_context *smu) 1127e098bc96SEvan Quan { 1128e098bc96SEvan Quan smu->ppt_funcs = &renoir_ppt_funcs; 1129e098bc96SEvan Quan smu->message_map = renoir_message_map; 1130e098bc96SEvan Quan smu->clock_map = renoir_clk_map; 1131e098bc96SEvan Quan smu->table_map = renoir_table_map; 1132e098bc96SEvan Quan smu->workload_map = renoir_workload_map; 1133e098bc96SEvan Quan smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; 1134e098bc96SEvan Quan smu->is_apu = true; 1135e098bc96SEvan Quan } 1136