1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 #include <asm/processor.h> 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 #define FEATURE_MASK(feature) (1ULL << feature) 50 #define SMC_DPM_FEATURE ( \ 51 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 52 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 53 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 54 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 55 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 56 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 57 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 58 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 59 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 60 61 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 62 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 63 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 64 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 65 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 66 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 67 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 68 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 69 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 70 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 71 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 72 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 73 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 74 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 75 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 76 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 77 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 78 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 79 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 80 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 81 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 82 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 83 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 84 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 85 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 86 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 87 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 88 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 89 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 95 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 96 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 97 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 98 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 99 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 100 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 101 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 102 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 103 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 104 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 105 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 106 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 107 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 108 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 109 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 110 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 111 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 112 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 113 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 114 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 115 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 116 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 117 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 118 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 119 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 120 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 121 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 122 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 123 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 124 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 125 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 126 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 127 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 128 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 129 }; 130 131 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 132 FEA_MAP(PPT), 133 FEA_MAP(TDC), 134 FEA_MAP(THERMAL), 135 FEA_MAP(DS_GFXCLK), 136 FEA_MAP(DS_SOCCLK), 137 FEA_MAP(DS_LCLK), 138 FEA_MAP(DS_FCLK), 139 FEA_MAP(DS_MP1CLK), 140 FEA_MAP(DS_MP0CLK), 141 FEA_MAP(ATHUB_PG), 142 FEA_MAP(CCLK_DPM), 143 FEA_MAP(FAN_CONTROLLER), 144 FEA_MAP(ULV), 145 FEA_MAP(VCN_DPM), 146 FEA_MAP(LCLK_DPM), 147 FEA_MAP(SHUBCLK_DPM), 148 FEA_MAP(DCFCLK_DPM), 149 FEA_MAP(DS_DCFCLK), 150 FEA_MAP(S0I2), 151 FEA_MAP(SMU_LOW_POWER), 152 FEA_MAP(GFX_DEM), 153 FEA_MAP(PSI), 154 FEA_MAP(PROCHOT), 155 FEA_MAP(CPUOFF), 156 FEA_MAP(STAPM), 157 FEA_MAP(S0I3), 158 FEA_MAP(DF_CSTATES), 159 FEA_MAP(PERF_LIMIT), 160 FEA_MAP(CORE_DLDO), 161 FEA_MAP(RSMU_LOW_POWER), 162 FEA_MAP(SMN_LOW_POWER), 163 FEA_MAP(THM_LOW_POWER), 164 FEA_MAP(SMUIO_LOW_POWER), 165 FEA_MAP(MP1_LOW_POWER), 166 FEA_MAP(DS_VCN), 167 FEA_MAP(CPPC), 168 FEA_MAP(OS_CSTATES), 169 FEA_MAP(ISP_DPM), 170 FEA_MAP(A55_DPM), 171 FEA_MAP(CVIP_DSP_DPM), 172 FEA_MAP(MSMU_LOW_POWER), 173 FEA_MAP_REVERSE(SOCCLK), 174 FEA_MAP_REVERSE(FCLK), 175 FEA_MAP_HALF_REVERSE(GFX), 176 }; 177 178 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 179 TAB_MAP_VALID(WATERMARKS), 180 TAB_MAP_VALID(SMU_METRICS), 181 TAB_MAP_VALID(CUSTOM_DPM), 182 TAB_MAP_VALID(DPMCLOCKS), 183 }; 184 185 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 187 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 188 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 189 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 190 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 191 }; 192 193 static int vangogh_tables_init(struct smu_context *smu) 194 { 195 struct smu_table_context *smu_table = &smu->smu_table; 196 struct smu_table *tables = smu_table->tables; 197 struct amdgpu_device *adev = smu->adev; 198 uint32_t if_version; 199 uint32_t ret = 0; 200 201 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 202 if (ret) { 203 dev_err(adev->dev, "Failed to get smu if version!\n"); 204 goto err0_out; 205 } 206 207 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 208 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 209 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 210 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 211 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 212 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 213 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 214 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 215 216 if (if_version < 0x3) { 217 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t), 218 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 219 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL); 220 } else { 221 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 222 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 223 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 224 } 225 if (!smu_table->metrics_table) 226 goto err0_out; 227 smu_table->metrics_time = 0; 228 229 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); 230 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 231 if (!smu_table->gpu_metrics_table) 232 goto err1_out; 233 234 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 235 if (!smu_table->watermarks_table) 236 goto err2_out; 237 238 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 239 if (!smu_table->clocks_table) 240 goto err3_out; 241 242 return 0; 243 244 err3_out: 245 kfree(smu_table->clocks_table); 246 err2_out: 247 kfree(smu_table->gpu_metrics_table); 248 err1_out: 249 kfree(smu_table->metrics_table); 250 err0_out: 251 return -ENOMEM; 252 } 253 254 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu, 255 MetricsMember_t member, 256 uint32_t *value) 257 { 258 struct smu_table_context *smu_table = &smu->smu_table; 259 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table; 260 int ret = 0; 261 262 mutex_lock(&smu->metrics_lock); 263 264 ret = smu_cmn_get_metrics_table_locked(smu, 265 NULL, 266 false); 267 if (ret) { 268 mutex_unlock(&smu->metrics_lock); 269 return ret; 270 } 271 272 switch (member) { 273 case METRICS_CURR_GFXCLK: 274 *value = metrics->GfxclkFrequency; 275 break; 276 case METRICS_AVERAGE_SOCCLK: 277 *value = metrics->SocclkFrequency; 278 break; 279 case METRICS_AVERAGE_VCLK: 280 *value = metrics->VclkFrequency; 281 break; 282 case METRICS_AVERAGE_DCLK: 283 *value = metrics->DclkFrequency; 284 break; 285 case METRICS_CURR_UCLK: 286 *value = metrics->MemclkFrequency; 287 break; 288 case METRICS_AVERAGE_GFXACTIVITY: 289 *value = metrics->GfxActivity / 100; 290 break; 291 case METRICS_AVERAGE_VCNACTIVITY: 292 *value = metrics->UvdActivity; 293 break; 294 case METRICS_AVERAGE_SOCKETPOWER: 295 *value = (metrics->CurrentSocketPower << 8) / 296 1000 ; 297 break; 298 case METRICS_TEMPERATURE_EDGE: 299 *value = metrics->GfxTemperature / 100 * 300 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 301 break; 302 case METRICS_TEMPERATURE_HOTSPOT: 303 *value = metrics->SocTemperature / 100 * 304 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 305 break; 306 case METRICS_THROTTLER_STATUS: 307 *value = metrics->ThrottlerStatus; 308 break; 309 case METRICS_VOLTAGE_VDDGFX: 310 *value = metrics->Voltage[2]; 311 break; 312 case METRICS_VOLTAGE_VDDSOC: 313 *value = metrics->Voltage[1]; 314 break; 315 case METRICS_AVERAGE_CPUCLK: 316 memcpy(value, &metrics->CoreFrequency[0], 317 smu->cpu_core_num * sizeof(uint16_t)); 318 break; 319 default: 320 *value = UINT_MAX; 321 break; 322 } 323 324 mutex_unlock(&smu->metrics_lock); 325 326 return ret; 327 } 328 329 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 330 MetricsMember_t member, 331 uint32_t *value) 332 { 333 struct smu_table_context *smu_table = &smu->smu_table; 334 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 335 int ret = 0; 336 337 mutex_lock(&smu->metrics_lock); 338 339 ret = smu_cmn_get_metrics_table_locked(smu, 340 NULL, 341 false); 342 if (ret) { 343 mutex_unlock(&smu->metrics_lock); 344 return ret; 345 } 346 347 switch (member) { 348 case METRICS_CURR_GFXCLK: 349 *value = metrics->Current.GfxclkFrequency; 350 break; 351 case METRICS_AVERAGE_SOCCLK: 352 *value = metrics->Current.SocclkFrequency; 353 break; 354 case METRICS_AVERAGE_VCLK: 355 *value = metrics->Current.VclkFrequency; 356 break; 357 case METRICS_AVERAGE_DCLK: 358 *value = metrics->Current.DclkFrequency; 359 break; 360 case METRICS_CURR_UCLK: 361 *value = metrics->Current.MemclkFrequency; 362 break; 363 case METRICS_AVERAGE_GFXACTIVITY: 364 *value = metrics->Current.GfxActivity; 365 break; 366 case METRICS_AVERAGE_VCNACTIVITY: 367 *value = metrics->Current.UvdActivity; 368 break; 369 case METRICS_AVERAGE_SOCKETPOWER: 370 *value = (metrics->Current.CurrentSocketPower << 8) / 371 1000; 372 break; 373 case METRICS_TEMPERATURE_EDGE: 374 *value = metrics->Current.GfxTemperature / 100 * 375 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 376 break; 377 case METRICS_TEMPERATURE_HOTSPOT: 378 *value = metrics->Current.SocTemperature / 100 * 379 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 380 break; 381 case METRICS_THROTTLER_STATUS: 382 *value = metrics->Current.ThrottlerStatus; 383 break; 384 case METRICS_VOLTAGE_VDDGFX: 385 *value = metrics->Current.Voltage[2]; 386 break; 387 case METRICS_VOLTAGE_VDDSOC: 388 *value = metrics->Current.Voltage[1]; 389 break; 390 case METRICS_AVERAGE_CPUCLK: 391 memcpy(value, &metrics->Current.CoreFrequency[0], 392 smu->cpu_core_num * sizeof(uint16_t)); 393 break; 394 default: 395 *value = UINT_MAX; 396 break; 397 } 398 399 mutex_unlock(&smu->metrics_lock); 400 401 return ret; 402 } 403 404 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu, 405 MetricsMember_t member, 406 uint32_t *value) 407 { 408 struct amdgpu_device *adev = smu->adev; 409 uint32_t if_version; 410 int ret = 0; 411 412 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 413 if (ret) { 414 dev_err(adev->dev, "Failed to get smu if version!\n"); 415 return ret; 416 } 417 418 if (if_version < 0x3) 419 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value); 420 else 421 ret = vangogh_get_smu_metrics_data(smu, member, value); 422 423 return ret; 424 } 425 426 static int vangogh_allocate_dpm_context(struct smu_context *smu) 427 { 428 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 429 430 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 431 GFP_KERNEL); 432 if (!smu_dpm->dpm_context) 433 return -ENOMEM; 434 435 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 436 437 return 0; 438 } 439 440 static int vangogh_init_smc_tables(struct smu_context *smu) 441 { 442 int ret = 0; 443 444 ret = vangogh_tables_init(smu); 445 if (ret) 446 return ret; 447 448 ret = vangogh_allocate_dpm_context(smu); 449 if (ret) 450 return ret; 451 452 #ifdef CONFIG_X86 453 /* AMD x86 APU only */ 454 smu->cpu_core_num = boot_cpu_data.x86_max_cores; 455 #else 456 smu->cpu_core_num = 4; 457 #endif 458 459 return smu_v11_0_init_smc_tables(smu); 460 } 461 462 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 463 { 464 int ret = 0; 465 466 if (enable) { 467 /* vcn dpm on is a prerequisite for vcn power gate messages */ 468 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 469 if (ret) 470 return ret; 471 } else { 472 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 473 if (ret) 474 return ret; 475 } 476 477 return ret; 478 } 479 480 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 481 { 482 int ret = 0; 483 484 if (enable) { 485 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 486 if (ret) 487 return ret; 488 } else { 489 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 490 if (ret) 491 return ret; 492 } 493 494 return ret; 495 } 496 497 static bool vangogh_is_dpm_running(struct smu_context *smu) 498 { 499 struct amdgpu_device *adev = smu->adev; 500 int ret = 0; 501 uint32_t feature_mask[2]; 502 uint64_t feature_enabled; 503 504 /* we need to re-init after suspend so return false */ 505 if (adev->in_suspend) 506 return false; 507 508 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 509 510 if (ret) 511 return false; 512 513 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 514 ((uint64_t)feature_mask[1] << 32)); 515 516 return !!(feature_enabled & SMC_DPM_FEATURE); 517 } 518 519 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 520 uint32_t dpm_level, uint32_t *freq) 521 { 522 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 523 524 if (!clk_table || clk_type >= SMU_CLK_COUNT) 525 return -EINVAL; 526 527 switch (clk_type) { 528 case SMU_SOCCLK: 529 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 530 return -EINVAL; 531 *freq = clk_table->SocClocks[dpm_level]; 532 break; 533 case SMU_VCLK: 534 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 535 return -EINVAL; 536 *freq = clk_table->VcnClocks[dpm_level].vclk; 537 break; 538 case SMU_DCLK: 539 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 540 return -EINVAL; 541 *freq = clk_table->VcnClocks[dpm_level].dclk; 542 break; 543 case SMU_UCLK: 544 case SMU_MCLK: 545 if (dpm_level >= clk_table->NumDfPstatesEnabled) 546 return -EINVAL; 547 *freq = clk_table->DfPstateTable[dpm_level].memclk; 548 549 break; 550 case SMU_FCLK: 551 if (dpm_level >= clk_table->NumDfPstatesEnabled) 552 return -EINVAL; 553 *freq = clk_table->DfPstateTable[dpm_level].fclk; 554 break; 555 default: 556 return -EINVAL; 557 } 558 559 return 0; 560 } 561 562 static int vangogh_print_legacy_clk_levels(struct smu_context *smu, 563 enum smu_clk_type clk_type, char *buf) 564 { 565 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 566 SmuMetrics_legacy_t metrics; 567 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 568 int i, size = 0, ret = 0; 569 uint32_t cur_value = 0, value = 0, count = 0; 570 bool cur_value_match_level = false; 571 572 memset(&metrics, 0, sizeof(metrics)); 573 574 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 575 if (ret) 576 return ret; 577 578 switch (clk_type) { 579 case SMU_OD_SCLK: 580 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 581 size = sprintf(buf, "%s:\n", "OD_SCLK"); 582 size += sprintf(buf + size, "0: %10uMhz\n", 583 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 584 size += sprintf(buf + size, "1: %10uMhz\n", 585 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 586 } 587 break; 588 case SMU_OD_CCLK: 589 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 590 size = sprintf(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 591 size += sprintf(buf + size, "0: %10uMhz\n", 592 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 593 size += sprintf(buf + size, "1: %10uMhz\n", 594 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 595 } 596 break; 597 case SMU_OD_RANGE: 598 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 599 size = sprintf(buf, "%s:\n", "OD_RANGE"); 600 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 601 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 602 size += sprintf(buf + size, "CCLK: %7uMhz %10uMhz\n", 603 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 604 } 605 break; 606 case SMU_SOCCLK: 607 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 608 count = clk_table->NumSocClkLevelsEnabled; 609 cur_value = metrics.SocclkFrequency; 610 break; 611 case SMU_VCLK: 612 count = clk_table->VcnClkLevelsEnabled; 613 cur_value = metrics.VclkFrequency; 614 break; 615 case SMU_DCLK: 616 count = clk_table->VcnClkLevelsEnabled; 617 cur_value = metrics.DclkFrequency; 618 break; 619 case SMU_MCLK: 620 count = clk_table->NumDfPstatesEnabled; 621 cur_value = metrics.MemclkFrequency; 622 break; 623 case SMU_FCLK: 624 count = clk_table->NumDfPstatesEnabled; 625 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 626 if (ret) 627 return ret; 628 break; 629 default: 630 break; 631 } 632 633 switch (clk_type) { 634 case SMU_SOCCLK: 635 case SMU_VCLK: 636 case SMU_DCLK: 637 case SMU_MCLK: 638 case SMU_FCLK: 639 for (i = 0; i < count; i++) { 640 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 641 if (ret) 642 return ret; 643 if (!value) 644 continue; 645 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 646 cur_value == value ? "*" : ""); 647 if (cur_value == value) 648 cur_value_match_level = true; 649 } 650 651 if (!cur_value_match_level) 652 size += sprintf(buf + size, " %uMhz *\n", cur_value); 653 break; 654 default: 655 break; 656 } 657 658 return size; 659 } 660 661 static int vangogh_print_clk_levels(struct smu_context *smu, 662 enum smu_clk_type clk_type, char *buf) 663 { 664 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 665 SmuMetrics_t metrics; 666 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 667 int i, size = 0, ret = 0; 668 uint32_t cur_value = 0, value = 0, count = 0; 669 bool cur_value_match_level = false; 670 671 memset(&metrics, 0, sizeof(metrics)); 672 673 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 674 if (ret) 675 return ret; 676 677 switch (clk_type) { 678 case SMU_OD_SCLK: 679 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 680 size = sprintf(buf, "%s:\n", "OD_SCLK"); 681 size += sprintf(buf + size, "0: %10uMhz\n", 682 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 683 size += sprintf(buf + size, "1: %10uMhz\n", 684 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 685 } 686 break; 687 case SMU_OD_CCLK: 688 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 689 size = sprintf(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 690 size += sprintf(buf + size, "0: %10uMhz\n", 691 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 692 size += sprintf(buf + size, "1: %10uMhz\n", 693 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 694 } 695 break; 696 case SMU_OD_RANGE: 697 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 698 size = sprintf(buf, "%s:\n", "OD_RANGE"); 699 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 700 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 701 size += sprintf(buf + size, "CCLK: %7uMhz %10uMhz\n", 702 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 703 } 704 break; 705 case SMU_SOCCLK: 706 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 707 count = clk_table->NumSocClkLevelsEnabled; 708 cur_value = metrics.Current.SocclkFrequency; 709 break; 710 case SMU_VCLK: 711 count = clk_table->VcnClkLevelsEnabled; 712 cur_value = metrics.Current.VclkFrequency; 713 break; 714 case SMU_DCLK: 715 count = clk_table->VcnClkLevelsEnabled; 716 cur_value = metrics.Current.DclkFrequency; 717 break; 718 case SMU_MCLK: 719 count = clk_table->NumDfPstatesEnabled; 720 cur_value = metrics.Current.MemclkFrequency; 721 break; 722 case SMU_FCLK: 723 count = clk_table->NumDfPstatesEnabled; 724 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 725 if (ret) 726 return ret; 727 break; 728 default: 729 break; 730 } 731 732 switch (clk_type) { 733 case SMU_SOCCLK: 734 case SMU_VCLK: 735 case SMU_DCLK: 736 case SMU_MCLK: 737 case SMU_FCLK: 738 for (i = 0; i < count; i++) { 739 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 740 if (ret) 741 return ret; 742 if (!value) 743 continue; 744 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 745 cur_value == value ? "*" : ""); 746 if (cur_value == value) 747 cur_value_match_level = true; 748 } 749 750 if (!cur_value_match_level) 751 size += sprintf(buf + size, " %uMhz *\n", cur_value); 752 break; 753 default: 754 break; 755 } 756 757 return size; 758 } 759 760 static int vangogh_common_print_clk_levels(struct smu_context *smu, 761 enum smu_clk_type clk_type, char *buf) 762 { 763 struct amdgpu_device *adev = smu->adev; 764 uint32_t if_version; 765 int ret = 0; 766 767 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 768 if (ret) { 769 dev_err(adev->dev, "Failed to get smu if version!\n"); 770 return ret; 771 } 772 773 if (if_version < 0x3) 774 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf); 775 else 776 ret = vangogh_print_clk_levels(smu, clk_type, buf); 777 778 return ret; 779 } 780 781 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 782 enum amd_dpm_forced_level level, 783 uint32_t *vclk_mask, 784 uint32_t *dclk_mask, 785 uint32_t *mclk_mask, 786 uint32_t *fclk_mask, 787 uint32_t *soc_mask) 788 { 789 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 790 791 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 792 if (mclk_mask) 793 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 794 795 if (fclk_mask) 796 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 797 798 if (soc_mask) 799 *soc_mask = 0; 800 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 801 if (mclk_mask) 802 *mclk_mask = 0; 803 804 if (fclk_mask) 805 *fclk_mask = 0; 806 807 if (soc_mask) 808 *soc_mask = 1; 809 810 if (vclk_mask) 811 *vclk_mask = 1; 812 813 if (dclk_mask) 814 *dclk_mask = 1; 815 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 816 if (mclk_mask) 817 *mclk_mask = 0; 818 819 if (fclk_mask) 820 *fclk_mask = 0; 821 822 if (soc_mask) 823 *soc_mask = 1; 824 825 if (vclk_mask) 826 *vclk_mask = 1; 827 828 if (dclk_mask) 829 *dclk_mask = 1; 830 } 831 832 return 0; 833 } 834 835 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 836 enum smu_clk_type clk_type) 837 { 838 enum smu_feature_mask feature_id = 0; 839 840 switch (clk_type) { 841 case SMU_MCLK: 842 case SMU_UCLK: 843 case SMU_FCLK: 844 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 845 break; 846 case SMU_GFXCLK: 847 case SMU_SCLK: 848 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 849 break; 850 case SMU_SOCCLK: 851 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 852 break; 853 case SMU_VCLK: 854 case SMU_DCLK: 855 feature_id = SMU_FEATURE_VCN_DPM_BIT; 856 break; 857 default: 858 return true; 859 } 860 861 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 862 return false; 863 864 return true; 865 } 866 867 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 868 enum smu_clk_type clk_type, 869 uint32_t *min, 870 uint32_t *max) 871 { 872 int ret = 0; 873 uint32_t soc_mask; 874 uint32_t vclk_mask; 875 uint32_t dclk_mask; 876 uint32_t mclk_mask; 877 uint32_t fclk_mask; 878 uint32_t clock_limit; 879 880 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 881 switch (clk_type) { 882 case SMU_MCLK: 883 case SMU_UCLK: 884 clock_limit = smu->smu_table.boot_values.uclk; 885 break; 886 case SMU_FCLK: 887 clock_limit = smu->smu_table.boot_values.fclk; 888 break; 889 case SMU_GFXCLK: 890 case SMU_SCLK: 891 clock_limit = smu->smu_table.boot_values.gfxclk; 892 break; 893 case SMU_SOCCLK: 894 clock_limit = smu->smu_table.boot_values.socclk; 895 break; 896 case SMU_VCLK: 897 clock_limit = smu->smu_table.boot_values.vclk; 898 break; 899 case SMU_DCLK: 900 clock_limit = smu->smu_table.boot_values.dclk; 901 break; 902 default: 903 clock_limit = 0; 904 break; 905 } 906 907 /* clock in Mhz unit */ 908 if (min) 909 *min = clock_limit / 100; 910 if (max) 911 *max = clock_limit / 100; 912 913 return 0; 914 } 915 if (max) { 916 ret = vangogh_get_profiling_clk_mask(smu, 917 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 918 &vclk_mask, 919 &dclk_mask, 920 &mclk_mask, 921 &fclk_mask, 922 &soc_mask); 923 if (ret) 924 goto failed; 925 926 switch (clk_type) { 927 case SMU_UCLK: 928 case SMU_MCLK: 929 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 930 if (ret) 931 goto failed; 932 break; 933 case SMU_SOCCLK: 934 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 935 if (ret) 936 goto failed; 937 break; 938 case SMU_FCLK: 939 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 940 if (ret) 941 goto failed; 942 break; 943 case SMU_VCLK: 944 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 945 if (ret) 946 goto failed; 947 break; 948 case SMU_DCLK: 949 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 950 if (ret) 951 goto failed; 952 break; 953 default: 954 ret = -EINVAL; 955 goto failed; 956 } 957 } 958 if (min) { 959 switch (clk_type) { 960 case SMU_UCLK: 961 case SMU_MCLK: 962 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 963 if (ret) 964 goto failed; 965 break; 966 case SMU_SOCCLK: 967 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 968 if (ret) 969 goto failed; 970 break; 971 case SMU_FCLK: 972 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 973 if (ret) 974 goto failed; 975 break; 976 case SMU_VCLK: 977 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 978 if (ret) 979 goto failed; 980 break; 981 case SMU_DCLK: 982 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 983 if (ret) 984 goto failed; 985 break; 986 default: 987 ret = -EINVAL; 988 goto failed; 989 } 990 } 991 failed: 992 return ret; 993 } 994 995 static int vangogh_get_power_profile_mode(struct smu_context *smu, 996 char *buf) 997 { 998 static const char *profile_name[] = { 999 "BOOTUP_DEFAULT", 1000 "3D_FULL_SCREEN", 1001 "POWER_SAVING", 1002 "VIDEO", 1003 "VR", 1004 "COMPUTE", 1005 "CUSTOM"}; 1006 uint32_t i, size = 0; 1007 int16_t workload_type = 0; 1008 1009 if (!buf) 1010 return -EINVAL; 1011 1012 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1013 /* 1014 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1015 * Not all profile modes are supported on vangogh. 1016 */ 1017 workload_type = smu_cmn_to_asic_specific_index(smu, 1018 CMN2ASIC_MAPPING_WORKLOAD, 1019 i); 1020 1021 if (workload_type < 0) 1022 continue; 1023 1024 size += sprintf(buf + size, "%2d %14s%s\n", 1025 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1026 } 1027 1028 return size; 1029 } 1030 1031 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1032 { 1033 int workload_type, ret; 1034 uint32_t profile_mode = input[size]; 1035 1036 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1037 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1038 return -EINVAL; 1039 } 1040 1041 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 1042 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 1043 return 0; 1044 1045 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1046 workload_type = smu_cmn_to_asic_specific_index(smu, 1047 CMN2ASIC_MAPPING_WORKLOAD, 1048 profile_mode); 1049 if (workload_type < 0) { 1050 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 1051 profile_mode); 1052 return -EINVAL; 1053 } 1054 1055 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 1056 1 << workload_type, 1057 NULL); 1058 if (ret) { 1059 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 1060 workload_type); 1061 return ret; 1062 } 1063 1064 smu->power_profile_mode = profile_mode; 1065 1066 return 0; 1067 } 1068 1069 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 1070 enum smu_clk_type clk_type, 1071 uint32_t min, 1072 uint32_t max) 1073 { 1074 int ret = 0; 1075 1076 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 1077 return 0; 1078 1079 switch (clk_type) { 1080 case SMU_GFXCLK: 1081 case SMU_SCLK: 1082 ret = smu_cmn_send_smc_msg_with_param(smu, 1083 SMU_MSG_SetHardMinGfxClk, 1084 min, NULL); 1085 if (ret) 1086 return ret; 1087 1088 ret = smu_cmn_send_smc_msg_with_param(smu, 1089 SMU_MSG_SetSoftMaxGfxClk, 1090 max, NULL); 1091 if (ret) 1092 return ret; 1093 break; 1094 case SMU_FCLK: 1095 ret = smu_cmn_send_smc_msg_with_param(smu, 1096 SMU_MSG_SetHardMinFclkByFreq, 1097 min, NULL); 1098 if (ret) 1099 return ret; 1100 1101 ret = smu_cmn_send_smc_msg_with_param(smu, 1102 SMU_MSG_SetSoftMaxFclkByFreq, 1103 max, NULL); 1104 if (ret) 1105 return ret; 1106 break; 1107 case SMU_SOCCLK: 1108 ret = smu_cmn_send_smc_msg_with_param(smu, 1109 SMU_MSG_SetHardMinSocclkByFreq, 1110 min, NULL); 1111 if (ret) 1112 return ret; 1113 1114 ret = smu_cmn_send_smc_msg_with_param(smu, 1115 SMU_MSG_SetSoftMaxSocclkByFreq, 1116 max, NULL); 1117 if (ret) 1118 return ret; 1119 break; 1120 case SMU_VCLK: 1121 ret = smu_cmn_send_smc_msg_with_param(smu, 1122 SMU_MSG_SetHardMinVcn, 1123 min << 16, NULL); 1124 if (ret) 1125 return ret; 1126 ret = smu_cmn_send_smc_msg_with_param(smu, 1127 SMU_MSG_SetSoftMaxVcn, 1128 max << 16, NULL); 1129 if (ret) 1130 return ret; 1131 break; 1132 case SMU_DCLK: 1133 ret = smu_cmn_send_smc_msg_with_param(smu, 1134 SMU_MSG_SetHardMinVcn, 1135 min, NULL); 1136 if (ret) 1137 return ret; 1138 ret = smu_cmn_send_smc_msg_with_param(smu, 1139 SMU_MSG_SetSoftMaxVcn, 1140 max, NULL); 1141 if (ret) 1142 return ret; 1143 break; 1144 default: 1145 return -EINVAL; 1146 } 1147 1148 return ret; 1149 } 1150 1151 static int vangogh_force_clk_levels(struct smu_context *smu, 1152 enum smu_clk_type clk_type, uint32_t mask) 1153 { 1154 uint32_t soft_min_level = 0, soft_max_level = 0; 1155 uint32_t min_freq = 0, max_freq = 0; 1156 int ret = 0 ; 1157 1158 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1159 soft_max_level = mask ? (fls(mask) - 1) : 0; 1160 1161 switch (clk_type) { 1162 case SMU_SOCCLK: 1163 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1164 soft_min_level, &min_freq); 1165 if (ret) 1166 return ret; 1167 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1168 soft_max_level, &max_freq); 1169 if (ret) 1170 return ret; 1171 ret = smu_cmn_send_smc_msg_with_param(smu, 1172 SMU_MSG_SetSoftMaxSocclkByFreq, 1173 max_freq, NULL); 1174 if (ret) 1175 return ret; 1176 ret = smu_cmn_send_smc_msg_with_param(smu, 1177 SMU_MSG_SetHardMinSocclkByFreq, 1178 min_freq, NULL); 1179 if (ret) 1180 return ret; 1181 break; 1182 case SMU_FCLK: 1183 ret = vangogh_get_dpm_clk_limited(smu, 1184 clk_type, soft_min_level, &min_freq); 1185 if (ret) 1186 return ret; 1187 ret = vangogh_get_dpm_clk_limited(smu, 1188 clk_type, soft_max_level, &max_freq); 1189 if (ret) 1190 return ret; 1191 ret = smu_cmn_send_smc_msg_with_param(smu, 1192 SMU_MSG_SetSoftMaxFclkByFreq, 1193 max_freq, NULL); 1194 if (ret) 1195 return ret; 1196 ret = smu_cmn_send_smc_msg_with_param(smu, 1197 SMU_MSG_SetHardMinFclkByFreq, 1198 min_freq, NULL); 1199 if (ret) 1200 return ret; 1201 break; 1202 case SMU_VCLK: 1203 ret = vangogh_get_dpm_clk_limited(smu, 1204 clk_type, soft_min_level, &min_freq); 1205 if (ret) 1206 return ret; 1207 1208 ret = vangogh_get_dpm_clk_limited(smu, 1209 clk_type, soft_max_level, &max_freq); 1210 if (ret) 1211 return ret; 1212 1213 1214 ret = smu_cmn_send_smc_msg_with_param(smu, 1215 SMU_MSG_SetHardMinVcn, 1216 min_freq << 16, NULL); 1217 if (ret) 1218 return ret; 1219 1220 ret = smu_cmn_send_smc_msg_with_param(smu, 1221 SMU_MSG_SetSoftMaxVcn, 1222 max_freq << 16, NULL); 1223 if (ret) 1224 return ret; 1225 1226 break; 1227 case SMU_DCLK: 1228 ret = vangogh_get_dpm_clk_limited(smu, 1229 clk_type, soft_min_level, &min_freq); 1230 if (ret) 1231 return ret; 1232 1233 ret = vangogh_get_dpm_clk_limited(smu, 1234 clk_type, soft_max_level, &max_freq); 1235 if (ret) 1236 return ret; 1237 1238 ret = smu_cmn_send_smc_msg_with_param(smu, 1239 SMU_MSG_SetHardMinVcn, 1240 min_freq, NULL); 1241 if (ret) 1242 return ret; 1243 1244 ret = smu_cmn_send_smc_msg_with_param(smu, 1245 SMU_MSG_SetSoftMaxVcn, 1246 max_freq, NULL); 1247 if (ret) 1248 return ret; 1249 1250 break; 1251 default: 1252 break; 1253 } 1254 1255 return ret; 1256 } 1257 1258 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1259 { 1260 int ret = 0, i = 0; 1261 uint32_t min_freq, max_freq, force_freq; 1262 enum smu_clk_type clk_type; 1263 1264 enum smu_clk_type clks[] = { 1265 SMU_SOCCLK, 1266 SMU_VCLK, 1267 SMU_DCLK, 1268 SMU_FCLK, 1269 }; 1270 1271 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1272 clk_type = clks[i]; 1273 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1274 if (ret) 1275 return ret; 1276 1277 force_freq = highest ? max_freq : min_freq; 1278 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1279 if (ret) 1280 return ret; 1281 } 1282 1283 return ret; 1284 } 1285 1286 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1287 { 1288 int ret = 0, i = 0; 1289 uint32_t min_freq, max_freq; 1290 enum smu_clk_type clk_type; 1291 1292 struct clk_feature_map { 1293 enum smu_clk_type clk_type; 1294 uint32_t feature; 1295 } clk_feature_map[] = { 1296 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1297 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1298 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1299 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1300 }; 1301 1302 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1303 1304 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1305 continue; 1306 1307 clk_type = clk_feature_map[i].clk_type; 1308 1309 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1310 1311 if (ret) 1312 return ret; 1313 1314 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1315 1316 if (ret) 1317 return ret; 1318 } 1319 1320 return ret; 1321 } 1322 1323 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1324 { 1325 int ret = 0; 1326 uint32_t socclk_freq = 0, fclk_freq = 0; 1327 uint32_t vclk_freq = 0, dclk_freq = 0; 1328 1329 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1330 if (ret) 1331 return ret; 1332 1333 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1334 if (ret) 1335 return ret; 1336 1337 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1338 if (ret) 1339 return ret; 1340 1341 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1342 if (ret) 1343 return ret; 1344 1345 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1346 if (ret) 1347 return ret; 1348 1349 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1350 if (ret) 1351 return ret; 1352 1353 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1354 if (ret) 1355 return ret; 1356 1357 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1358 if (ret) 1359 return ret; 1360 1361 return ret; 1362 } 1363 1364 static int vangogh_set_performance_level(struct smu_context *smu, 1365 enum amd_dpm_forced_level level) 1366 { 1367 int ret = 0; 1368 uint32_t soc_mask, mclk_mask, fclk_mask; 1369 uint32_t vclk_mask = 0, dclk_mask = 0; 1370 1371 switch (level) { 1372 case AMD_DPM_FORCED_LEVEL_HIGH: 1373 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1374 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1375 1376 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1377 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1378 1379 ret = vangogh_force_dpm_limit_value(smu, true); 1380 break; 1381 case AMD_DPM_FORCED_LEVEL_LOW: 1382 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1383 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1384 1385 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1386 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1387 1388 ret = vangogh_force_dpm_limit_value(smu, false); 1389 break; 1390 case AMD_DPM_FORCED_LEVEL_AUTO: 1391 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1392 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1393 1394 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1395 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1396 1397 ret = vangogh_unforce_dpm_levels(smu); 1398 break; 1399 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1400 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1401 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1402 1403 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1404 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1405 1406 ret = smu_cmn_send_smc_msg_with_param(smu, 1407 SMU_MSG_SetHardMinGfxClk, 1408 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1409 if (ret) 1410 return ret; 1411 1412 ret = smu_cmn_send_smc_msg_with_param(smu, 1413 SMU_MSG_SetSoftMaxGfxClk, 1414 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1415 if (ret) 1416 return ret; 1417 1418 ret = vangogh_get_profiling_clk_mask(smu, level, 1419 &vclk_mask, 1420 &dclk_mask, 1421 &mclk_mask, 1422 &fclk_mask, 1423 &soc_mask); 1424 if (ret) 1425 return ret; 1426 1427 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1428 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1429 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1430 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1431 1432 break; 1433 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1434 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1435 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1436 1437 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1438 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1439 1440 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, 1441 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1442 if (ret) 1443 return ret; 1444 1445 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, 1446 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1447 if (ret) 1448 return ret; 1449 break; 1450 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1451 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1452 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1453 1454 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1455 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1456 1457 ret = vangogh_get_profiling_clk_mask(smu, level, 1458 NULL, 1459 NULL, 1460 &mclk_mask, 1461 &fclk_mask, 1462 NULL); 1463 if (ret) 1464 return ret; 1465 1466 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1467 break; 1468 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1469 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1470 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1471 1472 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1473 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1474 1475 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1476 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1477 if (ret) 1478 return ret; 1479 1480 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1481 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1482 if (ret) 1483 return ret; 1484 1485 ret = vangogh_set_peak_clock_by_device(smu); 1486 break; 1487 case AMD_DPM_FORCED_LEVEL_MANUAL: 1488 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1489 default: 1490 break; 1491 } 1492 return ret; 1493 } 1494 1495 static int vangogh_read_sensor(struct smu_context *smu, 1496 enum amd_pp_sensors sensor, 1497 void *data, uint32_t *size) 1498 { 1499 int ret = 0; 1500 1501 if (!data || !size) 1502 return -EINVAL; 1503 1504 mutex_lock(&smu->sensor_lock); 1505 switch (sensor) { 1506 case AMDGPU_PP_SENSOR_GPU_LOAD: 1507 ret = vangogh_common_get_smu_metrics_data(smu, 1508 METRICS_AVERAGE_GFXACTIVITY, 1509 (uint32_t *)data); 1510 *size = 4; 1511 break; 1512 case AMDGPU_PP_SENSOR_GPU_POWER: 1513 ret = vangogh_common_get_smu_metrics_data(smu, 1514 METRICS_AVERAGE_SOCKETPOWER, 1515 (uint32_t *)data); 1516 *size = 4; 1517 break; 1518 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1519 ret = vangogh_common_get_smu_metrics_data(smu, 1520 METRICS_TEMPERATURE_EDGE, 1521 (uint32_t *)data); 1522 *size = 4; 1523 break; 1524 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1525 ret = vangogh_common_get_smu_metrics_data(smu, 1526 METRICS_TEMPERATURE_HOTSPOT, 1527 (uint32_t *)data); 1528 *size = 4; 1529 break; 1530 case AMDGPU_PP_SENSOR_GFX_MCLK: 1531 ret = vangogh_common_get_smu_metrics_data(smu, 1532 METRICS_CURR_UCLK, 1533 (uint32_t *)data); 1534 *(uint32_t *)data *= 100; 1535 *size = 4; 1536 break; 1537 case AMDGPU_PP_SENSOR_GFX_SCLK: 1538 ret = vangogh_common_get_smu_metrics_data(smu, 1539 METRICS_CURR_GFXCLK, 1540 (uint32_t *)data); 1541 *(uint32_t *)data *= 100; 1542 *size = 4; 1543 break; 1544 case AMDGPU_PP_SENSOR_VDDGFX: 1545 ret = vangogh_common_get_smu_metrics_data(smu, 1546 METRICS_VOLTAGE_VDDGFX, 1547 (uint32_t *)data); 1548 *size = 4; 1549 break; 1550 case AMDGPU_PP_SENSOR_VDDNB: 1551 ret = vangogh_common_get_smu_metrics_data(smu, 1552 METRICS_VOLTAGE_VDDSOC, 1553 (uint32_t *)data); 1554 *size = 4; 1555 break; 1556 case AMDGPU_PP_SENSOR_CPU_CLK: 1557 ret = vangogh_common_get_smu_metrics_data(smu, 1558 METRICS_AVERAGE_CPUCLK, 1559 (uint32_t *)data); 1560 *size = smu->cpu_core_num * sizeof(uint16_t); 1561 break; 1562 default: 1563 ret = -EOPNOTSUPP; 1564 break; 1565 } 1566 mutex_unlock(&smu->sensor_lock); 1567 1568 return ret; 1569 } 1570 1571 static int vangogh_set_watermarks_table(struct smu_context *smu, 1572 struct pp_smu_wm_range_sets *clock_ranges) 1573 { 1574 int i; 1575 int ret = 0; 1576 Watermarks_t *table = smu->smu_table.watermarks_table; 1577 1578 if (!table || !clock_ranges) 1579 return -EINVAL; 1580 1581 if (clock_ranges) { 1582 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1583 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1584 return -EINVAL; 1585 1586 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1587 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1588 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1589 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1590 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1591 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1592 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1593 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1594 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1595 1596 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1597 clock_ranges->reader_wm_sets[i].wm_inst; 1598 } 1599 1600 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1601 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1602 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1603 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1604 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1605 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1606 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1607 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1608 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1609 1610 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1611 clock_ranges->writer_wm_sets[i].wm_inst; 1612 } 1613 1614 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1615 } 1616 1617 /* pass data to smu controller */ 1618 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1619 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1620 ret = smu_cmn_write_watermarks_table(smu); 1621 if (ret) { 1622 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1623 return ret; 1624 } 1625 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1626 } 1627 1628 return 0; 1629 } 1630 1631 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, 1632 void **table) 1633 { 1634 struct smu_table_context *smu_table = &smu->smu_table; 1635 struct gpu_metrics_v2_1 *gpu_metrics = 1636 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; 1637 SmuMetrics_legacy_t metrics; 1638 int ret = 0; 1639 1640 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1641 if (ret) 1642 return ret; 1643 1644 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); 1645 1646 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1647 gpu_metrics->temperature_soc = metrics.SocTemperature; 1648 memcpy(&gpu_metrics->temperature_core[0], 1649 &metrics.CoreTemperature[0], 1650 sizeof(uint16_t) * 4); 1651 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1652 1653 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1654 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1655 1656 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1657 gpu_metrics->average_cpu_power = metrics.Power[0]; 1658 gpu_metrics->average_soc_power = metrics.Power[1]; 1659 gpu_metrics->average_gfx_power = metrics.Power[2]; 1660 memcpy(&gpu_metrics->average_core_power[0], 1661 &metrics.CorePower[0], 1662 sizeof(uint16_t) * 4); 1663 1664 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1665 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1666 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1667 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1668 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1669 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1670 1671 memcpy(&gpu_metrics->current_coreclk[0], 1672 &metrics.CoreFrequency[0], 1673 sizeof(uint16_t) * 4); 1674 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1675 1676 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1677 1678 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1679 1680 *table = (void *)gpu_metrics; 1681 1682 return sizeof(struct gpu_metrics_v2_1); 1683 } 1684 1685 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1686 void **table) 1687 { 1688 struct smu_table_context *smu_table = &smu->smu_table; 1689 struct gpu_metrics_v2_1 *gpu_metrics = 1690 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; 1691 SmuMetrics_t metrics; 1692 int ret = 0; 1693 1694 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1695 if (ret) 1696 return ret; 1697 1698 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); 1699 1700 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1701 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1702 memcpy(&gpu_metrics->temperature_core[0], 1703 &metrics.Current.CoreTemperature[0], 1704 sizeof(uint16_t) * 4); 1705 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1706 1707 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1708 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1709 1710 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1711 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1712 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1713 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1714 memcpy(&gpu_metrics->average_core_power[0], 1715 &metrics.Average.CorePower[0], 1716 sizeof(uint16_t) * 4); 1717 1718 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1719 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1720 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1721 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1722 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1723 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1724 1725 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1726 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1727 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1728 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1729 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1730 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1731 1732 memcpy(&gpu_metrics->current_coreclk[0], 1733 &metrics.Current.CoreFrequency[0], 1734 sizeof(uint16_t) * 4); 1735 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1736 1737 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1738 1739 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1740 1741 *table = (void *)gpu_metrics; 1742 1743 return sizeof(struct gpu_metrics_v2_1); 1744 } 1745 1746 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, 1747 void **table) 1748 { 1749 struct amdgpu_device *adev = smu->adev; 1750 uint32_t if_version; 1751 int ret = 0; 1752 1753 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 1754 if (ret) { 1755 dev_err(adev->dev, "Failed to get smu if version!\n"); 1756 return ret; 1757 } 1758 1759 if (if_version < 0x3) 1760 ret = vangogh_get_legacy_gpu_metrics(smu, table); 1761 else 1762 ret = vangogh_get_gpu_metrics(smu, table); 1763 1764 return ret; 1765 } 1766 1767 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1768 long input[], uint32_t size) 1769 { 1770 int ret = 0; 1771 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1772 1773 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 1774 dev_warn(smu->adev->dev, 1775 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 1776 return -EINVAL; 1777 } 1778 1779 switch (type) { 1780 case PP_OD_EDIT_CCLK_VDDC_TABLE: 1781 if (size != 3) { 1782 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 1783 return -EINVAL; 1784 } 1785 if (input[0] >= smu->cpu_core_num) { 1786 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 1787 smu->cpu_core_num); 1788 } 1789 smu->cpu_core_id_select = input[0]; 1790 if (input[1] == 0) { 1791 if (input[2] < smu->cpu_default_soft_min_freq) { 1792 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1793 input[2], smu->cpu_default_soft_min_freq); 1794 return -EINVAL; 1795 } 1796 smu->cpu_actual_soft_min_freq = input[2]; 1797 } else if (input[1] == 1) { 1798 if (input[2] > smu->cpu_default_soft_max_freq) { 1799 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1800 input[2], smu->cpu_default_soft_max_freq); 1801 return -EINVAL; 1802 } 1803 smu->cpu_actual_soft_max_freq = input[2]; 1804 } else { 1805 return -EINVAL; 1806 } 1807 break; 1808 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1809 if (size != 2) { 1810 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1811 return -EINVAL; 1812 } 1813 1814 if (input[0] == 0) { 1815 if (input[1] < smu->gfx_default_hard_min_freq) { 1816 dev_warn(smu->adev->dev, 1817 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1818 input[1], smu->gfx_default_hard_min_freq); 1819 return -EINVAL; 1820 } 1821 smu->gfx_actual_hard_min_freq = input[1]; 1822 } else if (input[0] == 1) { 1823 if (input[1] > smu->gfx_default_soft_max_freq) { 1824 dev_warn(smu->adev->dev, 1825 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1826 input[1], smu->gfx_default_soft_max_freq); 1827 return -EINVAL; 1828 } 1829 smu->gfx_actual_soft_max_freq = input[1]; 1830 } else { 1831 return -EINVAL; 1832 } 1833 break; 1834 case PP_OD_RESTORE_DEFAULT_TABLE: 1835 if (size != 0) { 1836 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1837 return -EINVAL; 1838 } else { 1839 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1840 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1841 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1842 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1843 } 1844 break; 1845 case PP_OD_COMMIT_DPM_TABLE: 1846 if (size != 0) { 1847 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1848 return -EINVAL; 1849 } else { 1850 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1851 dev_err(smu->adev->dev, 1852 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1853 smu->gfx_actual_hard_min_freq, 1854 smu->gfx_actual_soft_max_freq); 1855 return -EINVAL; 1856 } 1857 1858 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1859 smu->gfx_actual_hard_min_freq, NULL); 1860 if (ret) { 1861 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1862 return ret; 1863 } 1864 1865 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1866 smu->gfx_actual_soft_max_freq, NULL); 1867 if (ret) { 1868 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1869 return ret; 1870 } 1871 1872 if (smu->adev->pm.fw_version < 0x43f1b00) { 1873 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 1874 break; 1875 } 1876 1877 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1878 ((smu->cpu_core_id_select << 20) 1879 | smu->cpu_actual_soft_min_freq), 1880 NULL); 1881 if (ret) { 1882 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 1883 return ret; 1884 } 1885 1886 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1887 ((smu->cpu_core_id_select << 20) 1888 | smu->cpu_actual_soft_max_freq), 1889 NULL); 1890 if (ret) { 1891 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 1892 return ret; 1893 } 1894 } 1895 break; 1896 default: 1897 return -ENOSYS; 1898 } 1899 1900 return ret; 1901 } 1902 1903 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 1904 { 1905 struct smu_table_context *smu_table = &smu->smu_table; 1906 1907 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 1908 } 1909 1910 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1911 { 1912 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1913 1914 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1915 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1916 smu->gfx_actual_hard_min_freq = 0; 1917 smu->gfx_actual_soft_max_freq = 0; 1918 1919 smu->cpu_default_soft_min_freq = 1400; 1920 smu->cpu_default_soft_max_freq = 3500; 1921 smu->cpu_actual_soft_min_freq = 0; 1922 smu->cpu_actual_soft_max_freq = 0; 1923 1924 return 0; 1925 } 1926 1927 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 1928 { 1929 DpmClocks_t *table = smu->smu_table.clocks_table; 1930 int i; 1931 1932 if (!clock_table || !table) 1933 return -EINVAL; 1934 1935 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 1936 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 1937 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 1938 } 1939 1940 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1941 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 1942 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 1943 } 1944 1945 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1946 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 1947 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 1948 } 1949 1950 return 0; 1951 } 1952 1953 1954 static int vangogh_system_features_control(struct smu_context *smu, bool en) 1955 { 1956 struct amdgpu_device *adev = smu->adev; 1957 struct smu_feature *feature = &smu->smu_feature; 1958 uint32_t feature_mask[2]; 1959 int ret = 0; 1960 1961 if (adev->pm.fw_version >= 0x43f1700 && !en) 1962 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 1963 RLC_STATUS_OFF, NULL); 1964 1965 bitmap_zero(feature->enabled, feature->feature_num); 1966 bitmap_zero(feature->supported, feature->feature_num); 1967 1968 if (!en) 1969 return ret; 1970 1971 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 1972 if (ret) 1973 return ret; 1974 1975 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, 1976 feature->feature_num); 1977 bitmap_copy(feature->supported, (unsigned long *)&feature_mask, 1978 feature->feature_num); 1979 1980 return 0; 1981 } 1982 1983 static int vangogh_post_smu_init(struct smu_context *smu) 1984 { 1985 struct amdgpu_device *adev = smu->adev; 1986 uint32_t tmp; 1987 int ret = 0; 1988 uint8_t aon_bits = 0; 1989 /* Two CUs in one WGP */ 1990 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 1991 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 1992 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1993 1994 /* allow message will be sent after enable message on Vangogh*/ 1995 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 1996 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 1997 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 1998 if (ret) { 1999 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 2000 return ret; 2001 } 2002 } else { 2003 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 2004 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 2005 } 2006 2007 /* if all CUs are active, no need to power off any WGPs */ 2008 if (total_cu == adev->gfx.cu_info.number) 2009 return 0; 2010 2011 /* 2012 * Calculate the total bits number of always on WGPs for all SA/SEs in 2013 * RLC_PG_ALWAYS_ON_WGP_MASK. 2014 */ 2015 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 2016 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 2017 2018 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2019 2020 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 2021 if (aon_bits > req_active_wgps) { 2022 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 2023 return 0; 2024 } else { 2025 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 2026 } 2027 } 2028 2029 static int vangogh_mode_reset(struct smu_context *smu, int type) 2030 { 2031 int ret = 0, index = 0; 2032 2033 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2034 SMU_MSG_GfxDeviceDriverReset); 2035 if (index < 0) 2036 return index == -EACCES ? 0 : index; 2037 2038 mutex_lock(&smu->message_lock); 2039 2040 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 2041 2042 mutex_unlock(&smu->message_lock); 2043 2044 mdelay(10); 2045 2046 return ret; 2047 } 2048 2049 static int vangogh_mode2_reset(struct smu_context *smu) 2050 { 2051 return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 2052 } 2053 2054 static int vangogh_get_power_limit(struct smu_context *smu) 2055 { 2056 struct smu_11_5_power_context *power_context = 2057 smu->smu_power.power_context; 2058 uint32_t ppt_limit; 2059 int ret = 0; 2060 2061 if (smu->adev->pm.fw_version < 0x43f1e00) 2062 return ret; 2063 2064 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 2065 if (ret) { 2066 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 2067 return ret; 2068 } 2069 /* convert from milliwatt to watt */ 2070 smu->current_power_limit = smu->default_power_limit = ppt_limit / 1000; 2071 smu->max_power_limit = 29; 2072 2073 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 2074 if (ret) { 2075 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 2076 return ret; 2077 } 2078 /* convert from milliwatt to watt */ 2079 power_context->current_fast_ppt_limit = 2080 power_context->default_fast_ppt_limit = ppt_limit / 1000; 2081 power_context->max_fast_ppt_limit = 30; 2082 2083 return ret; 2084 } 2085 2086 static int vangogh_get_ppt_limit(struct smu_context *smu, 2087 uint32_t *ppt_limit, 2088 enum smu_ppt_limit_type type, 2089 enum smu_ppt_limit_level level) 2090 { 2091 struct smu_11_5_power_context *power_context = 2092 smu->smu_power.power_context; 2093 2094 if (!power_context) 2095 return -EOPNOTSUPP; 2096 2097 if (type == SMU_FAST_PPT_LIMIT) { 2098 switch (level) { 2099 case SMU_PPT_LIMIT_MAX: 2100 *ppt_limit = power_context->max_fast_ppt_limit; 2101 break; 2102 case SMU_PPT_LIMIT_CURRENT: 2103 *ppt_limit = power_context->current_fast_ppt_limit; 2104 break; 2105 case SMU_PPT_LIMIT_DEFAULT: 2106 *ppt_limit = power_context->default_fast_ppt_limit; 2107 break; 2108 default: 2109 break; 2110 } 2111 } 2112 2113 return 0; 2114 } 2115 2116 static int vangogh_set_power_limit(struct smu_context *smu, uint32_t ppt_limit) 2117 { 2118 struct smu_11_5_power_context *power_context = 2119 smu->smu_power.power_context; 2120 uint32_t limit_type = ppt_limit >> 24; 2121 int ret = 0; 2122 2123 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 2124 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 2125 return -EOPNOTSUPP; 2126 } 2127 2128 switch (limit_type) { 2129 case SMU_DEFAULT_PPT_LIMIT: 2130 ret = smu_cmn_send_smc_msg_with_param(smu, 2131 SMU_MSG_SetSlowPPTLimit, 2132 ppt_limit * 1000, /* convert from watt to milliwatt */ 2133 NULL); 2134 if (ret) 2135 return ret; 2136 2137 smu->current_power_limit = ppt_limit; 2138 break; 2139 case SMU_FAST_PPT_LIMIT: 2140 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 2141 if (ppt_limit > power_context->max_fast_ppt_limit) { 2142 dev_err(smu->adev->dev, 2143 "New power limit (%d) is over the max allowed %d\n", 2144 ppt_limit, power_context->max_fast_ppt_limit); 2145 return ret; 2146 } 2147 2148 ret = smu_cmn_send_smc_msg_with_param(smu, 2149 SMU_MSG_SetFastPPTLimit, 2150 ppt_limit * 1000, /* convert from watt to milliwatt */ 2151 NULL); 2152 if (ret) 2153 return ret; 2154 2155 power_context->current_fast_ppt_limit = ppt_limit; 2156 break; 2157 default: 2158 return -EINVAL; 2159 } 2160 2161 return ret; 2162 } 2163 2164 static const struct pptable_funcs vangogh_ppt_funcs = { 2165 2166 .check_fw_status = smu_v11_0_check_fw_status, 2167 .check_fw_version = smu_v11_0_check_fw_version, 2168 .init_smc_tables = vangogh_init_smc_tables, 2169 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2170 .init_power = smu_v11_0_init_power, 2171 .fini_power = smu_v11_0_fini_power, 2172 .register_irq_handler = smu_v11_0_register_irq_handler, 2173 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2174 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2175 .send_smc_msg = smu_cmn_send_smc_msg, 2176 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 2177 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 2178 .is_dpm_running = vangogh_is_dpm_running, 2179 .read_sensor = vangogh_read_sensor, 2180 .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask, 2181 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2182 .set_watermarks_table = vangogh_set_watermarks_table, 2183 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2184 .interrupt_work = smu_v11_0_interrupt_work, 2185 .get_gpu_metrics = vangogh_common_get_gpu_metrics, 2186 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 2187 .print_clk_levels = vangogh_common_print_clk_levels, 2188 .set_default_dpm_table = vangogh_set_default_dpm_tables, 2189 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 2190 .system_features_control = vangogh_system_features_control, 2191 .feature_is_enabled = smu_cmn_feature_is_enabled, 2192 .set_power_profile_mode = vangogh_set_power_profile_mode, 2193 .get_power_profile_mode = vangogh_get_power_profile_mode, 2194 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 2195 .force_clk_levels = vangogh_force_clk_levels, 2196 .set_performance_level = vangogh_set_performance_level, 2197 .post_init = vangogh_post_smu_init, 2198 .mode2_reset = vangogh_mode2_reset, 2199 .gfx_off_control = smu_v11_0_gfx_off_control, 2200 .get_ppt_limit = vangogh_get_ppt_limit, 2201 .get_power_limit = vangogh_get_power_limit, 2202 .set_power_limit = vangogh_set_power_limit, 2203 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2204 }; 2205 2206 void vangogh_set_ppt_funcs(struct smu_context *smu) 2207 { 2208 smu->ppt_funcs = &vangogh_ppt_funcs; 2209 smu->message_map = vangogh_message_map; 2210 smu->feature_map = vangogh_feature_mask_map; 2211 smu->table_map = vangogh_table_map; 2212 smu->workload_map = vangogh_workload_map; 2213 smu->is_apu = true; 2214 } 2215