1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 #include <asm/processor.h> 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 // Registers related to GFXOFF 50 // addressBlock: smuio_smuio_SmuSmuioDec 51 // base address: 0x5a000 52 #define mmSMUIO_GFX_MISC_CNTL 0x00c5 53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0 54 55 //SMUIO_GFX_MISC_CNTL 56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0 57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L 59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 64 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 65 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 66 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 67 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 68 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 69 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 70 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 71 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 72 73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 77 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 78 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 79 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 80 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 81 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 82 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 83 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 84 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 85 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 86 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 87 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 88 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 89 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 92 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 93 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 94 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 95 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 96 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 97 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 98 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 99 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 100 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 101 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 102 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 103 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 104 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 105 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 106 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 107 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 110 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 111 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 112 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 113 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 114 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 115 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 116 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 117 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 118 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 119 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 120 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 121 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 122 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 123 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 124 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 125 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 126 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 127 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 128 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 129 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 130 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 131 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 132 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 133 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 134 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 135 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 136 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 137 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 138 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 139 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 140 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 141 MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0), 142 MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0), 143 MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0), 144 }; 145 146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 147 FEA_MAP(PPT), 148 FEA_MAP(TDC), 149 FEA_MAP(THERMAL), 150 FEA_MAP(DS_GFXCLK), 151 FEA_MAP(DS_SOCCLK), 152 FEA_MAP(DS_LCLK), 153 FEA_MAP(DS_FCLK), 154 FEA_MAP(DS_MP1CLK), 155 FEA_MAP(DS_MP0CLK), 156 FEA_MAP(ATHUB_PG), 157 FEA_MAP(CCLK_DPM), 158 FEA_MAP(FAN_CONTROLLER), 159 FEA_MAP(ULV), 160 FEA_MAP(VCN_DPM), 161 FEA_MAP(LCLK_DPM), 162 FEA_MAP(SHUBCLK_DPM), 163 FEA_MAP(DCFCLK_DPM), 164 FEA_MAP(DS_DCFCLK), 165 FEA_MAP(S0I2), 166 FEA_MAP(SMU_LOW_POWER), 167 FEA_MAP(GFX_DEM), 168 FEA_MAP(PSI), 169 FEA_MAP(PROCHOT), 170 FEA_MAP(CPUOFF), 171 FEA_MAP(STAPM), 172 FEA_MAP(S0I3), 173 FEA_MAP(DF_CSTATES), 174 FEA_MAP(PERF_LIMIT), 175 FEA_MAP(CORE_DLDO), 176 FEA_MAP(RSMU_LOW_POWER), 177 FEA_MAP(SMN_LOW_POWER), 178 FEA_MAP(THM_LOW_POWER), 179 FEA_MAP(SMUIO_LOW_POWER), 180 FEA_MAP(MP1_LOW_POWER), 181 FEA_MAP(DS_VCN), 182 FEA_MAP(CPPC), 183 FEA_MAP(OS_CSTATES), 184 FEA_MAP(ISP_DPM), 185 FEA_MAP(A55_DPM), 186 FEA_MAP(CVIP_DSP_DPM), 187 FEA_MAP(MSMU_LOW_POWER), 188 FEA_MAP_REVERSE(SOCCLK), 189 FEA_MAP_REVERSE(FCLK), 190 FEA_MAP_HALF_REVERSE(GFX), 191 }; 192 193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 194 TAB_MAP_VALID(WATERMARKS), 195 TAB_MAP_VALID(SMU_METRICS), 196 TAB_MAP_VALID(CUSTOM_DPM), 197 TAB_MAP_VALID(DPMCLOCKS), 198 }; 199 200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 201 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 202 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT), 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT), 208 }; 209 210 static const uint8_t vangogh_throttler_map[] = { 211 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), 212 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), 213 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), 214 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), 215 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), 216 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), 217 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), 218 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), 219 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), 220 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT), 221 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT), 222 }; 223 224 static int vangogh_tables_init(struct smu_context *smu) 225 { 226 struct smu_table_context *smu_table = &smu->smu_table; 227 struct smu_table *tables = smu_table->tables; 228 uint32_t if_version; 229 uint32_t smu_version; 230 uint32_t ret = 0; 231 232 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 233 if (ret) { 234 return ret; 235 } 236 237 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 238 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 239 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 240 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 241 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 242 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 243 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 244 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 245 246 if (if_version < 0x3) { 247 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t), 248 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 249 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL); 250 } else { 251 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 252 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 253 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 254 } 255 if (!smu_table->metrics_table) 256 goto err0_out; 257 smu_table->metrics_time = 0; 258 259 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); 260 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_3)); 261 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_4)); 262 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 263 if (!smu_table->gpu_metrics_table) 264 goto err1_out; 265 266 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 267 if (!smu_table->watermarks_table) 268 goto err2_out; 269 270 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 271 if (!smu_table->clocks_table) 272 goto err3_out; 273 274 return 0; 275 276 err3_out: 277 kfree(smu_table->watermarks_table); 278 err2_out: 279 kfree(smu_table->gpu_metrics_table); 280 err1_out: 281 kfree(smu_table->metrics_table); 282 err0_out: 283 return -ENOMEM; 284 } 285 286 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu, 287 MetricsMember_t member, 288 uint32_t *value) 289 { 290 struct smu_table_context *smu_table = &smu->smu_table; 291 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table; 292 int ret = 0; 293 294 ret = smu_cmn_get_metrics_table(smu, 295 NULL, 296 false); 297 if (ret) 298 return ret; 299 300 switch (member) { 301 case METRICS_CURR_GFXCLK: 302 *value = metrics->GfxclkFrequency; 303 break; 304 case METRICS_AVERAGE_SOCCLK: 305 *value = metrics->SocclkFrequency; 306 break; 307 case METRICS_AVERAGE_VCLK: 308 *value = metrics->VclkFrequency; 309 break; 310 case METRICS_AVERAGE_DCLK: 311 *value = metrics->DclkFrequency; 312 break; 313 case METRICS_CURR_UCLK: 314 *value = metrics->MemclkFrequency; 315 break; 316 case METRICS_AVERAGE_GFXACTIVITY: 317 *value = metrics->GfxActivity / 100; 318 break; 319 case METRICS_AVERAGE_VCNACTIVITY: 320 *value = metrics->UvdActivity; 321 break; 322 case METRICS_AVERAGE_SOCKETPOWER: 323 *value = (metrics->CurrentSocketPower << 8) / 324 1000 ; 325 break; 326 case METRICS_TEMPERATURE_EDGE: 327 *value = metrics->GfxTemperature / 100 * 328 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 329 break; 330 case METRICS_TEMPERATURE_HOTSPOT: 331 *value = metrics->SocTemperature / 100 * 332 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 333 break; 334 case METRICS_THROTTLER_STATUS: 335 *value = metrics->ThrottlerStatus; 336 break; 337 case METRICS_VOLTAGE_VDDGFX: 338 *value = metrics->Voltage[2]; 339 break; 340 case METRICS_VOLTAGE_VDDSOC: 341 *value = metrics->Voltage[1]; 342 break; 343 case METRICS_AVERAGE_CPUCLK: 344 memcpy(value, &metrics->CoreFrequency[0], 345 smu->cpu_core_num * sizeof(uint16_t)); 346 break; 347 default: 348 *value = UINT_MAX; 349 break; 350 } 351 352 return ret; 353 } 354 355 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 356 MetricsMember_t member, 357 uint32_t *value) 358 { 359 struct smu_table_context *smu_table = &smu->smu_table; 360 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 361 int ret = 0; 362 363 ret = smu_cmn_get_metrics_table(smu, 364 NULL, 365 false); 366 if (ret) 367 return ret; 368 369 switch (member) { 370 case METRICS_CURR_GFXCLK: 371 *value = metrics->Current.GfxclkFrequency; 372 break; 373 case METRICS_AVERAGE_SOCCLK: 374 *value = metrics->Current.SocclkFrequency; 375 break; 376 case METRICS_AVERAGE_VCLK: 377 *value = metrics->Current.VclkFrequency; 378 break; 379 case METRICS_AVERAGE_DCLK: 380 *value = metrics->Current.DclkFrequency; 381 break; 382 case METRICS_CURR_UCLK: 383 *value = metrics->Current.MemclkFrequency; 384 break; 385 case METRICS_AVERAGE_GFXACTIVITY: 386 *value = metrics->Current.GfxActivity; 387 break; 388 case METRICS_AVERAGE_VCNACTIVITY: 389 *value = metrics->Current.UvdActivity; 390 break; 391 case METRICS_AVERAGE_SOCKETPOWER: 392 *value = (metrics->Average.CurrentSocketPower << 8) / 393 1000; 394 break; 395 case METRICS_CURR_SOCKETPOWER: 396 *value = (metrics->Current.CurrentSocketPower << 8) / 397 1000; 398 break; 399 case METRICS_TEMPERATURE_EDGE: 400 *value = metrics->Current.GfxTemperature / 100 * 401 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 402 break; 403 case METRICS_TEMPERATURE_HOTSPOT: 404 *value = metrics->Current.SocTemperature / 100 * 405 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 406 break; 407 case METRICS_THROTTLER_STATUS: 408 *value = metrics->Current.ThrottlerStatus; 409 break; 410 case METRICS_VOLTAGE_VDDGFX: 411 *value = metrics->Current.Voltage[2]; 412 break; 413 case METRICS_VOLTAGE_VDDSOC: 414 *value = metrics->Current.Voltage[1]; 415 break; 416 case METRICS_AVERAGE_CPUCLK: 417 memcpy(value, &metrics->Current.CoreFrequency[0], 418 smu->cpu_core_num * sizeof(uint16_t)); 419 break; 420 default: 421 *value = UINT_MAX; 422 break; 423 } 424 425 return ret; 426 } 427 428 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu, 429 MetricsMember_t member, 430 uint32_t *value) 431 { 432 struct amdgpu_device *adev = smu->adev; 433 uint32_t if_version; 434 int ret = 0; 435 436 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 437 if (ret) { 438 dev_err(adev->dev, "Failed to get smu if version!\n"); 439 return ret; 440 } 441 442 if (if_version < 0x3) 443 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value); 444 else 445 ret = vangogh_get_smu_metrics_data(smu, member, value); 446 447 return ret; 448 } 449 450 static int vangogh_allocate_dpm_context(struct smu_context *smu) 451 { 452 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 453 454 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 455 GFP_KERNEL); 456 if (!smu_dpm->dpm_context) 457 return -ENOMEM; 458 459 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 460 461 return 0; 462 } 463 464 static int vangogh_init_smc_tables(struct smu_context *smu) 465 { 466 int ret = 0; 467 468 ret = vangogh_tables_init(smu); 469 if (ret) 470 return ret; 471 472 ret = vangogh_allocate_dpm_context(smu); 473 if (ret) 474 return ret; 475 476 #ifdef CONFIG_X86 477 /* AMD x86 APU only */ 478 smu->cpu_core_num = boot_cpu_data.x86_max_cores; 479 #else 480 smu->cpu_core_num = 4; 481 #endif 482 483 return smu_v11_0_init_smc_tables(smu); 484 } 485 486 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 487 { 488 int ret = 0; 489 490 if (enable) { 491 /* vcn dpm on is a prerequisite for vcn power gate messages */ 492 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 493 if (ret) 494 return ret; 495 } else { 496 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 497 if (ret) 498 return ret; 499 } 500 501 return ret; 502 } 503 504 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 505 { 506 int ret = 0; 507 508 if (enable) { 509 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 510 if (ret) 511 return ret; 512 } else { 513 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 514 if (ret) 515 return ret; 516 } 517 518 return ret; 519 } 520 521 static bool vangogh_is_dpm_running(struct smu_context *smu) 522 { 523 struct amdgpu_device *adev = smu->adev; 524 int ret = 0; 525 uint64_t feature_enabled; 526 527 /* we need to re-init after suspend so return false */ 528 if (adev->in_suspend) 529 return false; 530 531 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 532 533 if (ret) 534 return false; 535 536 return !!(feature_enabled & SMC_DPM_FEATURE); 537 } 538 539 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 540 uint32_t dpm_level, uint32_t *freq) 541 { 542 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 543 544 if (!clk_table || clk_type >= SMU_CLK_COUNT) 545 return -EINVAL; 546 547 switch (clk_type) { 548 case SMU_SOCCLK: 549 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 550 return -EINVAL; 551 *freq = clk_table->SocClocks[dpm_level]; 552 break; 553 case SMU_VCLK: 554 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 555 return -EINVAL; 556 *freq = clk_table->VcnClocks[dpm_level].vclk; 557 break; 558 case SMU_DCLK: 559 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 560 return -EINVAL; 561 *freq = clk_table->VcnClocks[dpm_level].dclk; 562 break; 563 case SMU_UCLK: 564 case SMU_MCLK: 565 if (dpm_level >= clk_table->NumDfPstatesEnabled) 566 return -EINVAL; 567 *freq = clk_table->DfPstateTable[dpm_level].memclk; 568 569 break; 570 case SMU_FCLK: 571 if (dpm_level >= clk_table->NumDfPstatesEnabled) 572 return -EINVAL; 573 *freq = clk_table->DfPstateTable[dpm_level].fclk; 574 break; 575 default: 576 return -EINVAL; 577 } 578 579 return 0; 580 } 581 582 static int vangogh_print_legacy_clk_levels(struct smu_context *smu, 583 enum smu_clk_type clk_type, char *buf) 584 { 585 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 586 SmuMetrics_legacy_t metrics; 587 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 588 int i, idx, size = 0, ret = 0; 589 uint32_t cur_value = 0, value = 0, count = 0; 590 bool cur_value_match_level = false; 591 592 memset(&metrics, 0, sizeof(metrics)); 593 594 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 595 if (ret) 596 return ret; 597 598 smu_cmn_get_sysfs_buf(&buf, &size); 599 600 switch (clk_type) { 601 case SMU_OD_SCLK: 602 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 603 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 604 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 605 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 606 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 607 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 608 } 609 break; 610 case SMU_OD_CCLK: 611 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 612 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 613 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 614 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 615 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 616 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 617 } 618 break; 619 case SMU_OD_RANGE: 620 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 621 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 622 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 623 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 624 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 625 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 626 } 627 break; 628 case SMU_SOCCLK: 629 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 630 count = clk_table->NumSocClkLevelsEnabled; 631 cur_value = metrics.SocclkFrequency; 632 break; 633 case SMU_VCLK: 634 count = clk_table->VcnClkLevelsEnabled; 635 cur_value = metrics.VclkFrequency; 636 break; 637 case SMU_DCLK: 638 count = clk_table->VcnClkLevelsEnabled; 639 cur_value = metrics.DclkFrequency; 640 break; 641 case SMU_MCLK: 642 count = clk_table->NumDfPstatesEnabled; 643 cur_value = metrics.MemclkFrequency; 644 break; 645 case SMU_FCLK: 646 count = clk_table->NumDfPstatesEnabled; 647 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 648 if (ret) 649 return ret; 650 break; 651 default: 652 break; 653 } 654 655 switch (clk_type) { 656 case SMU_SOCCLK: 657 case SMU_VCLK: 658 case SMU_DCLK: 659 case SMU_MCLK: 660 case SMU_FCLK: 661 for (i = 0; i < count; i++) { 662 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; 663 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); 664 if (ret) 665 return ret; 666 if (!value) 667 continue; 668 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 669 cur_value == value ? "*" : ""); 670 if (cur_value == value) 671 cur_value_match_level = true; 672 } 673 674 if (!cur_value_match_level) 675 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 676 break; 677 default: 678 break; 679 } 680 681 return size; 682 } 683 684 static int vangogh_print_clk_levels(struct smu_context *smu, 685 enum smu_clk_type clk_type, char *buf) 686 { 687 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 688 SmuMetrics_t metrics; 689 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 690 int i, idx, size = 0, ret = 0; 691 uint32_t cur_value = 0, value = 0, count = 0; 692 bool cur_value_match_level = false; 693 uint32_t min, max; 694 695 memset(&metrics, 0, sizeof(metrics)); 696 697 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 698 if (ret) 699 return ret; 700 701 smu_cmn_get_sysfs_buf(&buf, &size); 702 703 switch (clk_type) { 704 case SMU_OD_SCLK: 705 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 706 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 707 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 708 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 709 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 710 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 711 } 712 break; 713 case SMU_OD_CCLK: 714 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 715 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 716 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 717 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 718 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 719 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 720 } 721 break; 722 case SMU_OD_RANGE: 723 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 724 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 725 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 726 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 727 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 728 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 729 } 730 break; 731 case SMU_SOCCLK: 732 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 733 count = clk_table->NumSocClkLevelsEnabled; 734 cur_value = metrics.Current.SocclkFrequency; 735 break; 736 case SMU_VCLK: 737 count = clk_table->VcnClkLevelsEnabled; 738 cur_value = metrics.Current.VclkFrequency; 739 break; 740 case SMU_DCLK: 741 count = clk_table->VcnClkLevelsEnabled; 742 cur_value = metrics.Current.DclkFrequency; 743 break; 744 case SMU_MCLK: 745 count = clk_table->NumDfPstatesEnabled; 746 cur_value = metrics.Current.MemclkFrequency; 747 break; 748 case SMU_FCLK: 749 count = clk_table->NumDfPstatesEnabled; 750 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 751 if (ret) 752 return ret; 753 break; 754 case SMU_GFXCLK: 755 case SMU_SCLK: 756 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value); 757 if (ret) { 758 return ret; 759 } 760 break; 761 default: 762 break; 763 } 764 765 switch (clk_type) { 766 case SMU_SOCCLK: 767 case SMU_VCLK: 768 case SMU_DCLK: 769 case SMU_MCLK: 770 case SMU_FCLK: 771 for (i = 0; i < count; i++) { 772 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; 773 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); 774 if (ret) 775 return ret; 776 if (!value) 777 continue; 778 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 779 cur_value == value ? "*" : ""); 780 if (cur_value == value) 781 cur_value_match_level = true; 782 } 783 784 if (!cur_value_match_level) 785 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 786 break; 787 case SMU_GFXCLK: 788 case SMU_SCLK: 789 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 790 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 791 if (cur_value == max) 792 i = 2; 793 else if (cur_value == min) 794 i = 0; 795 else 796 i = 1; 797 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 798 i == 0 ? "*" : ""); 799 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 800 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, 801 i == 1 ? "*" : ""); 802 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 803 i == 2 ? "*" : ""); 804 break; 805 default: 806 break; 807 } 808 809 return size; 810 } 811 812 static int vangogh_common_print_clk_levels(struct smu_context *smu, 813 enum smu_clk_type clk_type, char *buf) 814 { 815 struct amdgpu_device *adev = smu->adev; 816 uint32_t if_version; 817 int ret = 0; 818 819 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 820 if (ret) { 821 dev_err(adev->dev, "Failed to get smu if version!\n"); 822 return ret; 823 } 824 825 if (if_version < 0x3) 826 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf); 827 else 828 ret = vangogh_print_clk_levels(smu, clk_type, buf); 829 830 return ret; 831 } 832 833 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 834 enum amd_dpm_forced_level level, 835 uint32_t *vclk_mask, 836 uint32_t *dclk_mask, 837 uint32_t *mclk_mask, 838 uint32_t *fclk_mask, 839 uint32_t *soc_mask) 840 { 841 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 842 843 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 844 if (mclk_mask) 845 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 846 847 if (fclk_mask) 848 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 849 850 if (soc_mask) 851 *soc_mask = 0; 852 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 853 if (mclk_mask) 854 *mclk_mask = 0; 855 856 if (fclk_mask) 857 *fclk_mask = 0; 858 859 if (soc_mask) 860 *soc_mask = 1; 861 862 if (vclk_mask) 863 *vclk_mask = 1; 864 865 if (dclk_mask) 866 *dclk_mask = 1; 867 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 868 if (mclk_mask) 869 *mclk_mask = 0; 870 871 if (fclk_mask) 872 *fclk_mask = 0; 873 874 if (soc_mask) 875 *soc_mask = 1; 876 877 if (vclk_mask) 878 *vclk_mask = 1; 879 880 if (dclk_mask) 881 *dclk_mask = 1; 882 } 883 884 return 0; 885 } 886 887 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 888 enum smu_clk_type clk_type) 889 { 890 enum smu_feature_mask feature_id = 0; 891 892 switch (clk_type) { 893 case SMU_MCLK: 894 case SMU_UCLK: 895 case SMU_FCLK: 896 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 897 break; 898 case SMU_GFXCLK: 899 case SMU_SCLK: 900 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 901 break; 902 case SMU_SOCCLK: 903 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 904 break; 905 case SMU_VCLK: 906 case SMU_DCLK: 907 feature_id = SMU_FEATURE_VCN_DPM_BIT; 908 break; 909 default: 910 return true; 911 } 912 913 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 914 return false; 915 916 return true; 917 } 918 919 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 920 enum smu_clk_type clk_type, 921 uint32_t *min, 922 uint32_t *max) 923 { 924 int ret = 0; 925 uint32_t soc_mask; 926 uint32_t vclk_mask; 927 uint32_t dclk_mask; 928 uint32_t mclk_mask; 929 uint32_t fclk_mask; 930 uint32_t clock_limit; 931 932 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 933 switch (clk_type) { 934 case SMU_MCLK: 935 case SMU_UCLK: 936 clock_limit = smu->smu_table.boot_values.uclk; 937 break; 938 case SMU_FCLK: 939 clock_limit = smu->smu_table.boot_values.fclk; 940 break; 941 case SMU_GFXCLK: 942 case SMU_SCLK: 943 clock_limit = smu->smu_table.boot_values.gfxclk; 944 break; 945 case SMU_SOCCLK: 946 clock_limit = smu->smu_table.boot_values.socclk; 947 break; 948 case SMU_VCLK: 949 clock_limit = smu->smu_table.boot_values.vclk; 950 break; 951 case SMU_DCLK: 952 clock_limit = smu->smu_table.boot_values.dclk; 953 break; 954 default: 955 clock_limit = 0; 956 break; 957 } 958 959 /* clock in Mhz unit */ 960 if (min) 961 *min = clock_limit / 100; 962 if (max) 963 *max = clock_limit / 100; 964 965 return 0; 966 } 967 if (max) { 968 ret = vangogh_get_profiling_clk_mask(smu, 969 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 970 &vclk_mask, 971 &dclk_mask, 972 &mclk_mask, 973 &fclk_mask, 974 &soc_mask); 975 if (ret) 976 goto failed; 977 978 switch (clk_type) { 979 case SMU_UCLK: 980 case SMU_MCLK: 981 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 982 if (ret) 983 goto failed; 984 break; 985 case SMU_SOCCLK: 986 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 987 if (ret) 988 goto failed; 989 break; 990 case SMU_FCLK: 991 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 992 if (ret) 993 goto failed; 994 break; 995 case SMU_VCLK: 996 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 997 if (ret) 998 goto failed; 999 break; 1000 case SMU_DCLK: 1001 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 1002 if (ret) 1003 goto failed; 1004 break; 1005 default: 1006 ret = -EINVAL; 1007 goto failed; 1008 } 1009 } 1010 if (min) { 1011 ret = vangogh_get_profiling_clk_mask(smu, 1012 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK, 1013 NULL, 1014 NULL, 1015 &mclk_mask, 1016 &fclk_mask, 1017 &soc_mask); 1018 if (ret) 1019 goto failed; 1020 1021 vclk_mask = dclk_mask = 0; 1022 1023 switch (clk_type) { 1024 case SMU_UCLK: 1025 case SMU_MCLK: 1026 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 1027 if (ret) 1028 goto failed; 1029 break; 1030 case SMU_SOCCLK: 1031 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 1032 if (ret) 1033 goto failed; 1034 break; 1035 case SMU_FCLK: 1036 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 1037 if (ret) 1038 goto failed; 1039 break; 1040 case SMU_VCLK: 1041 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 1042 if (ret) 1043 goto failed; 1044 break; 1045 case SMU_DCLK: 1046 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 1047 if (ret) 1048 goto failed; 1049 break; 1050 default: 1051 ret = -EINVAL; 1052 goto failed; 1053 } 1054 } 1055 failed: 1056 return ret; 1057 } 1058 1059 static int vangogh_get_power_profile_mode(struct smu_context *smu, 1060 char *buf) 1061 { 1062 uint32_t i, size = 0; 1063 int16_t workload_type = 0; 1064 1065 if (!buf) 1066 return -EINVAL; 1067 1068 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 1069 /* 1070 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1071 * Not all profile modes are supported on vangogh. 1072 */ 1073 workload_type = smu_cmn_to_asic_specific_index(smu, 1074 CMN2ASIC_MAPPING_WORKLOAD, 1075 i); 1076 1077 if (workload_type < 0) 1078 continue; 1079 1080 size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 1081 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1082 } 1083 1084 return size; 1085 } 1086 1087 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1088 { 1089 int workload_type, ret; 1090 uint32_t profile_mode = input[size]; 1091 1092 if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { 1093 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1094 return -EINVAL; 1095 } 1096 1097 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 1098 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 1099 return 0; 1100 1101 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1102 workload_type = smu_cmn_to_asic_specific_index(smu, 1103 CMN2ASIC_MAPPING_WORKLOAD, 1104 profile_mode); 1105 if (workload_type < 0) { 1106 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 1107 profile_mode); 1108 return -EINVAL; 1109 } 1110 1111 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 1112 1 << workload_type, 1113 NULL); 1114 if (ret) { 1115 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 1116 workload_type); 1117 return ret; 1118 } 1119 1120 smu->power_profile_mode = profile_mode; 1121 1122 return 0; 1123 } 1124 1125 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 1126 enum smu_clk_type clk_type, 1127 uint32_t min, 1128 uint32_t max) 1129 { 1130 int ret = 0; 1131 1132 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 1133 return 0; 1134 1135 switch (clk_type) { 1136 case SMU_GFXCLK: 1137 case SMU_SCLK: 1138 ret = smu_cmn_send_smc_msg_with_param(smu, 1139 SMU_MSG_SetHardMinGfxClk, 1140 min, NULL); 1141 if (ret) 1142 return ret; 1143 1144 ret = smu_cmn_send_smc_msg_with_param(smu, 1145 SMU_MSG_SetSoftMaxGfxClk, 1146 max, NULL); 1147 if (ret) 1148 return ret; 1149 break; 1150 case SMU_FCLK: 1151 ret = smu_cmn_send_smc_msg_with_param(smu, 1152 SMU_MSG_SetHardMinFclkByFreq, 1153 min, NULL); 1154 if (ret) 1155 return ret; 1156 1157 ret = smu_cmn_send_smc_msg_with_param(smu, 1158 SMU_MSG_SetSoftMaxFclkByFreq, 1159 max, NULL); 1160 if (ret) 1161 return ret; 1162 break; 1163 case SMU_SOCCLK: 1164 ret = smu_cmn_send_smc_msg_with_param(smu, 1165 SMU_MSG_SetHardMinSocclkByFreq, 1166 min, NULL); 1167 if (ret) 1168 return ret; 1169 1170 ret = smu_cmn_send_smc_msg_with_param(smu, 1171 SMU_MSG_SetSoftMaxSocclkByFreq, 1172 max, NULL); 1173 if (ret) 1174 return ret; 1175 break; 1176 case SMU_VCLK: 1177 ret = smu_cmn_send_smc_msg_with_param(smu, 1178 SMU_MSG_SetHardMinVcn, 1179 min << 16, NULL); 1180 if (ret) 1181 return ret; 1182 ret = smu_cmn_send_smc_msg_with_param(smu, 1183 SMU_MSG_SetSoftMaxVcn, 1184 max << 16, NULL); 1185 if (ret) 1186 return ret; 1187 break; 1188 case SMU_DCLK: 1189 ret = smu_cmn_send_smc_msg_with_param(smu, 1190 SMU_MSG_SetHardMinVcn, 1191 min, NULL); 1192 if (ret) 1193 return ret; 1194 ret = smu_cmn_send_smc_msg_with_param(smu, 1195 SMU_MSG_SetSoftMaxVcn, 1196 max, NULL); 1197 if (ret) 1198 return ret; 1199 break; 1200 default: 1201 return -EINVAL; 1202 } 1203 1204 return ret; 1205 } 1206 1207 static int vangogh_force_clk_levels(struct smu_context *smu, 1208 enum smu_clk_type clk_type, uint32_t mask) 1209 { 1210 uint32_t soft_min_level = 0, soft_max_level = 0; 1211 uint32_t min_freq = 0, max_freq = 0; 1212 int ret = 0 ; 1213 1214 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1215 soft_max_level = mask ? (fls(mask) - 1) : 0; 1216 1217 switch (clk_type) { 1218 case SMU_SOCCLK: 1219 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1220 soft_min_level, &min_freq); 1221 if (ret) 1222 return ret; 1223 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1224 soft_max_level, &max_freq); 1225 if (ret) 1226 return ret; 1227 ret = smu_cmn_send_smc_msg_with_param(smu, 1228 SMU_MSG_SetSoftMaxSocclkByFreq, 1229 max_freq, NULL); 1230 if (ret) 1231 return ret; 1232 ret = smu_cmn_send_smc_msg_with_param(smu, 1233 SMU_MSG_SetHardMinSocclkByFreq, 1234 min_freq, NULL); 1235 if (ret) 1236 return ret; 1237 break; 1238 case SMU_FCLK: 1239 ret = vangogh_get_dpm_clk_limited(smu, 1240 clk_type, soft_min_level, &min_freq); 1241 if (ret) 1242 return ret; 1243 ret = vangogh_get_dpm_clk_limited(smu, 1244 clk_type, soft_max_level, &max_freq); 1245 if (ret) 1246 return ret; 1247 ret = smu_cmn_send_smc_msg_with_param(smu, 1248 SMU_MSG_SetSoftMaxFclkByFreq, 1249 max_freq, NULL); 1250 if (ret) 1251 return ret; 1252 ret = smu_cmn_send_smc_msg_with_param(smu, 1253 SMU_MSG_SetHardMinFclkByFreq, 1254 min_freq, NULL); 1255 if (ret) 1256 return ret; 1257 break; 1258 case SMU_VCLK: 1259 ret = vangogh_get_dpm_clk_limited(smu, 1260 clk_type, soft_min_level, &min_freq); 1261 if (ret) 1262 return ret; 1263 1264 ret = vangogh_get_dpm_clk_limited(smu, 1265 clk_type, soft_max_level, &max_freq); 1266 if (ret) 1267 return ret; 1268 1269 1270 ret = smu_cmn_send_smc_msg_with_param(smu, 1271 SMU_MSG_SetHardMinVcn, 1272 min_freq << 16, NULL); 1273 if (ret) 1274 return ret; 1275 1276 ret = smu_cmn_send_smc_msg_with_param(smu, 1277 SMU_MSG_SetSoftMaxVcn, 1278 max_freq << 16, NULL); 1279 if (ret) 1280 return ret; 1281 1282 break; 1283 case SMU_DCLK: 1284 ret = vangogh_get_dpm_clk_limited(smu, 1285 clk_type, soft_min_level, &min_freq); 1286 if (ret) 1287 return ret; 1288 1289 ret = vangogh_get_dpm_clk_limited(smu, 1290 clk_type, soft_max_level, &max_freq); 1291 if (ret) 1292 return ret; 1293 1294 ret = smu_cmn_send_smc_msg_with_param(smu, 1295 SMU_MSG_SetHardMinVcn, 1296 min_freq, NULL); 1297 if (ret) 1298 return ret; 1299 1300 ret = smu_cmn_send_smc_msg_with_param(smu, 1301 SMU_MSG_SetSoftMaxVcn, 1302 max_freq, NULL); 1303 if (ret) 1304 return ret; 1305 1306 break; 1307 default: 1308 break; 1309 } 1310 1311 return ret; 1312 } 1313 1314 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1315 { 1316 int ret = 0, i = 0; 1317 uint32_t min_freq, max_freq, force_freq; 1318 enum smu_clk_type clk_type; 1319 1320 enum smu_clk_type clks[] = { 1321 SMU_SOCCLK, 1322 SMU_VCLK, 1323 SMU_DCLK, 1324 SMU_FCLK, 1325 }; 1326 1327 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1328 clk_type = clks[i]; 1329 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1330 if (ret) 1331 return ret; 1332 1333 force_freq = highest ? max_freq : min_freq; 1334 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1335 if (ret) 1336 return ret; 1337 } 1338 1339 return ret; 1340 } 1341 1342 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1343 { 1344 int ret = 0, i = 0; 1345 uint32_t min_freq, max_freq; 1346 enum smu_clk_type clk_type; 1347 1348 struct clk_feature_map { 1349 enum smu_clk_type clk_type; 1350 uint32_t feature; 1351 } clk_feature_map[] = { 1352 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1353 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1354 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1355 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1356 }; 1357 1358 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1359 1360 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1361 continue; 1362 1363 clk_type = clk_feature_map[i].clk_type; 1364 1365 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1366 1367 if (ret) 1368 return ret; 1369 1370 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1371 1372 if (ret) 1373 return ret; 1374 } 1375 1376 return ret; 1377 } 1378 1379 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1380 { 1381 int ret = 0; 1382 uint32_t socclk_freq = 0, fclk_freq = 0; 1383 uint32_t vclk_freq = 0, dclk_freq = 0; 1384 1385 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1386 if (ret) 1387 return ret; 1388 1389 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1390 if (ret) 1391 return ret; 1392 1393 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1394 if (ret) 1395 return ret; 1396 1397 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1398 if (ret) 1399 return ret; 1400 1401 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1402 if (ret) 1403 return ret; 1404 1405 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1406 if (ret) 1407 return ret; 1408 1409 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1410 if (ret) 1411 return ret; 1412 1413 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1414 if (ret) 1415 return ret; 1416 1417 return ret; 1418 } 1419 1420 static int vangogh_set_performance_level(struct smu_context *smu, 1421 enum amd_dpm_forced_level level) 1422 { 1423 int ret = 0, i; 1424 uint32_t soc_mask, mclk_mask, fclk_mask; 1425 uint32_t vclk_mask = 0, dclk_mask = 0; 1426 1427 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1428 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1429 1430 switch (level) { 1431 case AMD_DPM_FORCED_LEVEL_HIGH: 1432 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq; 1433 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1434 1435 1436 ret = vangogh_force_dpm_limit_value(smu, true); 1437 if (ret) 1438 return ret; 1439 break; 1440 case AMD_DPM_FORCED_LEVEL_LOW: 1441 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1442 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1443 1444 ret = vangogh_force_dpm_limit_value(smu, false); 1445 if (ret) 1446 return ret; 1447 break; 1448 case AMD_DPM_FORCED_LEVEL_AUTO: 1449 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1450 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1451 1452 ret = vangogh_unforce_dpm_levels(smu); 1453 if (ret) 1454 return ret; 1455 break; 1456 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1457 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1458 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1459 1460 ret = vangogh_get_profiling_clk_mask(smu, level, 1461 &vclk_mask, 1462 &dclk_mask, 1463 &mclk_mask, 1464 &fclk_mask, 1465 &soc_mask); 1466 if (ret) 1467 return ret; 1468 1469 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1470 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1471 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1472 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1473 break; 1474 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1475 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1476 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1477 break; 1478 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1479 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1480 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1481 1482 ret = vangogh_get_profiling_clk_mask(smu, level, 1483 NULL, 1484 NULL, 1485 &mclk_mask, 1486 &fclk_mask, 1487 NULL); 1488 if (ret) 1489 return ret; 1490 1491 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1492 break; 1493 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1494 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1495 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1496 1497 ret = vangogh_set_peak_clock_by_device(smu); 1498 if (ret) 1499 return ret; 1500 break; 1501 case AMD_DPM_FORCED_LEVEL_MANUAL: 1502 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1503 default: 1504 return 0; 1505 } 1506 1507 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1508 smu->gfx_actual_hard_min_freq, NULL); 1509 if (ret) 1510 return ret; 1511 1512 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1513 smu->gfx_actual_soft_max_freq, NULL); 1514 if (ret) 1515 return ret; 1516 1517 if (smu->adev->pm.fw_version >= 0x43f1b00) { 1518 for (i = 0; i < smu->cpu_core_num; i++) { 1519 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1520 ((i << 20) 1521 | smu->cpu_actual_soft_min_freq), 1522 NULL); 1523 if (ret) 1524 return ret; 1525 1526 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1527 ((i << 20) 1528 | smu->cpu_actual_soft_max_freq), 1529 NULL); 1530 if (ret) 1531 return ret; 1532 } 1533 } 1534 1535 return ret; 1536 } 1537 1538 static int vangogh_read_sensor(struct smu_context *smu, 1539 enum amd_pp_sensors sensor, 1540 void *data, uint32_t *size) 1541 { 1542 int ret = 0; 1543 1544 if (!data || !size) 1545 return -EINVAL; 1546 1547 switch (sensor) { 1548 case AMDGPU_PP_SENSOR_GPU_LOAD: 1549 ret = vangogh_common_get_smu_metrics_data(smu, 1550 METRICS_AVERAGE_GFXACTIVITY, 1551 (uint32_t *)data); 1552 *size = 4; 1553 break; 1554 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 1555 ret = vangogh_common_get_smu_metrics_data(smu, 1556 METRICS_AVERAGE_SOCKETPOWER, 1557 (uint32_t *)data); 1558 *size = 4; 1559 break; 1560 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 1561 ret = vangogh_common_get_smu_metrics_data(smu, 1562 METRICS_CURR_SOCKETPOWER, 1563 (uint32_t *)data); 1564 *size = 4; 1565 break; 1566 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1567 ret = vangogh_common_get_smu_metrics_data(smu, 1568 METRICS_TEMPERATURE_EDGE, 1569 (uint32_t *)data); 1570 *size = 4; 1571 break; 1572 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1573 ret = vangogh_common_get_smu_metrics_data(smu, 1574 METRICS_TEMPERATURE_HOTSPOT, 1575 (uint32_t *)data); 1576 *size = 4; 1577 break; 1578 case AMDGPU_PP_SENSOR_GFX_MCLK: 1579 ret = vangogh_common_get_smu_metrics_data(smu, 1580 METRICS_CURR_UCLK, 1581 (uint32_t *)data); 1582 *(uint32_t *)data *= 100; 1583 *size = 4; 1584 break; 1585 case AMDGPU_PP_SENSOR_GFX_SCLK: 1586 ret = vangogh_common_get_smu_metrics_data(smu, 1587 METRICS_CURR_GFXCLK, 1588 (uint32_t *)data); 1589 *(uint32_t *)data *= 100; 1590 *size = 4; 1591 break; 1592 case AMDGPU_PP_SENSOR_VDDGFX: 1593 ret = vangogh_common_get_smu_metrics_data(smu, 1594 METRICS_VOLTAGE_VDDGFX, 1595 (uint32_t *)data); 1596 *size = 4; 1597 break; 1598 case AMDGPU_PP_SENSOR_VDDNB: 1599 ret = vangogh_common_get_smu_metrics_data(smu, 1600 METRICS_VOLTAGE_VDDSOC, 1601 (uint32_t *)data); 1602 *size = 4; 1603 break; 1604 case AMDGPU_PP_SENSOR_CPU_CLK: 1605 ret = vangogh_common_get_smu_metrics_data(smu, 1606 METRICS_AVERAGE_CPUCLK, 1607 (uint32_t *)data); 1608 *size = smu->cpu_core_num * sizeof(uint16_t); 1609 break; 1610 default: 1611 ret = -EOPNOTSUPP; 1612 break; 1613 } 1614 1615 return ret; 1616 } 1617 1618 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit) 1619 { 1620 return smu_cmn_send_smc_msg_with_param(smu, 1621 SMU_MSG_GetThermalLimit, 1622 0, limit); 1623 } 1624 1625 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit) 1626 { 1627 return smu_cmn_send_smc_msg_with_param(smu, 1628 SMU_MSG_SetReducedThermalLimit, 1629 limit, NULL); 1630 } 1631 1632 1633 static int vangogh_set_watermarks_table(struct smu_context *smu, 1634 struct pp_smu_wm_range_sets *clock_ranges) 1635 { 1636 int i; 1637 int ret = 0; 1638 Watermarks_t *table = smu->smu_table.watermarks_table; 1639 1640 if (!table || !clock_ranges) 1641 return -EINVAL; 1642 1643 if (clock_ranges) { 1644 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1645 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1646 return -EINVAL; 1647 1648 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1649 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1650 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1651 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1652 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1653 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1654 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1655 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1656 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1657 1658 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1659 clock_ranges->reader_wm_sets[i].wm_inst; 1660 } 1661 1662 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1663 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1664 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1665 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1666 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1667 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1668 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1669 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1670 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1671 1672 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1673 clock_ranges->writer_wm_sets[i].wm_inst; 1674 } 1675 1676 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1677 } 1678 1679 /* pass data to smu controller */ 1680 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1681 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1682 ret = smu_cmn_write_watermarks_table(smu); 1683 if (ret) { 1684 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1685 return ret; 1686 } 1687 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1688 } 1689 1690 return 0; 1691 } 1692 1693 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu, 1694 void **table) 1695 { 1696 struct smu_table_context *smu_table = &smu->smu_table; 1697 struct gpu_metrics_v2_3 *gpu_metrics = 1698 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1699 SmuMetrics_legacy_t metrics; 1700 int ret = 0; 1701 1702 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1703 if (ret) 1704 return ret; 1705 1706 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1707 1708 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1709 gpu_metrics->temperature_soc = metrics.SocTemperature; 1710 memcpy(&gpu_metrics->temperature_core[0], 1711 &metrics.CoreTemperature[0], 1712 sizeof(uint16_t) * 4); 1713 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1714 1715 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1716 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1717 1718 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1719 gpu_metrics->average_cpu_power = metrics.Power[0]; 1720 gpu_metrics->average_soc_power = metrics.Power[1]; 1721 gpu_metrics->average_gfx_power = metrics.Power[2]; 1722 memcpy(&gpu_metrics->average_core_power[0], 1723 &metrics.CorePower[0], 1724 sizeof(uint16_t) * 4); 1725 1726 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1727 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1728 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1729 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1730 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1731 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1732 1733 memcpy(&gpu_metrics->current_coreclk[0], 1734 &metrics.CoreFrequency[0], 1735 sizeof(uint16_t) * 4); 1736 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1737 1738 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1739 gpu_metrics->indep_throttle_status = 1740 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1741 vangogh_throttler_map); 1742 1743 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1744 1745 *table = (void *)gpu_metrics; 1746 1747 return sizeof(struct gpu_metrics_v2_3); 1748 } 1749 1750 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, 1751 void **table) 1752 { 1753 struct smu_table_context *smu_table = &smu->smu_table; 1754 struct gpu_metrics_v2_2 *gpu_metrics = 1755 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1756 SmuMetrics_legacy_t metrics; 1757 int ret = 0; 1758 1759 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1760 if (ret) 1761 return ret; 1762 1763 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1764 1765 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1766 gpu_metrics->temperature_soc = metrics.SocTemperature; 1767 memcpy(&gpu_metrics->temperature_core[0], 1768 &metrics.CoreTemperature[0], 1769 sizeof(uint16_t) * 4); 1770 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1771 1772 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1773 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1774 1775 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1776 gpu_metrics->average_cpu_power = metrics.Power[0]; 1777 gpu_metrics->average_soc_power = metrics.Power[1]; 1778 gpu_metrics->average_gfx_power = metrics.Power[2]; 1779 memcpy(&gpu_metrics->average_core_power[0], 1780 &metrics.CorePower[0], 1781 sizeof(uint16_t) * 4); 1782 1783 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1784 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1785 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1786 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1787 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1788 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1789 1790 memcpy(&gpu_metrics->current_coreclk[0], 1791 &metrics.CoreFrequency[0], 1792 sizeof(uint16_t) * 4); 1793 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1794 1795 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1796 gpu_metrics->indep_throttle_status = 1797 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1798 vangogh_throttler_map); 1799 1800 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1801 1802 *table = (void *)gpu_metrics; 1803 1804 return sizeof(struct gpu_metrics_v2_2); 1805 } 1806 1807 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu, 1808 void **table) 1809 { 1810 struct smu_table_context *smu_table = &smu->smu_table; 1811 struct gpu_metrics_v2_3 *gpu_metrics = 1812 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1813 SmuMetrics_t metrics; 1814 int ret = 0; 1815 1816 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1817 if (ret) 1818 return ret; 1819 1820 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1821 1822 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1823 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1824 memcpy(&gpu_metrics->temperature_core[0], 1825 &metrics.Current.CoreTemperature[0], 1826 sizeof(uint16_t) * 4); 1827 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1828 1829 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature; 1830 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature; 1831 memcpy(&gpu_metrics->average_temperature_core[0], 1832 &metrics.Average.CoreTemperature[0], 1833 sizeof(uint16_t) * 4); 1834 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0]; 1835 1836 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1837 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1838 1839 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1840 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1841 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1842 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1843 memcpy(&gpu_metrics->average_core_power[0], 1844 &metrics.Average.CorePower[0], 1845 sizeof(uint16_t) * 4); 1846 1847 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1848 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1849 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1850 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1851 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1852 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1853 1854 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1855 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1856 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1857 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1858 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1859 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1860 1861 memcpy(&gpu_metrics->current_coreclk[0], 1862 &metrics.Current.CoreFrequency[0], 1863 sizeof(uint16_t) * 4); 1864 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1865 1866 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1867 gpu_metrics->indep_throttle_status = 1868 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1869 vangogh_throttler_map); 1870 1871 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1872 1873 *table = (void *)gpu_metrics; 1874 1875 return sizeof(struct gpu_metrics_v2_3); 1876 } 1877 1878 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu, 1879 void **table) 1880 { 1881 SmuMetrics_t metrics; 1882 struct smu_table_context *smu_table = &smu->smu_table; 1883 struct gpu_metrics_v2_4 *gpu_metrics = 1884 (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table; 1885 int ret = 0; 1886 1887 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1888 if (ret) 1889 return ret; 1890 1891 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4); 1892 1893 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1894 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1895 memcpy(&gpu_metrics->temperature_core[0], 1896 &metrics.Current.CoreTemperature[0], 1897 sizeof(uint16_t) * 4); 1898 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1899 1900 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature; 1901 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature; 1902 memcpy(&gpu_metrics->average_temperature_core[0], 1903 &metrics.Average.CoreTemperature[0], 1904 sizeof(uint16_t) * 4); 1905 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0]; 1906 1907 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1908 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1909 1910 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1911 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1912 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1913 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1914 1915 gpu_metrics->average_cpu_voltage = metrics.Current.Voltage[0]; 1916 gpu_metrics->average_soc_voltage = metrics.Current.Voltage[1]; 1917 gpu_metrics->average_gfx_voltage = metrics.Current.Voltage[2]; 1918 1919 gpu_metrics->average_cpu_current = metrics.Current.Current[0]; 1920 gpu_metrics->average_soc_current = metrics.Current.Current[1]; 1921 gpu_metrics->average_gfx_current = metrics.Current.Current[2]; 1922 1923 memcpy(&gpu_metrics->average_core_power[0], 1924 &metrics.Average.CorePower[0], 1925 sizeof(uint16_t) * 4); 1926 1927 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1928 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1929 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1930 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1931 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1932 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1933 1934 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1935 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1936 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1937 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1938 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1939 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1940 1941 memcpy(&gpu_metrics->current_coreclk[0], 1942 &metrics.Current.CoreFrequency[0], 1943 sizeof(uint16_t) * 4); 1944 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1945 1946 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1947 gpu_metrics->indep_throttle_status = 1948 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1949 vangogh_throttler_map); 1950 1951 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1952 1953 *table = (void *)gpu_metrics; 1954 1955 return sizeof(struct gpu_metrics_v2_4); 1956 } 1957 1958 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1959 void **table) 1960 { 1961 struct smu_table_context *smu_table = &smu->smu_table; 1962 struct gpu_metrics_v2_2 *gpu_metrics = 1963 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1964 SmuMetrics_t metrics; 1965 int ret = 0; 1966 1967 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1968 if (ret) 1969 return ret; 1970 1971 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1972 1973 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1974 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1975 memcpy(&gpu_metrics->temperature_core[0], 1976 &metrics.Current.CoreTemperature[0], 1977 sizeof(uint16_t) * 4); 1978 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1979 1980 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1981 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1982 1983 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1984 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1985 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1986 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1987 memcpy(&gpu_metrics->average_core_power[0], 1988 &metrics.Average.CorePower[0], 1989 sizeof(uint16_t) * 4); 1990 1991 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1992 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1993 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1994 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1995 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1996 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1997 1998 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1999 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 2000 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 2001 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 2002 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 2003 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 2004 2005 memcpy(&gpu_metrics->current_coreclk[0], 2006 &metrics.Current.CoreFrequency[0], 2007 sizeof(uint16_t) * 4); 2008 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 2009 2010 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 2011 gpu_metrics->indep_throttle_status = 2012 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 2013 vangogh_throttler_map); 2014 2015 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2016 2017 *table = (void *)gpu_metrics; 2018 2019 return sizeof(struct gpu_metrics_v2_2); 2020 } 2021 2022 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, 2023 void **table) 2024 { 2025 uint32_t if_version; 2026 uint32_t smu_version; 2027 uint32_t smu_program; 2028 uint32_t fw_version; 2029 int ret = 0; 2030 2031 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 2032 if (ret) 2033 return ret; 2034 2035 smu_program = (smu_version >> 24) & 0xff; 2036 fw_version = smu_version & 0xffffff; 2037 if (smu_program == 6) { 2038 if (fw_version >= 0x3F0800) 2039 ret = vangogh_get_gpu_metrics_v2_4(smu, table); 2040 else 2041 ret = vangogh_get_gpu_metrics_v2_3(smu, table); 2042 2043 } else { 2044 if (smu_version >= 0x043F3E00) { 2045 if (if_version < 0x3) 2046 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table); 2047 else 2048 ret = vangogh_get_gpu_metrics_v2_3(smu, table); 2049 } else { 2050 if (if_version < 0x3) 2051 ret = vangogh_get_legacy_gpu_metrics(smu, table); 2052 else 2053 ret = vangogh_get_gpu_metrics(smu, table); 2054 } 2055 } 2056 2057 return ret; 2058 } 2059 2060 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 2061 long input[], uint32_t size) 2062 { 2063 int ret = 0; 2064 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2065 2066 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 2067 dev_warn(smu->adev->dev, 2068 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 2069 return -EINVAL; 2070 } 2071 2072 switch (type) { 2073 case PP_OD_EDIT_CCLK_VDDC_TABLE: 2074 if (size != 3) { 2075 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 2076 return -EINVAL; 2077 } 2078 if (input[0] >= smu->cpu_core_num) { 2079 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 2080 smu->cpu_core_num); 2081 } 2082 smu->cpu_core_id_select = input[0]; 2083 if (input[1] == 0) { 2084 if (input[2] < smu->cpu_default_soft_min_freq) { 2085 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2086 input[2], smu->cpu_default_soft_min_freq); 2087 return -EINVAL; 2088 } 2089 smu->cpu_actual_soft_min_freq = input[2]; 2090 } else if (input[1] == 1) { 2091 if (input[2] > smu->cpu_default_soft_max_freq) { 2092 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2093 input[2], smu->cpu_default_soft_max_freq); 2094 return -EINVAL; 2095 } 2096 smu->cpu_actual_soft_max_freq = input[2]; 2097 } else { 2098 return -EINVAL; 2099 } 2100 break; 2101 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2102 if (size != 2) { 2103 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2104 return -EINVAL; 2105 } 2106 2107 if (input[0] == 0) { 2108 if (input[1] < smu->gfx_default_hard_min_freq) { 2109 dev_warn(smu->adev->dev, 2110 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2111 input[1], smu->gfx_default_hard_min_freq); 2112 return -EINVAL; 2113 } 2114 smu->gfx_actual_hard_min_freq = input[1]; 2115 } else if (input[0] == 1) { 2116 if (input[1] > smu->gfx_default_soft_max_freq) { 2117 dev_warn(smu->adev->dev, 2118 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2119 input[1], smu->gfx_default_soft_max_freq); 2120 return -EINVAL; 2121 } 2122 smu->gfx_actual_soft_max_freq = input[1]; 2123 } else { 2124 return -EINVAL; 2125 } 2126 break; 2127 case PP_OD_RESTORE_DEFAULT_TABLE: 2128 if (size != 0) { 2129 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2130 return -EINVAL; 2131 } else { 2132 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 2133 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 2134 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 2135 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 2136 } 2137 break; 2138 case PP_OD_COMMIT_DPM_TABLE: 2139 if (size != 0) { 2140 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2141 return -EINVAL; 2142 } else { 2143 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 2144 dev_err(smu->adev->dev, 2145 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 2146 smu->gfx_actual_hard_min_freq, 2147 smu->gfx_actual_soft_max_freq); 2148 return -EINVAL; 2149 } 2150 2151 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 2152 smu->gfx_actual_hard_min_freq, NULL); 2153 if (ret) { 2154 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 2155 return ret; 2156 } 2157 2158 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 2159 smu->gfx_actual_soft_max_freq, NULL); 2160 if (ret) { 2161 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 2162 return ret; 2163 } 2164 2165 if (smu->adev->pm.fw_version < 0x43f1b00) { 2166 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 2167 break; 2168 } 2169 2170 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 2171 ((smu->cpu_core_id_select << 20) 2172 | smu->cpu_actual_soft_min_freq), 2173 NULL); 2174 if (ret) { 2175 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 2176 return ret; 2177 } 2178 2179 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 2180 ((smu->cpu_core_id_select << 20) 2181 | smu->cpu_actual_soft_max_freq), 2182 NULL); 2183 if (ret) { 2184 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 2185 return ret; 2186 } 2187 } 2188 break; 2189 default: 2190 return -ENOSYS; 2191 } 2192 2193 return ret; 2194 } 2195 2196 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 2197 { 2198 struct smu_table_context *smu_table = &smu->smu_table; 2199 2200 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 2201 } 2202 2203 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 2204 { 2205 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 2206 2207 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 2208 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 2209 smu->gfx_actual_hard_min_freq = 0; 2210 smu->gfx_actual_soft_max_freq = 0; 2211 2212 smu->cpu_default_soft_min_freq = 1400; 2213 smu->cpu_default_soft_max_freq = 3500; 2214 smu->cpu_actual_soft_min_freq = 0; 2215 smu->cpu_actual_soft_max_freq = 0; 2216 2217 return 0; 2218 } 2219 2220 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 2221 { 2222 DpmClocks_t *table = smu->smu_table.clocks_table; 2223 int i; 2224 2225 if (!clock_table || !table) 2226 return -EINVAL; 2227 2228 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 2229 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 2230 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 2231 } 2232 2233 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2234 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 2235 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 2236 } 2237 2238 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2239 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 2240 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 2241 } 2242 2243 return 0; 2244 } 2245 2246 2247 static int vangogh_system_features_control(struct smu_context *smu, bool en) 2248 { 2249 struct amdgpu_device *adev = smu->adev; 2250 int ret = 0; 2251 2252 if (adev->pm.fw_version >= 0x43f1700 && !en) 2253 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 2254 RLC_STATUS_OFF, NULL); 2255 2256 return ret; 2257 } 2258 2259 static int vangogh_post_smu_init(struct smu_context *smu) 2260 { 2261 struct amdgpu_device *adev = smu->adev; 2262 uint32_t tmp; 2263 int ret = 0; 2264 uint8_t aon_bits = 0; 2265 /* Two CUs in one WGP */ 2266 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 2267 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 2268 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2269 2270 /* allow message will be sent after enable message on Vangogh*/ 2271 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 2272 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2273 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 2274 if (ret) { 2275 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 2276 return ret; 2277 } 2278 } else { 2279 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 2280 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 2281 } 2282 2283 /* if all CUs are active, no need to power off any WGPs */ 2284 if (total_cu == adev->gfx.cu_info.number) 2285 return 0; 2286 2287 /* 2288 * Calculate the total bits number of always on WGPs for all SA/SEs in 2289 * RLC_PG_ALWAYS_ON_WGP_MASK. 2290 */ 2291 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 2292 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 2293 2294 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2295 2296 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 2297 if (aon_bits > req_active_wgps) { 2298 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 2299 return 0; 2300 } else { 2301 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 2302 } 2303 } 2304 2305 static int vangogh_mode_reset(struct smu_context *smu, int type) 2306 { 2307 int ret = 0, index = 0; 2308 2309 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2310 SMU_MSG_GfxDeviceDriverReset); 2311 if (index < 0) 2312 return index == -EACCES ? 0 : index; 2313 2314 mutex_lock(&smu->message_lock); 2315 2316 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 2317 2318 mutex_unlock(&smu->message_lock); 2319 2320 mdelay(10); 2321 2322 return ret; 2323 } 2324 2325 static int vangogh_mode2_reset(struct smu_context *smu) 2326 { 2327 return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 2328 } 2329 2330 /** 2331 * vangogh_get_gfxoff_status - Get gfxoff status 2332 * 2333 * @smu: amdgpu_device pointer 2334 * 2335 * Get current gfxoff status 2336 * 2337 * Return: 2338 * * 0 - GFXOFF (default if enabled). 2339 * * 1 - Transition out of GFX State. 2340 * * 2 - Not in GFXOFF. 2341 * * 3 - Transition into GFXOFF. 2342 */ 2343 static u32 vangogh_get_gfxoff_status(struct smu_context *smu) 2344 { 2345 struct amdgpu_device *adev = smu->adev; 2346 u32 reg, gfxoff_status; 2347 2348 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL); 2349 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK) 2350 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT; 2351 2352 return gfxoff_status; 2353 } 2354 2355 static int vangogh_get_power_limit(struct smu_context *smu, 2356 uint32_t *current_power_limit, 2357 uint32_t *default_power_limit, 2358 uint32_t *max_power_limit) 2359 { 2360 struct smu_11_5_power_context *power_context = 2361 smu->smu_power.power_context; 2362 uint32_t ppt_limit; 2363 int ret = 0; 2364 2365 if (smu->adev->pm.fw_version < 0x43f1e00) 2366 return ret; 2367 2368 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 2369 if (ret) { 2370 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 2371 return ret; 2372 } 2373 /* convert from milliwatt to watt */ 2374 if (current_power_limit) 2375 *current_power_limit = ppt_limit / 1000; 2376 if (default_power_limit) 2377 *default_power_limit = ppt_limit / 1000; 2378 if (max_power_limit) 2379 *max_power_limit = 29; 2380 2381 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 2382 if (ret) { 2383 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 2384 return ret; 2385 } 2386 /* convert from milliwatt to watt */ 2387 power_context->current_fast_ppt_limit = 2388 power_context->default_fast_ppt_limit = ppt_limit / 1000; 2389 power_context->max_fast_ppt_limit = 30; 2390 2391 return ret; 2392 } 2393 2394 static int vangogh_get_ppt_limit(struct smu_context *smu, 2395 uint32_t *ppt_limit, 2396 enum smu_ppt_limit_type type, 2397 enum smu_ppt_limit_level level) 2398 { 2399 struct smu_11_5_power_context *power_context = 2400 smu->smu_power.power_context; 2401 2402 if (!power_context) 2403 return -EOPNOTSUPP; 2404 2405 if (type == SMU_FAST_PPT_LIMIT) { 2406 switch (level) { 2407 case SMU_PPT_LIMIT_MAX: 2408 *ppt_limit = power_context->max_fast_ppt_limit; 2409 break; 2410 case SMU_PPT_LIMIT_CURRENT: 2411 *ppt_limit = power_context->current_fast_ppt_limit; 2412 break; 2413 case SMU_PPT_LIMIT_DEFAULT: 2414 *ppt_limit = power_context->default_fast_ppt_limit; 2415 break; 2416 default: 2417 break; 2418 } 2419 } 2420 2421 return 0; 2422 } 2423 2424 static int vangogh_set_power_limit(struct smu_context *smu, 2425 enum smu_ppt_limit_type limit_type, 2426 uint32_t ppt_limit) 2427 { 2428 struct smu_11_5_power_context *power_context = 2429 smu->smu_power.power_context; 2430 int ret = 0; 2431 2432 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 2433 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 2434 return -EOPNOTSUPP; 2435 } 2436 2437 switch (limit_type) { 2438 case SMU_DEFAULT_PPT_LIMIT: 2439 ret = smu_cmn_send_smc_msg_with_param(smu, 2440 SMU_MSG_SetSlowPPTLimit, 2441 ppt_limit * 1000, /* convert from watt to milliwatt */ 2442 NULL); 2443 if (ret) 2444 return ret; 2445 2446 smu->current_power_limit = ppt_limit; 2447 break; 2448 case SMU_FAST_PPT_LIMIT: 2449 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 2450 if (ppt_limit > power_context->max_fast_ppt_limit) { 2451 dev_err(smu->adev->dev, 2452 "New power limit (%d) is over the max allowed %d\n", 2453 ppt_limit, power_context->max_fast_ppt_limit); 2454 return ret; 2455 } 2456 2457 ret = smu_cmn_send_smc_msg_with_param(smu, 2458 SMU_MSG_SetFastPPTLimit, 2459 ppt_limit * 1000, /* convert from watt to milliwatt */ 2460 NULL); 2461 if (ret) 2462 return ret; 2463 2464 power_context->current_fast_ppt_limit = ppt_limit; 2465 break; 2466 default: 2467 return -EINVAL; 2468 } 2469 2470 return ret; 2471 } 2472 2473 /** 2474 * vangogh_set_gfxoff_residency 2475 * 2476 * @smu: amdgpu_device pointer 2477 * @start: start/stop residency log 2478 * 2479 * This function will be used to log gfxoff residency 2480 * 2481 * 2482 * Returns standard response codes. 2483 */ 2484 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start) 2485 { 2486 int ret = 0; 2487 u32 residency; 2488 struct amdgpu_device *adev = smu->adev; 2489 2490 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2491 return 0; 2492 2493 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency, 2494 start, &residency); 2495 if (ret) 2496 return ret; 2497 2498 if (!start) 2499 adev->gfx.gfx_off_residency = residency; 2500 2501 return ret; 2502 } 2503 2504 /** 2505 * vangogh_get_gfxoff_residency 2506 * 2507 * @smu: amdgpu_device pointer 2508 * @residency: placeholder for return value 2509 * 2510 * This function will be used to get gfxoff residency. 2511 * 2512 * Returns standard response codes. 2513 */ 2514 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency) 2515 { 2516 struct amdgpu_device *adev = smu->adev; 2517 2518 *residency = adev->gfx.gfx_off_residency; 2519 2520 return 0; 2521 } 2522 2523 /** 2524 * vangogh_get_gfxoff_entrycount - get gfxoff entry count 2525 * 2526 * @smu: amdgpu_device pointer 2527 * @entrycount: placeholder for return value 2528 * 2529 * This function will be used to get gfxoff entry count 2530 * 2531 * Returns standard response codes. 2532 */ 2533 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount) 2534 { 2535 int ret = 0, value = 0; 2536 struct amdgpu_device *adev = smu->adev; 2537 2538 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2539 return 0; 2540 2541 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value); 2542 *entrycount = value + adev->gfx.gfx_off_entrycount; 2543 2544 return ret; 2545 } 2546 2547 static const struct pptable_funcs vangogh_ppt_funcs = { 2548 2549 .check_fw_status = smu_v11_0_check_fw_status, 2550 .check_fw_version = smu_v11_0_check_fw_version, 2551 .init_smc_tables = vangogh_init_smc_tables, 2552 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2553 .init_power = smu_v11_0_init_power, 2554 .fini_power = smu_v11_0_fini_power, 2555 .register_irq_handler = smu_v11_0_register_irq_handler, 2556 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2557 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2558 .send_smc_msg = smu_cmn_send_smc_msg, 2559 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 2560 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 2561 .is_dpm_running = vangogh_is_dpm_running, 2562 .read_sensor = vangogh_read_sensor, 2563 .get_apu_thermal_limit = vangogh_get_apu_thermal_limit, 2564 .set_apu_thermal_limit = vangogh_set_apu_thermal_limit, 2565 .get_enabled_mask = smu_cmn_get_enabled_mask, 2566 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2567 .set_watermarks_table = vangogh_set_watermarks_table, 2568 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2569 .interrupt_work = smu_v11_0_interrupt_work, 2570 .get_gpu_metrics = vangogh_common_get_gpu_metrics, 2571 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 2572 .print_clk_levels = vangogh_common_print_clk_levels, 2573 .set_default_dpm_table = vangogh_set_default_dpm_tables, 2574 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 2575 .system_features_control = vangogh_system_features_control, 2576 .feature_is_enabled = smu_cmn_feature_is_enabled, 2577 .set_power_profile_mode = vangogh_set_power_profile_mode, 2578 .get_power_profile_mode = vangogh_get_power_profile_mode, 2579 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 2580 .force_clk_levels = vangogh_force_clk_levels, 2581 .set_performance_level = vangogh_set_performance_level, 2582 .post_init = vangogh_post_smu_init, 2583 .mode2_reset = vangogh_mode2_reset, 2584 .gfx_off_control = smu_v11_0_gfx_off_control, 2585 .get_gfx_off_status = vangogh_get_gfxoff_status, 2586 .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount, 2587 .get_gfx_off_residency = vangogh_get_gfxoff_residency, 2588 .set_gfx_off_residency = vangogh_set_gfxoff_residency, 2589 .get_ppt_limit = vangogh_get_ppt_limit, 2590 .get_power_limit = vangogh_get_power_limit, 2591 .set_power_limit = vangogh_set_power_limit, 2592 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2593 }; 2594 2595 void vangogh_set_ppt_funcs(struct smu_context *smu) 2596 { 2597 smu->ppt_funcs = &vangogh_ppt_funcs; 2598 smu->message_map = vangogh_message_map; 2599 smu->feature_map = vangogh_feature_mask_map; 2600 smu->table_map = vangogh_table_map; 2601 smu->workload_map = vangogh_workload_map; 2602 smu->is_apu = true; 2603 smu_v11_0_set_smu_mailbox_registers(smu); 2604 } 2605