1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 #include <asm/processor.h> 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 #define FEATURE_MASK(feature) (1ULL << feature) 50 #define SMC_DPM_FEATURE ( \ 51 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 52 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 53 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 54 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 55 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 56 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 57 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 58 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 59 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 60 61 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 62 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 63 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 64 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 65 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 66 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 67 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 68 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 69 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 70 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 71 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 72 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 73 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 74 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 75 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 76 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 77 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 78 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 79 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 80 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 81 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 82 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 83 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 84 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 85 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 86 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 87 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 88 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 89 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 95 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 96 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 97 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 98 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 99 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 100 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 101 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 102 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 103 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 104 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 105 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 106 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 107 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 108 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 109 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 110 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 111 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 112 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 113 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 114 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 115 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 116 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 117 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 118 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 119 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 120 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 121 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 122 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 123 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 124 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 125 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 126 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 127 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 128 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 129 }; 130 131 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 132 FEA_MAP(PPT), 133 FEA_MAP(TDC), 134 FEA_MAP(THERMAL), 135 FEA_MAP(DS_GFXCLK), 136 FEA_MAP(DS_SOCCLK), 137 FEA_MAP(DS_LCLK), 138 FEA_MAP(DS_FCLK), 139 FEA_MAP(DS_MP1CLK), 140 FEA_MAP(DS_MP0CLK), 141 FEA_MAP(ATHUB_PG), 142 FEA_MAP(CCLK_DPM), 143 FEA_MAP(FAN_CONTROLLER), 144 FEA_MAP(ULV), 145 FEA_MAP(VCN_DPM), 146 FEA_MAP(LCLK_DPM), 147 FEA_MAP(SHUBCLK_DPM), 148 FEA_MAP(DCFCLK_DPM), 149 FEA_MAP(DS_DCFCLK), 150 FEA_MAP(S0I2), 151 FEA_MAP(SMU_LOW_POWER), 152 FEA_MAP(GFX_DEM), 153 FEA_MAP(PSI), 154 FEA_MAP(PROCHOT), 155 FEA_MAP(CPUOFF), 156 FEA_MAP(STAPM), 157 FEA_MAP(S0I3), 158 FEA_MAP(DF_CSTATES), 159 FEA_MAP(PERF_LIMIT), 160 FEA_MAP(CORE_DLDO), 161 FEA_MAP(RSMU_LOW_POWER), 162 FEA_MAP(SMN_LOW_POWER), 163 FEA_MAP(THM_LOW_POWER), 164 FEA_MAP(SMUIO_LOW_POWER), 165 FEA_MAP(MP1_LOW_POWER), 166 FEA_MAP(DS_VCN), 167 FEA_MAP(CPPC), 168 FEA_MAP(OS_CSTATES), 169 FEA_MAP(ISP_DPM), 170 FEA_MAP(A55_DPM), 171 FEA_MAP(CVIP_DSP_DPM), 172 FEA_MAP(MSMU_LOW_POWER), 173 FEA_MAP_REVERSE(SOCCLK), 174 FEA_MAP_REVERSE(FCLK), 175 FEA_MAP_HALF_REVERSE(GFX), 176 }; 177 178 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 179 TAB_MAP_VALID(WATERMARKS), 180 TAB_MAP_VALID(SMU_METRICS), 181 TAB_MAP_VALID(CUSTOM_DPM), 182 TAB_MAP_VALID(DPMCLOCKS), 183 }; 184 185 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 187 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 188 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 189 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 190 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 191 }; 192 193 static int vangogh_tables_init(struct smu_context *smu) 194 { 195 struct smu_table_context *smu_table = &smu->smu_table; 196 struct smu_table *tables = smu_table->tables; 197 198 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 199 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 200 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 201 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 202 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 203 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 204 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 205 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 206 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 207 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 208 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 209 if (!smu_table->metrics_table) 210 goto err0_out; 211 smu_table->metrics_time = 0; 212 213 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); 214 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 215 if (!smu_table->gpu_metrics_table) 216 goto err1_out; 217 218 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 219 if (!smu_table->watermarks_table) 220 goto err2_out; 221 222 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 223 if (!smu_table->clocks_table) 224 goto err3_out; 225 226 return 0; 227 228 err3_out: 229 kfree(smu_table->clocks_table); 230 err2_out: 231 kfree(smu_table->gpu_metrics_table); 232 err1_out: 233 kfree(smu_table->metrics_table); 234 err0_out: 235 return -ENOMEM; 236 } 237 238 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 239 MetricsMember_t member, 240 uint32_t *value) 241 { 242 struct smu_table_context *smu_table = &smu->smu_table; 243 244 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 245 int ret = 0; 246 247 mutex_lock(&smu->metrics_lock); 248 249 ret = smu_cmn_get_metrics_table_locked(smu, 250 NULL, 251 false); 252 if (ret) { 253 mutex_unlock(&smu->metrics_lock); 254 return ret; 255 } 256 257 switch (member) { 258 case METRICS_AVERAGE_GFXCLK: 259 *value = metrics->GfxclkFrequency; 260 break; 261 case METRICS_AVERAGE_SOCCLK: 262 *value = metrics->SocclkFrequency; 263 break; 264 case METRICS_AVERAGE_VCLK: 265 *value = metrics->VclkFrequency; 266 break; 267 case METRICS_AVERAGE_DCLK: 268 *value = metrics->DclkFrequency; 269 break; 270 case METRICS_AVERAGE_UCLK: 271 *value = metrics->MemclkFrequency; 272 break; 273 case METRICS_AVERAGE_GFXACTIVITY: 274 *value = metrics->GfxActivity / 100; 275 break; 276 case METRICS_AVERAGE_VCNACTIVITY: 277 *value = metrics->UvdActivity; 278 break; 279 case METRICS_AVERAGE_SOCKETPOWER: 280 *value = (metrics->CurrentSocketPower << 8) / 281 1000 ; 282 break; 283 case METRICS_TEMPERATURE_EDGE: 284 *value = metrics->GfxTemperature / 100 * 285 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 286 break; 287 case METRICS_TEMPERATURE_HOTSPOT: 288 *value = metrics->SocTemperature / 100 * 289 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 290 break; 291 case METRICS_THROTTLER_STATUS: 292 *value = metrics->ThrottlerStatus; 293 break; 294 case METRICS_VOLTAGE_VDDGFX: 295 *value = metrics->Voltage[2]; 296 break; 297 case METRICS_VOLTAGE_VDDSOC: 298 *value = metrics->Voltage[1]; 299 break; 300 case METRICS_AVERAGE_CPUCLK: 301 memcpy(value, &metrics->CoreFrequency[0], 302 smu->cpu_core_num * sizeof(uint16_t)); 303 break; 304 default: 305 *value = UINT_MAX; 306 break; 307 } 308 309 mutex_unlock(&smu->metrics_lock); 310 311 return ret; 312 } 313 314 static int vangogh_allocate_dpm_context(struct smu_context *smu) 315 { 316 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 317 318 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 319 GFP_KERNEL); 320 if (!smu_dpm->dpm_context) 321 return -ENOMEM; 322 323 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 324 325 return 0; 326 } 327 328 static int vangogh_init_smc_tables(struct smu_context *smu) 329 { 330 int ret = 0; 331 332 ret = vangogh_tables_init(smu); 333 if (ret) 334 return ret; 335 336 ret = vangogh_allocate_dpm_context(smu); 337 if (ret) 338 return ret; 339 340 #ifdef CONFIG_X86 341 /* AMD x86 APU only */ 342 smu->cpu_core_num = boot_cpu_data.x86_max_cores; 343 #else 344 smu->cpu_core_num = 4; 345 #endif 346 347 return smu_v11_0_init_smc_tables(smu); 348 } 349 350 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 351 { 352 int ret = 0; 353 354 if (enable) { 355 /* vcn dpm on is a prerequisite for vcn power gate messages */ 356 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 357 if (ret) 358 return ret; 359 } else { 360 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 361 if (ret) 362 return ret; 363 } 364 365 return ret; 366 } 367 368 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 369 { 370 int ret = 0; 371 372 if (enable) { 373 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 374 if (ret) 375 return ret; 376 } else { 377 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 378 if (ret) 379 return ret; 380 } 381 382 return ret; 383 } 384 385 static bool vangogh_is_dpm_running(struct smu_context *smu) 386 { 387 struct amdgpu_device *adev = smu->adev; 388 int ret = 0; 389 uint32_t feature_mask[2]; 390 uint64_t feature_enabled; 391 392 /* we need to re-init after suspend so return false */ 393 if (adev->in_suspend) 394 return false; 395 396 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 397 398 if (ret) 399 return false; 400 401 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 402 ((uint64_t)feature_mask[1] << 32)); 403 404 return !!(feature_enabled & SMC_DPM_FEATURE); 405 } 406 407 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 408 uint32_t dpm_level, uint32_t *freq) 409 { 410 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 411 412 if (!clk_table || clk_type >= SMU_CLK_COUNT) 413 return -EINVAL; 414 415 switch (clk_type) { 416 case SMU_SOCCLK: 417 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 418 return -EINVAL; 419 *freq = clk_table->SocClocks[dpm_level]; 420 break; 421 case SMU_VCLK: 422 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 423 return -EINVAL; 424 *freq = clk_table->VcnClocks[dpm_level].vclk; 425 break; 426 case SMU_DCLK: 427 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 428 return -EINVAL; 429 *freq = clk_table->VcnClocks[dpm_level].dclk; 430 break; 431 case SMU_UCLK: 432 case SMU_MCLK: 433 if (dpm_level >= clk_table->NumDfPstatesEnabled) 434 return -EINVAL; 435 *freq = clk_table->DfPstateTable[dpm_level].memclk; 436 437 break; 438 case SMU_FCLK: 439 if (dpm_level >= clk_table->NumDfPstatesEnabled) 440 return -EINVAL; 441 *freq = clk_table->DfPstateTable[dpm_level].fclk; 442 break; 443 default: 444 return -EINVAL; 445 } 446 447 return 0; 448 } 449 450 static int vangogh_print_fine_grain_clk(struct smu_context *smu, 451 enum smu_clk_type clk_type, char *buf) 452 { 453 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 454 SmuMetrics_t metrics; 455 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 456 int i, size = 0, ret = 0; 457 uint32_t cur_value = 0, value = 0, count = 0; 458 bool cur_value_match_level = false; 459 460 memset(&metrics, 0, sizeof(metrics)); 461 462 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 463 if (ret) 464 return ret; 465 466 switch (clk_type) { 467 case SMU_OD_SCLK: 468 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 469 size = sprintf(buf, "%s:\n", "OD_SCLK"); 470 size += sprintf(buf + size, "0: %10uMhz\n", 471 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 472 size += sprintf(buf + size, "1: %10uMhz\n", 473 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 474 } 475 break; 476 case SMU_OD_CCLK: 477 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 478 size = sprintf(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 479 size += sprintf(buf + size, "0: %10uMhz\n", 480 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 481 size += sprintf(buf + size, "1: %10uMhz\n", 482 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 483 } 484 break; 485 case SMU_OD_RANGE: 486 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 487 size = sprintf(buf, "%s:\n", "OD_RANGE"); 488 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 489 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 490 size += sprintf(buf + size, "CCLK: %7uMhz %10uMhz\n", 491 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 492 } 493 break; 494 case SMU_SOCCLK: 495 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 496 count = clk_table->NumSocClkLevelsEnabled; 497 cur_value = metrics.SocclkFrequency; 498 break; 499 case SMU_VCLK: 500 count = clk_table->VcnClkLevelsEnabled; 501 cur_value = metrics.VclkFrequency; 502 break; 503 case SMU_DCLK: 504 count = clk_table->VcnClkLevelsEnabled; 505 cur_value = metrics.DclkFrequency; 506 break; 507 case SMU_MCLK: 508 count = clk_table->NumDfPstatesEnabled; 509 cur_value = metrics.MemclkFrequency; 510 break; 511 case SMU_FCLK: 512 count = clk_table->NumDfPstatesEnabled; 513 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 514 if (ret) 515 return ret; 516 break; 517 default: 518 break; 519 } 520 521 switch (clk_type) { 522 case SMU_SOCCLK: 523 case SMU_VCLK: 524 case SMU_DCLK: 525 case SMU_MCLK: 526 case SMU_FCLK: 527 for (i = 0; i < count; i++) { 528 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 529 if (ret) 530 return ret; 531 if (!value) 532 continue; 533 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 534 cur_value == value ? "*" : ""); 535 if (cur_value == value) 536 cur_value_match_level = true; 537 } 538 539 if (!cur_value_match_level) 540 size += sprintf(buf + size, " %uMhz *\n", cur_value); 541 break; 542 default: 543 break; 544 } 545 546 return size; 547 } 548 549 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 550 enum amd_dpm_forced_level level, 551 uint32_t *vclk_mask, 552 uint32_t *dclk_mask, 553 uint32_t *mclk_mask, 554 uint32_t *fclk_mask, 555 uint32_t *soc_mask) 556 { 557 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 558 559 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 560 if (mclk_mask) 561 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 562 563 if (fclk_mask) 564 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 565 566 if (soc_mask) 567 *soc_mask = 0; 568 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 569 if (mclk_mask) 570 *mclk_mask = 0; 571 572 if (fclk_mask) 573 *fclk_mask = 0; 574 575 if (soc_mask) 576 *soc_mask = 1; 577 578 if (vclk_mask) 579 *vclk_mask = 1; 580 581 if (dclk_mask) 582 *dclk_mask = 1; 583 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 584 if (mclk_mask) 585 *mclk_mask = 0; 586 587 if (fclk_mask) 588 *fclk_mask = 0; 589 590 if (soc_mask) 591 *soc_mask = 1; 592 593 if (vclk_mask) 594 *vclk_mask = 1; 595 596 if (dclk_mask) 597 *dclk_mask = 1; 598 } 599 600 return 0; 601 } 602 603 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 604 enum smu_clk_type clk_type) 605 { 606 enum smu_feature_mask feature_id = 0; 607 608 switch (clk_type) { 609 case SMU_MCLK: 610 case SMU_UCLK: 611 case SMU_FCLK: 612 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 613 break; 614 case SMU_GFXCLK: 615 case SMU_SCLK: 616 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 617 break; 618 case SMU_SOCCLK: 619 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 620 break; 621 case SMU_VCLK: 622 case SMU_DCLK: 623 feature_id = SMU_FEATURE_VCN_DPM_BIT; 624 break; 625 default: 626 return true; 627 } 628 629 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 630 return false; 631 632 return true; 633 } 634 635 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 636 enum smu_clk_type clk_type, 637 uint32_t *min, 638 uint32_t *max) 639 { 640 int ret = 0; 641 uint32_t soc_mask; 642 uint32_t vclk_mask; 643 uint32_t dclk_mask; 644 uint32_t mclk_mask; 645 uint32_t fclk_mask; 646 uint32_t clock_limit; 647 648 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 649 switch (clk_type) { 650 case SMU_MCLK: 651 case SMU_UCLK: 652 clock_limit = smu->smu_table.boot_values.uclk; 653 break; 654 case SMU_FCLK: 655 clock_limit = smu->smu_table.boot_values.fclk; 656 break; 657 case SMU_GFXCLK: 658 case SMU_SCLK: 659 clock_limit = smu->smu_table.boot_values.gfxclk; 660 break; 661 case SMU_SOCCLK: 662 clock_limit = smu->smu_table.boot_values.socclk; 663 break; 664 case SMU_VCLK: 665 clock_limit = smu->smu_table.boot_values.vclk; 666 break; 667 case SMU_DCLK: 668 clock_limit = smu->smu_table.boot_values.dclk; 669 break; 670 default: 671 clock_limit = 0; 672 break; 673 } 674 675 /* clock in Mhz unit */ 676 if (min) 677 *min = clock_limit / 100; 678 if (max) 679 *max = clock_limit / 100; 680 681 return 0; 682 } 683 if (max) { 684 ret = vangogh_get_profiling_clk_mask(smu, 685 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 686 &vclk_mask, 687 &dclk_mask, 688 &mclk_mask, 689 &fclk_mask, 690 &soc_mask); 691 if (ret) 692 goto failed; 693 694 switch (clk_type) { 695 case SMU_UCLK: 696 case SMU_MCLK: 697 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 698 if (ret) 699 goto failed; 700 break; 701 case SMU_SOCCLK: 702 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 703 if (ret) 704 goto failed; 705 break; 706 case SMU_FCLK: 707 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 708 if (ret) 709 goto failed; 710 break; 711 case SMU_VCLK: 712 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 713 if (ret) 714 goto failed; 715 break; 716 case SMU_DCLK: 717 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 718 if (ret) 719 goto failed; 720 break; 721 default: 722 ret = -EINVAL; 723 goto failed; 724 } 725 } 726 if (min) { 727 switch (clk_type) { 728 case SMU_UCLK: 729 case SMU_MCLK: 730 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 731 if (ret) 732 goto failed; 733 break; 734 case SMU_SOCCLK: 735 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 736 if (ret) 737 goto failed; 738 break; 739 case SMU_FCLK: 740 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 741 if (ret) 742 goto failed; 743 break; 744 case SMU_VCLK: 745 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 746 if (ret) 747 goto failed; 748 break; 749 case SMU_DCLK: 750 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 751 if (ret) 752 goto failed; 753 break; 754 default: 755 ret = -EINVAL; 756 goto failed; 757 } 758 } 759 failed: 760 return ret; 761 } 762 763 static int vangogh_get_power_profile_mode(struct smu_context *smu, 764 char *buf) 765 { 766 static const char *profile_name[] = { 767 "BOOTUP_DEFAULT", 768 "3D_FULL_SCREEN", 769 "POWER_SAVING", 770 "VIDEO", 771 "VR", 772 "COMPUTE", 773 "CUSTOM"}; 774 uint32_t i, size = 0; 775 int16_t workload_type = 0; 776 777 if (!buf) 778 return -EINVAL; 779 780 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 781 /* 782 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 783 * Not all profile modes are supported on vangogh. 784 */ 785 workload_type = smu_cmn_to_asic_specific_index(smu, 786 CMN2ASIC_MAPPING_WORKLOAD, 787 i); 788 789 if (workload_type < 0) 790 continue; 791 792 size += sprintf(buf + size, "%2d %14s%s\n", 793 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 794 } 795 796 return size; 797 } 798 799 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 800 { 801 int workload_type, ret; 802 uint32_t profile_mode = input[size]; 803 804 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 805 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 806 return -EINVAL; 807 } 808 809 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 810 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 811 return 0; 812 813 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 814 workload_type = smu_cmn_to_asic_specific_index(smu, 815 CMN2ASIC_MAPPING_WORKLOAD, 816 profile_mode); 817 if (workload_type < 0) { 818 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 819 profile_mode); 820 return -EINVAL; 821 } 822 823 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 824 1 << workload_type, 825 NULL); 826 if (ret) { 827 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 828 workload_type); 829 return ret; 830 } 831 832 smu->power_profile_mode = profile_mode; 833 834 return 0; 835 } 836 837 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 838 enum smu_clk_type clk_type, 839 uint32_t min, 840 uint32_t max) 841 { 842 int ret = 0; 843 844 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 845 return 0; 846 847 switch (clk_type) { 848 case SMU_GFXCLK: 849 case SMU_SCLK: 850 ret = smu_cmn_send_smc_msg_with_param(smu, 851 SMU_MSG_SetHardMinGfxClk, 852 min, NULL); 853 if (ret) 854 return ret; 855 856 ret = smu_cmn_send_smc_msg_with_param(smu, 857 SMU_MSG_SetSoftMaxGfxClk, 858 max, NULL); 859 if (ret) 860 return ret; 861 break; 862 case SMU_FCLK: 863 case SMU_MCLK: 864 ret = smu_cmn_send_smc_msg_with_param(smu, 865 SMU_MSG_SetHardMinFclkByFreq, 866 min, NULL); 867 if (ret) 868 return ret; 869 870 ret = smu_cmn_send_smc_msg_with_param(smu, 871 SMU_MSG_SetSoftMaxFclkByFreq, 872 max, NULL); 873 if (ret) 874 return ret; 875 break; 876 case SMU_SOCCLK: 877 ret = smu_cmn_send_smc_msg_with_param(smu, 878 SMU_MSG_SetHardMinSocclkByFreq, 879 min, NULL); 880 if (ret) 881 return ret; 882 883 ret = smu_cmn_send_smc_msg_with_param(smu, 884 SMU_MSG_SetSoftMaxSocclkByFreq, 885 max, NULL); 886 if (ret) 887 return ret; 888 break; 889 case SMU_VCLK: 890 ret = smu_cmn_send_smc_msg_with_param(smu, 891 SMU_MSG_SetHardMinVcn, 892 min << 16, NULL); 893 if (ret) 894 return ret; 895 ret = smu_cmn_send_smc_msg_with_param(smu, 896 SMU_MSG_SetSoftMaxVcn, 897 max << 16, NULL); 898 if (ret) 899 return ret; 900 break; 901 case SMU_DCLK: 902 ret = smu_cmn_send_smc_msg_with_param(smu, 903 SMU_MSG_SetHardMinVcn, 904 min, NULL); 905 if (ret) 906 return ret; 907 ret = smu_cmn_send_smc_msg_with_param(smu, 908 SMU_MSG_SetSoftMaxVcn, 909 max, NULL); 910 if (ret) 911 return ret; 912 break; 913 default: 914 return -EINVAL; 915 } 916 917 return ret; 918 } 919 920 static int vangogh_force_clk_levels(struct smu_context *smu, 921 enum smu_clk_type clk_type, uint32_t mask) 922 { 923 uint32_t soft_min_level = 0, soft_max_level = 0; 924 uint32_t min_freq = 0, max_freq = 0; 925 int ret = 0 ; 926 927 soft_min_level = mask ? (ffs(mask) - 1) : 0; 928 soft_max_level = mask ? (fls(mask) - 1) : 0; 929 930 switch (clk_type) { 931 case SMU_SOCCLK: 932 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 933 soft_min_level, &min_freq); 934 if (ret) 935 return ret; 936 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 937 soft_max_level, &max_freq); 938 if (ret) 939 return ret; 940 ret = smu_cmn_send_smc_msg_with_param(smu, 941 SMU_MSG_SetSoftMaxSocclkByFreq, 942 max_freq, NULL); 943 if (ret) 944 return ret; 945 ret = smu_cmn_send_smc_msg_with_param(smu, 946 SMU_MSG_SetHardMinSocclkByFreq, 947 min_freq, NULL); 948 if (ret) 949 return ret; 950 break; 951 case SMU_MCLK: 952 case SMU_FCLK: 953 ret = vangogh_get_dpm_clk_limited(smu, 954 clk_type, soft_min_level, &min_freq); 955 if (ret) 956 return ret; 957 ret = vangogh_get_dpm_clk_limited(smu, 958 clk_type, soft_max_level, &max_freq); 959 if (ret) 960 return ret; 961 ret = smu_cmn_send_smc_msg_with_param(smu, 962 SMU_MSG_SetSoftMaxFclkByFreq, 963 max_freq, NULL); 964 if (ret) 965 return ret; 966 ret = smu_cmn_send_smc_msg_with_param(smu, 967 SMU_MSG_SetHardMinFclkByFreq, 968 min_freq, NULL); 969 if (ret) 970 return ret; 971 break; 972 case SMU_VCLK: 973 ret = vangogh_get_dpm_clk_limited(smu, 974 clk_type, soft_min_level, &min_freq); 975 if (ret) 976 return ret; 977 978 ret = vangogh_get_dpm_clk_limited(smu, 979 clk_type, soft_max_level, &max_freq); 980 if (ret) 981 return ret; 982 983 984 ret = smu_cmn_send_smc_msg_with_param(smu, 985 SMU_MSG_SetHardMinVcn, 986 min_freq << 16, NULL); 987 if (ret) 988 return ret; 989 990 ret = smu_cmn_send_smc_msg_with_param(smu, 991 SMU_MSG_SetSoftMaxVcn, 992 max_freq << 16, NULL); 993 if (ret) 994 return ret; 995 996 break; 997 case SMU_DCLK: 998 ret = vangogh_get_dpm_clk_limited(smu, 999 clk_type, soft_min_level, &min_freq); 1000 if (ret) 1001 return ret; 1002 1003 ret = vangogh_get_dpm_clk_limited(smu, 1004 clk_type, soft_max_level, &max_freq); 1005 if (ret) 1006 return ret; 1007 1008 ret = smu_cmn_send_smc_msg_with_param(smu, 1009 SMU_MSG_SetHardMinVcn, 1010 min_freq, NULL); 1011 if (ret) 1012 return ret; 1013 1014 ret = smu_cmn_send_smc_msg_with_param(smu, 1015 SMU_MSG_SetSoftMaxVcn, 1016 max_freq, NULL); 1017 if (ret) 1018 return ret; 1019 1020 break; 1021 default: 1022 break; 1023 } 1024 1025 return ret; 1026 } 1027 1028 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1029 { 1030 int ret = 0, i = 0; 1031 uint32_t min_freq, max_freq, force_freq; 1032 enum smu_clk_type clk_type; 1033 1034 enum smu_clk_type clks[] = { 1035 SMU_SOCCLK, 1036 SMU_VCLK, 1037 SMU_DCLK, 1038 SMU_MCLK, 1039 SMU_FCLK, 1040 }; 1041 1042 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1043 clk_type = clks[i]; 1044 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1045 if (ret) 1046 return ret; 1047 1048 force_freq = highest ? max_freq : min_freq; 1049 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1050 if (ret) 1051 return ret; 1052 } 1053 1054 return ret; 1055 } 1056 1057 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1058 { 1059 int ret = 0, i = 0; 1060 uint32_t min_freq, max_freq; 1061 enum smu_clk_type clk_type; 1062 1063 struct clk_feature_map { 1064 enum smu_clk_type clk_type; 1065 uint32_t feature; 1066 } clk_feature_map[] = { 1067 {SMU_MCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1068 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1069 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1070 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1071 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1072 }; 1073 1074 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1075 1076 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1077 continue; 1078 1079 clk_type = clk_feature_map[i].clk_type; 1080 1081 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1082 1083 if (ret) 1084 return ret; 1085 1086 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1087 1088 if (ret) 1089 return ret; 1090 } 1091 1092 return ret; 1093 } 1094 1095 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1096 { 1097 int ret = 0; 1098 uint32_t socclk_freq = 0, fclk_freq = 0; 1099 uint32_t vclk_freq = 0, dclk_freq = 0; 1100 1101 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1102 if (ret) 1103 return ret; 1104 1105 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1106 if (ret) 1107 return ret; 1108 1109 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1110 if (ret) 1111 return ret; 1112 1113 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1114 if (ret) 1115 return ret; 1116 1117 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1118 if (ret) 1119 return ret; 1120 1121 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1122 if (ret) 1123 return ret; 1124 1125 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1126 if (ret) 1127 return ret; 1128 1129 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1130 if (ret) 1131 return ret; 1132 1133 return ret; 1134 } 1135 1136 static int vangogh_set_performance_level(struct smu_context *smu, 1137 enum amd_dpm_forced_level level) 1138 { 1139 int ret = 0; 1140 uint32_t soc_mask, mclk_mask, fclk_mask; 1141 uint32_t vclk_mask = 0, dclk_mask = 0; 1142 1143 switch (level) { 1144 case AMD_DPM_FORCED_LEVEL_HIGH: 1145 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1146 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1147 1148 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1149 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1150 1151 ret = vangogh_force_dpm_limit_value(smu, true); 1152 break; 1153 case AMD_DPM_FORCED_LEVEL_LOW: 1154 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1155 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1156 1157 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1158 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1159 1160 ret = vangogh_force_dpm_limit_value(smu, false); 1161 break; 1162 case AMD_DPM_FORCED_LEVEL_AUTO: 1163 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1164 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1165 1166 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1167 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1168 1169 ret = vangogh_unforce_dpm_levels(smu); 1170 break; 1171 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1172 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1173 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1174 1175 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1176 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1177 1178 ret = smu_cmn_send_smc_msg_with_param(smu, 1179 SMU_MSG_SetHardMinGfxClk, 1180 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1181 if (ret) 1182 return ret; 1183 1184 ret = smu_cmn_send_smc_msg_with_param(smu, 1185 SMU_MSG_SetSoftMaxGfxClk, 1186 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1187 if (ret) 1188 return ret; 1189 1190 ret = vangogh_get_profiling_clk_mask(smu, level, 1191 &vclk_mask, 1192 &dclk_mask, 1193 &mclk_mask, 1194 &fclk_mask, 1195 &soc_mask); 1196 if (ret) 1197 return ret; 1198 1199 vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 1200 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1201 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1202 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1203 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1204 1205 break; 1206 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1207 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1208 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1209 1210 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1211 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1212 1213 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, 1214 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1215 if (ret) 1216 return ret; 1217 1218 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, 1219 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1220 if (ret) 1221 return ret; 1222 break; 1223 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1224 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1225 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1226 1227 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1228 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1229 1230 ret = vangogh_get_profiling_clk_mask(smu, level, 1231 NULL, 1232 NULL, 1233 &mclk_mask, 1234 &fclk_mask, 1235 NULL); 1236 if (ret) 1237 return ret; 1238 1239 vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 1240 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1241 break; 1242 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1243 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1244 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1245 1246 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1247 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1248 1249 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1250 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1251 if (ret) 1252 return ret; 1253 1254 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1255 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1256 if (ret) 1257 return ret; 1258 1259 ret = vangogh_set_peak_clock_by_device(smu); 1260 break; 1261 case AMD_DPM_FORCED_LEVEL_MANUAL: 1262 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1263 default: 1264 break; 1265 } 1266 return ret; 1267 } 1268 1269 static int vangogh_read_sensor(struct smu_context *smu, 1270 enum amd_pp_sensors sensor, 1271 void *data, uint32_t *size) 1272 { 1273 int ret = 0; 1274 1275 if (!data || !size) 1276 return -EINVAL; 1277 1278 mutex_lock(&smu->sensor_lock); 1279 switch (sensor) { 1280 case AMDGPU_PP_SENSOR_GPU_LOAD: 1281 ret = vangogh_get_smu_metrics_data(smu, 1282 METRICS_AVERAGE_GFXACTIVITY, 1283 (uint32_t *)data); 1284 *size = 4; 1285 break; 1286 case AMDGPU_PP_SENSOR_GPU_POWER: 1287 ret = vangogh_get_smu_metrics_data(smu, 1288 METRICS_AVERAGE_SOCKETPOWER, 1289 (uint32_t *)data); 1290 *size = 4; 1291 break; 1292 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1293 ret = vangogh_get_smu_metrics_data(smu, 1294 METRICS_TEMPERATURE_EDGE, 1295 (uint32_t *)data); 1296 *size = 4; 1297 break; 1298 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1299 ret = vangogh_get_smu_metrics_data(smu, 1300 METRICS_TEMPERATURE_HOTSPOT, 1301 (uint32_t *)data); 1302 *size = 4; 1303 break; 1304 case AMDGPU_PP_SENSOR_GFX_MCLK: 1305 ret = vangogh_get_smu_metrics_data(smu, 1306 METRICS_AVERAGE_UCLK, 1307 (uint32_t *)data); 1308 *(uint32_t *)data *= 100; 1309 *size = 4; 1310 break; 1311 case AMDGPU_PP_SENSOR_GFX_SCLK: 1312 ret = vangogh_get_smu_metrics_data(smu, 1313 METRICS_AVERAGE_GFXCLK, 1314 (uint32_t *)data); 1315 *(uint32_t *)data *= 100; 1316 *size = 4; 1317 break; 1318 case AMDGPU_PP_SENSOR_VDDGFX: 1319 ret = vangogh_get_smu_metrics_data(smu, 1320 METRICS_VOLTAGE_VDDGFX, 1321 (uint32_t *)data); 1322 *size = 4; 1323 break; 1324 case AMDGPU_PP_SENSOR_VDDNB: 1325 ret = vangogh_get_smu_metrics_data(smu, 1326 METRICS_VOLTAGE_VDDSOC, 1327 (uint32_t *)data); 1328 *size = 4; 1329 break; 1330 case AMDGPU_PP_SENSOR_CPU_CLK: 1331 ret = vangogh_get_smu_metrics_data(smu, 1332 METRICS_AVERAGE_CPUCLK, 1333 (uint32_t *)data); 1334 *size = smu->cpu_core_num * sizeof(uint16_t); 1335 break; 1336 default: 1337 ret = -EOPNOTSUPP; 1338 break; 1339 } 1340 mutex_unlock(&smu->sensor_lock); 1341 1342 return ret; 1343 } 1344 1345 static int vangogh_set_watermarks_table(struct smu_context *smu, 1346 struct pp_smu_wm_range_sets *clock_ranges) 1347 { 1348 int i; 1349 int ret = 0; 1350 Watermarks_t *table = smu->smu_table.watermarks_table; 1351 1352 if (!table || !clock_ranges) 1353 return -EINVAL; 1354 1355 if (clock_ranges) { 1356 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1357 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1358 return -EINVAL; 1359 1360 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1361 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1362 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1363 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1364 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1365 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1366 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1367 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1368 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1369 1370 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1371 clock_ranges->reader_wm_sets[i].wm_inst; 1372 } 1373 1374 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1375 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1376 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1377 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1378 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1379 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1380 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1381 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1382 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1383 1384 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1385 clock_ranges->writer_wm_sets[i].wm_inst; 1386 } 1387 1388 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1389 } 1390 1391 /* pass data to smu controller */ 1392 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1393 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1394 ret = smu_cmn_write_watermarks_table(smu); 1395 if (ret) { 1396 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1397 return ret; 1398 } 1399 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1400 } 1401 1402 return 0; 1403 } 1404 1405 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1406 void **table) 1407 { 1408 struct smu_table_context *smu_table = &smu->smu_table; 1409 struct gpu_metrics_v2_0 *gpu_metrics = 1410 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; 1411 SmuMetrics_t metrics; 1412 int ret = 0; 1413 1414 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1415 if (ret) 1416 return ret; 1417 1418 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 0); 1419 1420 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1421 gpu_metrics->temperature_soc = metrics.SocTemperature; 1422 memcpy(&gpu_metrics->temperature_core[0], 1423 &metrics.CoreTemperature[0], 1424 sizeof(uint16_t) * 8); 1425 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1426 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1427 1428 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1429 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1430 1431 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1432 gpu_metrics->average_cpu_power = metrics.Power[0]; 1433 gpu_metrics->average_soc_power = metrics.Power[1]; 1434 gpu_metrics->average_gfx_power = metrics.Power[2]; 1435 memcpy(&gpu_metrics->average_core_power[0], 1436 &metrics.CorePower[0], 1437 sizeof(uint16_t) * 8); 1438 1439 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1440 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1441 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1442 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1443 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1444 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1445 1446 memcpy(&gpu_metrics->current_coreclk[0], 1447 &metrics.CoreFrequency[0], 1448 sizeof(uint16_t) * 8); 1449 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1450 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1451 1452 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1453 1454 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1455 1456 *table = (void *)gpu_metrics; 1457 1458 return sizeof(struct gpu_metrics_v2_0); 1459 } 1460 1461 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1462 long input[], uint32_t size) 1463 { 1464 int ret = 0; 1465 int i; 1466 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1467 1468 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 1469 dev_warn(smu->adev->dev, 1470 "pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); 1471 return -EINVAL; 1472 } 1473 1474 switch (type) { 1475 case PP_OD_EDIT_CCLK_VDDC_TABLE: 1476 if (size != 3) { 1477 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 1478 return -EINVAL; 1479 } 1480 if (input[0] >= smu->cpu_core_num) { 1481 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 1482 smu->cpu_core_num); 1483 } 1484 smu->cpu_core_id_select = input[0]; 1485 if (input[1] == 0) { 1486 if (input[2] < smu->cpu_default_soft_min_freq) { 1487 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1488 input[2], smu->cpu_default_soft_min_freq); 1489 return -EINVAL; 1490 } 1491 smu->cpu_actual_soft_min_freq = input[2]; 1492 } else if (input[1] == 1) { 1493 if (input[2] > smu->cpu_default_soft_max_freq) { 1494 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1495 input[2], smu->cpu_default_soft_max_freq); 1496 return -EINVAL; 1497 } 1498 smu->cpu_actual_soft_max_freq = input[2]; 1499 } else { 1500 return -EINVAL; 1501 } 1502 break; 1503 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1504 if (size != 2) { 1505 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1506 return -EINVAL; 1507 } 1508 1509 if (input[0] == 0) { 1510 if (input[1] < smu->gfx_default_hard_min_freq) { 1511 dev_warn(smu->adev->dev, 1512 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1513 input[1], smu->gfx_default_hard_min_freq); 1514 return -EINVAL; 1515 } 1516 smu->gfx_actual_hard_min_freq = input[1]; 1517 } else if (input[0] == 1) { 1518 if (input[1] > smu->gfx_default_soft_max_freq) { 1519 dev_warn(smu->adev->dev, 1520 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1521 input[1], smu->gfx_default_soft_max_freq); 1522 return -EINVAL; 1523 } 1524 smu->gfx_actual_soft_max_freq = input[1]; 1525 } else { 1526 return -EINVAL; 1527 } 1528 break; 1529 case PP_OD_RESTORE_DEFAULT_TABLE: 1530 if (size != 0) { 1531 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1532 return -EINVAL; 1533 } else { 1534 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1535 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1536 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1537 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1538 1539 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1540 smu->gfx_actual_hard_min_freq, NULL); 1541 if (ret) { 1542 dev_err(smu->adev->dev, "Restore the default hard min sclk failed!"); 1543 return ret; 1544 } 1545 1546 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1547 smu->gfx_actual_soft_max_freq, NULL); 1548 if (ret) { 1549 dev_err(smu->adev->dev, "Restore the default soft max sclk failed!"); 1550 return ret; 1551 } 1552 1553 if (smu->adev->pm.fw_version < 0x43f1b00) { 1554 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 1555 break; 1556 } 1557 1558 for (i = 0; i < smu->cpu_core_num; i++) { 1559 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1560 (i << 20) | smu->cpu_actual_soft_min_freq, 1561 NULL); 1562 if (ret) { 1563 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 1564 return ret; 1565 } 1566 1567 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1568 (i << 20) | smu->cpu_actual_soft_max_freq, 1569 NULL); 1570 if (ret) { 1571 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 1572 return ret; 1573 } 1574 } 1575 } 1576 break; 1577 case PP_OD_COMMIT_DPM_TABLE: 1578 if (size != 0) { 1579 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1580 return -EINVAL; 1581 } else { 1582 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1583 dev_err(smu->adev->dev, 1584 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1585 smu->gfx_actual_hard_min_freq, 1586 smu->gfx_actual_soft_max_freq); 1587 return -EINVAL; 1588 } 1589 1590 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1591 smu->gfx_actual_hard_min_freq, NULL); 1592 if (ret) { 1593 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1594 return ret; 1595 } 1596 1597 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1598 smu->gfx_actual_soft_max_freq, NULL); 1599 if (ret) { 1600 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1601 return ret; 1602 } 1603 1604 if (smu->adev->pm.fw_version < 0x43f1b00) { 1605 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 1606 break; 1607 } 1608 1609 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1610 ((smu->cpu_core_id_select << 20) 1611 | smu->cpu_actual_soft_min_freq), 1612 NULL); 1613 if (ret) { 1614 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 1615 return ret; 1616 } 1617 1618 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1619 ((smu->cpu_core_id_select << 20) 1620 | smu->cpu_actual_soft_max_freq), 1621 NULL); 1622 if (ret) { 1623 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 1624 return ret; 1625 } 1626 } 1627 break; 1628 default: 1629 return -ENOSYS; 1630 } 1631 1632 return ret; 1633 } 1634 1635 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 1636 { 1637 struct smu_table_context *smu_table = &smu->smu_table; 1638 1639 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 1640 } 1641 1642 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1643 { 1644 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1645 1646 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1647 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1648 smu->gfx_actual_hard_min_freq = 0; 1649 smu->gfx_actual_soft_max_freq = 0; 1650 1651 smu->cpu_default_soft_min_freq = 1400; 1652 smu->cpu_default_soft_max_freq = 3500; 1653 smu->cpu_actual_soft_min_freq = 0; 1654 smu->cpu_actual_soft_max_freq = 0; 1655 1656 return 0; 1657 } 1658 1659 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 1660 { 1661 DpmClocks_t *table = smu->smu_table.clocks_table; 1662 int i; 1663 1664 if (!clock_table || !table) 1665 return -EINVAL; 1666 1667 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 1668 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 1669 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 1670 } 1671 1672 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1673 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 1674 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 1675 } 1676 1677 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1678 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 1679 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 1680 } 1681 1682 return 0; 1683 } 1684 1685 1686 static int vangogh_system_features_control(struct smu_context *smu, bool en) 1687 { 1688 struct amdgpu_device *adev = smu->adev; 1689 struct smu_feature *feature = &smu->smu_feature; 1690 uint32_t feature_mask[2]; 1691 int ret = 0; 1692 1693 if (adev->pm.fw_version >= 0x43f1700 && !en) 1694 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 1695 RLC_STATUS_OFF, NULL); 1696 1697 bitmap_zero(feature->enabled, feature->feature_num); 1698 bitmap_zero(feature->supported, feature->feature_num); 1699 1700 if (!en) 1701 return ret; 1702 1703 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 1704 if (ret) 1705 return ret; 1706 1707 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, 1708 feature->feature_num); 1709 bitmap_copy(feature->supported, (unsigned long *)&feature_mask, 1710 feature->feature_num); 1711 1712 return 0; 1713 } 1714 1715 static int vangogh_post_smu_init(struct smu_context *smu) 1716 { 1717 struct amdgpu_device *adev = smu->adev; 1718 uint32_t tmp; 1719 int ret = 0; 1720 uint8_t aon_bits = 0; 1721 /* Two CUs in one WGP */ 1722 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 1723 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 1724 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1725 1726 /* allow message will be sent after enable message on Vangogh*/ 1727 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 1728 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 1729 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 1730 if (ret) { 1731 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 1732 return ret; 1733 } 1734 } else { 1735 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1736 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 1737 } 1738 1739 /* if all CUs are active, no need to power off any WGPs */ 1740 if (total_cu == adev->gfx.cu_info.number) 1741 return 0; 1742 1743 /* 1744 * Calculate the total bits number of always on WGPs for all SA/SEs in 1745 * RLC_PG_ALWAYS_ON_WGP_MASK. 1746 */ 1747 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 1748 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 1749 1750 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1751 1752 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 1753 if (aon_bits > req_active_wgps) { 1754 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 1755 return 0; 1756 } else { 1757 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 1758 } 1759 } 1760 1761 static int vangogh_mode_reset(struct smu_context *smu, int type) 1762 { 1763 int ret = 0, index = 0; 1764 1765 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1766 SMU_MSG_GfxDeviceDriverReset); 1767 if (index < 0) 1768 return index == -EACCES ? 0 : index; 1769 1770 mutex_lock(&smu->message_lock); 1771 1772 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 1773 1774 mutex_unlock(&smu->message_lock); 1775 1776 mdelay(10); 1777 1778 return ret; 1779 } 1780 1781 static int vangogh_mode2_reset(struct smu_context *smu) 1782 { 1783 return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 1784 } 1785 1786 static int vangogh_get_power_limit(struct smu_context *smu) 1787 { 1788 struct smu_11_5_power_context *power_context = 1789 smu->smu_power.power_context; 1790 uint32_t ppt_limit; 1791 int ret = 0; 1792 1793 if (smu->adev->pm.fw_version < 0x43f1e00) 1794 return ret; 1795 1796 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 1797 if (ret) { 1798 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 1799 return ret; 1800 } 1801 /* convert from milliwatt to watt */ 1802 smu->current_power_limit = ppt_limit / 1000; 1803 smu->max_power_limit = 29; 1804 1805 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 1806 if (ret) { 1807 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 1808 return ret; 1809 } 1810 /* convert from milliwatt to watt */ 1811 power_context->current_fast_ppt_limit = ppt_limit / 1000; 1812 power_context->max_fast_ppt_limit = 30; 1813 1814 return ret; 1815 } 1816 1817 static int vangogh_get_ppt_limit(struct smu_context *smu, 1818 uint32_t *ppt_limit, 1819 enum smu_ppt_limit_type type, 1820 enum smu_ppt_limit_level level) 1821 { 1822 struct smu_11_5_power_context *power_context = 1823 smu->smu_power.power_context; 1824 1825 if (!power_context) 1826 return -EOPNOTSUPP; 1827 1828 if (type == SMU_FAST_PPT_LIMIT) { 1829 switch (level) { 1830 case SMU_PPT_LIMIT_MAX: 1831 *ppt_limit = power_context->max_fast_ppt_limit; 1832 break; 1833 case SMU_PPT_LIMIT_CURRENT: 1834 *ppt_limit = power_context->current_fast_ppt_limit; 1835 break; 1836 default: 1837 break; 1838 } 1839 } 1840 1841 return 0; 1842 } 1843 1844 static int vangogh_set_power_limit(struct smu_context *smu, uint32_t ppt_limit) 1845 { 1846 struct smu_11_5_power_context *power_context = 1847 smu->smu_power.power_context; 1848 uint32_t limit_type = ppt_limit >> 24; 1849 int ret = 0; 1850 1851 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1852 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 1853 return -EOPNOTSUPP; 1854 } 1855 1856 switch (limit_type) { 1857 case SMU_DEFAULT_PPT_LIMIT: 1858 ret = smu_cmn_send_smc_msg_with_param(smu, 1859 SMU_MSG_SetSlowPPTLimit, 1860 ppt_limit * 1000, /* convert from watt to milliwatt */ 1861 NULL); 1862 if (ret) 1863 return ret; 1864 1865 smu->current_power_limit = ppt_limit; 1866 break; 1867 case SMU_FAST_PPT_LIMIT: 1868 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 1869 if (ppt_limit > power_context->max_fast_ppt_limit) { 1870 dev_err(smu->adev->dev, 1871 "New power limit (%d) is over the max allowed %d\n", 1872 ppt_limit, power_context->max_fast_ppt_limit); 1873 return ret; 1874 } 1875 1876 ret = smu_cmn_send_smc_msg_with_param(smu, 1877 SMU_MSG_SetFastPPTLimit, 1878 ppt_limit * 1000, /* convert from watt to milliwatt */ 1879 NULL); 1880 if (ret) 1881 return ret; 1882 1883 power_context->current_fast_ppt_limit = ppt_limit; 1884 break; 1885 default: 1886 return -EINVAL; 1887 } 1888 1889 return ret; 1890 } 1891 1892 static const struct pptable_funcs vangogh_ppt_funcs = { 1893 1894 .check_fw_status = smu_v11_0_check_fw_status, 1895 .check_fw_version = smu_v11_0_check_fw_version, 1896 .init_smc_tables = vangogh_init_smc_tables, 1897 .fini_smc_tables = smu_v11_0_fini_smc_tables, 1898 .init_power = smu_v11_0_init_power, 1899 .fini_power = smu_v11_0_fini_power, 1900 .register_irq_handler = smu_v11_0_register_irq_handler, 1901 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 1902 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1903 .send_smc_msg = smu_cmn_send_smc_msg, 1904 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 1905 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 1906 .is_dpm_running = vangogh_is_dpm_running, 1907 .read_sensor = vangogh_read_sensor, 1908 .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask, 1909 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1910 .set_watermarks_table = vangogh_set_watermarks_table, 1911 .set_driver_table_location = smu_v11_0_set_driver_table_location, 1912 .interrupt_work = smu_v11_0_interrupt_work, 1913 .get_gpu_metrics = vangogh_get_gpu_metrics, 1914 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 1915 .print_clk_levels = vangogh_print_fine_grain_clk, 1916 .set_default_dpm_table = vangogh_set_default_dpm_tables, 1917 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 1918 .system_features_control = vangogh_system_features_control, 1919 .feature_is_enabled = smu_cmn_feature_is_enabled, 1920 .set_power_profile_mode = vangogh_set_power_profile_mode, 1921 .get_power_profile_mode = vangogh_get_power_profile_mode, 1922 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 1923 .force_clk_levels = vangogh_force_clk_levels, 1924 .set_performance_level = vangogh_set_performance_level, 1925 .post_init = vangogh_post_smu_init, 1926 .mode2_reset = vangogh_mode2_reset, 1927 .gfx_off_control = smu_v11_0_gfx_off_control, 1928 .get_ppt_limit = vangogh_get_ppt_limit, 1929 .get_power_limit = vangogh_get_power_limit, 1930 .set_power_limit = vangogh_set_power_limit, 1931 }; 1932 1933 void vangogh_set_ppt_funcs(struct smu_context *smu) 1934 { 1935 smu->ppt_funcs = &vangogh_ppt_funcs; 1936 smu->message_map = vangogh_message_map; 1937 smu->feature_map = vangogh_feature_mask_map; 1938 smu->table_map = vangogh_table_map; 1939 smu->workload_map = vangogh_workload_map; 1940 smu->is_apu = true; 1941 } 1942