1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 38 /* 39 * DO NOT use these for err/warn/info/debug messages. 40 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 41 * They are more MGPU friendly. 42 */ 43 #undef pr_err 44 #undef pr_warn 45 #undef pr_info 46 #undef pr_debug 47 48 #define FEATURE_MASK(feature) (1ULL << feature) 49 #define SMC_DPM_FEATURE ( \ 50 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 51 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 52 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 53 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 54 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 55 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 56 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 57 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 58 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 59 60 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 61 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 62 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 63 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 64 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 65 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 0), 66 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 67 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 68 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 69 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 70 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 71 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 72 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 73 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 74 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 75 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 76 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 77 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 78 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 79 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 80 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 81 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 82 MSG_MAP(Spare1, PPSMC_MSG_spare1, 0), 83 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 84 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 85 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 86 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 87 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 88 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 89 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 90 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 91 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 92 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 93 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 94 MSG_MAP(Spare2, PPSMC_MSG_spare2, 0), 95 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 96 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 97 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 98 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 99 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 100 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 101 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 102 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 103 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 104 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 105 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 106 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 107 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 108 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 109 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 110 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 111 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 112 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 113 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 114 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 115 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 116 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 117 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 118 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 119 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 120 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 121 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 122 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 123 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 124 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 125 }; 126 127 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 128 FEA_MAP(PPT), 129 FEA_MAP(TDC), 130 FEA_MAP(THERMAL), 131 FEA_MAP(DS_GFXCLK), 132 FEA_MAP(DS_SOCCLK), 133 FEA_MAP(DS_LCLK), 134 FEA_MAP(DS_FCLK), 135 FEA_MAP(DS_MP1CLK), 136 FEA_MAP(DS_MP0CLK), 137 FEA_MAP(ATHUB_PG), 138 FEA_MAP(CCLK_DPM), 139 FEA_MAP(FAN_CONTROLLER), 140 FEA_MAP(ULV), 141 FEA_MAP(VCN_DPM), 142 FEA_MAP(LCLK_DPM), 143 FEA_MAP(SHUBCLK_DPM), 144 FEA_MAP(DCFCLK_DPM), 145 FEA_MAP(DS_DCFCLK), 146 FEA_MAP(S0I2), 147 FEA_MAP(SMU_LOW_POWER), 148 FEA_MAP(GFX_DEM), 149 FEA_MAP(PSI), 150 FEA_MAP(PROCHOT), 151 FEA_MAP(CPUOFF), 152 FEA_MAP(STAPM), 153 FEA_MAP(S0I3), 154 FEA_MAP(DF_CSTATES), 155 FEA_MAP(PERF_LIMIT), 156 FEA_MAP(CORE_DLDO), 157 FEA_MAP(RSMU_LOW_POWER), 158 FEA_MAP(SMN_LOW_POWER), 159 FEA_MAP(THM_LOW_POWER), 160 FEA_MAP(SMUIO_LOW_POWER), 161 FEA_MAP(MP1_LOW_POWER), 162 FEA_MAP(DS_VCN), 163 FEA_MAP(CPPC), 164 FEA_MAP(OS_CSTATES), 165 FEA_MAP(ISP_DPM), 166 FEA_MAP(A55_DPM), 167 FEA_MAP(CVIP_DSP_DPM), 168 FEA_MAP(MSMU_LOW_POWER), 169 FEA_MAP_REVERSE(SOCCLK), 170 FEA_MAP_REVERSE(FCLK), 171 FEA_MAP_HALF_REVERSE(GFX), 172 }; 173 174 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 175 TAB_MAP_VALID(WATERMARKS), 176 TAB_MAP_VALID(SMU_METRICS), 177 TAB_MAP_VALID(CUSTOM_DPM), 178 TAB_MAP_VALID(DPMCLOCKS), 179 }; 180 181 static int vangogh_tables_init(struct smu_context *smu) 182 { 183 struct smu_table_context *smu_table = &smu->smu_table; 184 struct smu_table *tables = smu_table->tables; 185 186 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 187 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 188 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 189 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 190 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 191 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 192 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 193 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 194 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 195 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 196 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 197 if (!smu_table->metrics_table) 198 goto err0_out; 199 smu_table->metrics_time = 0; 200 201 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); 202 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 203 if (!smu_table->gpu_metrics_table) 204 goto err1_out; 205 206 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 207 if (!smu_table->watermarks_table) 208 goto err2_out; 209 210 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 211 if (!smu_table->clocks_table) 212 goto err3_out; 213 214 return 0; 215 216 err3_out: 217 kfree(smu_table->clocks_table); 218 err2_out: 219 kfree(smu_table->gpu_metrics_table); 220 err1_out: 221 kfree(smu_table->metrics_table); 222 err0_out: 223 return -ENOMEM; 224 } 225 226 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 227 MetricsMember_t member, 228 uint32_t *value) 229 { 230 struct smu_table_context *smu_table = &smu->smu_table; 231 232 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 233 int ret = 0; 234 235 mutex_lock(&smu->metrics_lock); 236 237 ret = smu_cmn_get_metrics_table_locked(smu, 238 NULL, 239 false); 240 if (ret) { 241 mutex_unlock(&smu->metrics_lock); 242 return ret; 243 } 244 245 switch (member) { 246 case METRICS_AVERAGE_GFXCLK: 247 *value = metrics->GfxclkFrequency; 248 break; 249 case METRICS_AVERAGE_SOCCLK: 250 *value = metrics->SocclkFrequency; 251 break; 252 case METRICS_AVERAGE_VCLK: 253 *value = metrics->VclkFrequency; 254 break; 255 case METRICS_AVERAGE_DCLK: 256 *value = metrics->DclkFrequency; 257 break; 258 case METRICS_AVERAGE_UCLK: 259 *value = metrics->MemclkFrequency; 260 break; 261 case METRICS_AVERAGE_GFXACTIVITY: 262 *value = metrics->GfxActivity / 100; 263 break; 264 case METRICS_AVERAGE_VCNACTIVITY: 265 *value = metrics->UvdActivity; 266 break; 267 case METRICS_AVERAGE_SOCKETPOWER: 268 *value = (metrics->CurrentSocketPower << 8) / 269 1000 ; 270 break; 271 case METRICS_TEMPERATURE_EDGE: 272 *value = metrics->GfxTemperature / 100 * 273 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 274 break; 275 case METRICS_TEMPERATURE_HOTSPOT: 276 *value = metrics->SocTemperature / 100 * 277 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 278 break; 279 case METRICS_THROTTLER_STATUS: 280 *value = metrics->ThrottlerStatus; 281 break; 282 case METRICS_VOLTAGE_VDDGFX: 283 *value = metrics->Voltage[2]; 284 break; 285 case METRICS_VOLTAGE_VDDSOC: 286 *value = metrics->Voltage[1]; 287 break; 288 default: 289 *value = UINT_MAX; 290 break; 291 } 292 293 mutex_unlock(&smu->metrics_lock); 294 295 return ret; 296 } 297 298 static int vangogh_allocate_dpm_context(struct smu_context *smu) 299 { 300 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 301 302 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 303 GFP_KERNEL); 304 if (!smu_dpm->dpm_context) 305 return -ENOMEM; 306 307 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 308 309 return 0; 310 } 311 312 static int vangogh_init_smc_tables(struct smu_context *smu) 313 { 314 int ret = 0; 315 316 ret = vangogh_tables_init(smu); 317 if (ret) 318 return ret; 319 320 ret = vangogh_allocate_dpm_context(smu); 321 if (ret) 322 return ret; 323 324 return smu_v11_0_init_smc_tables(smu); 325 } 326 327 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 328 { 329 int ret = 0; 330 331 if (enable) { 332 /* vcn dpm on is a prerequisite for vcn power gate messages */ 333 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 334 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 335 if (ret) 336 return ret; 337 } 338 } else { 339 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 340 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 341 if (ret) 342 return ret; 343 } 344 } 345 346 return ret; 347 } 348 349 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 350 { 351 int ret = 0; 352 353 if (enable) { 354 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 355 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 356 if (ret) 357 return ret; 358 } 359 } else { 360 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 361 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 362 if (ret) 363 return ret; 364 } 365 } 366 367 return ret; 368 } 369 370 static int vangogh_get_allowed_feature_mask(struct smu_context *smu, 371 uint32_t *feature_mask, 372 uint32_t num) 373 { 374 struct amdgpu_device *adev = smu->adev; 375 376 if (num > 2) 377 return -EINVAL; 378 379 memset(feature_mask, 0, sizeof(uint32_t) * num); 380 381 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DPM_BIT) 382 | FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) 383 | FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) 384 | FEATURE_MASK(FEATURE_VCN_DPM_BIT) 385 | FEATURE_MASK(FEATURE_FCLK_DPM_BIT) 386 | FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) 387 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 388 | FEATURE_MASK(FEATURE_PPT_BIT) 389 | FEATURE_MASK(FEATURE_TDC_BIT) 390 | FEATURE_MASK(FEATURE_FAN_CONTROLLER_BIT) 391 | FEATURE_MASK(FEATURE_DS_LCLK_BIT) 392 | FEATURE_MASK(FEATURE_DS_DCFCLK_BIT); 393 394 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 395 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT); 396 397 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 398 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT); 399 400 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) 401 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FCLK_DPM_BIT); 402 403 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 404 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DPM_BIT); 405 406 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 407 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 408 409 return 0; 410 } 411 412 static bool vangogh_is_dpm_running(struct smu_context *smu) 413 { 414 int ret = 0; 415 uint32_t feature_mask[2]; 416 uint64_t feature_enabled; 417 418 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 419 420 if (ret) 421 return false; 422 423 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 424 ((uint64_t)feature_mask[1] << 32)); 425 426 return !!(feature_enabled & SMC_DPM_FEATURE); 427 } 428 429 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 430 uint32_t dpm_level, uint32_t *freq) 431 { 432 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 433 434 if (!clk_table || clk_type >= SMU_CLK_COUNT) 435 return -EINVAL; 436 437 switch (clk_type) { 438 case SMU_SOCCLK: 439 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 440 return -EINVAL; 441 *freq = clk_table->SocClocks[dpm_level]; 442 break; 443 case SMU_VCLK: 444 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 445 return -EINVAL; 446 *freq = clk_table->VcnClocks[dpm_level].vclk; 447 break; 448 case SMU_DCLK: 449 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 450 return -EINVAL; 451 *freq = clk_table->VcnClocks[dpm_level].dclk; 452 break; 453 case SMU_UCLK: 454 case SMU_MCLK: 455 if (dpm_level >= clk_table->NumDfPstatesEnabled) 456 return -EINVAL; 457 *freq = clk_table->DfPstateTable[dpm_level].memclk; 458 459 break; 460 case SMU_FCLK: 461 if (dpm_level >= clk_table->NumDfPstatesEnabled) 462 return -EINVAL; 463 *freq = clk_table->DfPstateTable[dpm_level].fclk; 464 break; 465 default: 466 return -EINVAL; 467 } 468 469 return 0; 470 } 471 472 static int vangogh_print_fine_grain_clk(struct smu_context *smu, 473 enum smu_clk_type clk_type, char *buf) 474 { 475 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 476 SmuMetrics_t metrics; 477 int i, size = 0, ret = 0; 478 uint32_t cur_value = 0, value = 0, count = 0; 479 bool cur_value_match_level = false; 480 481 memset(&metrics, 0, sizeof(metrics)); 482 483 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 484 if (ret) 485 return ret; 486 487 switch (clk_type) { 488 case SMU_OD_SCLK: 489 if (smu->od_enabled) { 490 size = sprintf(buf, "%s:\n", "OD_SCLK"); 491 size += sprintf(buf + size, "0: %10uMhz\n", 492 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 493 size += sprintf(buf + size, "1: %10uMhz\n", 494 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 495 } 496 break; 497 case SMU_OD_RANGE: 498 if (smu->od_enabled) { 499 size = sprintf(buf, "%s:\n", "OD_RANGE"); 500 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 501 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 502 } 503 break; 504 case SMU_SOCCLK: 505 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 506 count = clk_table->NumSocClkLevelsEnabled; 507 cur_value = metrics.SocclkFrequency; 508 break; 509 case SMU_VCLK: 510 count = clk_table->VcnClkLevelsEnabled; 511 cur_value = metrics.VclkFrequency; 512 break; 513 case SMU_DCLK: 514 count = clk_table->VcnClkLevelsEnabled; 515 cur_value = metrics.DclkFrequency; 516 break; 517 case SMU_MCLK: 518 count = clk_table->NumDfPstatesEnabled; 519 cur_value = metrics.MemclkFrequency; 520 break; 521 case SMU_FCLK: 522 count = clk_table->NumDfPstatesEnabled; 523 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 524 if (ret) 525 return ret; 526 break; 527 default: 528 break; 529 } 530 531 switch (clk_type) { 532 case SMU_SOCCLK: 533 case SMU_VCLK: 534 case SMU_DCLK: 535 case SMU_MCLK: 536 case SMU_FCLK: 537 for (i = 0; i < count; i++) { 538 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 539 if (ret) 540 return ret; 541 if (!value) 542 continue; 543 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 544 cur_value == value ? "*" : ""); 545 if (cur_value == value) 546 cur_value_match_level = true; 547 } 548 549 if (!cur_value_match_level) 550 size += sprintf(buf + size, " %uMhz *\n", cur_value); 551 break; 552 default: 553 break; 554 } 555 556 return size; 557 } 558 559 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 560 enum amd_dpm_forced_level level, 561 uint32_t *vclk_mask, 562 uint32_t *dclk_mask, 563 uint32_t *mclk_mask, 564 uint32_t *fclk_mask, 565 uint32_t *soc_mask) 566 { 567 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 568 569 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 570 if (mclk_mask) 571 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 572 573 if (fclk_mask) 574 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 575 576 if (soc_mask) 577 *soc_mask = 0; 578 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 579 if (mclk_mask) 580 *mclk_mask = 0; 581 582 if (fclk_mask) 583 *fclk_mask = 0; 584 585 if (soc_mask) 586 *soc_mask = 1; 587 588 if (vclk_mask) 589 *vclk_mask = 1; 590 591 if (dclk_mask) 592 *dclk_mask = 1; 593 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 594 if (mclk_mask) 595 *mclk_mask = 0; 596 597 if (fclk_mask) 598 *fclk_mask = 0; 599 600 if (soc_mask) 601 *soc_mask = 1; 602 603 if (vclk_mask) 604 *vclk_mask = 1; 605 606 if (dclk_mask) 607 *dclk_mask = 1; 608 } 609 610 return 0; 611 } 612 613 bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 614 enum smu_clk_type clk_type) 615 { 616 enum smu_feature_mask feature_id = 0; 617 618 switch (clk_type) { 619 case SMU_MCLK: 620 case SMU_UCLK: 621 case SMU_FCLK: 622 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 623 break; 624 case SMU_GFXCLK: 625 case SMU_SCLK: 626 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 627 break; 628 case SMU_SOCCLK: 629 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 630 break; 631 case SMU_VCLK: 632 case SMU_DCLK: 633 feature_id = SMU_FEATURE_VCN_DPM_BIT; 634 break; 635 default: 636 return true; 637 } 638 639 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 640 return false; 641 642 return true; 643 } 644 645 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 646 enum smu_clk_type clk_type, 647 uint32_t *min, 648 uint32_t *max) 649 { 650 int ret = 0; 651 uint32_t soc_mask; 652 uint32_t vclk_mask; 653 uint32_t dclk_mask; 654 uint32_t mclk_mask; 655 uint32_t fclk_mask; 656 uint32_t clock_limit; 657 658 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 659 switch (clk_type) { 660 case SMU_MCLK: 661 case SMU_UCLK: 662 clock_limit = smu->smu_table.boot_values.uclk; 663 break; 664 case SMU_FCLK: 665 clock_limit = smu->smu_table.boot_values.fclk; 666 break; 667 case SMU_GFXCLK: 668 case SMU_SCLK: 669 clock_limit = smu->smu_table.boot_values.gfxclk; 670 break; 671 case SMU_SOCCLK: 672 clock_limit = smu->smu_table.boot_values.socclk; 673 break; 674 case SMU_VCLK: 675 clock_limit = smu->smu_table.boot_values.vclk; 676 break; 677 case SMU_DCLK: 678 clock_limit = smu->smu_table.boot_values.dclk; 679 break; 680 default: 681 clock_limit = 0; 682 break; 683 } 684 685 /* clock in Mhz unit */ 686 if (min) 687 *min = clock_limit / 100; 688 if (max) 689 *max = clock_limit / 100; 690 691 return 0; 692 } 693 if (max) { 694 ret = vangogh_get_profiling_clk_mask(smu, 695 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 696 &vclk_mask, 697 &dclk_mask, 698 &mclk_mask, 699 &fclk_mask, 700 &soc_mask); 701 if (ret) 702 goto failed; 703 704 switch (clk_type) { 705 case SMU_UCLK: 706 case SMU_MCLK: 707 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 708 if (ret) 709 goto failed; 710 break; 711 case SMU_SOCCLK: 712 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 713 if (ret) 714 goto failed; 715 break; 716 case SMU_FCLK: 717 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 718 if (ret) 719 goto failed; 720 break; 721 case SMU_VCLK: 722 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 723 if (ret) 724 goto failed; 725 break; 726 case SMU_DCLK: 727 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 728 if (ret) 729 goto failed; 730 break; 731 default: 732 ret = -EINVAL; 733 goto failed; 734 } 735 } 736 if (min) { 737 switch (clk_type) { 738 case SMU_UCLK: 739 case SMU_MCLK: 740 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 741 if (ret) 742 goto failed; 743 break; 744 case SMU_SOCCLK: 745 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 746 if (ret) 747 goto failed; 748 break; 749 case SMU_FCLK: 750 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 751 if (ret) 752 goto failed; 753 break; 754 case SMU_VCLK: 755 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 756 if (ret) 757 goto failed; 758 break; 759 case SMU_DCLK: 760 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 761 if (ret) 762 goto failed; 763 break; 764 default: 765 ret = -EINVAL; 766 goto failed; 767 } 768 } 769 failed: 770 return ret; 771 } 772 773 static int vangogh_get_power_profile_mode(struct smu_context *smu, 774 char *buf) 775 { 776 static const char *profile_name[] = { 777 "BOOTUP_DEFAULT", 778 "FULL_SCREEN_3D", 779 "VIDEO", 780 "VR", 781 "COMPUTE", 782 "CUSTOM"}; 783 uint32_t i, size = 0; 784 int16_t workload_type = 0; 785 786 if (!buf) 787 return -EINVAL; 788 789 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 790 /* 791 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 792 * Not all profile modes are supported on vangogh. 793 */ 794 workload_type = smu_cmn_to_asic_specific_index(smu, 795 CMN2ASIC_MAPPING_WORKLOAD, 796 i); 797 798 if (workload_type < 0) 799 continue; 800 801 size += sprintf(buf + size, "%2d %14s%s\n", 802 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 803 } 804 805 return size; 806 } 807 808 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 809 { 810 int workload_type, ret; 811 uint32_t profile_mode = input[size]; 812 813 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 814 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 815 return -EINVAL; 816 } 817 818 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 819 workload_type = smu_cmn_to_asic_specific_index(smu, 820 CMN2ASIC_MAPPING_WORKLOAD, 821 profile_mode); 822 if (workload_type < 0) { 823 dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 824 profile_mode); 825 return -EINVAL; 826 } 827 828 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 829 1 << workload_type, 830 NULL); 831 if (ret) { 832 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 833 workload_type); 834 return ret; 835 } 836 837 smu->power_profile_mode = profile_mode; 838 839 return 0; 840 } 841 842 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 843 enum smu_clk_type clk_type, 844 uint32_t min, 845 uint32_t max) 846 { 847 int ret = 0; 848 849 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 850 return 0; 851 852 switch (clk_type) { 853 case SMU_GFXCLK: 854 case SMU_SCLK: 855 ret = smu_cmn_send_smc_msg_with_param(smu, 856 SMU_MSG_SetHardMinGfxClk, 857 min, NULL); 858 if (ret) 859 return ret; 860 861 ret = smu_cmn_send_smc_msg_with_param(smu, 862 SMU_MSG_SetSoftMaxGfxClk, 863 max, NULL); 864 if (ret) 865 return ret; 866 break; 867 case SMU_FCLK: 868 case SMU_MCLK: 869 ret = smu_cmn_send_smc_msg_with_param(smu, 870 SMU_MSG_SetHardMinFclkByFreq, 871 min, NULL); 872 if (ret) 873 return ret; 874 875 ret = smu_cmn_send_smc_msg_with_param(smu, 876 SMU_MSG_SetSoftMaxFclkByFreq, 877 max, NULL); 878 if (ret) 879 return ret; 880 break; 881 case SMU_SOCCLK: 882 ret = smu_cmn_send_smc_msg_with_param(smu, 883 SMU_MSG_SetHardMinSocclkByFreq, 884 min, NULL); 885 if (ret) 886 return ret; 887 888 ret = smu_cmn_send_smc_msg_with_param(smu, 889 SMU_MSG_SetSoftMaxSocclkByFreq, 890 max, NULL); 891 if (ret) 892 return ret; 893 break; 894 case SMU_VCLK: 895 ret = smu_cmn_send_smc_msg_with_param(smu, 896 SMU_MSG_SetHardMinVcn, 897 min << 16, NULL); 898 if (ret) 899 return ret; 900 ret = smu_cmn_send_smc_msg_with_param(smu, 901 SMU_MSG_SetSoftMaxVcn, 902 max << 16, NULL); 903 if (ret) 904 return ret; 905 break; 906 case SMU_DCLK: 907 ret = smu_cmn_send_smc_msg_with_param(smu, 908 SMU_MSG_SetHardMinVcn, 909 min, NULL); 910 if (ret) 911 return ret; 912 ret = smu_cmn_send_smc_msg_with_param(smu, 913 SMU_MSG_SetSoftMaxVcn, 914 max, NULL); 915 if (ret) 916 return ret; 917 break; 918 default: 919 return -EINVAL; 920 } 921 922 return ret; 923 } 924 925 static int vangogh_force_clk_levels(struct smu_context *smu, 926 enum smu_clk_type clk_type, uint32_t mask) 927 { 928 uint32_t soft_min_level = 0, soft_max_level = 0; 929 uint32_t min_freq = 0, max_freq = 0; 930 int ret = 0 ; 931 932 soft_min_level = mask ? (ffs(mask) - 1) : 0; 933 soft_max_level = mask ? (fls(mask) - 1) : 0; 934 935 switch (clk_type) { 936 case SMU_SOCCLK: 937 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 938 soft_min_level, &min_freq); 939 if (ret) 940 return ret; 941 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 942 soft_max_level, &max_freq); 943 if (ret) 944 return ret; 945 ret = smu_cmn_send_smc_msg_with_param(smu, 946 SMU_MSG_SetSoftMaxSocclkByFreq, 947 max_freq, NULL); 948 if (ret) 949 return ret; 950 ret = smu_cmn_send_smc_msg_with_param(smu, 951 SMU_MSG_SetHardMinSocclkByFreq, 952 min_freq, NULL); 953 if (ret) 954 return ret; 955 break; 956 case SMU_MCLK: 957 case SMU_FCLK: 958 ret = vangogh_get_dpm_clk_limited(smu, 959 clk_type, soft_min_level, &min_freq); 960 if (ret) 961 return ret; 962 ret = vangogh_get_dpm_clk_limited(smu, 963 clk_type, soft_max_level, &max_freq); 964 if (ret) 965 return ret; 966 ret = smu_cmn_send_smc_msg_with_param(smu, 967 SMU_MSG_SetSoftMaxFclkByFreq, 968 max_freq, NULL); 969 if (ret) 970 return ret; 971 ret = smu_cmn_send_smc_msg_with_param(smu, 972 SMU_MSG_SetHardMinFclkByFreq, 973 min_freq, NULL); 974 if (ret) 975 return ret; 976 break; 977 case SMU_VCLK: 978 ret = vangogh_get_dpm_clk_limited(smu, 979 clk_type, soft_min_level, &min_freq); 980 if (ret) 981 return ret; 982 983 ret = vangogh_get_dpm_clk_limited(smu, 984 clk_type, soft_max_level, &max_freq); 985 if (ret) 986 return ret; 987 988 989 ret = smu_cmn_send_smc_msg_with_param(smu, 990 SMU_MSG_SetHardMinVcn, 991 min_freq << 16, NULL); 992 if (ret) 993 return ret; 994 995 ret = smu_cmn_send_smc_msg_with_param(smu, 996 SMU_MSG_SetSoftMaxVcn, 997 max_freq << 16, NULL); 998 if (ret) 999 return ret; 1000 1001 break; 1002 case SMU_DCLK: 1003 ret = vangogh_get_dpm_clk_limited(smu, 1004 clk_type, soft_min_level, &min_freq); 1005 if (ret) 1006 return ret; 1007 1008 ret = vangogh_get_dpm_clk_limited(smu, 1009 clk_type, soft_max_level, &max_freq); 1010 if (ret) 1011 return ret; 1012 1013 ret = smu_cmn_send_smc_msg_with_param(smu, 1014 SMU_MSG_SetHardMinVcn, 1015 min_freq, NULL); 1016 if (ret) 1017 return ret; 1018 1019 ret = smu_cmn_send_smc_msg_with_param(smu, 1020 SMU_MSG_SetSoftMaxVcn, 1021 max_freq, NULL); 1022 if (ret) 1023 return ret; 1024 1025 break; 1026 default: 1027 break; 1028 } 1029 1030 return ret; 1031 } 1032 1033 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1034 { 1035 int ret = 0, i = 0; 1036 uint32_t min_freq, max_freq, force_freq; 1037 enum smu_clk_type clk_type; 1038 1039 enum smu_clk_type clks[] = { 1040 SMU_SOCCLK, 1041 SMU_VCLK, 1042 SMU_DCLK, 1043 SMU_MCLK, 1044 SMU_FCLK, 1045 }; 1046 1047 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1048 clk_type = clks[i]; 1049 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1050 if (ret) 1051 return ret; 1052 1053 force_freq = highest ? max_freq : min_freq; 1054 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1055 if (ret) 1056 return ret; 1057 } 1058 1059 return ret; 1060 } 1061 1062 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1063 { 1064 int ret = 0, i = 0; 1065 uint32_t min_freq, max_freq; 1066 enum smu_clk_type clk_type; 1067 1068 struct clk_feature_map { 1069 enum smu_clk_type clk_type; 1070 uint32_t feature; 1071 } clk_feature_map[] = { 1072 {SMU_MCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1073 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1074 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1075 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1076 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1077 }; 1078 1079 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1080 1081 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1082 continue; 1083 1084 clk_type = clk_feature_map[i].clk_type; 1085 1086 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1087 1088 if (ret) 1089 return ret; 1090 1091 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1092 1093 if (ret) 1094 return ret; 1095 } 1096 1097 return ret; 1098 } 1099 1100 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1101 { 1102 int ret = 0; 1103 uint32_t socclk_freq = 0, fclk_freq = 0; 1104 uint32_t vclk_freq = 0, dclk_freq = 0; 1105 1106 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1107 if (ret) 1108 return ret; 1109 1110 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1111 if (ret) 1112 return ret; 1113 1114 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1115 if (ret) 1116 return ret; 1117 1118 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1119 if (ret) 1120 return ret; 1121 1122 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1123 if (ret) 1124 return ret; 1125 1126 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1127 if (ret) 1128 return ret; 1129 1130 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1131 if (ret) 1132 return ret; 1133 1134 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1135 if (ret) 1136 return ret; 1137 1138 return ret; 1139 } 1140 1141 static int vangogh_set_performance_level(struct smu_context *smu, 1142 enum amd_dpm_forced_level level) 1143 { 1144 int ret = 0; 1145 uint32_t soc_mask, mclk_mask, fclk_mask; 1146 uint32_t vclk_mask = 0, dclk_mask = 0; 1147 1148 switch (level) { 1149 case AMD_DPM_FORCED_LEVEL_HIGH: 1150 ret = vangogh_force_dpm_limit_value(smu, true); 1151 break; 1152 case AMD_DPM_FORCED_LEVEL_LOW: 1153 ret = vangogh_force_dpm_limit_value(smu, false); 1154 break; 1155 case AMD_DPM_FORCED_LEVEL_AUTO: 1156 ret = vangogh_unforce_dpm_levels(smu); 1157 break; 1158 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1159 ret = smu_cmn_send_smc_msg_with_param(smu, 1160 SMU_MSG_SetHardMinGfxClk, 1161 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1162 if (ret) 1163 return ret; 1164 1165 ret = smu_cmn_send_smc_msg_with_param(smu, 1166 SMU_MSG_SetSoftMaxGfxClk, 1167 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1168 if (ret) 1169 return ret; 1170 1171 ret = vangogh_get_profiling_clk_mask(smu, level, 1172 &vclk_mask, 1173 &dclk_mask, 1174 &mclk_mask, 1175 &fclk_mask, 1176 &soc_mask); 1177 if (ret) 1178 return ret; 1179 1180 vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 1181 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1182 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1183 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1184 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1185 1186 break; 1187 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1188 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, 1189 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1190 if (ret) 1191 return ret; 1192 1193 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, 1194 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1195 if (ret) 1196 return ret; 1197 break; 1198 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1199 ret = vangogh_get_profiling_clk_mask(smu, level, 1200 NULL, 1201 NULL, 1202 &mclk_mask, 1203 &fclk_mask, 1204 NULL); 1205 if (ret) 1206 return ret; 1207 1208 vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 1209 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1210 break; 1211 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1212 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1213 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1214 if (ret) 1215 return ret; 1216 1217 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1218 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1219 if (ret) 1220 return ret; 1221 1222 ret = vangogh_set_peak_clock_by_device(smu); 1223 break; 1224 case AMD_DPM_FORCED_LEVEL_MANUAL: 1225 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1226 default: 1227 break; 1228 } 1229 return ret; 1230 } 1231 1232 static int vangogh_read_sensor(struct smu_context *smu, 1233 enum amd_pp_sensors sensor, 1234 void *data, uint32_t *size) 1235 { 1236 int ret = 0; 1237 1238 if (!data || !size) 1239 return -EINVAL; 1240 1241 mutex_lock(&smu->sensor_lock); 1242 switch (sensor) { 1243 case AMDGPU_PP_SENSOR_GPU_LOAD: 1244 ret = vangogh_get_smu_metrics_data(smu, 1245 METRICS_AVERAGE_GFXACTIVITY, 1246 (uint32_t *)data); 1247 *size = 4; 1248 break; 1249 case AMDGPU_PP_SENSOR_GPU_POWER: 1250 ret = vangogh_get_smu_metrics_data(smu, 1251 METRICS_AVERAGE_SOCKETPOWER, 1252 (uint32_t *)data); 1253 *size = 4; 1254 break; 1255 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1256 ret = vangogh_get_smu_metrics_data(smu, 1257 METRICS_TEMPERATURE_EDGE, 1258 (uint32_t *)data); 1259 *size = 4; 1260 break; 1261 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1262 ret = vangogh_get_smu_metrics_data(smu, 1263 METRICS_TEMPERATURE_HOTSPOT, 1264 (uint32_t *)data); 1265 *size = 4; 1266 break; 1267 case AMDGPU_PP_SENSOR_GFX_MCLK: 1268 ret = vangogh_get_smu_metrics_data(smu, 1269 METRICS_AVERAGE_UCLK, 1270 (uint32_t *)data); 1271 *(uint32_t *)data *= 100; 1272 *size = 4; 1273 break; 1274 case AMDGPU_PP_SENSOR_GFX_SCLK: 1275 ret = vangogh_get_smu_metrics_data(smu, 1276 METRICS_AVERAGE_GFXCLK, 1277 (uint32_t *)data); 1278 *(uint32_t *)data *= 100; 1279 *size = 4; 1280 break; 1281 case AMDGPU_PP_SENSOR_VDDGFX: 1282 ret = vangogh_get_smu_metrics_data(smu, 1283 METRICS_VOLTAGE_VDDGFX, 1284 (uint32_t *)data); 1285 *size = 4; 1286 break; 1287 case AMDGPU_PP_SENSOR_VDDNB: 1288 ret = vangogh_get_smu_metrics_data(smu, 1289 METRICS_VOLTAGE_VDDSOC, 1290 (uint32_t *)data); 1291 *size = 4; 1292 break; 1293 default: 1294 ret = -EOPNOTSUPP; 1295 break; 1296 } 1297 mutex_unlock(&smu->sensor_lock); 1298 1299 return ret; 1300 } 1301 1302 static int vangogh_set_watermarks_table(struct smu_context *smu, 1303 struct pp_smu_wm_range_sets *clock_ranges) 1304 { 1305 int i; 1306 int ret = 0; 1307 Watermarks_t *table = smu->smu_table.watermarks_table; 1308 1309 if (!table || !clock_ranges) 1310 return -EINVAL; 1311 1312 if (clock_ranges) { 1313 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1314 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1315 return -EINVAL; 1316 1317 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1318 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1319 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1320 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1321 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1322 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1323 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1324 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1325 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1326 1327 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1328 clock_ranges->reader_wm_sets[i].wm_inst; 1329 } 1330 1331 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1332 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1333 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1334 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1335 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1336 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1337 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1338 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1339 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1340 1341 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1342 clock_ranges->writer_wm_sets[i].wm_inst; 1343 } 1344 1345 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1346 } 1347 1348 /* pass data to smu controller */ 1349 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1350 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1351 ret = smu_cmn_write_watermarks_table(smu); 1352 if (ret) { 1353 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1354 return ret; 1355 } 1356 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1357 } 1358 1359 return 0; 1360 } 1361 1362 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1363 void **table) 1364 { 1365 struct smu_table_context *smu_table = &smu->smu_table; 1366 struct gpu_metrics_v2_0 *gpu_metrics = 1367 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; 1368 SmuMetrics_t metrics; 1369 int ret = 0; 1370 1371 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1372 if (ret) 1373 return ret; 1374 1375 smu_v11_0_init_gpu_metrics_v2_0(gpu_metrics); 1376 1377 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1378 gpu_metrics->temperature_soc = metrics.SocTemperature; 1379 memcpy(&gpu_metrics->temperature_core[0], 1380 &metrics.CoreTemperature[0], 1381 sizeof(uint16_t) * 8); 1382 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1383 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1384 1385 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1386 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1387 1388 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1389 gpu_metrics->average_cpu_power = metrics.Power[0]; 1390 gpu_metrics->average_soc_power = metrics.Power[1]; 1391 memcpy(&gpu_metrics->average_core_power[0], 1392 &metrics.CorePower[0], 1393 sizeof(uint16_t) * 8); 1394 1395 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1396 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1397 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1398 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1399 1400 memcpy(&gpu_metrics->current_coreclk[0], 1401 &metrics.CoreFrequency[0], 1402 sizeof(uint16_t) * 8); 1403 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1404 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1405 1406 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1407 1408 *table = (void *)gpu_metrics; 1409 1410 return sizeof(struct gpu_metrics_v2_0); 1411 } 1412 1413 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1414 long input[], uint32_t size) 1415 { 1416 int ret = 0; 1417 1418 if (!smu->od_enabled) { 1419 dev_warn(smu->adev->dev, "Fine grain is not enabled!\n"); 1420 return -EINVAL; 1421 } 1422 1423 switch (type) { 1424 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1425 if (size != 2) { 1426 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1427 return -EINVAL; 1428 } 1429 1430 if (input[0] == 0) { 1431 if (input[1] < smu->gfx_default_hard_min_freq) { 1432 dev_warn(smu->adev->dev, 1433 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1434 input[1], smu->gfx_default_hard_min_freq); 1435 return -EINVAL; 1436 } 1437 smu->gfx_actual_hard_min_freq = input[1]; 1438 } else if (input[0] == 1) { 1439 if (input[1] > smu->gfx_default_soft_max_freq) { 1440 dev_warn(smu->adev->dev, 1441 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1442 input[1], smu->gfx_default_soft_max_freq); 1443 return -EINVAL; 1444 } 1445 smu->gfx_actual_soft_max_freq = input[1]; 1446 } else { 1447 return -EINVAL; 1448 } 1449 break; 1450 case PP_OD_RESTORE_DEFAULT_TABLE: 1451 if (size != 0) { 1452 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1453 return -EINVAL; 1454 } else { 1455 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1456 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1457 1458 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1459 smu->gfx_actual_hard_min_freq, NULL); 1460 if (ret) { 1461 dev_err(smu->adev->dev, "Restore the default hard min sclk failed!"); 1462 return ret; 1463 } 1464 1465 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1466 smu->gfx_actual_soft_max_freq, NULL); 1467 if (ret) { 1468 dev_err(smu->adev->dev, "Restore the default soft max sclk failed!"); 1469 return ret; 1470 } 1471 } 1472 break; 1473 case PP_OD_COMMIT_DPM_TABLE: 1474 if (size != 0) { 1475 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1476 return -EINVAL; 1477 } else { 1478 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1479 dev_err(smu->adev->dev, 1480 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1481 smu->gfx_actual_hard_min_freq, 1482 smu->gfx_actual_soft_max_freq); 1483 return -EINVAL; 1484 } 1485 1486 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1487 smu->gfx_actual_hard_min_freq, NULL); 1488 if (ret) { 1489 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1490 return ret; 1491 } 1492 1493 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1494 smu->gfx_actual_soft_max_freq, NULL); 1495 if (ret) { 1496 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1497 return ret; 1498 } 1499 } 1500 break; 1501 default: 1502 return -ENOSYS; 1503 } 1504 1505 return ret; 1506 } 1507 1508 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 1509 { 1510 struct smu_table_context *smu_table = &smu->smu_table; 1511 1512 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 1513 } 1514 1515 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1516 { 1517 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1518 1519 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1520 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1521 smu->gfx_actual_hard_min_freq = 0; 1522 smu->gfx_actual_soft_max_freq = 0; 1523 1524 return 0; 1525 } 1526 1527 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 1528 { 1529 DpmClocks_t *table = smu->smu_table.clocks_table; 1530 int i; 1531 1532 if (!clock_table || !table) 1533 return -EINVAL; 1534 1535 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 1536 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 1537 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 1538 } 1539 1540 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1541 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 1542 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 1543 } 1544 1545 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1546 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 1547 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 1548 } 1549 1550 return 0; 1551 } 1552 1553 1554 static int vangogh_system_features_control(struct smu_context *smu, bool en) 1555 { 1556 struct amdgpu_device *adev = smu->adev; 1557 1558 if (adev->pm.fw_version >= 0x43f1700) 1559 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 1560 en ? RLC_STATUS_NORMAL : RLC_STATUS_OFF, NULL); 1561 else 1562 return 0; 1563 } 1564 1565 static int vangogh_post_smu_init(struct smu_context *smu) 1566 { 1567 struct amdgpu_device *adev = smu->adev; 1568 uint32_t tmp; 1569 uint8_t aon_bits = 0; 1570 /* Two CUs in one WGP */ 1571 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 1572 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 1573 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1574 1575 /* if all CUs are active, no need to power off any WGPs */ 1576 if (total_cu == adev->gfx.cu_info.number) 1577 return 0; 1578 1579 /* 1580 * Calculate the total bits number of always on WGPs for all SA/SEs in 1581 * RLC_PG_ALWAYS_ON_WGP_MASK. 1582 */ 1583 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 1584 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 1585 1586 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1587 1588 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 1589 if (aon_bits > req_active_wgps) { 1590 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 1591 return 0; 1592 } else { 1593 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 1594 } 1595 } 1596 1597 static const struct pptable_funcs vangogh_ppt_funcs = { 1598 1599 .check_fw_status = smu_v11_0_check_fw_status, 1600 .check_fw_version = smu_v11_0_check_fw_version, 1601 .init_smc_tables = vangogh_init_smc_tables, 1602 .fini_smc_tables = smu_v11_0_fini_smc_tables, 1603 .init_power = smu_v11_0_init_power, 1604 .fini_power = smu_v11_0_fini_power, 1605 .register_irq_handler = smu_v11_0_register_irq_handler, 1606 .get_allowed_feature_mask = vangogh_get_allowed_feature_mask, 1607 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 1608 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1609 .send_smc_msg = smu_cmn_send_smc_msg, 1610 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 1611 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 1612 .is_dpm_running = vangogh_is_dpm_running, 1613 .read_sensor = vangogh_read_sensor, 1614 .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask, 1615 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1616 .set_watermarks_table = vangogh_set_watermarks_table, 1617 .set_driver_table_location = smu_v11_0_set_driver_table_location, 1618 .interrupt_work = smu_v11_0_interrupt_work, 1619 .get_gpu_metrics = vangogh_get_gpu_metrics, 1620 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 1621 .print_clk_levels = vangogh_print_fine_grain_clk, 1622 .set_default_dpm_table = vangogh_set_default_dpm_tables, 1623 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 1624 .system_features_control = vangogh_system_features_control, 1625 .feature_is_enabled = smu_cmn_feature_is_enabled, 1626 .set_power_profile_mode = vangogh_set_power_profile_mode, 1627 .get_power_profile_mode = vangogh_get_power_profile_mode, 1628 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 1629 .force_clk_levels = vangogh_force_clk_levels, 1630 .set_performance_level = vangogh_set_performance_level, 1631 .post_init = vangogh_post_smu_init, 1632 }; 1633 1634 void vangogh_set_ppt_funcs(struct smu_context *smu) 1635 { 1636 smu->ppt_funcs = &vangogh_ppt_funcs; 1637 smu->message_map = vangogh_message_map; 1638 smu->feature_map = vangogh_feature_mask_map; 1639 smu->table_map = vangogh_table_map; 1640 smu->is_apu = true; 1641 } 1642