1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 #include <asm/processor.h> 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 #define FEATURE_MASK(feature) (1ULL << feature) 50 #define SMC_DPM_FEATURE ( \ 51 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 52 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 53 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 54 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 55 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 56 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 57 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 58 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 59 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 60 61 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 62 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 63 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 64 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 65 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 66 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 67 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 68 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 69 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 70 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 71 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 72 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 73 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 74 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 75 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 76 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 77 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 78 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 79 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 80 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 81 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 82 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 83 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 84 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 85 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 86 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 87 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 88 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 89 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 95 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 96 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 97 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 98 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 99 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 100 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 101 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 102 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 103 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 104 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 105 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 106 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 107 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 108 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 109 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 110 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 111 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 112 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 113 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 114 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 115 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 116 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 117 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 118 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 119 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 120 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 121 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 122 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 123 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 124 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 125 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 126 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 127 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 128 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 129 }; 130 131 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 132 FEA_MAP(PPT), 133 FEA_MAP(TDC), 134 FEA_MAP(THERMAL), 135 FEA_MAP(DS_GFXCLK), 136 FEA_MAP(DS_SOCCLK), 137 FEA_MAP(DS_LCLK), 138 FEA_MAP(DS_FCLK), 139 FEA_MAP(DS_MP1CLK), 140 FEA_MAP(DS_MP0CLK), 141 FEA_MAP(ATHUB_PG), 142 FEA_MAP(CCLK_DPM), 143 FEA_MAP(FAN_CONTROLLER), 144 FEA_MAP(ULV), 145 FEA_MAP(VCN_DPM), 146 FEA_MAP(LCLK_DPM), 147 FEA_MAP(SHUBCLK_DPM), 148 FEA_MAP(DCFCLK_DPM), 149 FEA_MAP(DS_DCFCLK), 150 FEA_MAP(S0I2), 151 FEA_MAP(SMU_LOW_POWER), 152 FEA_MAP(GFX_DEM), 153 FEA_MAP(PSI), 154 FEA_MAP(PROCHOT), 155 FEA_MAP(CPUOFF), 156 FEA_MAP(STAPM), 157 FEA_MAP(S0I3), 158 FEA_MAP(DF_CSTATES), 159 FEA_MAP(PERF_LIMIT), 160 FEA_MAP(CORE_DLDO), 161 FEA_MAP(RSMU_LOW_POWER), 162 FEA_MAP(SMN_LOW_POWER), 163 FEA_MAP(THM_LOW_POWER), 164 FEA_MAP(SMUIO_LOW_POWER), 165 FEA_MAP(MP1_LOW_POWER), 166 FEA_MAP(DS_VCN), 167 FEA_MAP(CPPC), 168 FEA_MAP(OS_CSTATES), 169 FEA_MAP(ISP_DPM), 170 FEA_MAP(A55_DPM), 171 FEA_MAP(CVIP_DSP_DPM), 172 FEA_MAP(MSMU_LOW_POWER), 173 FEA_MAP_REVERSE(SOCCLK), 174 FEA_MAP_REVERSE(FCLK), 175 FEA_MAP_HALF_REVERSE(GFX), 176 }; 177 178 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 179 TAB_MAP_VALID(WATERMARKS), 180 TAB_MAP_VALID(SMU_METRICS), 181 TAB_MAP_VALID(CUSTOM_DPM), 182 TAB_MAP_VALID(DPMCLOCKS), 183 }; 184 185 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 187 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 188 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 189 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 190 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 191 }; 192 193 static int vangogh_tables_init(struct smu_context *smu) 194 { 195 struct smu_table_context *smu_table = &smu->smu_table; 196 struct smu_table *tables = smu_table->tables; 197 198 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 199 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 200 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 201 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 202 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 203 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 204 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 205 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 206 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 207 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 208 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 209 if (!smu_table->metrics_table) 210 goto err0_out; 211 smu_table->metrics_time = 0; 212 213 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); 214 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 215 if (!smu_table->gpu_metrics_table) 216 goto err1_out; 217 218 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 219 if (!smu_table->watermarks_table) 220 goto err2_out; 221 222 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 223 if (!smu_table->clocks_table) 224 goto err3_out; 225 226 return 0; 227 228 err3_out: 229 kfree(smu_table->clocks_table); 230 err2_out: 231 kfree(smu_table->gpu_metrics_table); 232 err1_out: 233 kfree(smu_table->metrics_table); 234 err0_out: 235 return -ENOMEM; 236 } 237 238 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 239 MetricsMember_t member, 240 uint32_t *value) 241 { 242 struct smu_table_context *smu_table = &smu->smu_table; 243 244 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 245 int ret = 0; 246 247 mutex_lock(&smu->metrics_lock); 248 249 ret = smu_cmn_get_metrics_table_locked(smu, 250 NULL, 251 false); 252 if (ret) { 253 mutex_unlock(&smu->metrics_lock); 254 return ret; 255 } 256 257 switch (member) { 258 case METRICS_AVERAGE_GFXCLK: 259 *value = metrics->GfxclkFrequency; 260 break; 261 case METRICS_AVERAGE_SOCCLK: 262 *value = metrics->SocclkFrequency; 263 break; 264 case METRICS_AVERAGE_VCLK: 265 *value = metrics->VclkFrequency; 266 break; 267 case METRICS_AVERAGE_DCLK: 268 *value = metrics->DclkFrequency; 269 break; 270 case METRICS_AVERAGE_UCLK: 271 *value = metrics->MemclkFrequency; 272 break; 273 case METRICS_AVERAGE_GFXACTIVITY: 274 *value = metrics->GfxActivity / 100; 275 break; 276 case METRICS_AVERAGE_VCNACTIVITY: 277 *value = metrics->UvdActivity; 278 break; 279 case METRICS_AVERAGE_SOCKETPOWER: 280 *value = (metrics->CurrentSocketPower << 8) / 281 1000 ; 282 break; 283 case METRICS_TEMPERATURE_EDGE: 284 *value = metrics->GfxTemperature / 100 * 285 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 286 break; 287 case METRICS_TEMPERATURE_HOTSPOT: 288 *value = metrics->SocTemperature / 100 * 289 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 290 break; 291 case METRICS_THROTTLER_STATUS: 292 *value = metrics->ThrottlerStatus; 293 break; 294 case METRICS_VOLTAGE_VDDGFX: 295 *value = metrics->Voltage[2]; 296 break; 297 case METRICS_VOLTAGE_VDDSOC: 298 *value = metrics->Voltage[1]; 299 break; 300 case METRICS_AVERAGE_CPUCLK: 301 memcpy(value, &metrics->CoreFrequency[0], 302 smu->cpu_core_num * sizeof(uint16_t)); 303 break; 304 default: 305 *value = UINT_MAX; 306 break; 307 } 308 309 mutex_unlock(&smu->metrics_lock); 310 311 return ret; 312 } 313 314 static int vangogh_allocate_dpm_context(struct smu_context *smu) 315 { 316 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 317 318 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 319 GFP_KERNEL); 320 if (!smu_dpm->dpm_context) 321 return -ENOMEM; 322 323 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 324 325 return 0; 326 } 327 328 static int vangogh_init_smc_tables(struct smu_context *smu) 329 { 330 int ret = 0; 331 332 ret = vangogh_tables_init(smu); 333 if (ret) 334 return ret; 335 336 ret = vangogh_allocate_dpm_context(smu); 337 if (ret) 338 return ret; 339 340 #ifdef CONFIG_X86 341 /* AMD x86 APU only */ 342 smu->cpu_core_num = boot_cpu_data.x86_max_cores; 343 #else 344 smu->cpu_core_num = 4; 345 #endif 346 347 return smu_v11_0_init_smc_tables(smu); 348 } 349 350 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 351 { 352 int ret = 0; 353 354 if (enable) { 355 /* vcn dpm on is a prerequisite for vcn power gate messages */ 356 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 357 if (ret) 358 return ret; 359 } else { 360 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 361 if (ret) 362 return ret; 363 } 364 365 return ret; 366 } 367 368 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 369 { 370 int ret = 0; 371 372 if (enable) { 373 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 374 if (ret) 375 return ret; 376 } else { 377 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 378 if (ret) 379 return ret; 380 } 381 382 return ret; 383 } 384 385 static bool vangogh_is_dpm_running(struct smu_context *smu) 386 { 387 int ret = 0; 388 uint32_t feature_mask[2]; 389 uint64_t feature_enabled; 390 391 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 392 393 if (ret) 394 return false; 395 396 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 397 ((uint64_t)feature_mask[1] << 32)); 398 399 return !!(feature_enabled & SMC_DPM_FEATURE); 400 } 401 402 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 403 uint32_t dpm_level, uint32_t *freq) 404 { 405 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 406 407 if (!clk_table || clk_type >= SMU_CLK_COUNT) 408 return -EINVAL; 409 410 switch (clk_type) { 411 case SMU_SOCCLK: 412 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 413 return -EINVAL; 414 *freq = clk_table->SocClocks[dpm_level]; 415 break; 416 case SMU_VCLK: 417 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 418 return -EINVAL; 419 *freq = clk_table->VcnClocks[dpm_level].vclk; 420 break; 421 case SMU_DCLK: 422 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 423 return -EINVAL; 424 *freq = clk_table->VcnClocks[dpm_level].dclk; 425 break; 426 case SMU_UCLK: 427 case SMU_MCLK: 428 if (dpm_level >= clk_table->NumDfPstatesEnabled) 429 return -EINVAL; 430 *freq = clk_table->DfPstateTable[dpm_level].memclk; 431 432 break; 433 case SMU_FCLK: 434 if (dpm_level >= clk_table->NumDfPstatesEnabled) 435 return -EINVAL; 436 *freq = clk_table->DfPstateTable[dpm_level].fclk; 437 break; 438 default: 439 return -EINVAL; 440 } 441 442 return 0; 443 } 444 445 static int vangogh_print_fine_grain_clk(struct smu_context *smu, 446 enum smu_clk_type clk_type, char *buf) 447 { 448 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 449 SmuMetrics_t metrics; 450 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 451 int i, size = 0, ret = 0; 452 uint32_t cur_value = 0, value = 0, count = 0; 453 bool cur_value_match_level = false; 454 455 memset(&metrics, 0, sizeof(metrics)); 456 457 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 458 if (ret) 459 return ret; 460 461 switch (clk_type) { 462 case SMU_OD_SCLK: 463 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 464 size = sprintf(buf, "%s:\n", "OD_SCLK"); 465 size += sprintf(buf + size, "0: %10uMhz\n", 466 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 467 size += sprintf(buf + size, "1: %10uMhz\n", 468 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 469 } 470 break; 471 case SMU_OD_CCLK: 472 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 473 size = sprintf(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 474 size += sprintf(buf + size, "0: %10uMhz\n", 475 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 476 size += sprintf(buf + size, "1: %10uMhz\n", 477 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 478 } 479 break; 480 case SMU_OD_RANGE: 481 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 482 size = sprintf(buf, "%s:\n", "OD_RANGE"); 483 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 484 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 485 size += sprintf(buf + size, "CCLK: %7uMhz %10uMhz\n", 486 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 487 } 488 break; 489 case SMU_SOCCLK: 490 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 491 count = clk_table->NumSocClkLevelsEnabled; 492 cur_value = metrics.SocclkFrequency; 493 break; 494 case SMU_VCLK: 495 count = clk_table->VcnClkLevelsEnabled; 496 cur_value = metrics.VclkFrequency; 497 break; 498 case SMU_DCLK: 499 count = clk_table->VcnClkLevelsEnabled; 500 cur_value = metrics.DclkFrequency; 501 break; 502 case SMU_MCLK: 503 count = clk_table->NumDfPstatesEnabled; 504 cur_value = metrics.MemclkFrequency; 505 break; 506 case SMU_FCLK: 507 count = clk_table->NumDfPstatesEnabled; 508 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 509 if (ret) 510 return ret; 511 break; 512 default: 513 break; 514 } 515 516 switch (clk_type) { 517 case SMU_SOCCLK: 518 case SMU_VCLK: 519 case SMU_DCLK: 520 case SMU_MCLK: 521 case SMU_FCLK: 522 for (i = 0; i < count; i++) { 523 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 524 if (ret) 525 return ret; 526 if (!value) 527 continue; 528 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 529 cur_value == value ? "*" : ""); 530 if (cur_value == value) 531 cur_value_match_level = true; 532 } 533 534 if (!cur_value_match_level) 535 size += sprintf(buf + size, " %uMhz *\n", cur_value); 536 break; 537 default: 538 break; 539 } 540 541 return size; 542 } 543 544 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 545 enum amd_dpm_forced_level level, 546 uint32_t *vclk_mask, 547 uint32_t *dclk_mask, 548 uint32_t *mclk_mask, 549 uint32_t *fclk_mask, 550 uint32_t *soc_mask) 551 { 552 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 553 554 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 555 if (mclk_mask) 556 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 557 558 if (fclk_mask) 559 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 560 561 if (soc_mask) 562 *soc_mask = 0; 563 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 564 if (mclk_mask) 565 *mclk_mask = 0; 566 567 if (fclk_mask) 568 *fclk_mask = 0; 569 570 if (soc_mask) 571 *soc_mask = 1; 572 573 if (vclk_mask) 574 *vclk_mask = 1; 575 576 if (dclk_mask) 577 *dclk_mask = 1; 578 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 579 if (mclk_mask) 580 *mclk_mask = 0; 581 582 if (fclk_mask) 583 *fclk_mask = 0; 584 585 if (soc_mask) 586 *soc_mask = 1; 587 588 if (vclk_mask) 589 *vclk_mask = 1; 590 591 if (dclk_mask) 592 *dclk_mask = 1; 593 } 594 595 return 0; 596 } 597 598 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 599 enum smu_clk_type clk_type) 600 { 601 enum smu_feature_mask feature_id = 0; 602 603 switch (clk_type) { 604 case SMU_MCLK: 605 case SMU_UCLK: 606 case SMU_FCLK: 607 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 608 break; 609 case SMU_GFXCLK: 610 case SMU_SCLK: 611 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 612 break; 613 case SMU_SOCCLK: 614 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 615 break; 616 case SMU_VCLK: 617 case SMU_DCLK: 618 feature_id = SMU_FEATURE_VCN_DPM_BIT; 619 break; 620 default: 621 return true; 622 } 623 624 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 625 return false; 626 627 return true; 628 } 629 630 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 631 enum smu_clk_type clk_type, 632 uint32_t *min, 633 uint32_t *max) 634 { 635 int ret = 0; 636 uint32_t soc_mask; 637 uint32_t vclk_mask; 638 uint32_t dclk_mask; 639 uint32_t mclk_mask; 640 uint32_t fclk_mask; 641 uint32_t clock_limit; 642 643 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 644 switch (clk_type) { 645 case SMU_MCLK: 646 case SMU_UCLK: 647 clock_limit = smu->smu_table.boot_values.uclk; 648 break; 649 case SMU_FCLK: 650 clock_limit = smu->smu_table.boot_values.fclk; 651 break; 652 case SMU_GFXCLK: 653 case SMU_SCLK: 654 clock_limit = smu->smu_table.boot_values.gfxclk; 655 break; 656 case SMU_SOCCLK: 657 clock_limit = smu->smu_table.boot_values.socclk; 658 break; 659 case SMU_VCLK: 660 clock_limit = smu->smu_table.boot_values.vclk; 661 break; 662 case SMU_DCLK: 663 clock_limit = smu->smu_table.boot_values.dclk; 664 break; 665 default: 666 clock_limit = 0; 667 break; 668 } 669 670 /* clock in Mhz unit */ 671 if (min) 672 *min = clock_limit / 100; 673 if (max) 674 *max = clock_limit / 100; 675 676 return 0; 677 } 678 if (max) { 679 ret = vangogh_get_profiling_clk_mask(smu, 680 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 681 &vclk_mask, 682 &dclk_mask, 683 &mclk_mask, 684 &fclk_mask, 685 &soc_mask); 686 if (ret) 687 goto failed; 688 689 switch (clk_type) { 690 case SMU_UCLK: 691 case SMU_MCLK: 692 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 693 if (ret) 694 goto failed; 695 break; 696 case SMU_SOCCLK: 697 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 698 if (ret) 699 goto failed; 700 break; 701 case SMU_FCLK: 702 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 703 if (ret) 704 goto failed; 705 break; 706 case SMU_VCLK: 707 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 708 if (ret) 709 goto failed; 710 break; 711 case SMU_DCLK: 712 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 713 if (ret) 714 goto failed; 715 break; 716 default: 717 ret = -EINVAL; 718 goto failed; 719 } 720 } 721 if (min) { 722 switch (clk_type) { 723 case SMU_UCLK: 724 case SMU_MCLK: 725 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 726 if (ret) 727 goto failed; 728 break; 729 case SMU_SOCCLK: 730 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 731 if (ret) 732 goto failed; 733 break; 734 case SMU_FCLK: 735 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 736 if (ret) 737 goto failed; 738 break; 739 case SMU_VCLK: 740 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 741 if (ret) 742 goto failed; 743 break; 744 case SMU_DCLK: 745 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 746 if (ret) 747 goto failed; 748 break; 749 default: 750 ret = -EINVAL; 751 goto failed; 752 } 753 } 754 failed: 755 return ret; 756 } 757 758 static int vangogh_get_power_profile_mode(struct smu_context *smu, 759 char *buf) 760 { 761 static const char *profile_name[] = { 762 "BOOTUP_DEFAULT", 763 "3D_FULL_SCREEN", 764 "POWER_SAVING", 765 "VIDEO", 766 "VR", 767 "COMPUTE", 768 "CUSTOM"}; 769 uint32_t i, size = 0; 770 int16_t workload_type = 0; 771 772 if (!buf) 773 return -EINVAL; 774 775 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 776 /* 777 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 778 * Not all profile modes are supported on vangogh. 779 */ 780 workload_type = smu_cmn_to_asic_specific_index(smu, 781 CMN2ASIC_MAPPING_WORKLOAD, 782 i); 783 784 if (workload_type < 0) 785 continue; 786 787 size += sprintf(buf + size, "%2d %14s%s\n", 788 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 789 } 790 791 return size; 792 } 793 794 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 795 { 796 int workload_type, ret; 797 uint32_t profile_mode = input[size]; 798 799 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 800 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 801 return -EINVAL; 802 } 803 804 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 805 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 806 return 0; 807 808 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 809 workload_type = smu_cmn_to_asic_specific_index(smu, 810 CMN2ASIC_MAPPING_WORKLOAD, 811 profile_mode); 812 if (workload_type < 0) { 813 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 814 profile_mode); 815 return -EINVAL; 816 } 817 818 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 819 1 << workload_type, 820 NULL); 821 if (ret) { 822 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 823 workload_type); 824 return ret; 825 } 826 827 smu->power_profile_mode = profile_mode; 828 829 return 0; 830 } 831 832 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 833 enum smu_clk_type clk_type, 834 uint32_t min, 835 uint32_t max) 836 { 837 int ret = 0; 838 839 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 840 return 0; 841 842 switch (clk_type) { 843 case SMU_GFXCLK: 844 case SMU_SCLK: 845 ret = smu_cmn_send_smc_msg_with_param(smu, 846 SMU_MSG_SetHardMinGfxClk, 847 min, NULL); 848 if (ret) 849 return ret; 850 851 ret = smu_cmn_send_smc_msg_with_param(smu, 852 SMU_MSG_SetSoftMaxGfxClk, 853 max, NULL); 854 if (ret) 855 return ret; 856 break; 857 case SMU_FCLK: 858 case SMU_MCLK: 859 ret = smu_cmn_send_smc_msg_with_param(smu, 860 SMU_MSG_SetHardMinFclkByFreq, 861 min, NULL); 862 if (ret) 863 return ret; 864 865 ret = smu_cmn_send_smc_msg_with_param(smu, 866 SMU_MSG_SetSoftMaxFclkByFreq, 867 max, NULL); 868 if (ret) 869 return ret; 870 break; 871 case SMU_SOCCLK: 872 ret = smu_cmn_send_smc_msg_with_param(smu, 873 SMU_MSG_SetHardMinSocclkByFreq, 874 min, NULL); 875 if (ret) 876 return ret; 877 878 ret = smu_cmn_send_smc_msg_with_param(smu, 879 SMU_MSG_SetSoftMaxSocclkByFreq, 880 max, NULL); 881 if (ret) 882 return ret; 883 break; 884 case SMU_VCLK: 885 ret = smu_cmn_send_smc_msg_with_param(smu, 886 SMU_MSG_SetHardMinVcn, 887 min << 16, NULL); 888 if (ret) 889 return ret; 890 ret = smu_cmn_send_smc_msg_with_param(smu, 891 SMU_MSG_SetSoftMaxVcn, 892 max << 16, NULL); 893 if (ret) 894 return ret; 895 break; 896 case SMU_DCLK: 897 ret = smu_cmn_send_smc_msg_with_param(smu, 898 SMU_MSG_SetHardMinVcn, 899 min, NULL); 900 if (ret) 901 return ret; 902 ret = smu_cmn_send_smc_msg_with_param(smu, 903 SMU_MSG_SetSoftMaxVcn, 904 max, NULL); 905 if (ret) 906 return ret; 907 break; 908 default: 909 return -EINVAL; 910 } 911 912 return ret; 913 } 914 915 static int vangogh_force_clk_levels(struct smu_context *smu, 916 enum smu_clk_type clk_type, uint32_t mask) 917 { 918 uint32_t soft_min_level = 0, soft_max_level = 0; 919 uint32_t min_freq = 0, max_freq = 0; 920 int ret = 0 ; 921 922 soft_min_level = mask ? (ffs(mask) - 1) : 0; 923 soft_max_level = mask ? (fls(mask) - 1) : 0; 924 925 switch (clk_type) { 926 case SMU_SOCCLK: 927 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 928 soft_min_level, &min_freq); 929 if (ret) 930 return ret; 931 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 932 soft_max_level, &max_freq); 933 if (ret) 934 return ret; 935 ret = smu_cmn_send_smc_msg_with_param(smu, 936 SMU_MSG_SetSoftMaxSocclkByFreq, 937 max_freq, NULL); 938 if (ret) 939 return ret; 940 ret = smu_cmn_send_smc_msg_with_param(smu, 941 SMU_MSG_SetHardMinSocclkByFreq, 942 min_freq, NULL); 943 if (ret) 944 return ret; 945 break; 946 case SMU_MCLK: 947 case SMU_FCLK: 948 ret = vangogh_get_dpm_clk_limited(smu, 949 clk_type, soft_min_level, &min_freq); 950 if (ret) 951 return ret; 952 ret = vangogh_get_dpm_clk_limited(smu, 953 clk_type, soft_max_level, &max_freq); 954 if (ret) 955 return ret; 956 ret = smu_cmn_send_smc_msg_with_param(smu, 957 SMU_MSG_SetSoftMaxFclkByFreq, 958 max_freq, NULL); 959 if (ret) 960 return ret; 961 ret = smu_cmn_send_smc_msg_with_param(smu, 962 SMU_MSG_SetHardMinFclkByFreq, 963 min_freq, NULL); 964 if (ret) 965 return ret; 966 break; 967 case SMU_VCLK: 968 ret = vangogh_get_dpm_clk_limited(smu, 969 clk_type, soft_min_level, &min_freq); 970 if (ret) 971 return ret; 972 973 ret = vangogh_get_dpm_clk_limited(smu, 974 clk_type, soft_max_level, &max_freq); 975 if (ret) 976 return ret; 977 978 979 ret = smu_cmn_send_smc_msg_with_param(smu, 980 SMU_MSG_SetHardMinVcn, 981 min_freq << 16, NULL); 982 if (ret) 983 return ret; 984 985 ret = smu_cmn_send_smc_msg_with_param(smu, 986 SMU_MSG_SetSoftMaxVcn, 987 max_freq << 16, NULL); 988 if (ret) 989 return ret; 990 991 break; 992 case SMU_DCLK: 993 ret = vangogh_get_dpm_clk_limited(smu, 994 clk_type, soft_min_level, &min_freq); 995 if (ret) 996 return ret; 997 998 ret = vangogh_get_dpm_clk_limited(smu, 999 clk_type, soft_max_level, &max_freq); 1000 if (ret) 1001 return ret; 1002 1003 ret = smu_cmn_send_smc_msg_with_param(smu, 1004 SMU_MSG_SetHardMinVcn, 1005 min_freq, NULL); 1006 if (ret) 1007 return ret; 1008 1009 ret = smu_cmn_send_smc_msg_with_param(smu, 1010 SMU_MSG_SetSoftMaxVcn, 1011 max_freq, NULL); 1012 if (ret) 1013 return ret; 1014 1015 break; 1016 default: 1017 break; 1018 } 1019 1020 return ret; 1021 } 1022 1023 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1024 { 1025 int ret = 0, i = 0; 1026 uint32_t min_freq, max_freq, force_freq; 1027 enum smu_clk_type clk_type; 1028 1029 enum smu_clk_type clks[] = { 1030 SMU_SOCCLK, 1031 SMU_VCLK, 1032 SMU_DCLK, 1033 SMU_MCLK, 1034 SMU_FCLK, 1035 }; 1036 1037 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1038 clk_type = clks[i]; 1039 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1040 if (ret) 1041 return ret; 1042 1043 force_freq = highest ? max_freq : min_freq; 1044 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1045 if (ret) 1046 return ret; 1047 } 1048 1049 return ret; 1050 } 1051 1052 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1053 { 1054 int ret = 0, i = 0; 1055 uint32_t min_freq, max_freq; 1056 enum smu_clk_type clk_type; 1057 1058 struct clk_feature_map { 1059 enum smu_clk_type clk_type; 1060 uint32_t feature; 1061 } clk_feature_map[] = { 1062 {SMU_MCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1063 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1064 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1065 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1066 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1067 }; 1068 1069 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1070 1071 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1072 continue; 1073 1074 clk_type = clk_feature_map[i].clk_type; 1075 1076 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1077 1078 if (ret) 1079 return ret; 1080 1081 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1082 1083 if (ret) 1084 return ret; 1085 } 1086 1087 return ret; 1088 } 1089 1090 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1091 { 1092 int ret = 0; 1093 uint32_t socclk_freq = 0, fclk_freq = 0; 1094 uint32_t vclk_freq = 0, dclk_freq = 0; 1095 1096 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1097 if (ret) 1098 return ret; 1099 1100 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1101 if (ret) 1102 return ret; 1103 1104 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1105 if (ret) 1106 return ret; 1107 1108 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1109 if (ret) 1110 return ret; 1111 1112 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1113 if (ret) 1114 return ret; 1115 1116 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1117 if (ret) 1118 return ret; 1119 1120 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1121 if (ret) 1122 return ret; 1123 1124 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1125 if (ret) 1126 return ret; 1127 1128 return ret; 1129 } 1130 1131 static int vangogh_set_performance_level(struct smu_context *smu, 1132 enum amd_dpm_forced_level level) 1133 { 1134 int ret = 0; 1135 uint32_t soc_mask, mclk_mask, fclk_mask; 1136 uint32_t vclk_mask = 0, dclk_mask = 0; 1137 1138 switch (level) { 1139 case AMD_DPM_FORCED_LEVEL_HIGH: 1140 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1141 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1142 1143 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1144 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1145 1146 ret = vangogh_force_dpm_limit_value(smu, true); 1147 break; 1148 case AMD_DPM_FORCED_LEVEL_LOW: 1149 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1150 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1151 1152 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1153 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1154 1155 ret = vangogh_force_dpm_limit_value(smu, false); 1156 break; 1157 case AMD_DPM_FORCED_LEVEL_AUTO: 1158 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1159 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1160 1161 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1162 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1163 1164 ret = vangogh_unforce_dpm_levels(smu); 1165 break; 1166 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1167 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1168 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1169 1170 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1171 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1172 1173 ret = smu_cmn_send_smc_msg_with_param(smu, 1174 SMU_MSG_SetHardMinGfxClk, 1175 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1176 if (ret) 1177 return ret; 1178 1179 ret = smu_cmn_send_smc_msg_with_param(smu, 1180 SMU_MSG_SetSoftMaxGfxClk, 1181 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1182 if (ret) 1183 return ret; 1184 1185 ret = vangogh_get_profiling_clk_mask(smu, level, 1186 &vclk_mask, 1187 &dclk_mask, 1188 &mclk_mask, 1189 &fclk_mask, 1190 &soc_mask); 1191 if (ret) 1192 return ret; 1193 1194 vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 1195 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1196 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1197 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1198 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1199 1200 break; 1201 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1202 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1203 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1204 1205 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1206 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1207 1208 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, 1209 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1210 if (ret) 1211 return ret; 1212 1213 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, 1214 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1215 if (ret) 1216 return ret; 1217 break; 1218 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1219 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1220 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1221 1222 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1223 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1224 1225 ret = vangogh_get_profiling_clk_mask(smu, level, 1226 NULL, 1227 NULL, 1228 &mclk_mask, 1229 &fclk_mask, 1230 NULL); 1231 if (ret) 1232 return ret; 1233 1234 vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 1235 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1236 break; 1237 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1238 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1239 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1240 1241 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1242 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1243 1244 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1245 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1246 if (ret) 1247 return ret; 1248 1249 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1250 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1251 if (ret) 1252 return ret; 1253 1254 ret = vangogh_set_peak_clock_by_device(smu); 1255 break; 1256 case AMD_DPM_FORCED_LEVEL_MANUAL: 1257 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1258 default: 1259 break; 1260 } 1261 return ret; 1262 } 1263 1264 static int vangogh_read_sensor(struct smu_context *smu, 1265 enum amd_pp_sensors sensor, 1266 void *data, uint32_t *size) 1267 { 1268 int ret = 0; 1269 1270 if (!data || !size) 1271 return -EINVAL; 1272 1273 mutex_lock(&smu->sensor_lock); 1274 switch (sensor) { 1275 case AMDGPU_PP_SENSOR_GPU_LOAD: 1276 ret = vangogh_get_smu_metrics_data(smu, 1277 METRICS_AVERAGE_GFXACTIVITY, 1278 (uint32_t *)data); 1279 *size = 4; 1280 break; 1281 case AMDGPU_PP_SENSOR_GPU_POWER: 1282 ret = vangogh_get_smu_metrics_data(smu, 1283 METRICS_AVERAGE_SOCKETPOWER, 1284 (uint32_t *)data); 1285 *size = 4; 1286 break; 1287 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1288 ret = vangogh_get_smu_metrics_data(smu, 1289 METRICS_TEMPERATURE_EDGE, 1290 (uint32_t *)data); 1291 *size = 4; 1292 break; 1293 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1294 ret = vangogh_get_smu_metrics_data(smu, 1295 METRICS_TEMPERATURE_HOTSPOT, 1296 (uint32_t *)data); 1297 *size = 4; 1298 break; 1299 case AMDGPU_PP_SENSOR_GFX_MCLK: 1300 ret = vangogh_get_smu_metrics_data(smu, 1301 METRICS_AVERAGE_UCLK, 1302 (uint32_t *)data); 1303 *(uint32_t *)data *= 100; 1304 *size = 4; 1305 break; 1306 case AMDGPU_PP_SENSOR_GFX_SCLK: 1307 ret = vangogh_get_smu_metrics_data(smu, 1308 METRICS_AVERAGE_GFXCLK, 1309 (uint32_t *)data); 1310 *(uint32_t *)data *= 100; 1311 *size = 4; 1312 break; 1313 case AMDGPU_PP_SENSOR_VDDGFX: 1314 ret = vangogh_get_smu_metrics_data(smu, 1315 METRICS_VOLTAGE_VDDGFX, 1316 (uint32_t *)data); 1317 *size = 4; 1318 break; 1319 case AMDGPU_PP_SENSOR_VDDNB: 1320 ret = vangogh_get_smu_metrics_data(smu, 1321 METRICS_VOLTAGE_VDDSOC, 1322 (uint32_t *)data); 1323 *size = 4; 1324 break; 1325 case AMDGPU_PP_SENSOR_CPU_CLK: 1326 ret = vangogh_get_smu_metrics_data(smu, 1327 METRICS_AVERAGE_CPUCLK, 1328 (uint32_t *)data); 1329 *size = smu->cpu_core_num * sizeof(uint16_t); 1330 break; 1331 default: 1332 ret = -EOPNOTSUPP; 1333 break; 1334 } 1335 mutex_unlock(&smu->sensor_lock); 1336 1337 return ret; 1338 } 1339 1340 static int vangogh_set_watermarks_table(struct smu_context *smu, 1341 struct pp_smu_wm_range_sets *clock_ranges) 1342 { 1343 int i; 1344 int ret = 0; 1345 Watermarks_t *table = smu->smu_table.watermarks_table; 1346 1347 if (!table || !clock_ranges) 1348 return -EINVAL; 1349 1350 if (clock_ranges) { 1351 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1352 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1353 return -EINVAL; 1354 1355 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1356 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1357 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1358 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1359 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1360 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1361 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1362 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1363 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1364 1365 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1366 clock_ranges->reader_wm_sets[i].wm_inst; 1367 } 1368 1369 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1370 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1371 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1372 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1373 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1374 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1375 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1376 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1377 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1378 1379 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1380 clock_ranges->writer_wm_sets[i].wm_inst; 1381 } 1382 1383 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1384 } 1385 1386 /* pass data to smu controller */ 1387 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1388 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1389 ret = smu_cmn_write_watermarks_table(smu); 1390 if (ret) { 1391 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1392 return ret; 1393 } 1394 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1395 } 1396 1397 return 0; 1398 } 1399 1400 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1401 void **table) 1402 { 1403 struct smu_table_context *smu_table = &smu->smu_table; 1404 struct gpu_metrics_v2_0 *gpu_metrics = 1405 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; 1406 SmuMetrics_t metrics; 1407 int ret = 0; 1408 1409 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1410 if (ret) 1411 return ret; 1412 1413 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 0); 1414 1415 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1416 gpu_metrics->temperature_soc = metrics.SocTemperature; 1417 memcpy(&gpu_metrics->temperature_core[0], 1418 &metrics.CoreTemperature[0], 1419 sizeof(uint16_t) * 8); 1420 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1421 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1422 1423 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1424 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1425 1426 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1427 gpu_metrics->average_cpu_power = metrics.Power[0]; 1428 gpu_metrics->average_soc_power = metrics.Power[1]; 1429 gpu_metrics->average_gfx_power = metrics.Power[2]; 1430 memcpy(&gpu_metrics->average_core_power[0], 1431 &metrics.CorePower[0], 1432 sizeof(uint16_t) * 8); 1433 1434 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1435 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1436 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1437 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1438 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1439 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1440 1441 memcpy(&gpu_metrics->current_coreclk[0], 1442 &metrics.CoreFrequency[0], 1443 sizeof(uint16_t) * 8); 1444 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1445 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1446 1447 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1448 1449 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1450 1451 *table = (void *)gpu_metrics; 1452 1453 return sizeof(struct gpu_metrics_v2_0); 1454 } 1455 1456 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1457 long input[], uint32_t size) 1458 { 1459 int ret = 0; 1460 int i; 1461 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1462 1463 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 1464 dev_warn(smu->adev->dev, 1465 "pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); 1466 return -EINVAL; 1467 } 1468 1469 switch (type) { 1470 case PP_OD_EDIT_CCLK_VDDC_TABLE: 1471 if (size != 3) { 1472 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 1473 return -EINVAL; 1474 } 1475 if (input[0] >= smu->cpu_core_num) { 1476 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 1477 smu->cpu_core_num); 1478 } 1479 smu->cpu_core_id_select = input[0]; 1480 if (input[1] == 0) { 1481 if (input[2] < smu->cpu_default_soft_min_freq) { 1482 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1483 input[2], smu->cpu_default_soft_min_freq); 1484 return -EINVAL; 1485 } 1486 smu->cpu_actual_soft_min_freq = input[2]; 1487 } else if (input[1] == 1) { 1488 if (input[2] > smu->cpu_default_soft_max_freq) { 1489 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1490 input[2], smu->cpu_default_soft_max_freq); 1491 return -EINVAL; 1492 } 1493 smu->cpu_actual_soft_max_freq = input[2]; 1494 } else { 1495 return -EINVAL; 1496 } 1497 break; 1498 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1499 if (size != 2) { 1500 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1501 return -EINVAL; 1502 } 1503 1504 if (input[0] == 0) { 1505 if (input[1] < smu->gfx_default_hard_min_freq) { 1506 dev_warn(smu->adev->dev, 1507 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1508 input[1], smu->gfx_default_hard_min_freq); 1509 return -EINVAL; 1510 } 1511 smu->gfx_actual_hard_min_freq = input[1]; 1512 } else if (input[0] == 1) { 1513 if (input[1] > smu->gfx_default_soft_max_freq) { 1514 dev_warn(smu->adev->dev, 1515 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1516 input[1], smu->gfx_default_soft_max_freq); 1517 return -EINVAL; 1518 } 1519 smu->gfx_actual_soft_max_freq = input[1]; 1520 } else { 1521 return -EINVAL; 1522 } 1523 break; 1524 case PP_OD_RESTORE_DEFAULT_TABLE: 1525 if (size != 0) { 1526 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1527 return -EINVAL; 1528 } else { 1529 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1530 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1531 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1532 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1533 1534 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1535 smu->gfx_actual_hard_min_freq, NULL); 1536 if (ret) { 1537 dev_err(smu->adev->dev, "Restore the default hard min sclk failed!"); 1538 return ret; 1539 } 1540 1541 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1542 smu->gfx_actual_soft_max_freq, NULL); 1543 if (ret) { 1544 dev_err(smu->adev->dev, "Restore the default soft max sclk failed!"); 1545 return ret; 1546 } 1547 1548 if (smu->adev->pm.fw_version < 0x43f1b00) { 1549 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 1550 break; 1551 } 1552 1553 for (i = 0; i < smu->cpu_core_num; i++) { 1554 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1555 (i << 20) | smu->cpu_actual_soft_min_freq, 1556 NULL); 1557 if (ret) { 1558 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 1559 return ret; 1560 } 1561 1562 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1563 (i << 20) | smu->cpu_actual_soft_max_freq, 1564 NULL); 1565 if (ret) { 1566 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 1567 return ret; 1568 } 1569 } 1570 } 1571 break; 1572 case PP_OD_COMMIT_DPM_TABLE: 1573 if (size != 0) { 1574 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1575 return -EINVAL; 1576 } else { 1577 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1578 dev_err(smu->adev->dev, 1579 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1580 smu->gfx_actual_hard_min_freq, 1581 smu->gfx_actual_soft_max_freq); 1582 return -EINVAL; 1583 } 1584 1585 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1586 smu->gfx_actual_hard_min_freq, NULL); 1587 if (ret) { 1588 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1589 return ret; 1590 } 1591 1592 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1593 smu->gfx_actual_soft_max_freq, NULL); 1594 if (ret) { 1595 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1596 return ret; 1597 } 1598 1599 if (smu->adev->pm.fw_version < 0x43f1b00) { 1600 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 1601 break; 1602 } 1603 1604 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1605 ((smu->cpu_core_id_select << 20) 1606 | smu->cpu_actual_soft_min_freq), 1607 NULL); 1608 if (ret) { 1609 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 1610 return ret; 1611 } 1612 1613 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1614 ((smu->cpu_core_id_select << 20) 1615 | smu->cpu_actual_soft_max_freq), 1616 NULL); 1617 if (ret) { 1618 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 1619 return ret; 1620 } 1621 } 1622 break; 1623 default: 1624 return -ENOSYS; 1625 } 1626 1627 return ret; 1628 } 1629 1630 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 1631 { 1632 struct smu_table_context *smu_table = &smu->smu_table; 1633 1634 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 1635 } 1636 1637 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1638 { 1639 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1640 1641 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1642 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1643 smu->gfx_actual_hard_min_freq = 0; 1644 smu->gfx_actual_soft_max_freq = 0; 1645 1646 smu->cpu_default_soft_min_freq = 1400; 1647 smu->cpu_default_soft_max_freq = 3500; 1648 smu->cpu_actual_soft_min_freq = 0; 1649 smu->cpu_actual_soft_max_freq = 0; 1650 1651 return 0; 1652 } 1653 1654 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 1655 { 1656 DpmClocks_t *table = smu->smu_table.clocks_table; 1657 int i; 1658 1659 if (!clock_table || !table) 1660 return -EINVAL; 1661 1662 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 1663 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 1664 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 1665 } 1666 1667 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1668 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 1669 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 1670 } 1671 1672 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1673 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 1674 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 1675 } 1676 1677 return 0; 1678 } 1679 1680 1681 static int vangogh_system_features_control(struct smu_context *smu, bool en) 1682 { 1683 struct amdgpu_device *adev = smu->adev; 1684 struct smu_feature *feature = &smu->smu_feature; 1685 uint32_t feature_mask[2]; 1686 int ret = 0; 1687 1688 if (adev->pm.fw_version >= 0x43f1700 && !en) 1689 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 1690 RLC_STATUS_OFF, NULL); 1691 1692 bitmap_zero(feature->enabled, feature->feature_num); 1693 bitmap_zero(feature->supported, feature->feature_num); 1694 1695 if (!en) 1696 return ret; 1697 1698 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 1699 if (ret) 1700 return ret; 1701 1702 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, 1703 feature->feature_num); 1704 bitmap_copy(feature->supported, (unsigned long *)&feature_mask, 1705 feature->feature_num); 1706 1707 return 0; 1708 } 1709 1710 static int vangogh_post_smu_init(struct smu_context *smu) 1711 { 1712 struct amdgpu_device *adev = smu->adev; 1713 uint32_t tmp; 1714 int ret = 0; 1715 uint8_t aon_bits = 0; 1716 /* Two CUs in one WGP */ 1717 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 1718 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 1719 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1720 1721 /* allow message will be sent after enable message on Vangogh*/ 1722 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 1723 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 1724 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 1725 if (ret) { 1726 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 1727 return ret; 1728 } 1729 } else { 1730 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1731 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 1732 } 1733 1734 /* if all CUs are active, no need to power off any WGPs */ 1735 if (total_cu == adev->gfx.cu_info.number) 1736 return 0; 1737 1738 /* 1739 * Calculate the total bits number of always on WGPs for all SA/SEs in 1740 * RLC_PG_ALWAYS_ON_WGP_MASK. 1741 */ 1742 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 1743 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 1744 1745 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1746 1747 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 1748 if (aon_bits > req_active_wgps) { 1749 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 1750 return 0; 1751 } else { 1752 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 1753 } 1754 } 1755 1756 static int vangogh_mode_reset(struct smu_context *smu, int type) 1757 { 1758 int ret = 0, index = 0; 1759 1760 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1761 SMU_MSG_GfxDeviceDriverReset); 1762 if (index < 0) 1763 return index == -EACCES ? 0 : index; 1764 1765 mutex_lock(&smu->message_lock); 1766 1767 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 1768 1769 mutex_unlock(&smu->message_lock); 1770 1771 mdelay(10); 1772 1773 return ret; 1774 } 1775 1776 static int vangogh_mode2_reset(struct smu_context *smu) 1777 { 1778 return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 1779 } 1780 1781 static int vangogh_get_power_limit(struct smu_context *smu) 1782 { 1783 struct smu_11_5_power_context *power_context = 1784 smu->smu_power.power_context; 1785 uint32_t ppt_limit; 1786 int ret = 0; 1787 1788 if (smu->adev->pm.fw_version < 0x43f1e00) 1789 return ret; 1790 1791 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 1792 if (ret) { 1793 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 1794 return ret; 1795 } 1796 /* convert from milliwatt to watt */ 1797 smu->current_power_limit = ppt_limit / 1000; 1798 smu->max_power_limit = 29; 1799 1800 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 1801 if (ret) { 1802 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 1803 return ret; 1804 } 1805 /* convert from milliwatt to watt */ 1806 power_context->current_fast_ppt_limit = ppt_limit / 1000; 1807 power_context->max_fast_ppt_limit = 30; 1808 1809 return ret; 1810 } 1811 1812 static int vangogh_get_ppt_limit(struct smu_context *smu, 1813 uint32_t *ppt_limit, 1814 enum smu_ppt_limit_type type, 1815 enum smu_ppt_limit_level level) 1816 { 1817 struct smu_11_5_power_context *power_context = 1818 smu->smu_power.power_context; 1819 1820 if (!power_context) 1821 return -EOPNOTSUPP; 1822 1823 if (type == SMU_FAST_PPT_LIMIT) { 1824 switch (level) { 1825 case SMU_PPT_LIMIT_MAX: 1826 *ppt_limit = power_context->max_fast_ppt_limit; 1827 break; 1828 case SMU_PPT_LIMIT_CURRENT: 1829 *ppt_limit = power_context->current_fast_ppt_limit; 1830 break; 1831 default: 1832 break; 1833 } 1834 } 1835 1836 return 0; 1837 } 1838 1839 static int vangogh_set_power_limit(struct smu_context *smu, uint32_t ppt_limit) 1840 { 1841 struct smu_11_5_power_context *power_context = 1842 smu->smu_power.power_context; 1843 uint32_t limit_type = ppt_limit >> 24; 1844 int ret = 0; 1845 1846 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1847 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 1848 return -EOPNOTSUPP; 1849 } 1850 1851 switch (limit_type) { 1852 case SMU_DEFAULT_PPT_LIMIT: 1853 ret = smu_cmn_send_smc_msg_with_param(smu, 1854 SMU_MSG_SetSlowPPTLimit, 1855 ppt_limit * 1000, /* convert from watt to milliwatt */ 1856 NULL); 1857 if (ret) 1858 return ret; 1859 1860 smu->current_power_limit = ppt_limit; 1861 break; 1862 case SMU_FAST_PPT_LIMIT: 1863 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 1864 if (ppt_limit > power_context->max_fast_ppt_limit) { 1865 dev_err(smu->adev->dev, 1866 "New power limit (%d) is over the max allowed %d\n", 1867 ppt_limit, power_context->max_fast_ppt_limit); 1868 return ret; 1869 } 1870 1871 ret = smu_cmn_send_smc_msg_with_param(smu, 1872 SMU_MSG_SetFastPPTLimit, 1873 ppt_limit * 1000, /* convert from watt to milliwatt */ 1874 NULL); 1875 if (ret) 1876 return ret; 1877 1878 power_context->current_fast_ppt_limit = ppt_limit; 1879 break; 1880 default: 1881 return -EINVAL; 1882 } 1883 1884 return ret; 1885 } 1886 1887 static const struct pptable_funcs vangogh_ppt_funcs = { 1888 1889 .check_fw_status = smu_v11_0_check_fw_status, 1890 .check_fw_version = smu_v11_0_check_fw_version, 1891 .init_smc_tables = vangogh_init_smc_tables, 1892 .fini_smc_tables = smu_v11_0_fini_smc_tables, 1893 .init_power = smu_v11_0_init_power, 1894 .fini_power = smu_v11_0_fini_power, 1895 .register_irq_handler = smu_v11_0_register_irq_handler, 1896 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 1897 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1898 .send_smc_msg = smu_cmn_send_smc_msg, 1899 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 1900 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 1901 .is_dpm_running = vangogh_is_dpm_running, 1902 .read_sensor = vangogh_read_sensor, 1903 .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask, 1904 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1905 .set_watermarks_table = vangogh_set_watermarks_table, 1906 .set_driver_table_location = smu_v11_0_set_driver_table_location, 1907 .interrupt_work = smu_v11_0_interrupt_work, 1908 .get_gpu_metrics = vangogh_get_gpu_metrics, 1909 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 1910 .print_clk_levels = vangogh_print_fine_grain_clk, 1911 .set_default_dpm_table = vangogh_set_default_dpm_tables, 1912 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 1913 .system_features_control = vangogh_system_features_control, 1914 .feature_is_enabled = smu_cmn_feature_is_enabled, 1915 .set_power_profile_mode = vangogh_set_power_profile_mode, 1916 .get_power_profile_mode = vangogh_get_power_profile_mode, 1917 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 1918 .force_clk_levels = vangogh_force_clk_levels, 1919 .set_performance_level = vangogh_set_performance_level, 1920 .post_init = vangogh_post_smu_init, 1921 .mode2_reset = vangogh_mode2_reset, 1922 .gfx_off_control = smu_v11_0_gfx_off_control, 1923 .get_ppt_limit = vangogh_get_ppt_limit, 1924 .get_power_limit = vangogh_get_power_limit, 1925 .set_power_limit = vangogh_set_power_limit, 1926 }; 1927 1928 void vangogh_set_ppt_funcs(struct smu_context *smu) 1929 { 1930 smu->ppt_funcs = &vangogh_ppt_funcs; 1931 smu->message_map = vangogh_message_map; 1932 smu->feature_map = vangogh_feature_mask_map; 1933 smu->table_map = vangogh_table_map; 1934 smu->workload_map = vangogh_workload_map; 1935 smu->is_apu = true; 1936 } 1937