1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 #include <asm/processor.h> 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 // Registers related to GFXOFF 50 // addressBlock: smuio_smuio_SmuSmuioDec 51 // base address: 0x5a000 52 #define mmSMUIO_GFX_MISC_CNTL 0x00c5 53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0 54 55 //SMUIO_GFX_MISC_CNTL 56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0 57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L 59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 64 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 65 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 66 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 67 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 68 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 69 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 70 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 71 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 72 73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 77 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 78 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 79 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 80 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 81 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 82 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 83 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 84 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 85 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 86 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 87 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 88 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 89 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 92 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 93 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 94 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 95 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 96 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 97 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 98 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 99 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 100 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 101 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 102 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 103 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 104 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 105 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 106 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 107 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 110 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 111 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 112 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 113 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 114 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 115 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 116 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 117 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 118 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 119 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 120 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 121 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 122 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 123 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 124 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 125 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 126 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 127 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 128 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 129 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 130 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 131 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 132 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 133 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 134 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 135 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 136 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 137 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 138 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 139 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 140 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 141 MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0), 142 MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0), 143 MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0), 144 }; 145 146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 147 FEA_MAP(PPT), 148 FEA_MAP(TDC), 149 FEA_MAP(THERMAL), 150 FEA_MAP(DS_GFXCLK), 151 FEA_MAP(DS_SOCCLK), 152 FEA_MAP(DS_LCLK), 153 FEA_MAP(DS_FCLK), 154 FEA_MAP(DS_MP1CLK), 155 FEA_MAP(DS_MP0CLK), 156 FEA_MAP(ATHUB_PG), 157 FEA_MAP(CCLK_DPM), 158 FEA_MAP(FAN_CONTROLLER), 159 FEA_MAP(ULV), 160 FEA_MAP(VCN_DPM), 161 FEA_MAP(LCLK_DPM), 162 FEA_MAP(SHUBCLK_DPM), 163 FEA_MAP(DCFCLK_DPM), 164 FEA_MAP(DS_DCFCLK), 165 FEA_MAP(S0I2), 166 FEA_MAP(SMU_LOW_POWER), 167 FEA_MAP(GFX_DEM), 168 FEA_MAP(PSI), 169 FEA_MAP(PROCHOT), 170 FEA_MAP(CPUOFF), 171 FEA_MAP(STAPM), 172 FEA_MAP(S0I3), 173 FEA_MAP(DF_CSTATES), 174 FEA_MAP(PERF_LIMIT), 175 FEA_MAP(CORE_DLDO), 176 FEA_MAP(RSMU_LOW_POWER), 177 FEA_MAP(SMN_LOW_POWER), 178 FEA_MAP(THM_LOW_POWER), 179 FEA_MAP(SMUIO_LOW_POWER), 180 FEA_MAP(MP1_LOW_POWER), 181 FEA_MAP(DS_VCN), 182 FEA_MAP(CPPC), 183 FEA_MAP(OS_CSTATES), 184 FEA_MAP(ISP_DPM), 185 FEA_MAP(A55_DPM), 186 FEA_MAP(CVIP_DSP_DPM), 187 FEA_MAP(MSMU_LOW_POWER), 188 FEA_MAP_REVERSE(SOCCLK), 189 FEA_MAP_REVERSE(FCLK), 190 FEA_MAP_HALF_REVERSE(GFX), 191 }; 192 193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 194 TAB_MAP_VALID(WATERMARKS), 195 TAB_MAP_VALID(SMU_METRICS), 196 TAB_MAP_VALID(CUSTOM_DPM), 197 TAB_MAP_VALID(DPMCLOCKS), 198 }; 199 200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 201 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 202 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT), 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT), 208 }; 209 210 static const uint8_t vangogh_throttler_map[] = { 211 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), 212 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), 213 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), 214 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), 215 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), 216 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), 217 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), 218 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), 219 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), 220 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT), 221 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT), 222 }; 223 224 static int vangogh_tables_init(struct smu_context *smu) 225 { 226 struct smu_table_context *smu_table = &smu->smu_table; 227 struct smu_table *tables = smu_table->tables; 228 uint32_t if_version; 229 uint32_t smu_version; 230 uint32_t ret = 0; 231 232 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 233 if (ret) { 234 return ret; 235 } 236 237 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 238 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 239 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 240 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 241 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 242 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 243 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 244 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 245 246 if (if_version < 0x3) { 247 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t), 248 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 249 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL); 250 } else { 251 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 252 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 253 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 254 } 255 if (!smu_table->metrics_table) 256 goto err0_out; 257 smu_table->metrics_time = 0; 258 259 if (smu_version >= 0x043F3E00) 260 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_3); 261 else 262 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); 263 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 264 if (!smu_table->gpu_metrics_table) 265 goto err1_out; 266 267 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 268 if (!smu_table->watermarks_table) 269 goto err2_out; 270 271 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 272 if (!smu_table->clocks_table) 273 goto err3_out; 274 275 return 0; 276 277 err3_out: 278 kfree(smu_table->watermarks_table); 279 err2_out: 280 kfree(smu_table->gpu_metrics_table); 281 err1_out: 282 kfree(smu_table->metrics_table); 283 err0_out: 284 return -ENOMEM; 285 } 286 287 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu, 288 MetricsMember_t member, 289 uint32_t *value) 290 { 291 struct smu_table_context *smu_table = &smu->smu_table; 292 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table; 293 int ret = 0; 294 295 ret = smu_cmn_get_metrics_table(smu, 296 NULL, 297 false); 298 if (ret) 299 return ret; 300 301 switch (member) { 302 case METRICS_CURR_GFXCLK: 303 *value = metrics->GfxclkFrequency; 304 break; 305 case METRICS_AVERAGE_SOCCLK: 306 *value = metrics->SocclkFrequency; 307 break; 308 case METRICS_AVERAGE_VCLK: 309 *value = metrics->VclkFrequency; 310 break; 311 case METRICS_AVERAGE_DCLK: 312 *value = metrics->DclkFrequency; 313 break; 314 case METRICS_CURR_UCLK: 315 *value = metrics->MemclkFrequency; 316 break; 317 case METRICS_AVERAGE_GFXACTIVITY: 318 *value = metrics->GfxActivity / 100; 319 break; 320 case METRICS_AVERAGE_VCNACTIVITY: 321 *value = metrics->UvdActivity; 322 break; 323 case METRICS_AVERAGE_SOCKETPOWER: 324 *value = (metrics->CurrentSocketPower << 8) / 325 1000 ; 326 break; 327 case METRICS_TEMPERATURE_EDGE: 328 *value = metrics->GfxTemperature / 100 * 329 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 330 break; 331 case METRICS_TEMPERATURE_HOTSPOT: 332 *value = metrics->SocTemperature / 100 * 333 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 334 break; 335 case METRICS_THROTTLER_STATUS: 336 *value = metrics->ThrottlerStatus; 337 break; 338 case METRICS_VOLTAGE_VDDGFX: 339 *value = metrics->Voltage[2]; 340 break; 341 case METRICS_VOLTAGE_VDDSOC: 342 *value = metrics->Voltage[1]; 343 break; 344 case METRICS_AVERAGE_CPUCLK: 345 memcpy(value, &metrics->CoreFrequency[0], 346 smu->cpu_core_num * sizeof(uint16_t)); 347 break; 348 default: 349 *value = UINT_MAX; 350 break; 351 } 352 353 return ret; 354 } 355 356 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 357 MetricsMember_t member, 358 uint32_t *value) 359 { 360 struct smu_table_context *smu_table = &smu->smu_table; 361 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 362 int ret = 0; 363 364 ret = smu_cmn_get_metrics_table(smu, 365 NULL, 366 false); 367 if (ret) 368 return ret; 369 370 switch (member) { 371 case METRICS_CURR_GFXCLK: 372 *value = metrics->Current.GfxclkFrequency; 373 break; 374 case METRICS_AVERAGE_SOCCLK: 375 *value = metrics->Current.SocclkFrequency; 376 break; 377 case METRICS_AVERAGE_VCLK: 378 *value = metrics->Current.VclkFrequency; 379 break; 380 case METRICS_AVERAGE_DCLK: 381 *value = metrics->Current.DclkFrequency; 382 break; 383 case METRICS_CURR_UCLK: 384 *value = metrics->Current.MemclkFrequency; 385 break; 386 case METRICS_AVERAGE_GFXACTIVITY: 387 *value = metrics->Current.GfxActivity; 388 break; 389 case METRICS_AVERAGE_VCNACTIVITY: 390 *value = metrics->Current.UvdActivity; 391 break; 392 case METRICS_AVERAGE_SOCKETPOWER: 393 *value = (metrics->Average.CurrentSocketPower << 8) / 394 1000; 395 break; 396 case METRICS_CURR_SOCKETPOWER: 397 *value = (metrics->Current.CurrentSocketPower << 8) / 398 1000; 399 break; 400 case METRICS_TEMPERATURE_EDGE: 401 *value = metrics->Current.GfxTemperature / 100 * 402 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 403 break; 404 case METRICS_TEMPERATURE_HOTSPOT: 405 *value = metrics->Current.SocTemperature / 100 * 406 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 407 break; 408 case METRICS_THROTTLER_STATUS: 409 *value = metrics->Current.ThrottlerStatus; 410 break; 411 case METRICS_VOLTAGE_VDDGFX: 412 *value = metrics->Current.Voltage[2]; 413 break; 414 case METRICS_VOLTAGE_VDDSOC: 415 *value = metrics->Current.Voltage[1]; 416 break; 417 case METRICS_AVERAGE_CPUCLK: 418 memcpy(value, &metrics->Current.CoreFrequency[0], 419 smu->cpu_core_num * sizeof(uint16_t)); 420 break; 421 default: 422 *value = UINT_MAX; 423 break; 424 } 425 426 return ret; 427 } 428 429 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu, 430 MetricsMember_t member, 431 uint32_t *value) 432 { 433 struct amdgpu_device *adev = smu->adev; 434 uint32_t if_version; 435 int ret = 0; 436 437 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 438 if (ret) { 439 dev_err(adev->dev, "Failed to get smu if version!\n"); 440 return ret; 441 } 442 443 if (if_version < 0x3) 444 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value); 445 else 446 ret = vangogh_get_smu_metrics_data(smu, member, value); 447 448 return ret; 449 } 450 451 static int vangogh_allocate_dpm_context(struct smu_context *smu) 452 { 453 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 454 455 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 456 GFP_KERNEL); 457 if (!smu_dpm->dpm_context) 458 return -ENOMEM; 459 460 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 461 462 return 0; 463 } 464 465 static int vangogh_init_smc_tables(struct smu_context *smu) 466 { 467 int ret = 0; 468 469 ret = vangogh_tables_init(smu); 470 if (ret) 471 return ret; 472 473 ret = vangogh_allocate_dpm_context(smu); 474 if (ret) 475 return ret; 476 477 #ifdef CONFIG_X86 478 /* AMD x86 APU only */ 479 smu->cpu_core_num = boot_cpu_data.x86_max_cores; 480 #else 481 smu->cpu_core_num = 4; 482 #endif 483 484 return smu_v11_0_init_smc_tables(smu); 485 } 486 487 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 488 { 489 int ret = 0; 490 491 if (enable) { 492 /* vcn dpm on is a prerequisite for vcn power gate messages */ 493 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 494 if (ret) 495 return ret; 496 } else { 497 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 498 if (ret) 499 return ret; 500 } 501 502 return ret; 503 } 504 505 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 506 { 507 int ret = 0; 508 509 if (enable) { 510 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 511 if (ret) 512 return ret; 513 } else { 514 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 515 if (ret) 516 return ret; 517 } 518 519 return ret; 520 } 521 522 static bool vangogh_is_dpm_running(struct smu_context *smu) 523 { 524 struct amdgpu_device *adev = smu->adev; 525 int ret = 0; 526 uint64_t feature_enabled; 527 528 /* we need to re-init after suspend so return false */ 529 if (adev->in_suspend) 530 return false; 531 532 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 533 534 if (ret) 535 return false; 536 537 return !!(feature_enabled & SMC_DPM_FEATURE); 538 } 539 540 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 541 uint32_t dpm_level, uint32_t *freq) 542 { 543 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 544 545 if (!clk_table || clk_type >= SMU_CLK_COUNT) 546 return -EINVAL; 547 548 switch (clk_type) { 549 case SMU_SOCCLK: 550 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 551 return -EINVAL; 552 *freq = clk_table->SocClocks[dpm_level]; 553 break; 554 case SMU_VCLK: 555 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 556 return -EINVAL; 557 *freq = clk_table->VcnClocks[dpm_level].vclk; 558 break; 559 case SMU_DCLK: 560 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 561 return -EINVAL; 562 *freq = clk_table->VcnClocks[dpm_level].dclk; 563 break; 564 case SMU_UCLK: 565 case SMU_MCLK: 566 if (dpm_level >= clk_table->NumDfPstatesEnabled) 567 return -EINVAL; 568 *freq = clk_table->DfPstateTable[dpm_level].memclk; 569 570 break; 571 case SMU_FCLK: 572 if (dpm_level >= clk_table->NumDfPstatesEnabled) 573 return -EINVAL; 574 *freq = clk_table->DfPstateTable[dpm_level].fclk; 575 break; 576 default: 577 return -EINVAL; 578 } 579 580 return 0; 581 } 582 583 static int vangogh_print_legacy_clk_levels(struct smu_context *smu, 584 enum smu_clk_type clk_type, char *buf) 585 { 586 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 587 SmuMetrics_legacy_t metrics; 588 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 589 int i, idx, size = 0, ret = 0; 590 uint32_t cur_value = 0, value = 0, count = 0; 591 bool cur_value_match_level = false; 592 593 memset(&metrics, 0, sizeof(metrics)); 594 595 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 596 if (ret) 597 return ret; 598 599 smu_cmn_get_sysfs_buf(&buf, &size); 600 601 switch (clk_type) { 602 case SMU_OD_SCLK: 603 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 604 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 605 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 606 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 607 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 608 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 609 } 610 break; 611 case SMU_OD_CCLK: 612 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 613 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 614 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 615 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 616 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 617 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 618 } 619 break; 620 case SMU_OD_RANGE: 621 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 622 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 623 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 624 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 625 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 626 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 627 } 628 break; 629 case SMU_SOCCLK: 630 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 631 count = clk_table->NumSocClkLevelsEnabled; 632 cur_value = metrics.SocclkFrequency; 633 break; 634 case SMU_VCLK: 635 count = clk_table->VcnClkLevelsEnabled; 636 cur_value = metrics.VclkFrequency; 637 break; 638 case SMU_DCLK: 639 count = clk_table->VcnClkLevelsEnabled; 640 cur_value = metrics.DclkFrequency; 641 break; 642 case SMU_MCLK: 643 count = clk_table->NumDfPstatesEnabled; 644 cur_value = metrics.MemclkFrequency; 645 break; 646 case SMU_FCLK: 647 count = clk_table->NumDfPstatesEnabled; 648 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 649 if (ret) 650 return ret; 651 break; 652 default: 653 break; 654 } 655 656 switch (clk_type) { 657 case SMU_SOCCLK: 658 case SMU_VCLK: 659 case SMU_DCLK: 660 case SMU_MCLK: 661 case SMU_FCLK: 662 for (i = 0; i < count; i++) { 663 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; 664 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); 665 if (ret) 666 return ret; 667 if (!value) 668 continue; 669 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 670 cur_value == value ? "*" : ""); 671 if (cur_value == value) 672 cur_value_match_level = true; 673 } 674 675 if (!cur_value_match_level) 676 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 677 break; 678 default: 679 break; 680 } 681 682 return size; 683 } 684 685 static int vangogh_print_clk_levels(struct smu_context *smu, 686 enum smu_clk_type clk_type, char *buf) 687 { 688 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 689 SmuMetrics_t metrics; 690 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 691 int i, idx, size = 0, ret = 0; 692 uint32_t cur_value = 0, value = 0, count = 0; 693 bool cur_value_match_level = false; 694 uint32_t min, max; 695 696 memset(&metrics, 0, sizeof(metrics)); 697 698 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 699 if (ret) 700 return ret; 701 702 smu_cmn_get_sysfs_buf(&buf, &size); 703 704 switch (clk_type) { 705 case SMU_OD_SCLK: 706 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 707 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 708 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 709 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 710 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 711 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 712 } 713 break; 714 case SMU_OD_CCLK: 715 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 716 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 717 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 718 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 719 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 720 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 721 } 722 break; 723 case SMU_OD_RANGE: 724 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 725 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 726 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 727 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 728 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 729 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 730 } 731 break; 732 case SMU_SOCCLK: 733 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 734 count = clk_table->NumSocClkLevelsEnabled; 735 cur_value = metrics.Current.SocclkFrequency; 736 break; 737 case SMU_VCLK: 738 count = clk_table->VcnClkLevelsEnabled; 739 cur_value = metrics.Current.VclkFrequency; 740 break; 741 case SMU_DCLK: 742 count = clk_table->VcnClkLevelsEnabled; 743 cur_value = metrics.Current.DclkFrequency; 744 break; 745 case SMU_MCLK: 746 count = clk_table->NumDfPstatesEnabled; 747 cur_value = metrics.Current.MemclkFrequency; 748 break; 749 case SMU_FCLK: 750 count = clk_table->NumDfPstatesEnabled; 751 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 752 if (ret) 753 return ret; 754 break; 755 case SMU_GFXCLK: 756 case SMU_SCLK: 757 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value); 758 if (ret) { 759 return ret; 760 } 761 break; 762 default: 763 break; 764 } 765 766 switch (clk_type) { 767 case SMU_SOCCLK: 768 case SMU_VCLK: 769 case SMU_DCLK: 770 case SMU_MCLK: 771 case SMU_FCLK: 772 for (i = 0; i < count; i++) { 773 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; 774 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); 775 if (ret) 776 return ret; 777 if (!value) 778 continue; 779 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 780 cur_value == value ? "*" : ""); 781 if (cur_value == value) 782 cur_value_match_level = true; 783 } 784 785 if (!cur_value_match_level) 786 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 787 break; 788 case SMU_GFXCLK: 789 case SMU_SCLK: 790 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 791 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 792 if (cur_value == max) 793 i = 2; 794 else if (cur_value == min) 795 i = 0; 796 else 797 i = 1; 798 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 799 i == 0 ? "*" : ""); 800 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 801 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, 802 i == 1 ? "*" : ""); 803 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 804 i == 2 ? "*" : ""); 805 break; 806 default: 807 break; 808 } 809 810 return size; 811 } 812 813 static int vangogh_common_print_clk_levels(struct smu_context *smu, 814 enum smu_clk_type clk_type, char *buf) 815 { 816 struct amdgpu_device *adev = smu->adev; 817 uint32_t if_version; 818 int ret = 0; 819 820 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 821 if (ret) { 822 dev_err(adev->dev, "Failed to get smu if version!\n"); 823 return ret; 824 } 825 826 if (if_version < 0x3) 827 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf); 828 else 829 ret = vangogh_print_clk_levels(smu, clk_type, buf); 830 831 return ret; 832 } 833 834 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 835 enum amd_dpm_forced_level level, 836 uint32_t *vclk_mask, 837 uint32_t *dclk_mask, 838 uint32_t *mclk_mask, 839 uint32_t *fclk_mask, 840 uint32_t *soc_mask) 841 { 842 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 843 844 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 845 if (mclk_mask) 846 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 847 848 if (fclk_mask) 849 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 850 851 if (soc_mask) 852 *soc_mask = 0; 853 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 854 if (mclk_mask) 855 *mclk_mask = 0; 856 857 if (fclk_mask) 858 *fclk_mask = 0; 859 860 if (soc_mask) 861 *soc_mask = 1; 862 863 if (vclk_mask) 864 *vclk_mask = 1; 865 866 if (dclk_mask) 867 *dclk_mask = 1; 868 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 869 if (mclk_mask) 870 *mclk_mask = 0; 871 872 if (fclk_mask) 873 *fclk_mask = 0; 874 875 if (soc_mask) 876 *soc_mask = 1; 877 878 if (vclk_mask) 879 *vclk_mask = 1; 880 881 if (dclk_mask) 882 *dclk_mask = 1; 883 } 884 885 return 0; 886 } 887 888 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 889 enum smu_clk_type clk_type) 890 { 891 enum smu_feature_mask feature_id = 0; 892 893 switch (clk_type) { 894 case SMU_MCLK: 895 case SMU_UCLK: 896 case SMU_FCLK: 897 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 898 break; 899 case SMU_GFXCLK: 900 case SMU_SCLK: 901 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 902 break; 903 case SMU_SOCCLK: 904 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 905 break; 906 case SMU_VCLK: 907 case SMU_DCLK: 908 feature_id = SMU_FEATURE_VCN_DPM_BIT; 909 break; 910 default: 911 return true; 912 } 913 914 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 915 return false; 916 917 return true; 918 } 919 920 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 921 enum smu_clk_type clk_type, 922 uint32_t *min, 923 uint32_t *max) 924 { 925 int ret = 0; 926 uint32_t soc_mask; 927 uint32_t vclk_mask; 928 uint32_t dclk_mask; 929 uint32_t mclk_mask; 930 uint32_t fclk_mask; 931 uint32_t clock_limit; 932 933 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 934 switch (clk_type) { 935 case SMU_MCLK: 936 case SMU_UCLK: 937 clock_limit = smu->smu_table.boot_values.uclk; 938 break; 939 case SMU_FCLK: 940 clock_limit = smu->smu_table.boot_values.fclk; 941 break; 942 case SMU_GFXCLK: 943 case SMU_SCLK: 944 clock_limit = smu->smu_table.boot_values.gfxclk; 945 break; 946 case SMU_SOCCLK: 947 clock_limit = smu->smu_table.boot_values.socclk; 948 break; 949 case SMU_VCLK: 950 clock_limit = smu->smu_table.boot_values.vclk; 951 break; 952 case SMU_DCLK: 953 clock_limit = smu->smu_table.boot_values.dclk; 954 break; 955 default: 956 clock_limit = 0; 957 break; 958 } 959 960 /* clock in Mhz unit */ 961 if (min) 962 *min = clock_limit / 100; 963 if (max) 964 *max = clock_limit / 100; 965 966 return 0; 967 } 968 if (max) { 969 ret = vangogh_get_profiling_clk_mask(smu, 970 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 971 &vclk_mask, 972 &dclk_mask, 973 &mclk_mask, 974 &fclk_mask, 975 &soc_mask); 976 if (ret) 977 goto failed; 978 979 switch (clk_type) { 980 case SMU_UCLK: 981 case SMU_MCLK: 982 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 983 if (ret) 984 goto failed; 985 break; 986 case SMU_SOCCLK: 987 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 988 if (ret) 989 goto failed; 990 break; 991 case SMU_FCLK: 992 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 993 if (ret) 994 goto failed; 995 break; 996 case SMU_VCLK: 997 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 998 if (ret) 999 goto failed; 1000 break; 1001 case SMU_DCLK: 1002 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 1003 if (ret) 1004 goto failed; 1005 break; 1006 default: 1007 ret = -EINVAL; 1008 goto failed; 1009 } 1010 } 1011 if (min) { 1012 ret = vangogh_get_profiling_clk_mask(smu, 1013 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK, 1014 NULL, 1015 NULL, 1016 &mclk_mask, 1017 &fclk_mask, 1018 &soc_mask); 1019 if (ret) 1020 goto failed; 1021 1022 vclk_mask = dclk_mask = 0; 1023 1024 switch (clk_type) { 1025 case SMU_UCLK: 1026 case SMU_MCLK: 1027 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 1028 if (ret) 1029 goto failed; 1030 break; 1031 case SMU_SOCCLK: 1032 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 1033 if (ret) 1034 goto failed; 1035 break; 1036 case SMU_FCLK: 1037 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 1038 if (ret) 1039 goto failed; 1040 break; 1041 case SMU_VCLK: 1042 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 1043 if (ret) 1044 goto failed; 1045 break; 1046 case SMU_DCLK: 1047 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 1048 if (ret) 1049 goto failed; 1050 break; 1051 default: 1052 ret = -EINVAL; 1053 goto failed; 1054 } 1055 } 1056 failed: 1057 return ret; 1058 } 1059 1060 static int vangogh_get_power_profile_mode(struct smu_context *smu, 1061 char *buf) 1062 { 1063 uint32_t i, size = 0; 1064 int16_t workload_type = 0; 1065 1066 if (!buf) 1067 return -EINVAL; 1068 1069 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 1070 /* 1071 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1072 * Not all profile modes are supported on vangogh. 1073 */ 1074 workload_type = smu_cmn_to_asic_specific_index(smu, 1075 CMN2ASIC_MAPPING_WORKLOAD, 1076 i); 1077 1078 if (workload_type < 0) 1079 continue; 1080 1081 size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 1082 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1083 } 1084 1085 return size; 1086 } 1087 1088 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1089 { 1090 int workload_type, ret; 1091 uint32_t profile_mode = input[size]; 1092 1093 if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { 1094 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1095 return -EINVAL; 1096 } 1097 1098 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 1099 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 1100 return 0; 1101 1102 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1103 workload_type = smu_cmn_to_asic_specific_index(smu, 1104 CMN2ASIC_MAPPING_WORKLOAD, 1105 profile_mode); 1106 if (workload_type < 0) { 1107 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 1108 profile_mode); 1109 return -EINVAL; 1110 } 1111 1112 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 1113 1 << workload_type, 1114 NULL); 1115 if (ret) { 1116 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 1117 workload_type); 1118 return ret; 1119 } 1120 1121 smu->power_profile_mode = profile_mode; 1122 1123 return 0; 1124 } 1125 1126 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 1127 enum smu_clk_type clk_type, 1128 uint32_t min, 1129 uint32_t max) 1130 { 1131 int ret = 0; 1132 1133 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 1134 return 0; 1135 1136 switch (clk_type) { 1137 case SMU_GFXCLK: 1138 case SMU_SCLK: 1139 ret = smu_cmn_send_smc_msg_with_param(smu, 1140 SMU_MSG_SetHardMinGfxClk, 1141 min, NULL); 1142 if (ret) 1143 return ret; 1144 1145 ret = smu_cmn_send_smc_msg_with_param(smu, 1146 SMU_MSG_SetSoftMaxGfxClk, 1147 max, NULL); 1148 if (ret) 1149 return ret; 1150 break; 1151 case SMU_FCLK: 1152 ret = smu_cmn_send_smc_msg_with_param(smu, 1153 SMU_MSG_SetHardMinFclkByFreq, 1154 min, NULL); 1155 if (ret) 1156 return ret; 1157 1158 ret = smu_cmn_send_smc_msg_with_param(smu, 1159 SMU_MSG_SetSoftMaxFclkByFreq, 1160 max, NULL); 1161 if (ret) 1162 return ret; 1163 break; 1164 case SMU_SOCCLK: 1165 ret = smu_cmn_send_smc_msg_with_param(smu, 1166 SMU_MSG_SetHardMinSocclkByFreq, 1167 min, NULL); 1168 if (ret) 1169 return ret; 1170 1171 ret = smu_cmn_send_smc_msg_with_param(smu, 1172 SMU_MSG_SetSoftMaxSocclkByFreq, 1173 max, NULL); 1174 if (ret) 1175 return ret; 1176 break; 1177 case SMU_VCLK: 1178 ret = smu_cmn_send_smc_msg_with_param(smu, 1179 SMU_MSG_SetHardMinVcn, 1180 min << 16, NULL); 1181 if (ret) 1182 return ret; 1183 ret = smu_cmn_send_smc_msg_with_param(smu, 1184 SMU_MSG_SetSoftMaxVcn, 1185 max << 16, NULL); 1186 if (ret) 1187 return ret; 1188 break; 1189 case SMU_DCLK: 1190 ret = smu_cmn_send_smc_msg_with_param(smu, 1191 SMU_MSG_SetHardMinVcn, 1192 min, NULL); 1193 if (ret) 1194 return ret; 1195 ret = smu_cmn_send_smc_msg_with_param(smu, 1196 SMU_MSG_SetSoftMaxVcn, 1197 max, NULL); 1198 if (ret) 1199 return ret; 1200 break; 1201 default: 1202 return -EINVAL; 1203 } 1204 1205 return ret; 1206 } 1207 1208 static int vangogh_force_clk_levels(struct smu_context *smu, 1209 enum smu_clk_type clk_type, uint32_t mask) 1210 { 1211 uint32_t soft_min_level = 0, soft_max_level = 0; 1212 uint32_t min_freq = 0, max_freq = 0; 1213 int ret = 0 ; 1214 1215 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1216 soft_max_level = mask ? (fls(mask) - 1) : 0; 1217 1218 switch (clk_type) { 1219 case SMU_SOCCLK: 1220 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1221 soft_min_level, &min_freq); 1222 if (ret) 1223 return ret; 1224 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1225 soft_max_level, &max_freq); 1226 if (ret) 1227 return ret; 1228 ret = smu_cmn_send_smc_msg_with_param(smu, 1229 SMU_MSG_SetSoftMaxSocclkByFreq, 1230 max_freq, NULL); 1231 if (ret) 1232 return ret; 1233 ret = smu_cmn_send_smc_msg_with_param(smu, 1234 SMU_MSG_SetHardMinSocclkByFreq, 1235 min_freq, NULL); 1236 if (ret) 1237 return ret; 1238 break; 1239 case SMU_FCLK: 1240 ret = vangogh_get_dpm_clk_limited(smu, 1241 clk_type, soft_min_level, &min_freq); 1242 if (ret) 1243 return ret; 1244 ret = vangogh_get_dpm_clk_limited(smu, 1245 clk_type, soft_max_level, &max_freq); 1246 if (ret) 1247 return ret; 1248 ret = smu_cmn_send_smc_msg_with_param(smu, 1249 SMU_MSG_SetSoftMaxFclkByFreq, 1250 max_freq, NULL); 1251 if (ret) 1252 return ret; 1253 ret = smu_cmn_send_smc_msg_with_param(smu, 1254 SMU_MSG_SetHardMinFclkByFreq, 1255 min_freq, NULL); 1256 if (ret) 1257 return ret; 1258 break; 1259 case SMU_VCLK: 1260 ret = vangogh_get_dpm_clk_limited(smu, 1261 clk_type, soft_min_level, &min_freq); 1262 if (ret) 1263 return ret; 1264 1265 ret = vangogh_get_dpm_clk_limited(smu, 1266 clk_type, soft_max_level, &max_freq); 1267 if (ret) 1268 return ret; 1269 1270 1271 ret = smu_cmn_send_smc_msg_with_param(smu, 1272 SMU_MSG_SetHardMinVcn, 1273 min_freq << 16, NULL); 1274 if (ret) 1275 return ret; 1276 1277 ret = smu_cmn_send_smc_msg_with_param(smu, 1278 SMU_MSG_SetSoftMaxVcn, 1279 max_freq << 16, NULL); 1280 if (ret) 1281 return ret; 1282 1283 break; 1284 case SMU_DCLK: 1285 ret = vangogh_get_dpm_clk_limited(smu, 1286 clk_type, soft_min_level, &min_freq); 1287 if (ret) 1288 return ret; 1289 1290 ret = vangogh_get_dpm_clk_limited(smu, 1291 clk_type, soft_max_level, &max_freq); 1292 if (ret) 1293 return ret; 1294 1295 ret = smu_cmn_send_smc_msg_with_param(smu, 1296 SMU_MSG_SetHardMinVcn, 1297 min_freq, NULL); 1298 if (ret) 1299 return ret; 1300 1301 ret = smu_cmn_send_smc_msg_with_param(smu, 1302 SMU_MSG_SetSoftMaxVcn, 1303 max_freq, NULL); 1304 if (ret) 1305 return ret; 1306 1307 break; 1308 default: 1309 break; 1310 } 1311 1312 return ret; 1313 } 1314 1315 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1316 { 1317 int ret = 0, i = 0; 1318 uint32_t min_freq, max_freq, force_freq; 1319 enum smu_clk_type clk_type; 1320 1321 enum smu_clk_type clks[] = { 1322 SMU_SOCCLK, 1323 SMU_VCLK, 1324 SMU_DCLK, 1325 SMU_FCLK, 1326 }; 1327 1328 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1329 clk_type = clks[i]; 1330 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1331 if (ret) 1332 return ret; 1333 1334 force_freq = highest ? max_freq : min_freq; 1335 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1336 if (ret) 1337 return ret; 1338 } 1339 1340 return ret; 1341 } 1342 1343 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1344 { 1345 int ret = 0, i = 0; 1346 uint32_t min_freq, max_freq; 1347 enum smu_clk_type clk_type; 1348 1349 struct clk_feature_map { 1350 enum smu_clk_type clk_type; 1351 uint32_t feature; 1352 } clk_feature_map[] = { 1353 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1354 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1355 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1356 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1357 }; 1358 1359 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1360 1361 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1362 continue; 1363 1364 clk_type = clk_feature_map[i].clk_type; 1365 1366 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1367 1368 if (ret) 1369 return ret; 1370 1371 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1372 1373 if (ret) 1374 return ret; 1375 } 1376 1377 return ret; 1378 } 1379 1380 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1381 { 1382 int ret = 0; 1383 uint32_t socclk_freq = 0, fclk_freq = 0; 1384 uint32_t vclk_freq = 0, dclk_freq = 0; 1385 1386 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1387 if (ret) 1388 return ret; 1389 1390 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1391 if (ret) 1392 return ret; 1393 1394 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1395 if (ret) 1396 return ret; 1397 1398 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1399 if (ret) 1400 return ret; 1401 1402 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1403 if (ret) 1404 return ret; 1405 1406 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1407 if (ret) 1408 return ret; 1409 1410 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1411 if (ret) 1412 return ret; 1413 1414 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1415 if (ret) 1416 return ret; 1417 1418 return ret; 1419 } 1420 1421 static int vangogh_set_performance_level(struct smu_context *smu, 1422 enum amd_dpm_forced_level level) 1423 { 1424 int ret = 0, i; 1425 uint32_t soc_mask, mclk_mask, fclk_mask; 1426 uint32_t vclk_mask = 0, dclk_mask = 0; 1427 1428 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1429 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1430 1431 switch (level) { 1432 case AMD_DPM_FORCED_LEVEL_HIGH: 1433 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq; 1434 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1435 1436 1437 ret = vangogh_force_dpm_limit_value(smu, true); 1438 if (ret) 1439 return ret; 1440 break; 1441 case AMD_DPM_FORCED_LEVEL_LOW: 1442 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1443 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1444 1445 ret = vangogh_force_dpm_limit_value(smu, false); 1446 if (ret) 1447 return ret; 1448 break; 1449 case AMD_DPM_FORCED_LEVEL_AUTO: 1450 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1451 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1452 1453 ret = vangogh_unforce_dpm_levels(smu); 1454 if (ret) 1455 return ret; 1456 break; 1457 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1458 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1459 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1460 1461 ret = vangogh_get_profiling_clk_mask(smu, level, 1462 &vclk_mask, 1463 &dclk_mask, 1464 &mclk_mask, 1465 &fclk_mask, 1466 &soc_mask); 1467 if (ret) 1468 return ret; 1469 1470 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1471 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1472 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1473 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1474 break; 1475 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1476 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1477 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1478 break; 1479 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1480 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1481 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1482 1483 ret = vangogh_get_profiling_clk_mask(smu, level, 1484 NULL, 1485 NULL, 1486 &mclk_mask, 1487 &fclk_mask, 1488 NULL); 1489 if (ret) 1490 return ret; 1491 1492 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1493 break; 1494 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1495 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1496 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1497 1498 ret = vangogh_set_peak_clock_by_device(smu); 1499 if (ret) 1500 return ret; 1501 break; 1502 case AMD_DPM_FORCED_LEVEL_MANUAL: 1503 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1504 default: 1505 return 0; 1506 } 1507 1508 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1509 smu->gfx_actual_hard_min_freq, NULL); 1510 if (ret) 1511 return ret; 1512 1513 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1514 smu->gfx_actual_soft_max_freq, NULL); 1515 if (ret) 1516 return ret; 1517 1518 if (smu->adev->pm.fw_version >= 0x43f1b00) { 1519 for (i = 0; i < smu->cpu_core_num; i++) { 1520 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1521 ((i << 20) 1522 | smu->cpu_actual_soft_min_freq), 1523 NULL); 1524 if (ret) 1525 return ret; 1526 1527 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1528 ((i << 20) 1529 | smu->cpu_actual_soft_max_freq), 1530 NULL); 1531 if (ret) 1532 return ret; 1533 } 1534 } 1535 1536 return ret; 1537 } 1538 1539 static int vangogh_read_sensor(struct smu_context *smu, 1540 enum amd_pp_sensors sensor, 1541 void *data, uint32_t *size) 1542 { 1543 int ret = 0; 1544 1545 if (!data || !size) 1546 return -EINVAL; 1547 1548 switch (sensor) { 1549 case AMDGPU_PP_SENSOR_GPU_LOAD: 1550 ret = vangogh_common_get_smu_metrics_data(smu, 1551 METRICS_AVERAGE_GFXACTIVITY, 1552 (uint32_t *)data); 1553 *size = 4; 1554 break; 1555 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 1556 ret = vangogh_common_get_smu_metrics_data(smu, 1557 METRICS_AVERAGE_SOCKETPOWER, 1558 (uint32_t *)data); 1559 *size = 4; 1560 break; 1561 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 1562 ret = vangogh_common_get_smu_metrics_data(smu, 1563 METRICS_CURR_SOCKETPOWER, 1564 (uint32_t *)data); 1565 *size = 4; 1566 break; 1567 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1568 ret = vangogh_common_get_smu_metrics_data(smu, 1569 METRICS_TEMPERATURE_EDGE, 1570 (uint32_t *)data); 1571 *size = 4; 1572 break; 1573 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1574 ret = vangogh_common_get_smu_metrics_data(smu, 1575 METRICS_TEMPERATURE_HOTSPOT, 1576 (uint32_t *)data); 1577 *size = 4; 1578 break; 1579 case AMDGPU_PP_SENSOR_GFX_MCLK: 1580 ret = vangogh_common_get_smu_metrics_data(smu, 1581 METRICS_CURR_UCLK, 1582 (uint32_t *)data); 1583 *(uint32_t *)data *= 100; 1584 *size = 4; 1585 break; 1586 case AMDGPU_PP_SENSOR_GFX_SCLK: 1587 ret = vangogh_common_get_smu_metrics_data(smu, 1588 METRICS_CURR_GFXCLK, 1589 (uint32_t *)data); 1590 *(uint32_t *)data *= 100; 1591 *size = 4; 1592 break; 1593 case AMDGPU_PP_SENSOR_VDDGFX: 1594 ret = vangogh_common_get_smu_metrics_data(smu, 1595 METRICS_VOLTAGE_VDDGFX, 1596 (uint32_t *)data); 1597 *size = 4; 1598 break; 1599 case AMDGPU_PP_SENSOR_VDDNB: 1600 ret = vangogh_common_get_smu_metrics_data(smu, 1601 METRICS_VOLTAGE_VDDSOC, 1602 (uint32_t *)data); 1603 *size = 4; 1604 break; 1605 case AMDGPU_PP_SENSOR_CPU_CLK: 1606 ret = vangogh_common_get_smu_metrics_data(smu, 1607 METRICS_AVERAGE_CPUCLK, 1608 (uint32_t *)data); 1609 *size = smu->cpu_core_num * sizeof(uint16_t); 1610 break; 1611 default: 1612 ret = -EOPNOTSUPP; 1613 break; 1614 } 1615 1616 return ret; 1617 } 1618 1619 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit) 1620 { 1621 return smu_cmn_send_smc_msg_with_param(smu, 1622 SMU_MSG_GetThermalLimit, 1623 0, limit); 1624 } 1625 1626 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit) 1627 { 1628 return smu_cmn_send_smc_msg_with_param(smu, 1629 SMU_MSG_SetReducedThermalLimit, 1630 limit, NULL); 1631 } 1632 1633 1634 static int vangogh_set_watermarks_table(struct smu_context *smu, 1635 struct pp_smu_wm_range_sets *clock_ranges) 1636 { 1637 int i; 1638 int ret = 0; 1639 Watermarks_t *table = smu->smu_table.watermarks_table; 1640 1641 if (!table || !clock_ranges) 1642 return -EINVAL; 1643 1644 if (clock_ranges) { 1645 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1646 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1647 return -EINVAL; 1648 1649 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1650 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1651 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1652 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1653 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1654 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1655 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1656 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1657 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1658 1659 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1660 clock_ranges->reader_wm_sets[i].wm_inst; 1661 } 1662 1663 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1664 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1665 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1666 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1667 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1668 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1669 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1670 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1671 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1672 1673 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1674 clock_ranges->writer_wm_sets[i].wm_inst; 1675 } 1676 1677 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1678 } 1679 1680 /* pass data to smu controller */ 1681 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1682 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1683 ret = smu_cmn_write_watermarks_table(smu); 1684 if (ret) { 1685 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1686 return ret; 1687 } 1688 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1689 } 1690 1691 return 0; 1692 } 1693 1694 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu, 1695 void **table) 1696 { 1697 struct smu_table_context *smu_table = &smu->smu_table; 1698 struct gpu_metrics_v2_3 *gpu_metrics = 1699 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1700 SmuMetrics_legacy_t metrics; 1701 int ret = 0; 1702 1703 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1704 if (ret) 1705 return ret; 1706 1707 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1708 1709 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1710 gpu_metrics->temperature_soc = metrics.SocTemperature; 1711 memcpy(&gpu_metrics->temperature_core[0], 1712 &metrics.CoreTemperature[0], 1713 sizeof(uint16_t) * 4); 1714 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1715 1716 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1717 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1718 1719 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1720 gpu_metrics->average_cpu_power = metrics.Power[0]; 1721 gpu_metrics->average_soc_power = metrics.Power[1]; 1722 gpu_metrics->average_gfx_power = metrics.Power[2]; 1723 memcpy(&gpu_metrics->average_core_power[0], 1724 &metrics.CorePower[0], 1725 sizeof(uint16_t) * 4); 1726 1727 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1728 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1729 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1730 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1731 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1732 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1733 1734 memcpy(&gpu_metrics->current_coreclk[0], 1735 &metrics.CoreFrequency[0], 1736 sizeof(uint16_t) * 4); 1737 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1738 1739 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1740 gpu_metrics->indep_throttle_status = 1741 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1742 vangogh_throttler_map); 1743 1744 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1745 1746 *table = (void *)gpu_metrics; 1747 1748 return sizeof(struct gpu_metrics_v2_3); 1749 } 1750 1751 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, 1752 void **table) 1753 { 1754 struct smu_table_context *smu_table = &smu->smu_table; 1755 struct gpu_metrics_v2_2 *gpu_metrics = 1756 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1757 SmuMetrics_legacy_t metrics; 1758 int ret = 0; 1759 1760 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1761 if (ret) 1762 return ret; 1763 1764 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1765 1766 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1767 gpu_metrics->temperature_soc = metrics.SocTemperature; 1768 memcpy(&gpu_metrics->temperature_core[0], 1769 &metrics.CoreTemperature[0], 1770 sizeof(uint16_t) * 4); 1771 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1772 1773 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1774 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1775 1776 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1777 gpu_metrics->average_cpu_power = metrics.Power[0]; 1778 gpu_metrics->average_soc_power = metrics.Power[1]; 1779 gpu_metrics->average_gfx_power = metrics.Power[2]; 1780 memcpy(&gpu_metrics->average_core_power[0], 1781 &metrics.CorePower[0], 1782 sizeof(uint16_t) * 4); 1783 1784 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1785 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1786 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1787 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1788 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1789 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1790 1791 memcpy(&gpu_metrics->current_coreclk[0], 1792 &metrics.CoreFrequency[0], 1793 sizeof(uint16_t) * 4); 1794 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1795 1796 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1797 gpu_metrics->indep_throttle_status = 1798 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1799 vangogh_throttler_map); 1800 1801 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1802 1803 *table = (void *)gpu_metrics; 1804 1805 return sizeof(struct gpu_metrics_v2_2); 1806 } 1807 1808 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu, 1809 void **table) 1810 { 1811 struct smu_table_context *smu_table = &smu->smu_table; 1812 struct gpu_metrics_v2_3 *gpu_metrics = 1813 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1814 SmuMetrics_t metrics; 1815 int ret = 0; 1816 1817 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1818 if (ret) 1819 return ret; 1820 1821 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1822 1823 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1824 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1825 memcpy(&gpu_metrics->temperature_core[0], 1826 &metrics.Current.CoreTemperature[0], 1827 sizeof(uint16_t) * 4); 1828 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1829 1830 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature; 1831 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature; 1832 memcpy(&gpu_metrics->average_temperature_core[0], 1833 &metrics.Average.CoreTemperature[0], 1834 sizeof(uint16_t) * 4); 1835 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0]; 1836 1837 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1838 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1839 1840 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1841 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1842 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1843 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1844 memcpy(&gpu_metrics->average_core_power[0], 1845 &metrics.Average.CorePower[0], 1846 sizeof(uint16_t) * 4); 1847 1848 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1849 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1850 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1851 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1852 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1853 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1854 1855 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1856 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1857 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1858 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1859 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1860 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1861 1862 memcpy(&gpu_metrics->current_coreclk[0], 1863 &metrics.Current.CoreFrequency[0], 1864 sizeof(uint16_t) * 4); 1865 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1866 1867 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1868 gpu_metrics->indep_throttle_status = 1869 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1870 vangogh_throttler_map); 1871 1872 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1873 1874 *table = (void *)gpu_metrics; 1875 1876 return sizeof(struct gpu_metrics_v2_3); 1877 } 1878 1879 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu, 1880 void **table) 1881 { 1882 SmuMetrics_t metrics; 1883 struct smu_table_context *smu_table = &smu->smu_table; 1884 struct gpu_metrics_v2_4 *gpu_metrics = 1885 (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table; 1886 int ret = 0; 1887 1888 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1889 if (ret) 1890 return ret; 1891 1892 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4); 1893 1894 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1895 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1896 memcpy(&gpu_metrics->temperature_core[0], 1897 &metrics.Current.CoreTemperature[0], 1898 sizeof(uint16_t) * 4); 1899 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1900 1901 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature; 1902 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature; 1903 memcpy(&gpu_metrics->average_temperature_core[0], 1904 &metrics.Average.CoreTemperature[0], 1905 sizeof(uint16_t) * 4); 1906 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0]; 1907 1908 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1909 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1910 1911 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1912 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1913 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1914 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1915 1916 gpu_metrics->average_cpu_voltage = metrics.Current.Voltage[0]; 1917 gpu_metrics->average_soc_voltage = metrics.Current.Voltage[1]; 1918 gpu_metrics->average_gfx_voltage = metrics.Current.Voltage[2]; 1919 1920 gpu_metrics->average_cpu_current = metrics.Current.Current[0]; 1921 gpu_metrics->average_soc_current = metrics.Current.Current[1]; 1922 gpu_metrics->average_gfx_current = metrics.Current.Current[2]; 1923 1924 memcpy(&gpu_metrics->average_core_power[0], 1925 &metrics.Average.CorePower[0], 1926 sizeof(uint16_t) * 4); 1927 1928 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1929 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1930 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1931 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1932 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1933 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1934 1935 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1936 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1937 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1938 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1939 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1940 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1941 1942 memcpy(&gpu_metrics->current_coreclk[0], 1943 &metrics.Current.CoreFrequency[0], 1944 sizeof(uint16_t) * 4); 1945 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1946 1947 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1948 gpu_metrics->indep_throttle_status = 1949 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1950 vangogh_throttler_map); 1951 1952 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1953 1954 *table = (void *)gpu_metrics; 1955 1956 return sizeof(struct gpu_metrics_v2_4); 1957 } 1958 1959 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1960 void **table) 1961 { 1962 struct smu_table_context *smu_table = &smu->smu_table; 1963 struct gpu_metrics_v2_2 *gpu_metrics = 1964 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1965 SmuMetrics_t metrics; 1966 int ret = 0; 1967 1968 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1969 if (ret) 1970 return ret; 1971 1972 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1973 1974 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1975 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1976 memcpy(&gpu_metrics->temperature_core[0], 1977 &metrics.Current.CoreTemperature[0], 1978 sizeof(uint16_t) * 4); 1979 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1980 1981 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1982 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1983 1984 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1985 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1986 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1987 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1988 memcpy(&gpu_metrics->average_core_power[0], 1989 &metrics.Average.CorePower[0], 1990 sizeof(uint16_t) * 4); 1991 1992 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1993 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1994 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1995 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1996 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1997 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1998 1999 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 2000 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 2001 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 2002 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 2003 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 2004 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 2005 2006 memcpy(&gpu_metrics->current_coreclk[0], 2007 &metrics.Current.CoreFrequency[0], 2008 sizeof(uint16_t) * 4); 2009 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 2010 2011 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 2012 gpu_metrics->indep_throttle_status = 2013 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 2014 vangogh_throttler_map); 2015 2016 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2017 2018 *table = (void *)gpu_metrics; 2019 2020 return sizeof(struct gpu_metrics_v2_2); 2021 } 2022 2023 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, 2024 void **table) 2025 { 2026 uint32_t if_version; 2027 uint32_t smu_version; 2028 uint32_t smu_program; 2029 uint32_t fw_version; 2030 int ret = 0; 2031 2032 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 2033 if (ret) 2034 return ret; 2035 2036 smu_program = (smu_version >> 24) & 0xff; 2037 fw_version = smu_version & 0xffffff; 2038 if (smu_program == 6) { 2039 if (fw_version >= 0x3F0800) 2040 ret = vangogh_get_gpu_metrics_v2_4(smu, table); 2041 else 2042 ret = vangogh_get_gpu_metrics_v2_3(smu, table); 2043 2044 } else { 2045 if (smu_version >= 0x043F3E00) { 2046 if (if_version < 0x3) 2047 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table); 2048 else 2049 ret = vangogh_get_gpu_metrics_v2_3(smu, table); 2050 } else { 2051 if (if_version < 0x3) 2052 ret = vangogh_get_legacy_gpu_metrics(smu, table); 2053 else 2054 ret = vangogh_get_gpu_metrics(smu, table); 2055 } 2056 } 2057 2058 return ret; 2059 } 2060 2061 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 2062 long input[], uint32_t size) 2063 { 2064 int ret = 0; 2065 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2066 2067 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 2068 dev_warn(smu->adev->dev, 2069 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 2070 return -EINVAL; 2071 } 2072 2073 switch (type) { 2074 case PP_OD_EDIT_CCLK_VDDC_TABLE: 2075 if (size != 3) { 2076 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 2077 return -EINVAL; 2078 } 2079 if (input[0] >= smu->cpu_core_num) { 2080 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 2081 smu->cpu_core_num); 2082 } 2083 smu->cpu_core_id_select = input[0]; 2084 if (input[1] == 0) { 2085 if (input[2] < smu->cpu_default_soft_min_freq) { 2086 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2087 input[2], smu->cpu_default_soft_min_freq); 2088 return -EINVAL; 2089 } 2090 smu->cpu_actual_soft_min_freq = input[2]; 2091 } else if (input[1] == 1) { 2092 if (input[2] > smu->cpu_default_soft_max_freq) { 2093 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2094 input[2], smu->cpu_default_soft_max_freq); 2095 return -EINVAL; 2096 } 2097 smu->cpu_actual_soft_max_freq = input[2]; 2098 } else { 2099 return -EINVAL; 2100 } 2101 break; 2102 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2103 if (size != 2) { 2104 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2105 return -EINVAL; 2106 } 2107 2108 if (input[0] == 0) { 2109 if (input[1] < smu->gfx_default_hard_min_freq) { 2110 dev_warn(smu->adev->dev, 2111 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2112 input[1], smu->gfx_default_hard_min_freq); 2113 return -EINVAL; 2114 } 2115 smu->gfx_actual_hard_min_freq = input[1]; 2116 } else if (input[0] == 1) { 2117 if (input[1] > smu->gfx_default_soft_max_freq) { 2118 dev_warn(smu->adev->dev, 2119 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2120 input[1], smu->gfx_default_soft_max_freq); 2121 return -EINVAL; 2122 } 2123 smu->gfx_actual_soft_max_freq = input[1]; 2124 } else { 2125 return -EINVAL; 2126 } 2127 break; 2128 case PP_OD_RESTORE_DEFAULT_TABLE: 2129 if (size != 0) { 2130 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2131 return -EINVAL; 2132 } else { 2133 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 2134 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 2135 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 2136 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 2137 } 2138 break; 2139 case PP_OD_COMMIT_DPM_TABLE: 2140 if (size != 0) { 2141 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2142 return -EINVAL; 2143 } else { 2144 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 2145 dev_err(smu->adev->dev, 2146 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 2147 smu->gfx_actual_hard_min_freq, 2148 smu->gfx_actual_soft_max_freq); 2149 return -EINVAL; 2150 } 2151 2152 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 2153 smu->gfx_actual_hard_min_freq, NULL); 2154 if (ret) { 2155 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 2156 return ret; 2157 } 2158 2159 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 2160 smu->gfx_actual_soft_max_freq, NULL); 2161 if (ret) { 2162 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 2163 return ret; 2164 } 2165 2166 if (smu->adev->pm.fw_version < 0x43f1b00) { 2167 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 2168 break; 2169 } 2170 2171 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 2172 ((smu->cpu_core_id_select << 20) 2173 | smu->cpu_actual_soft_min_freq), 2174 NULL); 2175 if (ret) { 2176 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 2177 return ret; 2178 } 2179 2180 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 2181 ((smu->cpu_core_id_select << 20) 2182 | smu->cpu_actual_soft_max_freq), 2183 NULL); 2184 if (ret) { 2185 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 2186 return ret; 2187 } 2188 } 2189 break; 2190 default: 2191 return -ENOSYS; 2192 } 2193 2194 return ret; 2195 } 2196 2197 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 2198 { 2199 struct smu_table_context *smu_table = &smu->smu_table; 2200 2201 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 2202 } 2203 2204 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 2205 { 2206 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 2207 2208 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 2209 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 2210 smu->gfx_actual_hard_min_freq = 0; 2211 smu->gfx_actual_soft_max_freq = 0; 2212 2213 smu->cpu_default_soft_min_freq = 1400; 2214 smu->cpu_default_soft_max_freq = 3500; 2215 smu->cpu_actual_soft_min_freq = 0; 2216 smu->cpu_actual_soft_max_freq = 0; 2217 2218 return 0; 2219 } 2220 2221 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 2222 { 2223 DpmClocks_t *table = smu->smu_table.clocks_table; 2224 int i; 2225 2226 if (!clock_table || !table) 2227 return -EINVAL; 2228 2229 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 2230 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 2231 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 2232 } 2233 2234 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2235 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 2236 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 2237 } 2238 2239 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2240 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 2241 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 2242 } 2243 2244 return 0; 2245 } 2246 2247 2248 static int vangogh_system_features_control(struct smu_context *smu, bool en) 2249 { 2250 struct amdgpu_device *adev = smu->adev; 2251 int ret = 0; 2252 2253 if (adev->pm.fw_version >= 0x43f1700 && !en) 2254 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 2255 RLC_STATUS_OFF, NULL); 2256 2257 return ret; 2258 } 2259 2260 static int vangogh_post_smu_init(struct smu_context *smu) 2261 { 2262 struct amdgpu_device *adev = smu->adev; 2263 uint32_t tmp; 2264 int ret = 0; 2265 uint8_t aon_bits = 0; 2266 /* Two CUs in one WGP */ 2267 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 2268 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 2269 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2270 2271 /* allow message will be sent after enable message on Vangogh*/ 2272 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 2273 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2274 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 2275 if (ret) { 2276 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 2277 return ret; 2278 } 2279 } else { 2280 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 2281 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 2282 } 2283 2284 /* if all CUs are active, no need to power off any WGPs */ 2285 if (total_cu == adev->gfx.cu_info.number) 2286 return 0; 2287 2288 /* 2289 * Calculate the total bits number of always on WGPs for all SA/SEs in 2290 * RLC_PG_ALWAYS_ON_WGP_MASK. 2291 */ 2292 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 2293 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 2294 2295 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2296 2297 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 2298 if (aon_bits > req_active_wgps) { 2299 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 2300 return 0; 2301 } else { 2302 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 2303 } 2304 } 2305 2306 static int vangogh_mode_reset(struct smu_context *smu, int type) 2307 { 2308 int ret = 0, index = 0; 2309 2310 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2311 SMU_MSG_GfxDeviceDriverReset); 2312 if (index < 0) 2313 return index == -EACCES ? 0 : index; 2314 2315 mutex_lock(&smu->message_lock); 2316 2317 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 2318 2319 mutex_unlock(&smu->message_lock); 2320 2321 mdelay(10); 2322 2323 return ret; 2324 } 2325 2326 static int vangogh_mode2_reset(struct smu_context *smu) 2327 { 2328 return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 2329 } 2330 2331 /** 2332 * vangogh_get_gfxoff_status - Get gfxoff status 2333 * 2334 * @smu: amdgpu_device pointer 2335 * 2336 * Get current gfxoff status 2337 * 2338 * Return: 2339 * * 0 - GFXOFF (default if enabled). 2340 * * 1 - Transition out of GFX State. 2341 * * 2 - Not in GFXOFF. 2342 * * 3 - Transition into GFXOFF. 2343 */ 2344 static u32 vangogh_get_gfxoff_status(struct smu_context *smu) 2345 { 2346 struct amdgpu_device *adev = smu->adev; 2347 u32 reg, gfxoff_status; 2348 2349 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL); 2350 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK) 2351 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT; 2352 2353 return gfxoff_status; 2354 } 2355 2356 static int vangogh_get_power_limit(struct smu_context *smu, 2357 uint32_t *current_power_limit, 2358 uint32_t *default_power_limit, 2359 uint32_t *max_power_limit) 2360 { 2361 struct smu_11_5_power_context *power_context = 2362 smu->smu_power.power_context; 2363 uint32_t ppt_limit; 2364 int ret = 0; 2365 2366 if (smu->adev->pm.fw_version < 0x43f1e00) 2367 return ret; 2368 2369 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 2370 if (ret) { 2371 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 2372 return ret; 2373 } 2374 /* convert from milliwatt to watt */ 2375 if (current_power_limit) 2376 *current_power_limit = ppt_limit / 1000; 2377 if (default_power_limit) 2378 *default_power_limit = ppt_limit / 1000; 2379 if (max_power_limit) 2380 *max_power_limit = 29; 2381 2382 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 2383 if (ret) { 2384 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 2385 return ret; 2386 } 2387 /* convert from milliwatt to watt */ 2388 power_context->current_fast_ppt_limit = 2389 power_context->default_fast_ppt_limit = ppt_limit / 1000; 2390 power_context->max_fast_ppt_limit = 30; 2391 2392 return ret; 2393 } 2394 2395 static int vangogh_get_ppt_limit(struct smu_context *smu, 2396 uint32_t *ppt_limit, 2397 enum smu_ppt_limit_type type, 2398 enum smu_ppt_limit_level level) 2399 { 2400 struct smu_11_5_power_context *power_context = 2401 smu->smu_power.power_context; 2402 2403 if (!power_context) 2404 return -EOPNOTSUPP; 2405 2406 if (type == SMU_FAST_PPT_LIMIT) { 2407 switch (level) { 2408 case SMU_PPT_LIMIT_MAX: 2409 *ppt_limit = power_context->max_fast_ppt_limit; 2410 break; 2411 case SMU_PPT_LIMIT_CURRENT: 2412 *ppt_limit = power_context->current_fast_ppt_limit; 2413 break; 2414 case SMU_PPT_LIMIT_DEFAULT: 2415 *ppt_limit = power_context->default_fast_ppt_limit; 2416 break; 2417 default: 2418 break; 2419 } 2420 } 2421 2422 return 0; 2423 } 2424 2425 static int vangogh_set_power_limit(struct smu_context *smu, 2426 enum smu_ppt_limit_type limit_type, 2427 uint32_t ppt_limit) 2428 { 2429 struct smu_11_5_power_context *power_context = 2430 smu->smu_power.power_context; 2431 int ret = 0; 2432 2433 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 2434 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 2435 return -EOPNOTSUPP; 2436 } 2437 2438 switch (limit_type) { 2439 case SMU_DEFAULT_PPT_LIMIT: 2440 ret = smu_cmn_send_smc_msg_with_param(smu, 2441 SMU_MSG_SetSlowPPTLimit, 2442 ppt_limit * 1000, /* convert from watt to milliwatt */ 2443 NULL); 2444 if (ret) 2445 return ret; 2446 2447 smu->current_power_limit = ppt_limit; 2448 break; 2449 case SMU_FAST_PPT_LIMIT: 2450 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 2451 if (ppt_limit > power_context->max_fast_ppt_limit) { 2452 dev_err(smu->adev->dev, 2453 "New power limit (%d) is over the max allowed %d\n", 2454 ppt_limit, power_context->max_fast_ppt_limit); 2455 return ret; 2456 } 2457 2458 ret = smu_cmn_send_smc_msg_with_param(smu, 2459 SMU_MSG_SetFastPPTLimit, 2460 ppt_limit * 1000, /* convert from watt to milliwatt */ 2461 NULL); 2462 if (ret) 2463 return ret; 2464 2465 power_context->current_fast_ppt_limit = ppt_limit; 2466 break; 2467 default: 2468 return -EINVAL; 2469 } 2470 2471 return ret; 2472 } 2473 2474 /** 2475 * vangogh_set_gfxoff_residency 2476 * 2477 * @smu: amdgpu_device pointer 2478 * @start: start/stop residency log 2479 * 2480 * This function will be used to log gfxoff residency 2481 * 2482 * 2483 * Returns standard response codes. 2484 */ 2485 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start) 2486 { 2487 int ret = 0; 2488 u32 residency; 2489 struct amdgpu_device *adev = smu->adev; 2490 2491 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2492 return 0; 2493 2494 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency, 2495 start, &residency); 2496 if (ret) 2497 return ret; 2498 2499 if (!start) 2500 adev->gfx.gfx_off_residency = residency; 2501 2502 return ret; 2503 } 2504 2505 /** 2506 * vangogh_get_gfxoff_residency 2507 * 2508 * @smu: amdgpu_device pointer 2509 * @residency: placeholder for return value 2510 * 2511 * This function will be used to get gfxoff residency. 2512 * 2513 * Returns standard response codes. 2514 */ 2515 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency) 2516 { 2517 struct amdgpu_device *adev = smu->adev; 2518 2519 *residency = adev->gfx.gfx_off_residency; 2520 2521 return 0; 2522 } 2523 2524 /** 2525 * vangogh_get_gfxoff_entrycount - get gfxoff entry count 2526 * 2527 * @smu: amdgpu_device pointer 2528 * @entrycount: placeholder for return value 2529 * 2530 * This function will be used to get gfxoff entry count 2531 * 2532 * Returns standard response codes. 2533 */ 2534 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount) 2535 { 2536 int ret = 0, value = 0; 2537 struct amdgpu_device *adev = smu->adev; 2538 2539 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2540 return 0; 2541 2542 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value); 2543 *entrycount = value + adev->gfx.gfx_off_entrycount; 2544 2545 return ret; 2546 } 2547 2548 static const struct pptable_funcs vangogh_ppt_funcs = { 2549 2550 .check_fw_status = smu_v11_0_check_fw_status, 2551 .check_fw_version = smu_v11_0_check_fw_version, 2552 .init_smc_tables = vangogh_init_smc_tables, 2553 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2554 .init_power = smu_v11_0_init_power, 2555 .fini_power = smu_v11_0_fini_power, 2556 .register_irq_handler = smu_v11_0_register_irq_handler, 2557 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2558 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2559 .send_smc_msg = smu_cmn_send_smc_msg, 2560 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 2561 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 2562 .is_dpm_running = vangogh_is_dpm_running, 2563 .read_sensor = vangogh_read_sensor, 2564 .get_apu_thermal_limit = vangogh_get_apu_thermal_limit, 2565 .set_apu_thermal_limit = vangogh_set_apu_thermal_limit, 2566 .get_enabled_mask = smu_cmn_get_enabled_mask, 2567 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2568 .set_watermarks_table = vangogh_set_watermarks_table, 2569 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2570 .interrupt_work = smu_v11_0_interrupt_work, 2571 .get_gpu_metrics = vangogh_common_get_gpu_metrics, 2572 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 2573 .print_clk_levels = vangogh_common_print_clk_levels, 2574 .set_default_dpm_table = vangogh_set_default_dpm_tables, 2575 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 2576 .system_features_control = vangogh_system_features_control, 2577 .feature_is_enabled = smu_cmn_feature_is_enabled, 2578 .set_power_profile_mode = vangogh_set_power_profile_mode, 2579 .get_power_profile_mode = vangogh_get_power_profile_mode, 2580 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 2581 .force_clk_levels = vangogh_force_clk_levels, 2582 .set_performance_level = vangogh_set_performance_level, 2583 .post_init = vangogh_post_smu_init, 2584 .mode2_reset = vangogh_mode2_reset, 2585 .gfx_off_control = smu_v11_0_gfx_off_control, 2586 .get_gfx_off_status = vangogh_get_gfxoff_status, 2587 .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount, 2588 .get_gfx_off_residency = vangogh_get_gfxoff_residency, 2589 .set_gfx_off_residency = vangogh_set_gfxoff_residency, 2590 .get_ppt_limit = vangogh_get_ppt_limit, 2591 .get_power_limit = vangogh_get_power_limit, 2592 .set_power_limit = vangogh_set_power_limit, 2593 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2594 }; 2595 2596 void vangogh_set_ppt_funcs(struct smu_context *smu) 2597 { 2598 smu->ppt_funcs = &vangogh_ppt_funcs; 2599 smu->message_map = vangogh_message_map; 2600 smu->feature_map = vangogh_feature_mask_map; 2601 smu->table_map = vangogh_table_map; 2602 smu->workload_map = vangogh_workload_map; 2603 smu->is_apu = true; 2604 smu_v11_0_set_smu_mailbox_registers(smu); 2605 } 2606