1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 #include <asm/processor.h> 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 // Registers related to GFXOFF 50 // addressBlock: smuio_smuio_SmuSmuioDec 51 // base address: 0x5a000 52 #define mmSMUIO_GFX_MISC_CNTL 0x00c5 53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0 54 55 //SMUIO_GFX_MISC_CNTL 56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0 57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L 59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 64 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 65 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 66 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 67 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 68 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 69 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 70 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 71 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 72 73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 77 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 78 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 79 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 80 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 81 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 82 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 83 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 84 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 85 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 86 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 87 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 88 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 89 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 92 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 93 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 94 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 95 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 96 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 97 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 98 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 99 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 100 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 101 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 102 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 103 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 104 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 105 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 106 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 107 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 110 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 111 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 112 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 113 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 114 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 115 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 116 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 117 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 118 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 119 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 120 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 121 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 122 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 123 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 124 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 125 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 126 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 127 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 128 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 129 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 130 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 131 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 132 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 133 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 134 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 135 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 136 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 137 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 138 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 139 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 140 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 141 MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0), 142 MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0), 143 MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0), 144 }; 145 146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 147 FEA_MAP(PPT), 148 FEA_MAP(TDC), 149 FEA_MAP(THERMAL), 150 FEA_MAP(DS_GFXCLK), 151 FEA_MAP(DS_SOCCLK), 152 FEA_MAP(DS_LCLK), 153 FEA_MAP(DS_FCLK), 154 FEA_MAP(DS_MP1CLK), 155 FEA_MAP(DS_MP0CLK), 156 FEA_MAP(ATHUB_PG), 157 FEA_MAP(CCLK_DPM), 158 FEA_MAP(FAN_CONTROLLER), 159 FEA_MAP(ULV), 160 FEA_MAP(VCN_DPM), 161 FEA_MAP(LCLK_DPM), 162 FEA_MAP(SHUBCLK_DPM), 163 FEA_MAP(DCFCLK_DPM), 164 FEA_MAP(DS_DCFCLK), 165 FEA_MAP(S0I2), 166 FEA_MAP(SMU_LOW_POWER), 167 FEA_MAP(GFX_DEM), 168 FEA_MAP(PSI), 169 FEA_MAP(PROCHOT), 170 FEA_MAP(CPUOFF), 171 FEA_MAP(STAPM), 172 FEA_MAP(S0I3), 173 FEA_MAP(DF_CSTATES), 174 FEA_MAP(PERF_LIMIT), 175 FEA_MAP(CORE_DLDO), 176 FEA_MAP(RSMU_LOW_POWER), 177 FEA_MAP(SMN_LOW_POWER), 178 FEA_MAP(THM_LOW_POWER), 179 FEA_MAP(SMUIO_LOW_POWER), 180 FEA_MAP(MP1_LOW_POWER), 181 FEA_MAP(DS_VCN), 182 FEA_MAP(CPPC), 183 FEA_MAP(OS_CSTATES), 184 FEA_MAP(ISP_DPM), 185 FEA_MAP(A55_DPM), 186 FEA_MAP(CVIP_DSP_DPM), 187 FEA_MAP(MSMU_LOW_POWER), 188 FEA_MAP_REVERSE(SOCCLK), 189 FEA_MAP_REVERSE(FCLK), 190 FEA_MAP_HALF_REVERSE(GFX), 191 }; 192 193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 194 TAB_MAP_VALID(WATERMARKS), 195 TAB_MAP_VALID(SMU_METRICS), 196 TAB_MAP_VALID(CUSTOM_DPM), 197 TAB_MAP_VALID(DPMCLOCKS), 198 }; 199 200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 201 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 202 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT), 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT), 208 }; 209 210 static const uint8_t vangogh_throttler_map[] = { 211 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), 212 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), 213 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), 214 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), 215 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), 216 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), 217 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), 218 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), 219 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), 220 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT), 221 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT), 222 }; 223 224 static int vangogh_tables_init(struct smu_context *smu) 225 { 226 struct smu_table_context *smu_table = &smu->smu_table; 227 struct smu_table *tables = smu_table->tables; 228 uint32_t if_version; 229 uint32_t smu_version; 230 uint32_t ret = 0; 231 232 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 233 if (ret) { 234 return ret; 235 } 236 237 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 238 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 239 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 240 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 241 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 242 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 243 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 244 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 245 246 if (if_version < 0x3) { 247 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t), 248 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 249 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL); 250 } else { 251 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 252 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 253 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 254 } 255 if (!smu_table->metrics_table) 256 goto err0_out; 257 smu_table->metrics_time = 0; 258 259 if (smu_version >= 0x043F3E00) 260 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_3); 261 else 262 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); 263 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 264 if (!smu_table->gpu_metrics_table) 265 goto err1_out; 266 267 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 268 if (!smu_table->watermarks_table) 269 goto err2_out; 270 271 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 272 if (!smu_table->clocks_table) 273 goto err3_out; 274 275 return 0; 276 277 err3_out: 278 kfree(smu_table->watermarks_table); 279 err2_out: 280 kfree(smu_table->gpu_metrics_table); 281 err1_out: 282 kfree(smu_table->metrics_table); 283 err0_out: 284 return -ENOMEM; 285 } 286 287 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu, 288 MetricsMember_t member, 289 uint32_t *value) 290 { 291 struct smu_table_context *smu_table = &smu->smu_table; 292 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table; 293 int ret = 0; 294 295 ret = smu_cmn_get_metrics_table(smu, 296 NULL, 297 false); 298 if (ret) 299 return ret; 300 301 switch (member) { 302 case METRICS_CURR_GFXCLK: 303 *value = metrics->GfxclkFrequency; 304 break; 305 case METRICS_AVERAGE_SOCCLK: 306 *value = metrics->SocclkFrequency; 307 break; 308 case METRICS_AVERAGE_VCLK: 309 *value = metrics->VclkFrequency; 310 break; 311 case METRICS_AVERAGE_DCLK: 312 *value = metrics->DclkFrequency; 313 break; 314 case METRICS_CURR_UCLK: 315 *value = metrics->MemclkFrequency; 316 break; 317 case METRICS_AVERAGE_GFXACTIVITY: 318 *value = metrics->GfxActivity / 100; 319 break; 320 case METRICS_AVERAGE_VCNACTIVITY: 321 *value = metrics->UvdActivity; 322 break; 323 case METRICS_AVERAGE_SOCKETPOWER: 324 *value = (metrics->CurrentSocketPower << 8) / 325 1000 ; 326 break; 327 case METRICS_TEMPERATURE_EDGE: 328 *value = metrics->GfxTemperature / 100 * 329 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 330 break; 331 case METRICS_TEMPERATURE_HOTSPOT: 332 *value = metrics->SocTemperature / 100 * 333 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 334 break; 335 case METRICS_THROTTLER_STATUS: 336 *value = metrics->ThrottlerStatus; 337 break; 338 case METRICS_VOLTAGE_VDDGFX: 339 *value = metrics->Voltage[2]; 340 break; 341 case METRICS_VOLTAGE_VDDSOC: 342 *value = metrics->Voltage[1]; 343 break; 344 case METRICS_AVERAGE_CPUCLK: 345 memcpy(value, &metrics->CoreFrequency[0], 346 smu->cpu_core_num * sizeof(uint16_t)); 347 break; 348 default: 349 *value = UINT_MAX; 350 break; 351 } 352 353 return ret; 354 } 355 356 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 357 MetricsMember_t member, 358 uint32_t *value) 359 { 360 struct smu_table_context *smu_table = &smu->smu_table; 361 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 362 int ret = 0; 363 364 ret = smu_cmn_get_metrics_table(smu, 365 NULL, 366 false); 367 if (ret) 368 return ret; 369 370 switch (member) { 371 case METRICS_CURR_GFXCLK: 372 *value = metrics->Current.GfxclkFrequency; 373 break; 374 case METRICS_AVERAGE_SOCCLK: 375 *value = metrics->Current.SocclkFrequency; 376 break; 377 case METRICS_AVERAGE_VCLK: 378 *value = metrics->Current.VclkFrequency; 379 break; 380 case METRICS_AVERAGE_DCLK: 381 *value = metrics->Current.DclkFrequency; 382 break; 383 case METRICS_CURR_UCLK: 384 *value = metrics->Current.MemclkFrequency; 385 break; 386 case METRICS_AVERAGE_GFXACTIVITY: 387 *value = metrics->Current.GfxActivity; 388 break; 389 case METRICS_AVERAGE_VCNACTIVITY: 390 *value = metrics->Current.UvdActivity; 391 break; 392 case METRICS_AVERAGE_SOCKETPOWER: 393 *value = (metrics->Current.CurrentSocketPower << 8) / 394 1000; 395 break; 396 case METRICS_TEMPERATURE_EDGE: 397 *value = metrics->Current.GfxTemperature / 100 * 398 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 399 break; 400 case METRICS_TEMPERATURE_HOTSPOT: 401 *value = metrics->Current.SocTemperature / 100 * 402 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 403 break; 404 case METRICS_THROTTLER_STATUS: 405 *value = metrics->Current.ThrottlerStatus; 406 break; 407 case METRICS_VOLTAGE_VDDGFX: 408 *value = metrics->Current.Voltage[2]; 409 break; 410 case METRICS_VOLTAGE_VDDSOC: 411 *value = metrics->Current.Voltage[1]; 412 break; 413 case METRICS_AVERAGE_CPUCLK: 414 memcpy(value, &metrics->Current.CoreFrequency[0], 415 smu->cpu_core_num * sizeof(uint16_t)); 416 break; 417 default: 418 *value = UINT_MAX; 419 break; 420 } 421 422 return ret; 423 } 424 425 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu, 426 MetricsMember_t member, 427 uint32_t *value) 428 { 429 struct amdgpu_device *adev = smu->adev; 430 uint32_t if_version; 431 int ret = 0; 432 433 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 434 if (ret) { 435 dev_err(adev->dev, "Failed to get smu if version!\n"); 436 return ret; 437 } 438 439 if (if_version < 0x3) 440 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value); 441 else 442 ret = vangogh_get_smu_metrics_data(smu, member, value); 443 444 return ret; 445 } 446 447 static int vangogh_allocate_dpm_context(struct smu_context *smu) 448 { 449 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 450 451 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 452 GFP_KERNEL); 453 if (!smu_dpm->dpm_context) 454 return -ENOMEM; 455 456 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 457 458 return 0; 459 } 460 461 static int vangogh_init_smc_tables(struct smu_context *smu) 462 { 463 int ret = 0; 464 465 ret = vangogh_tables_init(smu); 466 if (ret) 467 return ret; 468 469 ret = vangogh_allocate_dpm_context(smu); 470 if (ret) 471 return ret; 472 473 #ifdef CONFIG_X86 474 /* AMD x86 APU only */ 475 smu->cpu_core_num = boot_cpu_data.x86_max_cores; 476 #else 477 smu->cpu_core_num = 4; 478 #endif 479 480 return smu_v11_0_init_smc_tables(smu); 481 } 482 483 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 484 { 485 int ret = 0; 486 487 if (enable) { 488 /* vcn dpm on is a prerequisite for vcn power gate messages */ 489 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 490 if (ret) 491 return ret; 492 } else { 493 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 494 if (ret) 495 return ret; 496 } 497 498 return ret; 499 } 500 501 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 502 { 503 int ret = 0; 504 505 if (enable) { 506 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 507 if (ret) 508 return ret; 509 } else { 510 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 511 if (ret) 512 return ret; 513 } 514 515 return ret; 516 } 517 518 static bool vangogh_is_dpm_running(struct smu_context *smu) 519 { 520 struct amdgpu_device *adev = smu->adev; 521 int ret = 0; 522 uint64_t feature_enabled; 523 524 /* we need to re-init after suspend so return false */ 525 if (adev->in_suspend) 526 return false; 527 528 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 529 530 if (ret) 531 return false; 532 533 return !!(feature_enabled & SMC_DPM_FEATURE); 534 } 535 536 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 537 uint32_t dpm_level, uint32_t *freq) 538 { 539 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 540 541 if (!clk_table || clk_type >= SMU_CLK_COUNT) 542 return -EINVAL; 543 544 switch (clk_type) { 545 case SMU_SOCCLK: 546 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 547 return -EINVAL; 548 *freq = clk_table->SocClocks[dpm_level]; 549 break; 550 case SMU_VCLK: 551 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 552 return -EINVAL; 553 *freq = clk_table->VcnClocks[dpm_level].vclk; 554 break; 555 case SMU_DCLK: 556 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 557 return -EINVAL; 558 *freq = clk_table->VcnClocks[dpm_level].dclk; 559 break; 560 case SMU_UCLK: 561 case SMU_MCLK: 562 if (dpm_level >= clk_table->NumDfPstatesEnabled) 563 return -EINVAL; 564 *freq = clk_table->DfPstateTable[dpm_level].memclk; 565 566 break; 567 case SMU_FCLK: 568 if (dpm_level >= clk_table->NumDfPstatesEnabled) 569 return -EINVAL; 570 *freq = clk_table->DfPstateTable[dpm_level].fclk; 571 break; 572 default: 573 return -EINVAL; 574 } 575 576 return 0; 577 } 578 579 static int vangogh_print_legacy_clk_levels(struct smu_context *smu, 580 enum smu_clk_type clk_type, char *buf) 581 { 582 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 583 SmuMetrics_legacy_t metrics; 584 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 585 int i, size = 0, ret = 0; 586 uint32_t cur_value = 0, value = 0, count = 0; 587 bool cur_value_match_level = false; 588 589 memset(&metrics, 0, sizeof(metrics)); 590 591 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 592 if (ret) 593 return ret; 594 595 smu_cmn_get_sysfs_buf(&buf, &size); 596 597 switch (clk_type) { 598 case SMU_OD_SCLK: 599 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 600 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 601 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 602 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 603 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 604 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 605 } 606 break; 607 case SMU_OD_CCLK: 608 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 609 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 610 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 611 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 612 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 613 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 614 } 615 break; 616 case SMU_OD_RANGE: 617 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 618 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 619 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 620 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 621 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 622 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 623 } 624 break; 625 case SMU_SOCCLK: 626 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 627 count = clk_table->NumSocClkLevelsEnabled; 628 cur_value = metrics.SocclkFrequency; 629 break; 630 case SMU_VCLK: 631 count = clk_table->VcnClkLevelsEnabled; 632 cur_value = metrics.VclkFrequency; 633 break; 634 case SMU_DCLK: 635 count = clk_table->VcnClkLevelsEnabled; 636 cur_value = metrics.DclkFrequency; 637 break; 638 case SMU_MCLK: 639 count = clk_table->NumDfPstatesEnabled; 640 cur_value = metrics.MemclkFrequency; 641 break; 642 case SMU_FCLK: 643 count = clk_table->NumDfPstatesEnabled; 644 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 645 if (ret) 646 return ret; 647 break; 648 default: 649 break; 650 } 651 652 switch (clk_type) { 653 case SMU_SOCCLK: 654 case SMU_VCLK: 655 case SMU_DCLK: 656 case SMU_MCLK: 657 case SMU_FCLK: 658 for (i = 0; i < count; i++) { 659 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 660 if (ret) 661 return ret; 662 if (!value) 663 continue; 664 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 665 cur_value == value ? "*" : ""); 666 if (cur_value == value) 667 cur_value_match_level = true; 668 } 669 670 if (!cur_value_match_level) 671 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 672 break; 673 default: 674 break; 675 } 676 677 return size; 678 } 679 680 static int vangogh_print_clk_levels(struct smu_context *smu, 681 enum smu_clk_type clk_type, char *buf) 682 { 683 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 684 SmuMetrics_t metrics; 685 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 686 int i, size = 0, ret = 0; 687 uint32_t cur_value = 0, value = 0, count = 0; 688 bool cur_value_match_level = false; 689 uint32_t min, max; 690 691 memset(&metrics, 0, sizeof(metrics)); 692 693 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 694 if (ret) 695 return ret; 696 697 smu_cmn_get_sysfs_buf(&buf, &size); 698 699 switch (clk_type) { 700 case SMU_OD_SCLK: 701 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 702 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 703 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 704 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 705 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 706 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 707 } 708 break; 709 case SMU_OD_CCLK: 710 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 711 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 712 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 713 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 714 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 715 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 716 } 717 break; 718 case SMU_OD_RANGE: 719 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 720 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 721 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 722 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 723 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 724 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 725 } 726 break; 727 case SMU_SOCCLK: 728 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 729 count = clk_table->NumSocClkLevelsEnabled; 730 cur_value = metrics.Current.SocclkFrequency; 731 break; 732 case SMU_VCLK: 733 count = clk_table->VcnClkLevelsEnabled; 734 cur_value = metrics.Current.VclkFrequency; 735 break; 736 case SMU_DCLK: 737 count = clk_table->VcnClkLevelsEnabled; 738 cur_value = metrics.Current.DclkFrequency; 739 break; 740 case SMU_MCLK: 741 count = clk_table->NumDfPstatesEnabled; 742 cur_value = metrics.Current.MemclkFrequency; 743 break; 744 case SMU_FCLK: 745 count = clk_table->NumDfPstatesEnabled; 746 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 747 if (ret) 748 return ret; 749 break; 750 case SMU_GFXCLK: 751 case SMU_SCLK: 752 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value); 753 if (ret) { 754 return ret; 755 } 756 break; 757 default: 758 break; 759 } 760 761 switch (clk_type) { 762 case SMU_SOCCLK: 763 case SMU_VCLK: 764 case SMU_DCLK: 765 case SMU_MCLK: 766 case SMU_FCLK: 767 for (i = 0; i < count; i++) { 768 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 769 if (ret) 770 return ret; 771 if (!value) 772 continue; 773 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 774 cur_value == value ? "*" : ""); 775 if (cur_value == value) 776 cur_value_match_level = true; 777 } 778 779 if (!cur_value_match_level) 780 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 781 break; 782 case SMU_GFXCLK: 783 case SMU_SCLK: 784 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 785 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 786 if (cur_value == max) 787 i = 2; 788 else if (cur_value == min) 789 i = 0; 790 else 791 i = 1; 792 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 793 i == 0 ? "*" : ""); 794 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 795 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, 796 i == 1 ? "*" : ""); 797 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 798 i == 2 ? "*" : ""); 799 break; 800 default: 801 break; 802 } 803 804 return size; 805 } 806 807 static int vangogh_common_print_clk_levels(struct smu_context *smu, 808 enum smu_clk_type clk_type, char *buf) 809 { 810 struct amdgpu_device *adev = smu->adev; 811 uint32_t if_version; 812 int ret = 0; 813 814 ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 815 if (ret) { 816 dev_err(adev->dev, "Failed to get smu if version!\n"); 817 return ret; 818 } 819 820 if (if_version < 0x3) 821 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf); 822 else 823 ret = vangogh_print_clk_levels(smu, clk_type, buf); 824 825 return ret; 826 } 827 828 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 829 enum amd_dpm_forced_level level, 830 uint32_t *vclk_mask, 831 uint32_t *dclk_mask, 832 uint32_t *mclk_mask, 833 uint32_t *fclk_mask, 834 uint32_t *soc_mask) 835 { 836 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 837 838 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 839 if (mclk_mask) 840 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 841 842 if (fclk_mask) 843 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 844 845 if (soc_mask) 846 *soc_mask = 0; 847 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 848 if (mclk_mask) 849 *mclk_mask = 0; 850 851 if (fclk_mask) 852 *fclk_mask = 0; 853 854 if (soc_mask) 855 *soc_mask = 1; 856 857 if (vclk_mask) 858 *vclk_mask = 1; 859 860 if (dclk_mask) 861 *dclk_mask = 1; 862 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 863 if (mclk_mask) 864 *mclk_mask = 0; 865 866 if (fclk_mask) 867 *fclk_mask = 0; 868 869 if (soc_mask) 870 *soc_mask = 1; 871 872 if (vclk_mask) 873 *vclk_mask = 1; 874 875 if (dclk_mask) 876 *dclk_mask = 1; 877 } 878 879 return 0; 880 } 881 882 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 883 enum smu_clk_type clk_type) 884 { 885 enum smu_feature_mask feature_id = 0; 886 887 switch (clk_type) { 888 case SMU_MCLK: 889 case SMU_UCLK: 890 case SMU_FCLK: 891 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 892 break; 893 case SMU_GFXCLK: 894 case SMU_SCLK: 895 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 896 break; 897 case SMU_SOCCLK: 898 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 899 break; 900 case SMU_VCLK: 901 case SMU_DCLK: 902 feature_id = SMU_FEATURE_VCN_DPM_BIT; 903 break; 904 default: 905 return true; 906 } 907 908 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 909 return false; 910 911 return true; 912 } 913 914 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 915 enum smu_clk_type clk_type, 916 uint32_t *min, 917 uint32_t *max) 918 { 919 int ret = 0; 920 uint32_t soc_mask; 921 uint32_t vclk_mask; 922 uint32_t dclk_mask; 923 uint32_t mclk_mask; 924 uint32_t fclk_mask; 925 uint32_t clock_limit; 926 927 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 928 switch (clk_type) { 929 case SMU_MCLK: 930 case SMU_UCLK: 931 clock_limit = smu->smu_table.boot_values.uclk; 932 break; 933 case SMU_FCLK: 934 clock_limit = smu->smu_table.boot_values.fclk; 935 break; 936 case SMU_GFXCLK: 937 case SMU_SCLK: 938 clock_limit = smu->smu_table.boot_values.gfxclk; 939 break; 940 case SMU_SOCCLK: 941 clock_limit = smu->smu_table.boot_values.socclk; 942 break; 943 case SMU_VCLK: 944 clock_limit = smu->smu_table.boot_values.vclk; 945 break; 946 case SMU_DCLK: 947 clock_limit = smu->smu_table.boot_values.dclk; 948 break; 949 default: 950 clock_limit = 0; 951 break; 952 } 953 954 /* clock in Mhz unit */ 955 if (min) 956 *min = clock_limit / 100; 957 if (max) 958 *max = clock_limit / 100; 959 960 return 0; 961 } 962 if (max) { 963 ret = vangogh_get_profiling_clk_mask(smu, 964 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 965 &vclk_mask, 966 &dclk_mask, 967 &mclk_mask, 968 &fclk_mask, 969 &soc_mask); 970 if (ret) 971 goto failed; 972 973 switch (clk_type) { 974 case SMU_UCLK: 975 case SMU_MCLK: 976 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 977 if (ret) 978 goto failed; 979 break; 980 case SMU_SOCCLK: 981 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 982 if (ret) 983 goto failed; 984 break; 985 case SMU_FCLK: 986 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 987 if (ret) 988 goto failed; 989 break; 990 case SMU_VCLK: 991 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 992 if (ret) 993 goto failed; 994 break; 995 case SMU_DCLK: 996 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 997 if (ret) 998 goto failed; 999 break; 1000 default: 1001 ret = -EINVAL; 1002 goto failed; 1003 } 1004 } 1005 if (min) { 1006 switch (clk_type) { 1007 case SMU_UCLK: 1008 case SMU_MCLK: 1009 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 1010 if (ret) 1011 goto failed; 1012 break; 1013 case SMU_SOCCLK: 1014 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 1015 if (ret) 1016 goto failed; 1017 break; 1018 case SMU_FCLK: 1019 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 1020 if (ret) 1021 goto failed; 1022 break; 1023 case SMU_VCLK: 1024 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 1025 if (ret) 1026 goto failed; 1027 break; 1028 case SMU_DCLK: 1029 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 1030 if (ret) 1031 goto failed; 1032 break; 1033 default: 1034 ret = -EINVAL; 1035 goto failed; 1036 } 1037 } 1038 failed: 1039 return ret; 1040 } 1041 1042 static int vangogh_get_power_profile_mode(struct smu_context *smu, 1043 char *buf) 1044 { 1045 uint32_t i, size = 0; 1046 int16_t workload_type = 0; 1047 1048 if (!buf) 1049 return -EINVAL; 1050 1051 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 1052 /* 1053 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1054 * Not all profile modes are supported on vangogh. 1055 */ 1056 workload_type = smu_cmn_to_asic_specific_index(smu, 1057 CMN2ASIC_MAPPING_WORKLOAD, 1058 i); 1059 1060 if (workload_type < 0) 1061 continue; 1062 1063 size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 1064 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1065 } 1066 1067 return size; 1068 } 1069 1070 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1071 { 1072 int workload_type, ret; 1073 uint32_t profile_mode = input[size]; 1074 1075 if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { 1076 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1077 return -EINVAL; 1078 } 1079 1080 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 1081 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 1082 return 0; 1083 1084 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1085 workload_type = smu_cmn_to_asic_specific_index(smu, 1086 CMN2ASIC_MAPPING_WORKLOAD, 1087 profile_mode); 1088 if (workload_type < 0) { 1089 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 1090 profile_mode); 1091 return -EINVAL; 1092 } 1093 1094 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 1095 1 << workload_type, 1096 NULL); 1097 if (ret) { 1098 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 1099 workload_type); 1100 return ret; 1101 } 1102 1103 smu->power_profile_mode = profile_mode; 1104 1105 return 0; 1106 } 1107 1108 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 1109 enum smu_clk_type clk_type, 1110 uint32_t min, 1111 uint32_t max) 1112 { 1113 int ret = 0; 1114 1115 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 1116 return 0; 1117 1118 switch (clk_type) { 1119 case SMU_GFXCLK: 1120 case SMU_SCLK: 1121 ret = smu_cmn_send_smc_msg_with_param(smu, 1122 SMU_MSG_SetHardMinGfxClk, 1123 min, NULL); 1124 if (ret) 1125 return ret; 1126 1127 ret = smu_cmn_send_smc_msg_with_param(smu, 1128 SMU_MSG_SetSoftMaxGfxClk, 1129 max, NULL); 1130 if (ret) 1131 return ret; 1132 break; 1133 case SMU_FCLK: 1134 ret = smu_cmn_send_smc_msg_with_param(smu, 1135 SMU_MSG_SetHardMinFclkByFreq, 1136 min, NULL); 1137 if (ret) 1138 return ret; 1139 1140 ret = smu_cmn_send_smc_msg_with_param(smu, 1141 SMU_MSG_SetSoftMaxFclkByFreq, 1142 max, NULL); 1143 if (ret) 1144 return ret; 1145 break; 1146 case SMU_SOCCLK: 1147 ret = smu_cmn_send_smc_msg_with_param(smu, 1148 SMU_MSG_SetHardMinSocclkByFreq, 1149 min, NULL); 1150 if (ret) 1151 return ret; 1152 1153 ret = smu_cmn_send_smc_msg_with_param(smu, 1154 SMU_MSG_SetSoftMaxSocclkByFreq, 1155 max, NULL); 1156 if (ret) 1157 return ret; 1158 break; 1159 case SMU_VCLK: 1160 ret = smu_cmn_send_smc_msg_with_param(smu, 1161 SMU_MSG_SetHardMinVcn, 1162 min << 16, NULL); 1163 if (ret) 1164 return ret; 1165 ret = smu_cmn_send_smc_msg_with_param(smu, 1166 SMU_MSG_SetSoftMaxVcn, 1167 max << 16, NULL); 1168 if (ret) 1169 return ret; 1170 break; 1171 case SMU_DCLK: 1172 ret = smu_cmn_send_smc_msg_with_param(smu, 1173 SMU_MSG_SetHardMinVcn, 1174 min, NULL); 1175 if (ret) 1176 return ret; 1177 ret = smu_cmn_send_smc_msg_with_param(smu, 1178 SMU_MSG_SetSoftMaxVcn, 1179 max, NULL); 1180 if (ret) 1181 return ret; 1182 break; 1183 default: 1184 return -EINVAL; 1185 } 1186 1187 return ret; 1188 } 1189 1190 static int vangogh_force_clk_levels(struct smu_context *smu, 1191 enum smu_clk_type clk_type, uint32_t mask) 1192 { 1193 uint32_t soft_min_level = 0, soft_max_level = 0; 1194 uint32_t min_freq = 0, max_freq = 0; 1195 int ret = 0 ; 1196 1197 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1198 soft_max_level = mask ? (fls(mask) - 1) : 0; 1199 1200 switch (clk_type) { 1201 case SMU_SOCCLK: 1202 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1203 soft_min_level, &min_freq); 1204 if (ret) 1205 return ret; 1206 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1207 soft_max_level, &max_freq); 1208 if (ret) 1209 return ret; 1210 ret = smu_cmn_send_smc_msg_with_param(smu, 1211 SMU_MSG_SetSoftMaxSocclkByFreq, 1212 max_freq, NULL); 1213 if (ret) 1214 return ret; 1215 ret = smu_cmn_send_smc_msg_with_param(smu, 1216 SMU_MSG_SetHardMinSocclkByFreq, 1217 min_freq, NULL); 1218 if (ret) 1219 return ret; 1220 break; 1221 case SMU_FCLK: 1222 ret = vangogh_get_dpm_clk_limited(smu, 1223 clk_type, soft_min_level, &min_freq); 1224 if (ret) 1225 return ret; 1226 ret = vangogh_get_dpm_clk_limited(smu, 1227 clk_type, soft_max_level, &max_freq); 1228 if (ret) 1229 return ret; 1230 ret = smu_cmn_send_smc_msg_with_param(smu, 1231 SMU_MSG_SetSoftMaxFclkByFreq, 1232 max_freq, NULL); 1233 if (ret) 1234 return ret; 1235 ret = smu_cmn_send_smc_msg_with_param(smu, 1236 SMU_MSG_SetHardMinFclkByFreq, 1237 min_freq, NULL); 1238 if (ret) 1239 return ret; 1240 break; 1241 case SMU_VCLK: 1242 ret = vangogh_get_dpm_clk_limited(smu, 1243 clk_type, soft_min_level, &min_freq); 1244 if (ret) 1245 return ret; 1246 1247 ret = vangogh_get_dpm_clk_limited(smu, 1248 clk_type, soft_max_level, &max_freq); 1249 if (ret) 1250 return ret; 1251 1252 1253 ret = smu_cmn_send_smc_msg_with_param(smu, 1254 SMU_MSG_SetHardMinVcn, 1255 min_freq << 16, NULL); 1256 if (ret) 1257 return ret; 1258 1259 ret = smu_cmn_send_smc_msg_with_param(smu, 1260 SMU_MSG_SetSoftMaxVcn, 1261 max_freq << 16, NULL); 1262 if (ret) 1263 return ret; 1264 1265 break; 1266 case SMU_DCLK: 1267 ret = vangogh_get_dpm_clk_limited(smu, 1268 clk_type, soft_min_level, &min_freq); 1269 if (ret) 1270 return ret; 1271 1272 ret = vangogh_get_dpm_clk_limited(smu, 1273 clk_type, soft_max_level, &max_freq); 1274 if (ret) 1275 return ret; 1276 1277 ret = smu_cmn_send_smc_msg_with_param(smu, 1278 SMU_MSG_SetHardMinVcn, 1279 min_freq, NULL); 1280 if (ret) 1281 return ret; 1282 1283 ret = smu_cmn_send_smc_msg_with_param(smu, 1284 SMU_MSG_SetSoftMaxVcn, 1285 max_freq, NULL); 1286 if (ret) 1287 return ret; 1288 1289 break; 1290 default: 1291 break; 1292 } 1293 1294 return ret; 1295 } 1296 1297 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1298 { 1299 int ret = 0, i = 0; 1300 uint32_t min_freq, max_freq, force_freq; 1301 enum smu_clk_type clk_type; 1302 1303 enum smu_clk_type clks[] = { 1304 SMU_SOCCLK, 1305 SMU_VCLK, 1306 SMU_DCLK, 1307 SMU_FCLK, 1308 }; 1309 1310 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1311 clk_type = clks[i]; 1312 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1313 if (ret) 1314 return ret; 1315 1316 force_freq = highest ? max_freq : min_freq; 1317 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1318 if (ret) 1319 return ret; 1320 } 1321 1322 return ret; 1323 } 1324 1325 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1326 { 1327 int ret = 0, i = 0; 1328 uint32_t min_freq, max_freq; 1329 enum smu_clk_type clk_type; 1330 1331 struct clk_feature_map { 1332 enum smu_clk_type clk_type; 1333 uint32_t feature; 1334 } clk_feature_map[] = { 1335 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1336 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1337 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1338 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1339 }; 1340 1341 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1342 1343 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1344 continue; 1345 1346 clk_type = clk_feature_map[i].clk_type; 1347 1348 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1349 1350 if (ret) 1351 return ret; 1352 1353 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1354 1355 if (ret) 1356 return ret; 1357 } 1358 1359 return ret; 1360 } 1361 1362 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1363 { 1364 int ret = 0; 1365 uint32_t socclk_freq = 0, fclk_freq = 0; 1366 uint32_t vclk_freq = 0, dclk_freq = 0; 1367 1368 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1369 if (ret) 1370 return ret; 1371 1372 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1373 if (ret) 1374 return ret; 1375 1376 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1377 if (ret) 1378 return ret; 1379 1380 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1381 if (ret) 1382 return ret; 1383 1384 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1385 if (ret) 1386 return ret; 1387 1388 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1389 if (ret) 1390 return ret; 1391 1392 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1393 if (ret) 1394 return ret; 1395 1396 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1397 if (ret) 1398 return ret; 1399 1400 return ret; 1401 } 1402 1403 static int vangogh_set_performance_level(struct smu_context *smu, 1404 enum amd_dpm_forced_level level) 1405 { 1406 int ret = 0, i; 1407 uint32_t soc_mask, mclk_mask, fclk_mask; 1408 uint32_t vclk_mask = 0, dclk_mask = 0; 1409 1410 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1411 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1412 1413 switch (level) { 1414 case AMD_DPM_FORCED_LEVEL_HIGH: 1415 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq; 1416 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1417 1418 1419 ret = vangogh_force_dpm_limit_value(smu, true); 1420 if (ret) 1421 return ret; 1422 break; 1423 case AMD_DPM_FORCED_LEVEL_LOW: 1424 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1425 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1426 1427 ret = vangogh_force_dpm_limit_value(smu, false); 1428 if (ret) 1429 return ret; 1430 break; 1431 case AMD_DPM_FORCED_LEVEL_AUTO: 1432 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1433 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1434 1435 ret = vangogh_unforce_dpm_levels(smu); 1436 if (ret) 1437 return ret; 1438 break; 1439 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1440 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1441 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1442 1443 ret = vangogh_get_profiling_clk_mask(smu, level, 1444 &vclk_mask, 1445 &dclk_mask, 1446 &mclk_mask, 1447 &fclk_mask, 1448 &soc_mask); 1449 if (ret) 1450 return ret; 1451 1452 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1453 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1454 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1455 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1456 break; 1457 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1458 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1459 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1460 break; 1461 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1462 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1463 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1464 1465 ret = vangogh_get_profiling_clk_mask(smu, level, 1466 NULL, 1467 NULL, 1468 &mclk_mask, 1469 &fclk_mask, 1470 NULL); 1471 if (ret) 1472 return ret; 1473 1474 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1475 break; 1476 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1477 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1478 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1479 1480 ret = vangogh_set_peak_clock_by_device(smu); 1481 if (ret) 1482 return ret; 1483 break; 1484 case AMD_DPM_FORCED_LEVEL_MANUAL: 1485 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1486 default: 1487 return 0; 1488 } 1489 1490 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1491 smu->gfx_actual_hard_min_freq, NULL); 1492 if (ret) 1493 return ret; 1494 1495 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1496 smu->gfx_actual_soft_max_freq, NULL); 1497 if (ret) 1498 return ret; 1499 1500 if (smu->adev->pm.fw_version >= 0x43f1b00) { 1501 for (i = 0; i < smu->cpu_core_num; i++) { 1502 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1503 ((i << 20) 1504 | smu->cpu_actual_soft_min_freq), 1505 NULL); 1506 if (ret) 1507 return ret; 1508 1509 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1510 ((i << 20) 1511 | smu->cpu_actual_soft_max_freq), 1512 NULL); 1513 if (ret) 1514 return ret; 1515 } 1516 } 1517 1518 return ret; 1519 } 1520 1521 static int vangogh_read_sensor(struct smu_context *smu, 1522 enum amd_pp_sensors sensor, 1523 void *data, uint32_t *size) 1524 { 1525 int ret = 0; 1526 1527 if (!data || !size) 1528 return -EINVAL; 1529 1530 switch (sensor) { 1531 case AMDGPU_PP_SENSOR_GPU_LOAD: 1532 ret = vangogh_common_get_smu_metrics_data(smu, 1533 METRICS_AVERAGE_GFXACTIVITY, 1534 (uint32_t *)data); 1535 *size = 4; 1536 break; 1537 case AMDGPU_PP_SENSOR_GPU_POWER: 1538 ret = vangogh_common_get_smu_metrics_data(smu, 1539 METRICS_AVERAGE_SOCKETPOWER, 1540 (uint32_t *)data); 1541 *size = 4; 1542 break; 1543 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1544 ret = vangogh_common_get_smu_metrics_data(smu, 1545 METRICS_TEMPERATURE_EDGE, 1546 (uint32_t *)data); 1547 *size = 4; 1548 break; 1549 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1550 ret = vangogh_common_get_smu_metrics_data(smu, 1551 METRICS_TEMPERATURE_HOTSPOT, 1552 (uint32_t *)data); 1553 *size = 4; 1554 break; 1555 case AMDGPU_PP_SENSOR_GFX_MCLK: 1556 ret = vangogh_common_get_smu_metrics_data(smu, 1557 METRICS_CURR_UCLK, 1558 (uint32_t *)data); 1559 *(uint32_t *)data *= 100; 1560 *size = 4; 1561 break; 1562 case AMDGPU_PP_SENSOR_GFX_SCLK: 1563 ret = vangogh_common_get_smu_metrics_data(smu, 1564 METRICS_CURR_GFXCLK, 1565 (uint32_t *)data); 1566 *(uint32_t *)data *= 100; 1567 *size = 4; 1568 break; 1569 case AMDGPU_PP_SENSOR_VDDGFX: 1570 ret = vangogh_common_get_smu_metrics_data(smu, 1571 METRICS_VOLTAGE_VDDGFX, 1572 (uint32_t *)data); 1573 *size = 4; 1574 break; 1575 case AMDGPU_PP_SENSOR_VDDNB: 1576 ret = vangogh_common_get_smu_metrics_data(smu, 1577 METRICS_VOLTAGE_VDDSOC, 1578 (uint32_t *)data); 1579 *size = 4; 1580 break; 1581 case AMDGPU_PP_SENSOR_CPU_CLK: 1582 ret = vangogh_common_get_smu_metrics_data(smu, 1583 METRICS_AVERAGE_CPUCLK, 1584 (uint32_t *)data); 1585 *size = smu->cpu_core_num * sizeof(uint16_t); 1586 break; 1587 default: 1588 ret = -EOPNOTSUPP; 1589 break; 1590 } 1591 1592 return ret; 1593 } 1594 1595 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit) 1596 { 1597 return smu_cmn_send_smc_msg_with_param(smu, 1598 SMU_MSG_GetThermalLimit, 1599 0, limit); 1600 } 1601 1602 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit) 1603 { 1604 return smu_cmn_send_smc_msg_with_param(smu, 1605 SMU_MSG_SetReducedThermalLimit, 1606 limit, NULL); 1607 } 1608 1609 1610 static int vangogh_set_watermarks_table(struct smu_context *smu, 1611 struct pp_smu_wm_range_sets *clock_ranges) 1612 { 1613 int i; 1614 int ret = 0; 1615 Watermarks_t *table = smu->smu_table.watermarks_table; 1616 1617 if (!table || !clock_ranges) 1618 return -EINVAL; 1619 1620 if (clock_ranges) { 1621 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1622 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1623 return -EINVAL; 1624 1625 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1626 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1627 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1628 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1629 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1630 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1631 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1632 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1633 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1634 1635 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1636 clock_ranges->reader_wm_sets[i].wm_inst; 1637 } 1638 1639 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1640 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1641 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1642 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1643 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1644 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1645 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1646 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1647 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1648 1649 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1650 clock_ranges->writer_wm_sets[i].wm_inst; 1651 } 1652 1653 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1654 } 1655 1656 /* pass data to smu controller */ 1657 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1658 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1659 ret = smu_cmn_write_watermarks_table(smu); 1660 if (ret) { 1661 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1662 return ret; 1663 } 1664 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu, 1671 void **table) 1672 { 1673 struct smu_table_context *smu_table = &smu->smu_table; 1674 struct gpu_metrics_v2_3 *gpu_metrics = 1675 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1676 SmuMetrics_legacy_t metrics; 1677 int ret = 0; 1678 1679 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1680 if (ret) 1681 return ret; 1682 1683 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1684 1685 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1686 gpu_metrics->temperature_soc = metrics.SocTemperature; 1687 memcpy(&gpu_metrics->temperature_core[0], 1688 &metrics.CoreTemperature[0], 1689 sizeof(uint16_t) * 4); 1690 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1691 1692 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1693 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1694 1695 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1696 gpu_metrics->average_cpu_power = metrics.Power[0]; 1697 gpu_metrics->average_soc_power = metrics.Power[1]; 1698 gpu_metrics->average_gfx_power = metrics.Power[2]; 1699 memcpy(&gpu_metrics->average_core_power[0], 1700 &metrics.CorePower[0], 1701 sizeof(uint16_t) * 4); 1702 1703 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1704 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1705 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1706 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1707 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1708 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1709 1710 memcpy(&gpu_metrics->current_coreclk[0], 1711 &metrics.CoreFrequency[0], 1712 sizeof(uint16_t) * 4); 1713 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1714 1715 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1716 gpu_metrics->indep_throttle_status = 1717 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1718 vangogh_throttler_map); 1719 1720 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1721 1722 *table = (void *)gpu_metrics; 1723 1724 return sizeof(struct gpu_metrics_v2_3); 1725 } 1726 1727 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, 1728 void **table) 1729 { 1730 struct smu_table_context *smu_table = &smu->smu_table; 1731 struct gpu_metrics_v2_2 *gpu_metrics = 1732 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1733 SmuMetrics_legacy_t metrics; 1734 int ret = 0; 1735 1736 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1737 if (ret) 1738 return ret; 1739 1740 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1741 1742 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1743 gpu_metrics->temperature_soc = metrics.SocTemperature; 1744 memcpy(&gpu_metrics->temperature_core[0], 1745 &metrics.CoreTemperature[0], 1746 sizeof(uint16_t) * 4); 1747 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1748 1749 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1750 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1751 1752 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1753 gpu_metrics->average_cpu_power = metrics.Power[0]; 1754 gpu_metrics->average_soc_power = metrics.Power[1]; 1755 gpu_metrics->average_gfx_power = metrics.Power[2]; 1756 memcpy(&gpu_metrics->average_core_power[0], 1757 &metrics.CorePower[0], 1758 sizeof(uint16_t) * 4); 1759 1760 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1761 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1762 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1763 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1764 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1765 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1766 1767 memcpy(&gpu_metrics->current_coreclk[0], 1768 &metrics.CoreFrequency[0], 1769 sizeof(uint16_t) * 4); 1770 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1771 1772 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1773 gpu_metrics->indep_throttle_status = 1774 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1775 vangogh_throttler_map); 1776 1777 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1778 1779 *table = (void *)gpu_metrics; 1780 1781 return sizeof(struct gpu_metrics_v2_2); 1782 } 1783 1784 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu, 1785 void **table) 1786 { 1787 struct smu_table_context *smu_table = &smu->smu_table; 1788 struct gpu_metrics_v2_3 *gpu_metrics = 1789 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1790 SmuMetrics_t metrics; 1791 int ret = 0; 1792 1793 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1794 if (ret) 1795 return ret; 1796 1797 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1798 1799 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1800 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1801 memcpy(&gpu_metrics->temperature_core[0], 1802 &metrics.Current.CoreTemperature[0], 1803 sizeof(uint16_t) * 4); 1804 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1805 1806 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature; 1807 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature; 1808 memcpy(&gpu_metrics->average_temperature_core[0], 1809 &metrics.Average.CoreTemperature[0], 1810 sizeof(uint16_t) * 4); 1811 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0]; 1812 1813 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1814 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1815 1816 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1817 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1818 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1819 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1820 memcpy(&gpu_metrics->average_core_power[0], 1821 &metrics.Average.CorePower[0], 1822 sizeof(uint16_t) * 4); 1823 1824 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1825 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1826 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1827 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1828 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1829 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1830 1831 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1832 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1833 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1834 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1835 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1836 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1837 1838 memcpy(&gpu_metrics->current_coreclk[0], 1839 &metrics.Current.CoreFrequency[0], 1840 sizeof(uint16_t) * 4); 1841 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1842 1843 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1844 gpu_metrics->indep_throttle_status = 1845 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1846 vangogh_throttler_map); 1847 1848 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1849 1850 *table = (void *)gpu_metrics; 1851 1852 return sizeof(struct gpu_metrics_v2_3); 1853 } 1854 1855 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1856 void **table) 1857 { 1858 struct smu_table_context *smu_table = &smu->smu_table; 1859 struct gpu_metrics_v2_2 *gpu_metrics = 1860 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1861 SmuMetrics_t metrics; 1862 int ret = 0; 1863 1864 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1865 if (ret) 1866 return ret; 1867 1868 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1869 1870 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1871 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1872 memcpy(&gpu_metrics->temperature_core[0], 1873 &metrics.Current.CoreTemperature[0], 1874 sizeof(uint16_t) * 4); 1875 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1876 1877 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1878 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1879 1880 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1881 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1882 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1883 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1884 memcpy(&gpu_metrics->average_core_power[0], 1885 &metrics.Average.CorePower[0], 1886 sizeof(uint16_t) * 4); 1887 1888 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1889 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1890 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1891 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1892 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1893 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1894 1895 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1896 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1897 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1898 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1899 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1900 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1901 1902 memcpy(&gpu_metrics->current_coreclk[0], 1903 &metrics.Current.CoreFrequency[0], 1904 sizeof(uint16_t) * 4); 1905 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1906 1907 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1908 gpu_metrics->indep_throttle_status = 1909 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1910 vangogh_throttler_map); 1911 1912 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1913 1914 *table = (void *)gpu_metrics; 1915 1916 return sizeof(struct gpu_metrics_v2_2); 1917 } 1918 1919 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, 1920 void **table) 1921 { 1922 uint32_t if_version; 1923 uint32_t smu_version; 1924 int ret = 0; 1925 1926 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 1927 if (ret) { 1928 return ret; 1929 } 1930 1931 if (smu_version >= 0x043F3E00) { 1932 if (if_version < 0x3) 1933 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table); 1934 else 1935 ret = vangogh_get_gpu_metrics_v2_3(smu, table); 1936 } else { 1937 if (if_version < 0x3) 1938 ret = vangogh_get_legacy_gpu_metrics(smu, table); 1939 else 1940 ret = vangogh_get_gpu_metrics(smu, table); 1941 } 1942 1943 return ret; 1944 } 1945 1946 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1947 long input[], uint32_t size) 1948 { 1949 int ret = 0; 1950 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1951 1952 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 1953 dev_warn(smu->adev->dev, 1954 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 1955 return -EINVAL; 1956 } 1957 1958 switch (type) { 1959 case PP_OD_EDIT_CCLK_VDDC_TABLE: 1960 if (size != 3) { 1961 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 1962 return -EINVAL; 1963 } 1964 if (input[0] >= smu->cpu_core_num) { 1965 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 1966 smu->cpu_core_num); 1967 } 1968 smu->cpu_core_id_select = input[0]; 1969 if (input[1] == 0) { 1970 if (input[2] < smu->cpu_default_soft_min_freq) { 1971 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1972 input[2], smu->cpu_default_soft_min_freq); 1973 return -EINVAL; 1974 } 1975 smu->cpu_actual_soft_min_freq = input[2]; 1976 } else if (input[1] == 1) { 1977 if (input[2] > smu->cpu_default_soft_max_freq) { 1978 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1979 input[2], smu->cpu_default_soft_max_freq); 1980 return -EINVAL; 1981 } 1982 smu->cpu_actual_soft_max_freq = input[2]; 1983 } else { 1984 return -EINVAL; 1985 } 1986 break; 1987 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1988 if (size != 2) { 1989 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1990 return -EINVAL; 1991 } 1992 1993 if (input[0] == 0) { 1994 if (input[1] < smu->gfx_default_hard_min_freq) { 1995 dev_warn(smu->adev->dev, 1996 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1997 input[1], smu->gfx_default_hard_min_freq); 1998 return -EINVAL; 1999 } 2000 smu->gfx_actual_hard_min_freq = input[1]; 2001 } else if (input[0] == 1) { 2002 if (input[1] > smu->gfx_default_soft_max_freq) { 2003 dev_warn(smu->adev->dev, 2004 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2005 input[1], smu->gfx_default_soft_max_freq); 2006 return -EINVAL; 2007 } 2008 smu->gfx_actual_soft_max_freq = input[1]; 2009 } else { 2010 return -EINVAL; 2011 } 2012 break; 2013 case PP_OD_RESTORE_DEFAULT_TABLE: 2014 if (size != 0) { 2015 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2016 return -EINVAL; 2017 } else { 2018 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 2019 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 2020 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 2021 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 2022 } 2023 break; 2024 case PP_OD_COMMIT_DPM_TABLE: 2025 if (size != 0) { 2026 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2027 return -EINVAL; 2028 } else { 2029 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 2030 dev_err(smu->adev->dev, 2031 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 2032 smu->gfx_actual_hard_min_freq, 2033 smu->gfx_actual_soft_max_freq); 2034 return -EINVAL; 2035 } 2036 2037 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 2038 smu->gfx_actual_hard_min_freq, NULL); 2039 if (ret) { 2040 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 2041 return ret; 2042 } 2043 2044 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 2045 smu->gfx_actual_soft_max_freq, NULL); 2046 if (ret) { 2047 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 2048 return ret; 2049 } 2050 2051 if (smu->adev->pm.fw_version < 0x43f1b00) { 2052 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 2053 break; 2054 } 2055 2056 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 2057 ((smu->cpu_core_id_select << 20) 2058 | smu->cpu_actual_soft_min_freq), 2059 NULL); 2060 if (ret) { 2061 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 2062 return ret; 2063 } 2064 2065 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 2066 ((smu->cpu_core_id_select << 20) 2067 | smu->cpu_actual_soft_max_freq), 2068 NULL); 2069 if (ret) { 2070 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 2071 return ret; 2072 } 2073 } 2074 break; 2075 default: 2076 return -ENOSYS; 2077 } 2078 2079 return ret; 2080 } 2081 2082 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 2083 { 2084 struct smu_table_context *smu_table = &smu->smu_table; 2085 2086 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 2087 } 2088 2089 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 2090 { 2091 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 2092 2093 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 2094 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 2095 smu->gfx_actual_hard_min_freq = 0; 2096 smu->gfx_actual_soft_max_freq = 0; 2097 2098 smu->cpu_default_soft_min_freq = 1400; 2099 smu->cpu_default_soft_max_freq = 3500; 2100 smu->cpu_actual_soft_min_freq = 0; 2101 smu->cpu_actual_soft_max_freq = 0; 2102 2103 return 0; 2104 } 2105 2106 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 2107 { 2108 DpmClocks_t *table = smu->smu_table.clocks_table; 2109 int i; 2110 2111 if (!clock_table || !table) 2112 return -EINVAL; 2113 2114 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 2115 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 2116 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 2117 } 2118 2119 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2120 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 2121 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 2122 } 2123 2124 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2125 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 2126 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 2127 } 2128 2129 return 0; 2130 } 2131 2132 2133 static int vangogh_system_features_control(struct smu_context *smu, bool en) 2134 { 2135 struct amdgpu_device *adev = smu->adev; 2136 int ret = 0; 2137 2138 if (adev->pm.fw_version >= 0x43f1700 && !en) 2139 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 2140 RLC_STATUS_OFF, NULL); 2141 2142 return ret; 2143 } 2144 2145 static int vangogh_post_smu_init(struct smu_context *smu) 2146 { 2147 struct amdgpu_device *adev = smu->adev; 2148 uint32_t tmp; 2149 int ret = 0; 2150 uint8_t aon_bits = 0; 2151 /* Two CUs in one WGP */ 2152 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 2153 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 2154 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2155 2156 /* allow message will be sent after enable message on Vangogh*/ 2157 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 2158 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2159 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 2160 if (ret) { 2161 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 2162 return ret; 2163 } 2164 } else { 2165 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 2166 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 2167 } 2168 2169 /* if all CUs are active, no need to power off any WGPs */ 2170 if (total_cu == adev->gfx.cu_info.number) 2171 return 0; 2172 2173 /* 2174 * Calculate the total bits number of always on WGPs for all SA/SEs in 2175 * RLC_PG_ALWAYS_ON_WGP_MASK. 2176 */ 2177 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 2178 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 2179 2180 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2181 2182 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 2183 if (aon_bits > req_active_wgps) { 2184 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 2185 return 0; 2186 } else { 2187 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 2188 } 2189 } 2190 2191 static int vangogh_mode_reset(struct smu_context *smu, int type) 2192 { 2193 int ret = 0, index = 0; 2194 2195 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2196 SMU_MSG_GfxDeviceDriverReset); 2197 if (index < 0) 2198 return index == -EACCES ? 0 : index; 2199 2200 mutex_lock(&smu->message_lock); 2201 2202 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 2203 2204 mutex_unlock(&smu->message_lock); 2205 2206 mdelay(10); 2207 2208 return ret; 2209 } 2210 2211 static int vangogh_mode2_reset(struct smu_context *smu) 2212 { 2213 return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 2214 } 2215 2216 /** 2217 * vangogh_get_gfxoff_status - Get gfxoff status 2218 * 2219 * @smu: amdgpu_device pointer 2220 * 2221 * Get current gfxoff status 2222 * 2223 * Return: 2224 * * 0 - GFXOFF (default if enabled). 2225 * * 1 - Transition out of GFX State. 2226 * * 2 - Not in GFXOFF. 2227 * * 3 - Transition into GFXOFF. 2228 */ 2229 static u32 vangogh_get_gfxoff_status(struct smu_context *smu) 2230 { 2231 struct amdgpu_device *adev = smu->adev; 2232 u32 reg, gfxoff_status; 2233 2234 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL); 2235 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK) 2236 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT; 2237 2238 return gfxoff_status; 2239 } 2240 2241 static int vangogh_get_power_limit(struct smu_context *smu, 2242 uint32_t *current_power_limit, 2243 uint32_t *default_power_limit, 2244 uint32_t *max_power_limit) 2245 { 2246 struct smu_11_5_power_context *power_context = 2247 smu->smu_power.power_context; 2248 uint32_t ppt_limit; 2249 int ret = 0; 2250 2251 if (smu->adev->pm.fw_version < 0x43f1e00) 2252 return ret; 2253 2254 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 2255 if (ret) { 2256 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 2257 return ret; 2258 } 2259 /* convert from milliwatt to watt */ 2260 if (current_power_limit) 2261 *current_power_limit = ppt_limit / 1000; 2262 if (default_power_limit) 2263 *default_power_limit = ppt_limit / 1000; 2264 if (max_power_limit) 2265 *max_power_limit = 29; 2266 2267 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 2268 if (ret) { 2269 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 2270 return ret; 2271 } 2272 /* convert from milliwatt to watt */ 2273 power_context->current_fast_ppt_limit = 2274 power_context->default_fast_ppt_limit = ppt_limit / 1000; 2275 power_context->max_fast_ppt_limit = 30; 2276 2277 return ret; 2278 } 2279 2280 static int vangogh_get_ppt_limit(struct smu_context *smu, 2281 uint32_t *ppt_limit, 2282 enum smu_ppt_limit_type type, 2283 enum smu_ppt_limit_level level) 2284 { 2285 struct smu_11_5_power_context *power_context = 2286 smu->smu_power.power_context; 2287 2288 if (!power_context) 2289 return -EOPNOTSUPP; 2290 2291 if (type == SMU_FAST_PPT_LIMIT) { 2292 switch (level) { 2293 case SMU_PPT_LIMIT_MAX: 2294 *ppt_limit = power_context->max_fast_ppt_limit; 2295 break; 2296 case SMU_PPT_LIMIT_CURRENT: 2297 *ppt_limit = power_context->current_fast_ppt_limit; 2298 break; 2299 case SMU_PPT_LIMIT_DEFAULT: 2300 *ppt_limit = power_context->default_fast_ppt_limit; 2301 break; 2302 default: 2303 break; 2304 } 2305 } 2306 2307 return 0; 2308 } 2309 2310 static int vangogh_set_power_limit(struct smu_context *smu, 2311 enum smu_ppt_limit_type limit_type, 2312 uint32_t ppt_limit) 2313 { 2314 struct smu_11_5_power_context *power_context = 2315 smu->smu_power.power_context; 2316 int ret = 0; 2317 2318 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 2319 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 2320 return -EOPNOTSUPP; 2321 } 2322 2323 switch (limit_type) { 2324 case SMU_DEFAULT_PPT_LIMIT: 2325 ret = smu_cmn_send_smc_msg_with_param(smu, 2326 SMU_MSG_SetSlowPPTLimit, 2327 ppt_limit * 1000, /* convert from watt to milliwatt */ 2328 NULL); 2329 if (ret) 2330 return ret; 2331 2332 smu->current_power_limit = ppt_limit; 2333 break; 2334 case SMU_FAST_PPT_LIMIT: 2335 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 2336 if (ppt_limit > power_context->max_fast_ppt_limit) { 2337 dev_err(smu->adev->dev, 2338 "New power limit (%d) is over the max allowed %d\n", 2339 ppt_limit, power_context->max_fast_ppt_limit); 2340 return ret; 2341 } 2342 2343 ret = smu_cmn_send_smc_msg_with_param(smu, 2344 SMU_MSG_SetFastPPTLimit, 2345 ppt_limit * 1000, /* convert from watt to milliwatt */ 2346 NULL); 2347 if (ret) 2348 return ret; 2349 2350 power_context->current_fast_ppt_limit = ppt_limit; 2351 break; 2352 default: 2353 return -EINVAL; 2354 } 2355 2356 return ret; 2357 } 2358 2359 /** 2360 * vangogh_set_gfxoff_residency 2361 * 2362 * @smu: amdgpu_device pointer 2363 * @start: start/stop residency log 2364 * 2365 * This function will be used to log gfxoff residency 2366 * 2367 * 2368 * Returns standard response codes. 2369 */ 2370 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start) 2371 { 2372 int ret = 0; 2373 u32 residency; 2374 struct amdgpu_device *adev = smu->adev; 2375 2376 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2377 return 0; 2378 2379 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency, 2380 start, &residency); 2381 2382 if (!start) 2383 adev->gfx.gfx_off_residency = residency; 2384 2385 return ret; 2386 } 2387 2388 /** 2389 * vangogh_get_gfxoff_residency 2390 * 2391 * @smu: amdgpu_device pointer 2392 * 2393 * This function will be used to get gfxoff residency. 2394 * 2395 * Returns standard response codes. 2396 */ 2397 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency) 2398 { 2399 struct amdgpu_device *adev = smu->adev; 2400 2401 *residency = adev->gfx.gfx_off_residency; 2402 2403 return 0; 2404 } 2405 2406 /** 2407 * vangogh_get_gfxoff_entrycount - get gfxoff entry count 2408 * 2409 * @smu: amdgpu_device pointer 2410 * 2411 * This function will be used to get gfxoff entry count 2412 * 2413 * Returns standard response codes. 2414 */ 2415 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount) 2416 { 2417 int ret = 0, value = 0; 2418 struct amdgpu_device *adev = smu->adev; 2419 2420 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2421 return 0; 2422 2423 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value); 2424 *entrycount = value + adev->gfx.gfx_off_entrycount; 2425 2426 return ret; 2427 } 2428 2429 static const struct pptable_funcs vangogh_ppt_funcs = { 2430 2431 .check_fw_status = smu_v11_0_check_fw_status, 2432 .check_fw_version = smu_v11_0_check_fw_version, 2433 .init_smc_tables = vangogh_init_smc_tables, 2434 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2435 .init_power = smu_v11_0_init_power, 2436 .fini_power = smu_v11_0_fini_power, 2437 .register_irq_handler = smu_v11_0_register_irq_handler, 2438 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2439 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2440 .send_smc_msg = smu_cmn_send_smc_msg, 2441 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 2442 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 2443 .is_dpm_running = vangogh_is_dpm_running, 2444 .read_sensor = vangogh_read_sensor, 2445 .get_apu_thermal_limit = vangogh_get_apu_thermal_limit, 2446 .set_apu_thermal_limit = vangogh_set_apu_thermal_limit, 2447 .get_enabled_mask = smu_cmn_get_enabled_mask, 2448 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2449 .set_watermarks_table = vangogh_set_watermarks_table, 2450 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2451 .interrupt_work = smu_v11_0_interrupt_work, 2452 .get_gpu_metrics = vangogh_common_get_gpu_metrics, 2453 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 2454 .print_clk_levels = vangogh_common_print_clk_levels, 2455 .set_default_dpm_table = vangogh_set_default_dpm_tables, 2456 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 2457 .system_features_control = vangogh_system_features_control, 2458 .feature_is_enabled = smu_cmn_feature_is_enabled, 2459 .set_power_profile_mode = vangogh_set_power_profile_mode, 2460 .get_power_profile_mode = vangogh_get_power_profile_mode, 2461 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 2462 .force_clk_levels = vangogh_force_clk_levels, 2463 .set_performance_level = vangogh_set_performance_level, 2464 .post_init = vangogh_post_smu_init, 2465 .mode2_reset = vangogh_mode2_reset, 2466 .gfx_off_control = smu_v11_0_gfx_off_control, 2467 .get_gfx_off_status = vangogh_get_gfxoff_status, 2468 .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount, 2469 .get_gfx_off_residency = vangogh_get_gfxoff_residency, 2470 .set_gfx_off_residency = vangogh_set_gfxoff_residency, 2471 .get_ppt_limit = vangogh_get_ppt_limit, 2472 .get_power_limit = vangogh_get_power_limit, 2473 .set_power_limit = vangogh_set_power_limit, 2474 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2475 }; 2476 2477 void vangogh_set_ppt_funcs(struct smu_context *smu) 2478 { 2479 smu->ppt_funcs = &vangogh_ppt_funcs; 2480 smu->message_map = vangogh_message_map; 2481 smu->feature_map = vangogh_feature_mask_map; 2482 smu->table_map = vangogh_table_map; 2483 smu->workload_map = vangogh_workload_map; 2484 smu->is_apu = true; 2485 smu_v11_0_set_smu_mailbox_registers(smu); 2486 } 2487