1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 #include <asm/processor.h> 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 #define FEATURE_MASK(feature) (1ULL << feature) 50 #define SMC_DPM_FEATURE ( \ 51 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 52 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 53 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 54 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 55 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 56 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 57 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 58 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 59 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 60 61 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 62 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 63 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 64 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 65 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 66 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 67 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 68 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 69 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 70 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 71 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 72 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 73 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 74 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 75 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 76 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 77 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 78 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 79 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 80 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 81 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 82 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 83 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 84 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 85 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 86 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 87 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 88 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 89 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 95 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 96 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 97 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 98 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 99 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 100 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 101 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 102 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 103 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 104 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 105 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 106 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 107 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 108 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 109 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 110 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 111 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 112 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 113 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 114 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 115 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 116 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 117 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 118 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 119 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 120 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 121 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 122 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 123 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 124 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 125 }; 126 127 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 128 FEA_MAP(PPT), 129 FEA_MAP(TDC), 130 FEA_MAP(THERMAL), 131 FEA_MAP(DS_GFXCLK), 132 FEA_MAP(DS_SOCCLK), 133 FEA_MAP(DS_LCLK), 134 FEA_MAP(DS_FCLK), 135 FEA_MAP(DS_MP1CLK), 136 FEA_MAP(DS_MP0CLK), 137 FEA_MAP(ATHUB_PG), 138 FEA_MAP(CCLK_DPM), 139 FEA_MAP(FAN_CONTROLLER), 140 FEA_MAP(ULV), 141 FEA_MAP(VCN_DPM), 142 FEA_MAP(LCLK_DPM), 143 FEA_MAP(SHUBCLK_DPM), 144 FEA_MAP(DCFCLK_DPM), 145 FEA_MAP(DS_DCFCLK), 146 FEA_MAP(S0I2), 147 FEA_MAP(SMU_LOW_POWER), 148 FEA_MAP(GFX_DEM), 149 FEA_MAP(PSI), 150 FEA_MAP(PROCHOT), 151 FEA_MAP(CPUOFF), 152 FEA_MAP(STAPM), 153 FEA_MAP(S0I3), 154 FEA_MAP(DF_CSTATES), 155 FEA_MAP(PERF_LIMIT), 156 FEA_MAP(CORE_DLDO), 157 FEA_MAP(RSMU_LOW_POWER), 158 FEA_MAP(SMN_LOW_POWER), 159 FEA_MAP(THM_LOW_POWER), 160 FEA_MAP(SMUIO_LOW_POWER), 161 FEA_MAP(MP1_LOW_POWER), 162 FEA_MAP(DS_VCN), 163 FEA_MAP(CPPC), 164 FEA_MAP(OS_CSTATES), 165 FEA_MAP(ISP_DPM), 166 FEA_MAP(A55_DPM), 167 FEA_MAP(CVIP_DSP_DPM), 168 FEA_MAP(MSMU_LOW_POWER), 169 FEA_MAP_REVERSE(SOCCLK), 170 FEA_MAP_REVERSE(FCLK), 171 FEA_MAP_HALF_REVERSE(GFX), 172 }; 173 174 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 175 TAB_MAP_VALID(WATERMARKS), 176 TAB_MAP_VALID(SMU_METRICS), 177 TAB_MAP_VALID(CUSTOM_DPM), 178 TAB_MAP_VALID(DPMCLOCKS), 179 }; 180 181 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 182 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 183 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 184 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 185 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 187 }; 188 189 static int vangogh_tables_init(struct smu_context *smu) 190 { 191 struct smu_table_context *smu_table = &smu->smu_table; 192 struct smu_table *tables = smu_table->tables; 193 194 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 195 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 196 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 197 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 198 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 199 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 200 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 201 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 202 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 203 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 204 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 205 if (!smu_table->metrics_table) 206 goto err0_out; 207 smu_table->metrics_time = 0; 208 209 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0); 210 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 211 if (!smu_table->gpu_metrics_table) 212 goto err1_out; 213 214 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 215 if (!smu_table->watermarks_table) 216 goto err2_out; 217 218 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 219 if (!smu_table->clocks_table) 220 goto err3_out; 221 222 return 0; 223 224 err3_out: 225 kfree(smu_table->clocks_table); 226 err2_out: 227 kfree(smu_table->gpu_metrics_table); 228 err1_out: 229 kfree(smu_table->metrics_table); 230 err0_out: 231 return -ENOMEM; 232 } 233 234 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 235 MetricsMember_t member, 236 uint32_t *value) 237 { 238 struct smu_table_context *smu_table = &smu->smu_table; 239 240 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 241 int ret = 0; 242 243 mutex_lock(&smu->metrics_lock); 244 245 ret = smu_cmn_get_metrics_table_locked(smu, 246 NULL, 247 false); 248 if (ret) { 249 mutex_unlock(&smu->metrics_lock); 250 return ret; 251 } 252 253 switch (member) { 254 case METRICS_AVERAGE_GFXCLK: 255 *value = metrics->GfxclkFrequency; 256 break; 257 case METRICS_AVERAGE_SOCCLK: 258 *value = metrics->SocclkFrequency; 259 break; 260 case METRICS_AVERAGE_VCLK: 261 *value = metrics->VclkFrequency; 262 break; 263 case METRICS_AVERAGE_DCLK: 264 *value = metrics->DclkFrequency; 265 break; 266 case METRICS_AVERAGE_UCLK: 267 *value = metrics->MemclkFrequency; 268 break; 269 case METRICS_AVERAGE_GFXACTIVITY: 270 *value = metrics->GfxActivity / 100; 271 break; 272 case METRICS_AVERAGE_VCNACTIVITY: 273 *value = metrics->UvdActivity; 274 break; 275 case METRICS_AVERAGE_SOCKETPOWER: 276 *value = (metrics->CurrentSocketPower << 8) / 277 1000 ; 278 break; 279 case METRICS_TEMPERATURE_EDGE: 280 *value = metrics->GfxTemperature / 100 * 281 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 282 break; 283 case METRICS_TEMPERATURE_HOTSPOT: 284 *value = metrics->SocTemperature / 100 * 285 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 286 break; 287 case METRICS_THROTTLER_STATUS: 288 *value = metrics->ThrottlerStatus; 289 break; 290 case METRICS_VOLTAGE_VDDGFX: 291 *value = metrics->Voltage[2]; 292 break; 293 case METRICS_VOLTAGE_VDDSOC: 294 *value = metrics->Voltage[1]; 295 break; 296 case METRICS_AVERAGE_CPUCLK: 297 memcpy(value, &metrics->CoreFrequency[0], 298 smu->cpu_core_num * sizeof(uint16_t)); 299 break; 300 default: 301 *value = UINT_MAX; 302 break; 303 } 304 305 mutex_unlock(&smu->metrics_lock); 306 307 return ret; 308 } 309 310 static int vangogh_allocate_dpm_context(struct smu_context *smu) 311 { 312 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 313 314 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 315 GFP_KERNEL); 316 if (!smu_dpm->dpm_context) 317 return -ENOMEM; 318 319 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 320 321 return 0; 322 } 323 324 static int vangogh_init_smc_tables(struct smu_context *smu) 325 { 326 int ret = 0; 327 328 ret = vangogh_tables_init(smu); 329 if (ret) 330 return ret; 331 332 ret = vangogh_allocate_dpm_context(smu); 333 if (ret) 334 return ret; 335 336 #ifdef CONFIG_X86 337 /* AMD x86 APU only */ 338 smu->cpu_core_num = boot_cpu_data.x86_max_cores; 339 #else 340 smu->cpu_core_num = 4; 341 #endif 342 343 return smu_v11_0_init_smc_tables(smu); 344 } 345 346 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 347 { 348 int ret = 0; 349 350 if (enable) { 351 /* vcn dpm on is a prerequisite for vcn power gate messages */ 352 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 353 if (ret) 354 return ret; 355 } else { 356 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 357 if (ret) 358 return ret; 359 } 360 361 return ret; 362 } 363 364 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 365 { 366 int ret = 0; 367 368 if (enable) { 369 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 370 if (ret) 371 return ret; 372 } else { 373 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 374 if (ret) 375 return ret; 376 } 377 378 return ret; 379 } 380 381 static bool vangogh_is_dpm_running(struct smu_context *smu) 382 { 383 int ret = 0; 384 uint32_t feature_mask[2]; 385 uint64_t feature_enabled; 386 387 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 388 389 if (ret) 390 return false; 391 392 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 393 ((uint64_t)feature_mask[1] << 32)); 394 395 return !!(feature_enabled & SMC_DPM_FEATURE); 396 } 397 398 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 399 uint32_t dpm_level, uint32_t *freq) 400 { 401 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 402 403 if (!clk_table || clk_type >= SMU_CLK_COUNT) 404 return -EINVAL; 405 406 switch (clk_type) { 407 case SMU_SOCCLK: 408 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 409 return -EINVAL; 410 *freq = clk_table->SocClocks[dpm_level]; 411 break; 412 case SMU_VCLK: 413 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 414 return -EINVAL; 415 *freq = clk_table->VcnClocks[dpm_level].vclk; 416 break; 417 case SMU_DCLK: 418 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 419 return -EINVAL; 420 *freq = clk_table->VcnClocks[dpm_level].dclk; 421 break; 422 case SMU_UCLK: 423 case SMU_MCLK: 424 if (dpm_level >= clk_table->NumDfPstatesEnabled) 425 return -EINVAL; 426 *freq = clk_table->DfPstateTable[dpm_level].memclk; 427 428 break; 429 case SMU_FCLK: 430 if (dpm_level >= clk_table->NumDfPstatesEnabled) 431 return -EINVAL; 432 *freq = clk_table->DfPstateTable[dpm_level].fclk; 433 break; 434 default: 435 return -EINVAL; 436 } 437 438 return 0; 439 } 440 441 static int vangogh_print_fine_grain_clk(struct smu_context *smu, 442 enum smu_clk_type clk_type, char *buf) 443 { 444 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 445 SmuMetrics_t metrics; 446 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 447 int i, size = 0, ret = 0; 448 uint32_t cur_value = 0, value = 0, count = 0; 449 bool cur_value_match_level = false; 450 451 memset(&metrics, 0, sizeof(metrics)); 452 453 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 454 if (ret) 455 return ret; 456 457 switch (clk_type) { 458 case SMU_OD_SCLK: 459 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 460 size = sprintf(buf, "%s:\n", "OD_SCLK"); 461 size += sprintf(buf + size, "0: %10uMhz\n", 462 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 463 size += sprintf(buf + size, "1: %10uMhz\n", 464 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 465 } 466 break; 467 case SMU_OD_CCLK: 468 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 469 size = sprintf(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 470 size += sprintf(buf + size, "0: %10uMhz\n", 471 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 472 size += sprintf(buf + size, "1: %10uMhz\n", 473 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 474 } 475 break; 476 case SMU_OD_RANGE: 477 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 478 size = sprintf(buf, "%s:\n", "OD_RANGE"); 479 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 480 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 481 size += sprintf(buf + size, "CCLK: %7uMhz %10uMhz\n", 482 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 483 } 484 break; 485 case SMU_SOCCLK: 486 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 487 count = clk_table->NumSocClkLevelsEnabled; 488 cur_value = metrics.SocclkFrequency; 489 break; 490 case SMU_VCLK: 491 count = clk_table->VcnClkLevelsEnabled; 492 cur_value = metrics.VclkFrequency; 493 break; 494 case SMU_DCLK: 495 count = clk_table->VcnClkLevelsEnabled; 496 cur_value = metrics.DclkFrequency; 497 break; 498 case SMU_MCLK: 499 count = clk_table->NumDfPstatesEnabled; 500 cur_value = metrics.MemclkFrequency; 501 break; 502 case SMU_FCLK: 503 count = clk_table->NumDfPstatesEnabled; 504 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 505 if (ret) 506 return ret; 507 break; 508 default: 509 break; 510 } 511 512 switch (clk_type) { 513 case SMU_SOCCLK: 514 case SMU_VCLK: 515 case SMU_DCLK: 516 case SMU_MCLK: 517 case SMU_FCLK: 518 for (i = 0; i < count; i++) { 519 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 520 if (ret) 521 return ret; 522 if (!value) 523 continue; 524 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 525 cur_value == value ? "*" : ""); 526 if (cur_value == value) 527 cur_value_match_level = true; 528 } 529 530 if (!cur_value_match_level) 531 size += sprintf(buf + size, " %uMhz *\n", cur_value); 532 break; 533 default: 534 break; 535 } 536 537 return size; 538 } 539 540 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 541 enum amd_dpm_forced_level level, 542 uint32_t *vclk_mask, 543 uint32_t *dclk_mask, 544 uint32_t *mclk_mask, 545 uint32_t *fclk_mask, 546 uint32_t *soc_mask) 547 { 548 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 549 550 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 551 if (mclk_mask) 552 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 553 554 if (fclk_mask) 555 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 556 557 if (soc_mask) 558 *soc_mask = 0; 559 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 560 if (mclk_mask) 561 *mclk_mask = 0; 562 563 if (fclk_mask) 564 *fclk_mask = 0; 565 566 if (soc_mask) 567 *soc_mask = 1; 568 569 if (vclk_mask) 570 *vclk_mask = 1; 571 572 if (dclk_mask) 573 *dclk_mask = 1; 574 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 575 if (mclk_mask) 576 *mclk_mask = 0; 577 578 if (fclk_mask) 579 *fclk_mask = 0; 580 581 if (soc_mask) 582 *soc_mask = 1; 583 584 if (vclk_mask) 585 *vclk_mask = 1; 586 587 if (dclk_mask) 588 *dclk_mask = 1; 589 } 590 591 return 0; 592 } 593 594 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 595 enum smu_clk_type clk_type) 596 { 597 enum smu_feature_mask feature_id = 0; 598 599 switch (clk_type) { 600 case SMU_MCLK: 601 case SMU_UCLK: 602 case SMU_FCLK: 603 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 604 break; 605 case SMU_GFXCLK: 606 case SMU_SCLK: 607 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 608 break; 609 case SMU_SOCCLK: 610 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 611 break; 612 case SMU_VCLK: 613 case SMU_DCLK: 614 feature_id = SMU_FEATURE_VCN_DPM_BIT; 615 break; 616 default: 617 return true; 618 } 619 620 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 621 return false; 622 623 return true; 624 } 625 626 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 627 enum smu_clk_type clk_type, 628 uint32_t *min, 629 uint32_t *max) 630 { 631 int ret = 0; 632 uint32_t soc_mask; 633 uint32_t vclk_mask; 634 uint32_t dclk_mask; 635 uint32_t mclk_mask; 636 uint32_t fclk_mask; 637 uint32_t clock_limit; 638 639 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 640 switch (clk_type) { 641 case SMU_MCLK: 642 case SMU_UCLK: 643 clock_limit = smu->smu_table.boot_values.uclk; 644 break; 645 case SMU_FCLK: 646 clock_limit = smu->smu_table.boot_values.fclk; 647 break; 648 case SMU_GFXCLK: 649 case SMU_SCLK: 650 clock_limit = smu->smu_table.boot_values.gfxclk; 651 break; 652 case SMU_SOCCLK: 653 clock_limit = smu->smu_table.boot_values.socclk; 654 break; 655 case SMU_VCLK: 656 clock_limit = smu->smu_table.boot_values.vclk; 657 break; 658 case SMU_DCLK: 659 clock_limit = smu->smu_table.boot_values.dclk; 660 break; 661 default: 662 clock_limit = 0; 663 break; 664 } 665 666 /* clock in Mhz unit */ 667 if (min) 668 *min = clock_limit / 100; 669 if (max) 670 *max = clock_limit / 100; 671 672 return 0; 673 } 674 if (max) { 675 ret = vangogh_get_profiling_clk_mask(smu, 676 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 677 &vclk_mask, 678 &dclk_mask, 679 &mclk_mask, 680 &fclk_mask, 681 &soc_mask); 682 if (ret) 683 goto failed; 684 685 switch (clk_type) { 686 case SMU_UCLK: 687 case SMU_MCLK: 688 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 689 if (ret) 690 goto failed; 691 break; 692 case SMU_SOCCLK: 693 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 694 if (ret) 695 goto failed; 696 break; 697 case SMU_FCLK: 698 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 699 if (ret) 700 goto failed; 701 break; 702 case SMU_VCLK: 703 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 704 if (ret) 705 goto failed; 706 break; 707 case SMU_DCLK: 708 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 709 if (ret) 710 goto failed; 711 break; 712 default: 713 ret = -EINVAL; 714 goto failed; 715 } 716 } 717 if (min) { 718 switch (clk_type) { 719 case SMU_UCLK: 720 case SMU_MCLK: 721 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 722 if (ret) 723 goto failed; 724 break; 725 case SMU_SOCCLK: 726 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 727 if (ret) 728 goto failed; 729 break; 730 case SMU_FCLK: 731 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 732 if (ret) 733 goto failed; 734 break; 735 case SMU_VCLK: 736 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 737 if (ret) 738 goto failed; 739 break; 740 case SMU_DCLK: 741 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 742 if (ret) 743 goto failed; 744 break; 745 default: 746 ret = -EINVAL; 747 goto failed; 748 } 749 } 750 failed: 751 return ret; 752 } 753 754 static int vangogh_get_power_profile_mode(struct smu_context *smu, 755 char *buf) 756 { 757 static const char *profile_name[] = { 758 "BOOTUP_DEFAULT", 759 "3D_FULL_SCREEN", 760 "POWER_SAVING", 761 "VIDEO", 762 "VR", 763 "COMPUTE", 764 "CUSTOM"}; 765 uint32_t i, size = 0; 766 int16_t workload_type = 0; 767 768 if (!buf) 769 return -EINVAL; 770 771 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 772 /* 773 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 774 * Not all profile modes are supported on vangogh. 775 */ 776 workload_type = smu_cmn_to_asic_specific_index(smu, 777 CMN2ASIC_MAPPING_WORKLOAD, 778 i); 779 780 if (workload_type < 0) 781 continue; 782 783 size += sprintf(buf + size, "%2d %14s%s\n", 784 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 785 } 786 787 return size; 788 } 789 790 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 791 { 792 int workload_type, ret; 793 uint32_t profile_mode = input[size]; 794 795 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 796 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 797 return -EINVAL; 798 } 799 800 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 801 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 802 return 0; 803 804 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 805 workload_type = smu_cmn_to_asic_specific_index(smu, 806 CMN2ASIC_MAPPING_WORKLOAD, 807 profile_mode); 808 if (workload_type < 0) { 809 dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 810 profile_mode); 811 return -EINVAL; 812 } 813 814 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 815 1 << workload_type, 816 NULL); 817 if (ret) { 818 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 819 workload_type); 820 return ret; 821 } 822 823 smu->power_profile_mode = profile_mode; 824 825 return 0; 826 } 827 828 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 829 enum smu_clk_type clk_type, 830 uint32_t min, 831 uint32_t max) 832 { 833 int ret = 0; 834 835 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 836 return 0; 837 838 switch (clk_type) { 839 case SMU_GFXCLK: 840 case SMU_SCLK: 841 ret = smu_cmn_send_smc_msg_with_param(smu, 842 SMU_MSG_SetHardMinGfxClk, 843 min, NULL); 844 if (ret) 845 return ret; 846 847 ret = smu_cmn_send_smc_msg_with_param(smu, 848 SMU_MSG_SetSoftMaxGfxClk, 849 max, NULL); 850 if (ret) 851 return ret; 852 break; 853 case SMU_FCLK: 854 case SMU_MCLK: 855 ret = smu_cmn_send_smc_msg_with_param(smu, 856 SMU_MSG_SetHardMinFclkByFreq, 857 min, NULL); 858 if (ret) 859 return ret; 860 861 ret = smu_cmn_send_smc_msg_with_param(smu, 862 SMU_MSG_SetSoftMaxFclkByFreq, 863 max, NULL); 864 if (ret) 865 return ret; 866 break; 867 case SMU_SOCCLK: 868 ret = smu_cmn_send_smc_msg_with_param(smu, 869 SMU_MSG_SetHardMinSocclkByFreq, 870 min, NULL); 871 if (ret) 872 return ret; 873 874 ret = smu_cmn_send_smc_msg_with_param(smu, 875 SMU_MSG_SetSoftMaxSocclkByFreq, 876 max, NULL); 877 if (ret) 878 return ret; 879 break; 880 case SMU_VCLK: 881 ret = smu_cmn_send_smc_msg_with_param(smu, 882 SMU_MSG_SetHardMinVcn, 883 min << 16, NULL); 884 if (ret) 885 return ret; 886 ret = smu_cmn_send_smc_msg_with_param(smu, 887 SMU_MSG_SetSoftMaxVcn, 888 max << 16, NULL); 889 if (ret) 890 return ret; 891 break; 892 case SMU_DCLK: 893 ret = smu_cmn_send_smc_msg_with_param(smu, 894 SMU_MSG_SetHardMinVcn, 895 min, NULL); 896 if (ret) 897 return ret; 898 ret = smu_cmn_send_smc_msg_with_param(smu, 899 SMU_MSG_SetSoftMaxVcn, 900 max, NULL); 901 if (ret) 902 return ret; 903 break; 904 default: 905 return -EINVAL; 906 } 907 908 return ret; 909 } 910 911 static int vangogh_force_clk_levels(struct smu_context *smu, 912 enum smu_clk_type clk_type, uint32_t mask) 913 { 914 uint32_t soft_min_level = 0, soft_max_level = 0; 915 uint32_t min_freq = 0, max_freq = 0; 916 int ret = 0 ; 917 918 soft_min_level = mask ? (ffs(mask) - 1) : 0; 919 soft_max_level = mask ? (fls(mask) - 1) : 0; 920 921 switch (clk_type) { 922 case SMU_SOCCLK: 923 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 924 soft_min_level, &min_freq); 925 if (ret) 926 return ret; 927 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 928 soft_max_level, &max_freq); 929 if (ret) 930 return ret; 931 ret = smu_cmn_send_smc_msg_with_param(smu, 932 SMU_MSG_SetSoftMaxSocclkByFreq, 933 max_freq, NULL); 934 if (ret) 935 return ret; 936 ret = smu_cmn_send_smc_msg_with_param(smu, 937 SMU_MSG_SetHardMinSocclkByFreq, 938 min_freq, NULL); 939 if (ret) 940 return ret; 941 break; 942 case SMU_MCLK: 943 case SMU_FCLK: 944 ret = vangogh_get_dpm_clk_limited(smu, 945 clk_type, soft_min_level, &min_freq); 946 if (ret) 947 return ret; 948 ret = vangogh_get_dpm_clk_limited(smu, 949 clk_type, soft_max_level, &max_freq); 950 if (ret) 951 return ret; 952 ret = smu_cmn_send_smc_msg_with_param(smu, 953 SMU_MSG_SetSoftMaxFclkByFreq, 954 max_freq, NULL); 955 if (ret) 956 return ret; 957 ret = smu_cmn_send_smc_msg_with_param(smu, 958 SMU_MSG_SetHardMinFclkByFreq, 959 min_freq, NULL); 960 if (ret) 961 return ret; 962 break; 963 case SMU_VCLK: 964 ret = vangogh_get_dpm_clk_limited(smu, 965 clk_type, soft_min_level, &min_freq); 966 if (ret) 967 return ret; 968 969 ret = vangogh_get_dpm_clk_limited(smu, 970 clk_type, soft_max_level, &max_freq); 971 if (ret) 972 return ret; 973 974 975 ret = smu_cmn_send_smc_msg_with_param(smu, 976 SMU_MSG_SetHardMinVcn, 977 min_freq << 16, NULL); 978 if (ret) 979 return ret; 980 981 ret = smu_cmn_send_smc_msg_with_param(smu, 982 SMU_MSG_SetSoftMaxVcn, 983 max_freq << 16, NULL); 984 if (ret) 985 return ret; 986 987 break; 988 case SMU_DCLK: 989 ret = vangogh_get_dpm_clk_limited(smu, 990 clk_type, soft_min_level, &min_freq); 991 if (ret) 992 return ret; 993 994 ret = vangogh_get_dpm_clk_limited(smu, 995 clk_type, soft_max_level, &max_freq); 996 if (ret) 997 return ret; 998 999 ret = smu_cmn_send_smc_msg_with_param(smu, 1000 SMU_MSG_SetHardMinVcn, 1001 min_freq, NULL); 1002 if (ret) 1003 return ret; 1004 1005 ret = smu_cmn_send_smc_msg_with_param(smu, 1006 SMU_MSG_SetSoftMaxVcn, 1007 max_freq, NULL); 1008 if (ret) 1009 return ret; 1010 1011 break; 1012 default: 1013 break; 1014 } 1015 1016 return ret; 1017 } 1018 1019 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1020 { 1021 int ret = 0, i = 0; 1022 uint32_t min_freq, max_freq, force_freq; 1023 enum smu_clk_type clk_type; 1024 1025 enum smu_clk_type clks[] = { 1026 SMU_SOCCLK, 1027 SMU_VCLK, 1028 SMU_DCLK, 1029 SMU_MCLK, 1030 SMU_FCLK, 1031 }; 1032 1033 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1034 clk_type = clks[i]; 1035 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1036 if (ret) 1037 return ret; 1038 1039 force_freq = highest ? max_freq : min_freq; 1040 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1041 if (ret) 1042 return ret; 1043 } 1044 1045 return ret; 1046 } 1047 1048 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1049 { 1050 int ret = 0, i = 0; 1051 uint32_t min_freq, max_freq; 1052 enum smu_clk_type clk_type; 1053 1054 struct clk_feature_map { 1055 enum smu_clk_type clk_type; 1056 uint32_t feature; 1057 } clk_feature_map[] = { 1058 {SMU_MCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1059 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1060 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1061 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1062 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1063 }; 1064 1065 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1066 1067 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1068 continue; 1069 1070 clk_type = clk_feature_map[i].clk_type; 1071 1072 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1073 1074 if (ret) 1075 return ret; 1076 1077 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1078 1079 if (ret) 1080 return ret; 1081 } 1082 1083 return ret; 1084 } 1085 1086 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1087 { 1088 int ret = 0; 1089 uint32_t socclk_freq = 0, fclk_freq = 0; 1090 uint32_t vclk_freq = 0, dclk_freq = 0; 1091 1092 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1093 if (ret) 1094 return ret; 1095 1096 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1097 if (ret) 1098 return ret; 1099 1100 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1101 if (ret) 1102 return ret; 1103 1104 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1105 if (ret) 1106 return ret; 1107 1108 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1109 if (ret) 1110 return ret; 1111 1112 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1113 if (ret) 1114 return ret; 1115 1116 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1117 if (ret) 1118 return ret; 1119 1120 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1121 if (ret) 1122 return ret; 1123 1124 return ret; 1125 } 1126 1127 static int vangogh_set_performance_level(struct smu_context *smu, 1128 enum amd_dpm_forced_level level) 1129 { 1130 int ret = 0; 1131 uint32_t soc_mask, mclk_mask, fclk_mask; 1132 uint32_t vclk_mask = 0, dclk_mask = 0; 1133 1134 switch (level) { 1135 case AMD_DPM_FORCED_LEVEL_HIGH: 1136 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1137 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1138 1139 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1140 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1141 1142 ret = vangogh_force_dpm_limit_value(smu, true); 1143 break; 1144 case AMD_DPM_FORCED_LEVEL_LOW: 1145 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1146 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1147 1148 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1149 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1150 1151 ret = vangogh_force_dpm_limit_value(smu, false); 1152 break; 1153 case AMD_DPM_FORCED_LEVEL_AUTO: 1154 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1155 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1156 1157 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1158 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1159 1160 ret = vangogh_unforce_dpm_levels(smu); 1161 break; 1162 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1163 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1164 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1165 1166 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1167 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1168 1169 ret = smu_cmn_send_smc_msg_with_param(smu, 1170 SMU_MSG_SetHardMinGfxClk, 1171 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1172 if (ret) 1173 return ret; 1174 1175 ret = smu_cmn_send_smc_msg_with_param(smu, 1176 SMU_MSG_SetSoftMaxGfxClk, 1177 VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1178 if (ret) 1179 return ret; 1180 1181 ret = vangogh_get_profiling_clk_mask(smu, level, 1182 &vclk_mask, 1183 &dclk_mask, 1184 &mclk_mask, 1185 &fclk_mask, 1186 &soc_mask); 1187 if (ret) 1188 return ret; 1189 1190 vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 1191 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1192 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1193 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1194 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1195 1196 break; 1197 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1198 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1199 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1200 1201 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1202 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1203 1204 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, 1205 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1206 if (ret) 1207 return ret; 1208 1209 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, 1210 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1211 if (ret) 1212 return ret; 1213 break; 1214 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1215 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1216 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1217 1218 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1219 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1220 1221 ret = vangogh_get_profiling_clk_mask(smu, level, 1222 NULL, 1223 NULL, 1224 &mclk_mask, 1225 &fclk_mask, 1226 NULL); 1227 if (ret) 1228 return ret; 1229 1230 vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); 1231 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1232 break; 1233 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1234 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1235 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1236 1237 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1238 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1239 1240 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1241 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1242 if (ret) 1243 return ret; 1244 1245 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1246 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1247 if (ret) 1248 return ret; 1249 1250 ret = vangogh_set_peak_clock_by_device(smu); 1251 break; 1252 case AMD_DPM_FORCED_LEVEL_MANUAL: 1253 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1254 default: 1255 break; 1256 } 1257 return ret; 1258 } 1259 1260 static int vangogh_read_sensor(struct smu_context *smu, 1261 enum amd_pp_sensors sensor, 1262 void *data, uint32_t *size) 1263 { 1264 int ret = 0; 1265 1266 if (!data || !size) 1267 return -EINVAL; 1268 1269 mutex_lock(&smu->sensor_lock); 1270 switch (sensor) { 1271 case AMDGPU_PP_SENSOR_GPU_LOAD: 1272 ret = vangogh_get_smu_metrics_data(smu, 1273 METRICS_AVERAGE_GFXACTIVITY, 1274 (uint32_t *)data); 1275 *size = 4; 1276 break; 1277 case AMDGPU_PP_SENSOR_GPU_POWER: 1278 ret = vangogh_get_smu_metrics_data(smu, 1279 METRICS_AVERAGE_SOCKETPOWER, 1280 (uint32_t *)data); 1281 *size = 4; 1282 break; 1283 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1284 ret = vangogh_get_smu_metrics_data(smu, 1285 METRICS_TEMPERATURE_EDGE, 1286 (uint32_t *)data); 1287 *size = 4; 1288 break; 1289 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1290 ret = vangogh_get_smu_metrics_data(smu, 1291 METRICS_TEMPERATURE_HOTSPOT, 1292 (uint32_t *)data); 1293 *size = 4; 1294 break; 1295 case AMDGPU_PP_SENSOR_GFX_MCLK: 1296 ret = vangogh_get_smu_metrics_data(smu, 1297 METRICS_AVERAGE_UCLK, 1298 (uint32_t *)data); 1299 *(uint32_t *)data *= 100; 1300 *size = 4; 1301 break; 1302 case AMDGPU_PP_SENSOR_GFX_SCLK: 1303 ret = vangogh_get_smu_metrics_data(smu, 1304 METRICS_AVERAGE_GFXCLK, 1305 (uint32_t *)data); 1306 *(uint32_t *)data *= 100; 1307 *size = 4; 1308 break; 1309 case AMDGPU_PP_SENSOR_VDDGFX: 1310 ret = vangogh_get_smu_metrics_data(smu, 1311 METRICS_VOLTAGE_VDDGFX, 1312 (uint32_t *)data); 1313 *size = 4; 1314 break; 1315 case AMDGPU_PP_SENSOR_VDDNB: 1316 ret = vangogh_get_smu_metrics_data(smu, 1317 METRICS_VOLTAGE_VDDSOC, 1318 (uint32_t *)data); 1319 *size = 4; 1320 break; 1321 case AMDGPU_PP_SENSOR_CPU_CLK: 1322 ret = vangogh_get_smu_metrics_data(smu, 1323 METRICS_AVERAGE_CPUCLK, 1324 (uint32_t *)data); 1325 *size = smu->cpu_core_num * sizeof(uint16_t); 1326 break; 1327 default: 1328 ret = -EOPNOTSUPP; 1329 break; 1330 } 1331 mutex_unlock(&smu->sensor_lock); 1332 1333 return ret; 1334 } 1335 1336 static int vangogh_set_watermarks_table(struct smu_context *smu, 1337 struct pp_smu_wm_range_sets *clock_ranges) 1338 { 1339 int i; 1340 int ret = 0; 1341 Watermarks_t *table = smu->smu_table.watermarks_table; 1342 1343 if (!table || !clock_ranges) 1344 return -EINVAL; 1345 1346 if (clock_ranges) { 1347 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1348 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1349 return -EINVAL; 1350 1351 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1352 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1353 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1354 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1355 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1356 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1357 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1358 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1359 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1360 1361 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1362 clock_ranges->reader_wm_sets[i].wm_inst; 1363 } 1364 1365 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1366 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1367 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1368 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1369 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1370 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1371 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1372 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1373 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1374 1375 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1376 clock_ranges->writer_wm_sets[i].wm_inst; 1377 } 1378 1379 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1380 } 1381 1382 /* pass data to smu controller */ 1383 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1384 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1385 ret = smu_cmn_write_watermarks_table(smu); 1386 if (ret) { 1387 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1388 return ret; 1389 } 1390 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1391 } 1392 1393 return 0; 1394 } 1395 1396 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1397 void **table) 1398 { 1399 struct smu_table_context *smu_table = &smu->smu_table; 1400 struct gpu_metrics_v2_0 *gpu_metrics = 1401 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table; 1402 SmuMetrics_t metrics; 1403 int ret = 0; 1404 1405 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1406 if (ret) 1407 return ret; 1408 1409 smu_v11_0_init_gpu_metrics_v2_0(gpu_metrics); 1410 1411 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1412 gpu_metrics->temperature_soc = metrics.SocTemperature; 1413 memcpy(&gpu_metrics->temperature_core[0], 1414 &metrics.CoreTemperature[0], 1415 sizeof(uint16_t) * 8); 1416 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1417 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1]; 1418 1419 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1420 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1421 1422 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1423 gpu_metrics->average_cpu_power = metrics.Power[0]; 1424 gpu_metrics->average_soc_power = metrics.Power[1]; 1425 gpu_metrics->average_gfx_power = metrics.Power[2]; 1426 memcpy(&gpu_metrics->average_core_power[0], 1427 &metrics.CorePower[0], 1428 sizeof(uint16_t) * 8); 1429 1430 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1431 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1432 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1433 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1434 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1435 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1436 1437 memcpy(&gpu_metrics->current_coreclk[0], 1438 &metrics.CoreFrequency[0], 1439 sizeof(uint16_t) * 8); 1440 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1441 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1]; 1442 1443 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1444 1445 *table = (void *)gpu_metrics; 1446 1447 return sizeof(struct gpu_metrics_v2_0); 1448 } 1449 1450 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1451 long input[], uint32_t size) 1452 { 1453 int ret = 0; 1454 int i; 1455 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1456 1457 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 1458 dev_warn(smu->adev->dev, "Fine grain is not enabled!\n"); 1459 return -EINVAL; 1460 } 1461 1462 switch (type) { 1463 case PP_OD_EDIT_CCLK_VDDC_TABLE: 1464 if (size != 3) { 1465 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 1466 return -EINVAL; 1467 } 1468 if (input[0] >= smu->cpu_core_num) { 1469 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 1470 smu->cpu_core_num); 1471 } 1472 smu->cpu_core_id_select = input[0]; 1473 if (input[1] == 0) { 1474 if (input[2] < smu->cpu_default_soft_min_freq) { 1475 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1476 input[2], smu->cpu_default_soft_min_freq); 1477 return -EINVAL; 1478 } 1479 smu->cpu_actual_soft_min_freq = input[2]; 1480 } else if (input[1] == 1) { 1481 if (input[2] > smu->cpu_default_soft_max_freq) { 1482 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1483 input[2], smu->cpu_default_soft_max_freq); 1484 return -EINVAL; 1485 } 1486 smu->cpu_actual_soft_max_freq = input[2]; 1487 } else { 1488 return -EINVAL; 1489 } 1490 break; 1491 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1492 if (size != 2) { 1493 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1494 return -EINVAL; 1495 } 1496 1497 if (input[0] == 0) { 1498 if (input[1] < smu->gfx_default_hard_min_freq) { 1499 dev_warn(smu->adev->dev, 1500 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1501 input[1], smu->gfx_default_hard_min_freq); 1502 return -EINVAL; 1503 } 1504 smu->gfx_actual_hard_min_freq = input[1]; 1505 } else if (input[0] == 1) { 1506 if (input[1] > smu->gfx_default_soft_max_freq) { 1507 dev_warn(smu->adev->dev, 1508 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1509 input[1], smu->gfx_default_soft_max_freq); 1510 return -EINVAL; 1511 } 1512 smu->gfx_actual_soft_max_freq = input[1]; 1513 } else { 1514 return -EINVAL; 1515 } 1516 break; 1517 case PP_OD_RESTORE_DEFAULT_TABLE: 1518 if (size != 0) { 1519 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1520 return -EINVAL; 1521 } else { 1522 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1523 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1524 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1525 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1526 1527 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1528 smu->gfx_actual_hard_min_freq, NULL); 1529 if (ret) { 1530 dev_err(smu->adev->dev, "Restore the default hard min sclk failed!"); 1531 return ret; 1532 } 1533 1534 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1535 smu->gfx_actual_soft_max_freq, NULL); 1536 if (ret) { 1537 dev_err(smu->adev->dev, "Restore the default soft max sclk failed!"); 1538 return ret; 1539 } 1540 1541 if (smu->adev->pm.fw_version < 0x43f1b00) { 1542 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 1543 break; 1544 } 1545 1546 for (i = 0; i < smu->cpu_core_num; i++) { 1547 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1548 (i << 20) | smu->cpu_actual_soft_min_freq, 1549 NULL); 1550 if (ret) { 1551 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 1552 return ret; 1553 } 1554 1555 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1556 (i << 20) | smu->cpu_actual_soft_max_freq, 1557 NULL); 1558 if (ret) { 1559 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 1560 return ret; 1561 } 1562 } 1563 } 1564 break; 1565 case PP_OD_COMMIT_DPM_TABLE: 1566 if (size != 0) { 1567 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1568 return -EINVAL; 1569 } else { 1570 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1571 dev_err(smu->adev->dev, 1572 "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1573 smu->gfx_actual_hard_min_freq, 1574 smu->gfx_actual_soft_max_freq); 1575 return -EINVAL; 1576 } 1577 1578 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1579 smu->gfx_actual_hard_min_freq, NULL); 1580 if (ret) { 1581 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1582 return ret; 1583 } 1584 1585 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1586 smu->gfx_actual_soft_max_freq, NULL); 1587 if (ret) { 1588 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1589 return ret; 1590 } 1591 1592 if (smu->adev->pm.fw_version < 0x43f1b00) { 1593 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 1594 break; 1595 } 1596 1597 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1598 ((smu->cpu_core_id_select << 20) 1599 | smu->cpu_actual_soft_min_freq), 1600 NULL); 1601 if (ret) { 1602 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 1603 return ret; 1604 } 1605 1606 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1607 ((smu->cpu_core_id_select << 20) 1608 | smu->cpu_actual_soft_max_freq), 1609 NULL); 1610 if (ret) { 1611 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 1612 return ret; 1613 } 1614 } 1615 break; 1616 default: 1617 return -ENOSYS; 1618 } 1619 1620 return ret; 1621 } 1622 1623 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 1624 { 1625 struct smu_table_context *smu_table = &smu->smu_table; 1626 1627 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 1628 } 1629 1630 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1631 { 1632 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1633 1634 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1635 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1636 smu->gfx_actual_hard_min_freq = 0; 1637 smu->gfx_actual_soft_max_freq = 0; 1638 1639 smu->cpu_default_soft_min_freq = 1400; 1640 smu->cpu_default_soft_max_freq = 3500; 1641 smu->cpu_actual_soft_min_freq = 0; 1642 smu->cpu_actual_soft_max_freq = 0; 1643 1644 return 0; 1645 } 1646 1647 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 1648 { 1649 DpmClocks_t *table = smu->smu_table.clocks_table; 1650 int i; 1651 1652 if (!clock_table || !table) 1653 return -EINVAL; 1654 1655 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 1656 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 1657 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 1658 } 1659 1660 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1661 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 1662 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 1663 } 1664 1665 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1666 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 1667 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 1668 } 1669 1670 return 0; 1671 } 1672 1673 1674 static int vangogh_system_features_control(struct smu_context *smu, bool en) 1675 { 1676 struct amdgpu_device *adev = smu->adev; 1677 struct smu_feature *feature = &smu->smu_feature; 1678 uint32_t feature_mask[2]; 1679 int ret = 0; 1680 1681 if (adev->pm.fw_version >= 0x43f1700) 1682 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 1683 en ? RLC_STATUS_NORMAL : RLC_STATUS_OFF, NULL); 1684 1685 bitmap_zero(feature->enabled, feature->feature_num); 1686 bitmap_zero(feature->supported, feature->feature_num); 1687 1688 if (!en) 1689 return ret; 1690 1691 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 1692 if (ret) 1693 return ret; 1694 1695 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, 1696 feature->feature_num); 1697 bitmap_copy(feature->supported, (unsigned long *)&feature_mask, 1698 feature->feature_num); 1699 1700 return 0; 1701 } 1702 1703 static int vangogh_post_smu_init(struct smu_context *smu) 1704 { 1705 struct amdgpu_device *adev = smu->adev; 1706 uint32_t tmp; 1707 int ret = 0; 1708 uint8_t aon_bits = 0; 1709 /* Two CUs in one WGP */ 1710 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 1711 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 1712 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1713 1714 /* allow message will be sent after enable message on Vangogh*/ 1715 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 1716 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 1717 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 1718 if (ret) { 1719 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 1720 return ret; 1721 } 1722 } else { 1723 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1724 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 1725 } 1726 1727 /* if all CUs are active, no need to power off any WGPs */ 1728 if (total_cu == adev->gfx.cu_info.number) 1729 return 0; 1730 1731 /* 1732 * Calculate the total bits number of always on WGPs for all SA/SEs in 1733 * RLC_PG_ALWAYS_ON_WGP_MASK. 1734 */ 1735 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 1736 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 1737 1738 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1739 1740 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 1741 if (aon_bits > req_active_wgps) { 1742 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 1743 return 0; 1744 } else { 1745 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 1746 } 1747 } 1748 1749 static int vangogh_mode_reset(struct smu_context *smu, int type) 1750 { 1751 int ret = 0, index = 0; 1752 1753 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1754 SMU_MSG_GfxDeviceDriverReset); 1755 if (index < 0) 1756 return index == -EACCES ? 0 : index; 1757 1758 mutex_lock(&smu->message_lock); 1759 1760 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 1761 1762 mutex_unlock(&smu->message_lock); 1763 1764 mdelay(10); 1765 1766 return ret; 1767 } 1768 1769 static int vangogh_mode2_reset(struct smu_context *smu) 1770 { 1771 return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 1772 } 1773 1774 static const struct pptable_funcs vangogh_ppt_funcs = { 1775 1776 .check_fw_status = smu_v11_0_check_fw_status, 1777 .check_fw_version = smu_v11_0_check_fw_version, 1778 .init_smc_tables = vangogh_init_smc_tables, 1779 .fini_smc_tables = smu_v11_0_fini_smc_tables, 1780 .init_power = smu_v11_0_init_power, 1781 .fini_power = smu_v11_0_fini_power, 1782 .register_irq_handler = smu_v11_0_register_irq_handler, 1783 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 1784 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1785 .send_smc_msg = smu_cmn_send_smc_msg, 1786 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 1787 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 1788 .is_dpm_running = vangogh_is_dpm_running, 1789 .read_sensor = vangogh_read_sensor, 1790 .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask, 1791 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1792 .set_watermarks_table = vangogh_set_watermarks_table, 1793 .set_driver_table_location = smu_v11_0_set_driver_table_location, 1794 .interrupt_work = smu_v11_0_interrupt_work, 1795 .get_gpu_metrics = vangogh_get_gpu_metrics, 1796 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 1797 .print_clk_levels = vangogh_print_fine_grain_clk, 1798 .set_default_dpm_table = vangogh_set_default_dpm_tables, 1799 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 1800 .system_features_control = vangogh_system_features_control, 1801 .feature_is_enabled = smu_cmn_feature_is_enabled, 1802 .set_power_profile_mode = vangogh_set_power_profile_mode, 1803 .get_power_profile_mode = vangogh_get_power_profile_mode, 1804 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 1805 .force_clk_levels = vangogh_force_clk_levels, 1806 .set_performance_level = vangogh_set_performance_level, 1807 .post_init = vangogh_post_smu_init, 1808 .mode2_reset = vangogh_mode2_reset, 1809 .gfx_off_control = smu_v11_0_gfx_off_control, 1810 }; 1811 1812 void vangogh_set_ppt_funcs(struct smu_context *smu) 1813 { 1814 smu->ppt_funcs = &vangogh_ppt_funcs; 1815 smu->message_map = vangogh_message_map; 1816 smu->feature_map = vangogh_feature_mask_map; 1817 smu->table_map = vangogh_table_map; 1818 smu->workload_map = vangogh_workload_map; 1819 smu->is_apu = true; 1820 } 1821