1f46a221bSXiaojian Du /* 2f46a221bSXiaojian Du * Copyright 2020 Advanced Micro Devices, Inc. 3f46a221bSXiaojian Du * 4f46a221bSXiaojian Du * Permission is hereby granted, free of charge, to any person obtaining a 5f46a221bSXiaojian Du * copy of this software and associated documentation files (the "Software"), 6f46a221bSXiaojian Du * to deal in the Software without restriction, including without limitation 7f46a221bSXiaojian Du * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8f46a221bSXiaojian Du * and/or sell copies of the Software, and to permit persons to whom the 9f46a221bSXiaojian Du * Software is furnished to do so, subject to the following conditions: 10f46a221bSXiaojian Du * 11f46a221bSXiaojian Du * The above copyright notice and this permission notice shall be included in 12f46a221bSXiaojian Du * all copies or substantial portions of the Software. 13f46a221bSXiaojian Du * 14f46a221bSXiaojian Du * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15f46a221bSXiaojian Du * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16f46a221bSXiaojian Du * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17f46a221bSXiaojian Du * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18f46a221bSXiaojian Du * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19f46a221bSXiaojian Du * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20f46a221bSXiaojian Du * OTHER DEALINGS IN THE SOFTWARE. 21f46a221bSXiaojian Du * 22f46a221bSXiaojian Du */ 23f46a221bSXiaojian Du 24f46a221bSXiaojian Du #define SWSMU_CODE_LAYER_L2 25f46a221bSXiaojian Du 26f46a221bSXiaojian Du #include "amdgpu.h" 27f46a221bSXiaojian Du #include "amdgpu_smu.h" 28f46a221bSXiaojian Du #include "smu_v11_0.h" 29f46a221bSXiaojian Du #include "smu11_driver_if_vangogh.h" 30f46a221bSXiaojian Du #include "vangogh_ppt.h" 31f46a221bSXiaojian Du #include "smu_v11_5_ppsmc.h" 32f46a221bSXiaojian Du #include "smu_v11_5_pmfw.h" 33f46a221bSXiaojian Du #include "smu_cmn.h" 34eefdf047SJinzhou Su #include "soc15_common.h" 35eefdf047SJinzhou Su #include "asic_reg/gc/gc_10_3_0_offset.h" 36eefdf047SJinzhou Su #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37517cb957SHuang Rui #include <asm/processor.h> 38f46a221bSXiaojian Du 39f46a221bSXiaojian Du /* 40f46a221bSXiaojian Du * DO NOT use these for err/warn/info/debug messages. 41f46a221bSXiaojian Du * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42f46a221bSXiaojian Du * They are more MGPU friendly. 43f46a221bSXiaojian Du */ 44f46a221bSXiaojian Du #undef pr_err 45f46a221bSXiaojian Du #undef pr_warn 46f46a221bSXiaojian Du #undef pr_info 47f46a221bSXiaojian Du #undef pr_debug 48f46a221bSXiaojian Du 49f46a221bSXiaojian Du #define FEATURE_MASK(feature) (1ULL << feature) 50f46a221bSXiaojian Du #define SMC_DPM_FEATURE ( \ 51f46a221bSXiaojian Du FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 52f46a221bSXiaojian Du FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 53f46a221bSXiaojian Du FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 54f46a221bSXiaojian Du FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 55f46a221bSXiaojian Du FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 56f46a221bSXiaojian Du FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 57f46a221bSXiaojian Du FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 58f46a221bSXiaojian Du FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 59271ab489SXiaojian Du FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 60f46a221bSXiaojian Du 61f46a221bSXiaojian Du static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 62271ab489SXiaojian Du MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 63271ab489SXiaojian Du MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 64271ab489SXiaojian Du MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 65271ab489SXiaojian Du MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 66b58ce1feSJinzhou Su MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 67b58ce1feSJinzhou Su MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 68271ab489SXiaojian Du MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 69271ab489SXiaojian Du MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 70271ab489SXiaojian Du MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 71271ab489SXiaojian Du MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 72a0f55287SXiaomeng Hou MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 73271ab489SXiaojian Du MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 74271ab489SXiaojian Du MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 75271ab489SXiaojian Du MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 76271ab489SXiaojian Du MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 77271ab489SXiaojian Du MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 78271ab489SXiaojian Du MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 79271ab489SXiaojian Du MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 80271ab489SXiaojian Du MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 81271ab489SXiaojian Du MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 82271ab489SXiaojian Du MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 83271ab489SXiaojian Du MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 84271ab489SXiaojian Du MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 85271ab489SXiaojian Du MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 86271ab489SXiaojian Du MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 87271ab489SXiaojian Du MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 88271ab489SXiaojian Du MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 89271ab489SXiaojian Du MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 90271ab489SXiaojian Du MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 91271ab489SXiaojian Du MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 92271ab489SXiaojian Du MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 93271ab489SXiaojian Du MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 94271ab489SXiaojian Du MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 95271ab489SXiaojian Du MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 96271ab489SXiaojian Du MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 97271ab489SXiaojian Du MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 98271ab489SXiaojian Du MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 99271ab489SXiaojian Du MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 100271ab489SXiaojian Du MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 101271ab489SXiaojian Du MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 102271ab489SXiaojian Du MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 103271ab489SXiaojian Du MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 104271ab489SXiaojian Du MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 105271ab489SXiaojian Du MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 106271ab489SXiaojian Du MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 107271ab489SXiaojian Du MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 108271ab489SXiaojian Du MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 109271ab489SXiaojian Du MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 110271ab489SXiaojian Du MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 111271ab489SXiaojian Du MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 112271ab489SXiaojian Du MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 113271ab489SXiaojian Du MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 114271ab489SXiaojian Du MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 115271ab489SXiaojian Du MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 116271ab489SXiaojian Du MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 117271ab489SXiaojian Du MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 118271ab489SXiaojian Du MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 119271ab489SXiaojian Du MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 120271ab489SXiaojian Du MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 121271ab489SXiaojian Du MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 122271ab489SXiaojian Du MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 123271ab489SXiaojian Du MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 124eefdf047SJinzhou Su MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 125ae07970aSXiaomeng Hou MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 126ae07970aSXiaomeng Hou MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 127ae07970aSXiaomeng Hou MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 128ae07970aSXiaomeng Hou MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 129f46a221bSXiaojian Du }; 130f46a221bSXiaojian Du 131f46a221bSXiaojian Du static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 132f46a221bSXiaojian Du FEA_MAP(PPT), 133f46a221bSXiaojian Du FEA_MAP(TDC), 134f46a221bSXiaojian Du FEA_MAP(THERMAL), 135f46a221bSXiaojian Du FEA_MAP(DS_GFXCLK), 136f46a221bSXiaojian Du FEA_MAP(DS_SOCCLK), 137f46a221bSXiaojian Du FEA_MAP(DS_LCLK), 138f46a221bSXiaojian Du FEA_MAP(DS_FCLK), 139f46a221bSXiaojian Du FEA_MAP(DS_MP1CLK), 140f46a221bSXiaojian Du FEA_MAP(DS_MP0CLK), 141f46a221bSXiaojian Du FEA_MAP(ATHUB_PG), 142f46a221bSXiaojian Du FEA_MAP(CCLK_DPM), 143f46a221bSXiaojian Du FEA_MAP(FAN_CONTROLLER), 144f46a221bSXiaojian Du FEA_MAP(ULV), 145f46a221bSXiaojian Du FEA_MAP(VCN_DPM), 146f46a221bSXiaojian Du FEA_MAP(LCLK_DPM), 147f46a221bSXiaojian Du FEA_MAP(SHUBCLK_DPM), 148f46a221bSXiaojian Du FEA_MAP(DCFCLK_DPM), 149f46a221bSXiaojian Du FEA_MAP(DS_DCFCLK), 150f46a221bSXiaojian Du FEA_MAP(S0I2), 151f46a221bSXiaojian Du FEA_MAP(SMU_LOW_POWER), 152f46a221bSXiaojian Du FEA_MAP(GFX_DEM), 153f46a221bSXiaojian Du FEA_MAP(PSI), 154f46a221bSXiaojian Du FEA_MAP(PROCHOT), 155f46a221bSXiaojian Du FEA_MAP(CPUOFF), 156f46a221bSXiaojian Du FEA_MAP(STAPM), 157f46a221bSXiaojian Du FEA_MAP(S0I3), 158f46a221bSXiaojian Du FEA_MAP(DF_CSTATES), 159f46a221bSXiaojian Du FEA_MAP(PERF_LIMIT), 160f46a221bSXiaojian Du FEA_MAP(CORE_DLDO), 161f46a221bSXiaojian Du FEA_MAP(RSMU_LOW_POWER), 162f46a221bSXiaojian Du FEA_MAP(SMN_LOW_POWER), 163f46a221bSXiaojian Du FEA_MAP(THM_LOW_POWER), 164f46a221bSXiaojian Du FEA_MAP(SMUIO_LOW_POWER), 165f46a221bSXiaojian Du FEA_MAP(MP1_LOW_POWER), 166f46a221bSXiaojian Du FEA_MAP(DS_VCN), 167f46a221bSXiaojian Du FEA_MAP(CPPC), 168f46a221bSXiaojian Du FEA_MAP(OS_CSTATES), 169f46a221bSXiaojian Du FEA_MAP(ISP_DPM), 170f46a221bSXiaojian Du FEA_MAP(A55_DPM), 171f46a221bSXiaojian Du FEA_MAP(CVIP_DSP_DPM), 172f46a221bSXiaojian Du FEA_MAP(MSMU_LOW_POWER), 17354800b58SXiaojian Du FEA_MAP_REVERSE(SOCCLK), 17454800b58SXiaojian Du FEA_MAP_REVERSE(FCLK), 17554800b58SXiaojian Du FEA_MAP_HALF_REVERSE(GFX), 176f46a221bSXiaojian Du }; 177f46a221bSXiaojian Du 178f46a221bSXiaojian Du static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 179f46a221bSXiaojian Du TAB_MAP_VALID(WATERMARKS), 180f46a221bSXiaojian Du TAB_MAP_VALID(SMU_METRICS), 181f46a221bSXiaojian Du TAB_MAP_VALID(CUSTOM_DPM), 182f46a221bSXiaojian Du TAB_MAP_VALID(DPMCLOCKS), 183f46a221bSXiaojian Du }; 184f46a221bSXiaojian Du 185f727ebebSXiaojian Du static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 186f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 187f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 188f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 189f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 190f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 191f727ebebSXiaojian Du }; 192f727ebebSXiaojian Du 1937cab3cffSGraham Sider static const uint8_t vangogh_throttler_map[] = { 1947cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), 1957cab3cffSGraham Sider [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), 1967cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), 1977cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), 1987cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), 1997cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), 2007cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), 2017cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), 2027cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), 2037cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT), 2047cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT), 2057cab3cffSGraham Sider }; 2067cab3cffSGraham Sider 207f46a221bSXiaojian Du static int vangogh_tables_init(struct smu_context *smu) 208f46a221bSXiaojian Du { 209f46a221bSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 210f46a221bSXiaojian Du struct smu_table *tables = smu_table->tables; 21186c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev; 21286c8236eSXiaojian Du uint32_t if_version; 21386c8236eSXiaojian Du uint32_t ret = 0; 21486c8236eSXiaojian Du 21586c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 21686c8236eSXiaojian Du if (ret) { 21786c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n"); 21886c8236eSXiaojian Du goto err0_out; 21986c8236eSXiaojian Du } 220f46a221bSXiaojian Du 221f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 222f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 223f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 224f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 225f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 226f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 227f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 228f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 22986c8236eSXiaojian Du 23086c8236eSXiaojian Du if (if_version < 0x3) { 23186c8236eSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t), 23286c8236eSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 23386c8236eSXiaojian Du smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL); 23486c8236eSXiaojian Du } else { 23586c8236eSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 23686c8236eSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 237f46a221bSXiaojian Du smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 23886c8236eSXiaojian Du } 239f46a221bSXiaojian Du if (!smu_table->metrics_table) 240f46a221bSXiaojian Du goto err0_out; 241f46a221bSXiaojian Du smu_table->metrics_time = 0; 242f46a221bSXiaojian Du 2437cab3cffSGraham Sider smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); 244f46a221bSXiaojian Du smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 245f46a221bSXiaojian Du if (!smu_table->gpu_metrics_table) 246f46a221bSXiaojian Du goto err1_out; 247f46a221bSXiaojian Du 248f46a221bSXiaojian Du smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 249f46a221bSXiaojian Du if (!smu_table->watermarks_table) 250f46a221bSXiaojian Du goto err2_out; 251f46a221bSXiaojian Du 252c98ee897SXiaojian Du smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 253c98ee897SXiaojian Du if (!smu_table->clocks_table) 254c98ee897SXiaojian Du goto err3_out; 255c98ee897SXiaojian Du 256f46a221bSXiaojian Du return 0; 257f46a221bSXiaojian Du 258c98ee897SXiaojian Du err3_out: 259a5467ebdSChristophe JAILLET kfree(smu_table->watermarks_table); 260f46a221bSXiaojian Du err2_out: 261f46a221bSXiaojian Du kfree(smu_table->gpu_metrics_table); 262f46a221bSXiaojian Du err1_out: 263f46a221bSXiaojian Du kfree(smu_table->metrics_table); 264f46a221bSXiaojian Du err0_out: 265f46a221bSXiaojian Du return -ENOMEM; 266f46a221bSXiaojian Du } 267f46a221bSXiaojian Du 26886c8236eSXiaojian Du static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu, 269271ab489SXiaojian Du MetricsMember_t member, 270271ab489SXiaojian Du uint32_t *value) 271271ab489SXiaojian Du { 272271ab489SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 27386c8236eSXiaojian Du SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table; 274271ab489SXiaojian Du int ret = 0; 275271ab489SXiaojian Du 276271ab489SXiaojian Du mutex_lock(&smu->metrics_lock); 277271ab489SXiaojian Du 278271ab489SXiaojian Du ret = smu_cmn_get_metrics_table_locked(smu, 279271ab489SXiaojian Du NULL, 280271ab489SXiaojian Du false); 281271ab489SXiaojian Du if (ret) { 282271ab489SXiaojian Du mutex_unlock(&smu->metrics_lock); 283271ab489SXiaojian Du return ret; 284271ab489SXiaojian Du } 285271ab489SXiaojian Du 286271ab489SXiaojian Du switch (member) { 287a99a5116SXiaojian Du case METRICS_CURR_GFXCLK: 288271ab489SXiaojian Du *value = metrics->GfxclkFrequency; 289271ab489SXiaojian Du break; 290271ab489SXiaojian Du case METRICS_AVERAGE_SOCCLK: 291271ab489SXiaojian Du *value = metrics->SocclkFrequency; 292271ab489SXiaojian Du break; 293f02c7336SXiaojian Du case METRICS_AVERAGE_VCLK: 294f02c7336SXiaojian Du *value = metrics->VclkFrequency; 295f02c7336SXiaojian Du break; 296f02c7336SXiaojian Du case METRICS_AVERAGE_DCLK: 297f02c7336SXiaojian Du *value = metrics->DclkFrequency; 298f02c7336SXiaojian Du break; 299a99a5116SXiaojian Du case METRICS_CURR_UCLK: 300271ab489SXiaojian Du *value = metrics->MemclkFrequency; 301271ab489SXiaojian Du break; 302271ab489SXiaojian Du case METRICS_AVERAGE_GFXACTIVITY: 303271ab489SXiaojian Du *value = metrics->GfxActivity / 100; 304271ab489SXiaojian Du break; 305271ab489SXiaojian Du case METRICS_AVERAGE_VCNACTIVITY: 306271ab489SXiaojian Du *value = metrics->UvdActivity; 307271ab489SXiaojian Du break; 308271ab489SXiaojian Du case METRICS_AVERAGE_SOCKETPOWER: 30923289a22SXiaojian Du *value = (metrics->CurrentSocketPower << 8) / 31023289a22SXiaojian Du 1000 ; 311271ab489SXiaojian Du break; 312271ab489SXiaojian Du case METRICS_TEMPERATURE_EDGE: 313271ab489SXiaojian Du *value = metrics->GfxTemperature / 100 * 314271ab489SXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 315271ab489SXiaojian Du break; 316271ab489SXiaojian Du case METRICS_TEMPERATURE_HOTSPOT: 317271ab489SXiaojian Du *value = metrics->SocTemperature / 100 * 318271ab489SXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 319271ab489SXiaojian Du break; 320271ab489SXiaojian Du case METRICS_THROTTLER_STATUS: 321271ab489SXiaojian Du *value = metrics->ThrottlerStatus; 322271ab489SXiaojian Du break; 3232139d12bSAlex Deucher case METRICS_VOLTAGE_VDDGFX: 3242139d12bSAlex Deucher *value = metrics->Voltage[2]; 3252139d12bSAlex Deucher break; 3262139d12bSAlex Deucher case METRICS_VOLTAGE_VDDSOC: 3272139d12bSAlex Deucher *value = metrics->Voltage[1]; 3282139d12bSAlex Deucher break; 329517cb957SHuang Rui case METRICS_AVERAGE_CPUCLK: 330517cb957SHuang Rui memcpy(value, &metrics->CoreFrequency[0], 3314aef0ebcSHuang Rui smu->cpu_core_num * sizeof(uint16_t)); 332517cb957SHuang Rui break; 333271ab489SXiaojian Du default: 334271ab489SXiaojian Du *value = UINT_MAX; 335271ab489SXiaojian Du break; 336271ab489SXiaojian Du } 337271ab489SXiaojian Du 338271ab489SXiaojian Du mutex_unlock(&smu->metrics_lock); 339271ab489SXiaojian Du 340271ab489SXiaojian Du return ret; 341271ab489SXiaojian Du } 342271ab489SXiaojian Du 34386c8236eSXiaojian Du static int vangogh_get_smu_metrics_data(struct smu_context *smu, 34486c8236eSXiaojian Du MetricsMember_t member, 34586c8236eSXiaojian Du uint32_t *value) 34686c8236eSXiaojian Du { 34786c8236eSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 34886c8236eSXiaojian Du SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 34986c8236eSXiaojian Du int ret = 0; 35086c8236eSXiaojian Du 35186c8236eSXiaojian Du mutex_lock(&smu->metrics_lock); 35286c8236eSXiaojian Du 35386c8236eSXiaojian Du ret = smu_cmn_get_metrics_table_locked(smu, 35486c8236eSXiaojian Du NULL, 35586c8236eSXiaojian Du false); 35686c8236eSXiaojian Du if (ret) { 35786c8236eSXiaojian Du mutex_unlock(&smu->metrics_lock); 35886c8236eSXiaojian Du return ret; 35986c8236eSXiaojian Du } 36086c8236eSXiaojian Du 36186c8236eSXiaojian Du switch (member) { 362a99a5116SXiaojian Du case METRICS_CURR_GFXCLK: 36386c8236eSXiaojian Du *value = metrics->Current.GfxclkFrequency; 36486c8236eSXiaojian Du break; 36586c8236eSXiaojian Du case METRICS_AVERAGE_SOCCLK: 36686c8236eSXiaojian Du *value = metrics->Current.SocclkFrequency; 36786c8236eSXiaojian Du break; 36886c8236eSXiaojian Du case METRICS_AVERAGE_VCLK: 36986c8236eSXiaojian Du *value = metrics->Current.VclkFrequency; 37086c8236eSXiaojian Du break; 37186c8236eSXiaojian Du case METRICS_AVERAGE_DCLK: 37286c8236eSXiaojian Du *value = metrics->Current.DclkFrequency; 37386c8236eSXiaojian Du break; 374a99a5116SXiaojian Du case METRICS_CURR_UCLK: 37586c8236eSXiaojian Du *value = metrics->Current.MemclkFrequency; 37686c8236eSXiaojian Du break; 37786c8236eSXiaojian Du case METRICS_AVERAGE_GFXACTIVITY: 37886c8236eSXiaojian Du *value = metrics->Current.GfxActivity; 37986c8236eSXiaojian Du break; 38086c8236eSXiaojian Du case METRICS_AVERAGE_VCNACTIVITY: 38186c8236eSXiaojian Du *value = metrics->Current.UvdActivity; 38286c8236eSXiaojian Du break; 38386c8236eSXiaojian Du case METRICS_AVERAGE_SOCKETPOWER: 38486c8236eSXiaojian Du *value = (metrics->Current.CurrentSocketPower << 8) / 38586c8236eSXiaojian Du 1000; 38686c8236eSXiaojian Du break; 38786c8236eSXiaojian Du case METRICS_TEMPERATURE_EDGE: 38886c8236eSXiaojian Du *value = metrics->Current.GfxTemperature / 100 * 38986c8236eSXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 39086c8236eSXiaojian Du break; 39186c8236eSXiaojian Du case METRICS_TEMPERATURE_HOTSPOT: 39286c8236eSXiaojian Du *value = metrics->Current.SocTemperature / 100 * 39386c8236eSXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 39486c8236eSXiaojian Du break; 39586c8236eSXiaojian Du case METRICS_THROTTLER_STATUS: 39686c8236eSXiaojian Du *value = metrics->Current.ThrottlerStatus; 39786c8236eSXiaojian Du break; 39886c8236eSXiaojian Du case METRICS_VOLTAGE_VDDGFX: 39986c8236eSXiaojian Du *value = metrics->Current.Voltage[2]; 40086c8236eSXiaojian Du break; 40186c8236eSXiaojian Du case METRICS_VOLTAGE_VDDSOC: 40286c8236eSXiaojian Du *value = metrics->Current.Voltage[1]; 40386c8236eSXiaojian Du break; 40486c8236eSXiaojian Du case METRICS_AVERAGE_CPUCLK: 40586c8236eSXiaojian Du memcpy(value, &metrics->Current.CoreFrequency[0], 40686c8236eSXiaojian Du smu->cpu_core_num * sizeof(uint16_t)); 40786c8236eSXiaojian Du break; 40886c8236eSXiaojian Du default: 40986c8236eSXiaojian Du *value = UINT_MAX; 41086c8236eSXiaojian Du break; 41186c8236eSXiaojian Du } 41286c8236eSXiaojian Du 41386c8236eSXiaojian Du mutex_unlock(&smu->metrics_lock); 41486c8236eSXiaojian Du 41586c8236eSXiaojian Du return ret; 41686c8236eSXiaojian Du } 41786c8236eSXiaojian Du 41886c8236eSXiaojian Du static int vangogh_common_get_smu_metrics_data(struct smu_context *smu, 41986c8236eSXiaojian Du MetricsMember_t member, 42086c8236eSXiaojian Du uint32_t *value) 42186c8236eSXiaojian Du { 42286c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev; 42386c8236eSXiaojian Du uint32_t if_version; 42486c8236eSXiaojian Du int ret = 0; 42586c8236eSXiaojian Du 42686c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 42786c8236eSXiaojian Du if (ret) { 42886c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n"); 42986c8236eSXiaojian Du return ret; 43086c8236eSXiaojian Du } 43186c8236eSXiaojian Du 43286c8236eSXiaojian Du if (if_version < 0x3) 43386c8236eSXiaojian Du ret = vangogh_get_legacy_smu_metrics_data(smu, member, value); 43486c8236eSXiaojian Du else 43586c8236eSXiaojian Du ret = vangogh_get_smu_metrics_data(smu, member, value); 43686c8236eSXiaojian Du 43786c8236eSXiaojian Du return ret; 43886c8236eSXiaojian Du } 43986c8236eSXiaojian Du 440f46a221bSXiaojian Du static int vangogh_allocate_dpm_context(struct smu_context *smu) 441f46a221bSXiaojian Du { 442f46a221bSXiaojian Du struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 443f46a221bSXiaojian Du 444f46a221bSXiaojian Du smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 445f46a221bSXiaojian Du GFP_KERNEL); 446f46a221bSXiaojian Du if (!smu_dpm->dpm_context) 447f46a221bSXiaojian Du return -ENOMEM; 448f46a221bSXiaojian Du 449f46a221bSXiaojian Du smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 450f46a221bSXiaojian Du 451f46a221bSXiaojian Du return 0; 452f46a221bSXiaojian Du } 453f46a221bSXiaojian Du 454f46a221bSXiaojian Du static int vangogh_init_smc_tables(struct smu_context *smu) 455f46a221bSXiaojian Du { 456f46a221bSXiaojian Du int ret = 0; 457f46a221bSXiaojian Du 458f46a221bSXiaojian Du ret = vangogh_tables_init(smu); 459f46a221bSXiaojian Du if (ret) 460f46a221bSXiaojian Du return ret; 461f46a221bSXiaojian Du 462f46a221bSXiaojian Du ret = vangogh_allocate_dpm_context(smu); 463f46a221bSXiaojian Du if (ret) 464f46a221bSXiaojian Du return ret; 465f46a221bSXiaojian Du 4664aef0ebcSHuang Rui #ifdef CONFIG_X86 4674aef0ebcSHuang Rui /* AMD x86 APU only */ 4684aef0ebcSHuang Rui smu->cpu_core_num = boot_cpu_data.x86_max_cores; 4694aef0ebcSHuang Rui #else 4704aef0ebcSHuang Rui smu->cpu_core_num = 4; 4714aef0ebcSHuang Rui #endif 4724aef0ebcSHuang Rui 473f46a221bSXiaojian Du return smu_v11_0_init_smc_tables(smu); 474f46a221bSXiaojian Du } 475f46a221bSXiaojian Du 476f46a221bSXiaojian Du static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 477f46a221bSXiaojian Du { 478f46a221bSXiaojian Du int ret = 0; 479f46a221bSXiaojian Du 480f46a221bSXiaojian Du if (enable) { 481f46a221bSXiaojian Du /* vcn dpm on is a prerequisite for vcn power gate messages */ 482f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 483f46a221bSXiaojian Du if (ret) 484f46a221bSXiaojian Du return ret; 485f46a221bSXiaojian Du } else { 486f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 487f46a221bSXiaojian Du if (ret) 488f46a221bSXiaojian Du return ret; 489f46a221bSXiaojian Du } 490f46a221bSXiaojian Du 491f46a221bSXiaojian Du return ret; 492f46a221bSXiaojian Du } 493f46a221bSXiaojian Du 494f46a221bSXiaojian Du static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 495f46a221bSXiaojian Du { 496f46a221bSXiaojian Du int ret = 0; 497f46a221bSXiaojian Du 498f46a221bSXiaojian Du if (enable) { 499f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 500f46a221bSXiaojian Du if (ret) 501f46a221bSXiaojian Du return ret; 502f46a221bSXiaojian Du } else { 503f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 504f46a221bSXiaojian Du if (ret) 505f46a221bSXiaojian Du return ret; 506f46a221bSXiaojian Du } 507f46a221bSXiaojian Du 508f46a221bSXiaojian Du return ret; 509f46a221bSXiaojian Du } 510f46a221bSXiaojian Du 511f46a221bSXiaojian Du static bool vangogh_is_dpm_running(struct smu_context *smu) 512f46a221bSXiaojian Du { 5131c0f0430SAlex Deucher struct amdgpu_device *adev = smu->adev; 514271ab489SXiaojian Du int ret = 0; 515271ab489SXiaojian Du uint32_t feature_mask[2]; 516271ab489SXiaojian Du uint64_t feature_enabled; 517f46a221bSXiaojian Du 5181c0f0430SAlex Deucher /* we need to re-init after suspend so return false */ 5191c0f0430SAlex Deucher if (adev->in_suspend) 5201c0f0430SAlex Deucher return false; 5211c0f0430SAlex Deucher 522271ab489SXiaojian Du ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 523271ab489SXiaojian Du 524271ab489SXiaojian Du if (ret) 525f46a221bSXiaojian Du return false; 526f46a221bSXiaojian Du 527271ab489SXiaojian Du feature_enabled = (unsigned long)((uint64_t)feature_mask[0] | 528271ab489SXiaojian Du ((uint64_t)feature_mask[1] << 32)); 529271ab489SXiaojian Du 530271ab489SXiaojian Du return !!(feature_enabled & SMC_DPM_FEATURE); 531271ab489SXiaojian Du } 532271ab489SXiaojian Du 533ae7b32e7SXiaojian Du static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 534ae7b32e7SXiaojian Du uint32_t dpm_level, uint32_t *freq) 535ae7b32e7SXiaojian Du { 536ae7b32e7SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 537ae7b32e7SXiaojian Du 538ae7b32e7SXiaojian Du if (!clk_table || clk_type >= SMU_CLK_COUNT) 539ae7b32e7SXiaojian Du return -EINVAL; 540ae7b32e7SXiaojian Du 541ae7b32e7SXiaojian Du switch (clk_type) { 542ae7b32e7SXiaojian Du case SMU_SOCCLK: 543ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 544ae7b32e7SXiaojian Du return -EINVAL; 545ae7b32e7SXiaojian Du *freq = clk_table->SocClocks[dpm_level]; 546ae7b32e7SXiaojian Du break; 547f02c7336SXiaojian Du case SMU_VCLK: 548f02c7336SXiaojian Du if (dpm_level >= clk_table->VcnClkLevelsEnabled) 549f02c7336SXiaojian Du return -EINVAL; 550f02c7336SXiaojian Du *freq = clk_table->VcnClocks[dpm_level].vclk; 551f02c7336SXiaojian Du break; 552f02c7336SXiaojian Du case SMU_DCLK: 553f02c7336SXiaojian Du if (dpm_level >= clk_table->VcnClkLevelsEnabled) 554f02c7336SXiaojian Du return -EINVAL; 555f02c7336SXiaojian Du *freq = clk_table->VcnClocks[dpm_level].dclk; 556f02c7336SXiaojian Du break; 557ae7b32e7SXiaojian Du case SMU_UCLK: 558ae7b32e7SXiaojian Du case SMU_MCLK: 559ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumDfPstatesEnabled) 560ae7b32e7SXiaojian Du return -EINVAL; 561ae7b32e7SXiaojian Du *freq = clk_table->DfPstateTable[dpm_level].memclk; 562ae7b32e7SXiaojian Du 563ae7b32e7SXiaojian Du break; 564ae7b32e7SXiaojian Du case SMU_FCLK: 565ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumDfPstatesEnabled) 566ae7b32e7SXiaojian Du return -EINVAL; 567ae7b32e7SXiaojian Du *freq = clk_table->DfPstateTable[dpm_level].fclk; 568ae7b32e7SXiaojian Du break; 569ae7b32e7SXiaojian Du default: 570ae7b32e7SXiaojian Du return -EINVAL; 571ae7b32e7SXiaojian Du } 572ae7b32e7SXiaojian Du 573ae7b32e7SXiaojian Du return 0; 574ae7b32e7SXiaojian Du } 575ae7b32e7SXiaojian Du 57686c8236eSXiaojian Du static int vangogh_print_legacy_clk_levels(struct smu_context *smu, 577c98ee897SXiaojian Du enum smu_clk_type clk_type, char *buf) 578c98ee897SXiaojian Du { 579ae7b32e7SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 58086c8236eSXiaojian Du SmuMetrics_legacy_t metrics; 581d7379efaSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 582ae7b32e7SXiaojian Du int i, size = 0, ret = 0; 583ae7b32e7SXiaojian Du uint32_t cur_value = 0, value = 0, count = 0; 584ae7b32e7SXiaojian Du bool cur_value_match_level = false; 585ae7b32e7SXiaojian Du 586ae7b32e7SXiaojian Du memset(&metrics, 0, sizeof(metrics)); 587ae7b32e7SXiaojian Du 588ae7b32e7SXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, false); 589ae7b32e7SXiaojian Du if (ret) 590ae7b32e7SXiaojian Du return ret; 591c98ee897SXiaojian Du 592c98ee897SXiaojian Du switch (clk_type) { 593c98ee897SXiaojian Du case SMU_OD_SCLK: 594d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 595*fe14c285SDarren Powell size = sysfs_emit(buf, "%s:\n", "OD_SCLK"); 596*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 597c98ee897SXiaojian Du (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 598*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 599c98ee897SXiaojian Du (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 600c98ee897SXiaojian Du } 601c98ee897SXiaojian Du break; 6020d90d0ddSHuang Rui case SMU_OD_CCLK: 603d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 604*fe14c285SDarren Powell size = sysfs_emit(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 605*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 6060d90d0ddSHuang Rui (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 607*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 6080d90d0ddSHuang Rui (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 6090d90d0ddSHuang Rui } 6100d90d0ddSHuang Rui break; 611c98ee897SXiaojian Du case SMU_OD_RANGE: 612d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 613*fe14c285SDarren Powell size = sysfs_emit(buf, "%s:\n", "OD_RANGE"); 614*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 615c98ee897SXiaojian Du smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 616*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 6170d90d0ddSHuang Rui smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 618c98ee897SXiaojian Du } 619c98ee897SXiaojian Du break; 620ae7b32e7SXiaojian Du case SMU_SOCCLK: 621ae7b32e7SXiaojian Du /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 622ae7b32e7SXiaojian Du count = clk_table->NumSocClkLevelsEnabled; 623ae7b32e7SXiaojian Du cur_value = metrics.SocclkFrequency; 624ae7b32e7SXiaojian Du break; 625f02c7336SXiaojian Du case SMU_VCLK: 626f02c7336SXiaojian Du count = clk_table->VcnClkLevelsEnabled; 627f02c7336SXiaojian Du cur_value = metrics.VclkFrequency; 628f02c7336SXiaojian Du break; 629f02c7336SXiaojian Du case SMU_DCLK: 630f02c7336SXiaojian Du count = clk_table->VcnClkLevelsEnabled; 631f02c7336SXiaojian Du cur_value = metrics.DclkFrequency; 632f02c7336SXiaojian Du break; 633ae7b32e7SXiaojian Du case SMU_MCLK: 634ae7b32e7SXiaojian Du count = clk_table->NumDfPstatesEnabled; 635ae7b32e7SXiaojian Du cur_value = metrics.MemclkFrequency; 636ae7b32e7SXiaojian Du break; 637ae7b32e7SXiaojian Du case SMU_FCLK: 638ae7b32e7SXiaojian Du count = clk_table->NumDfPstatesEnabled; 639ae7b32e7SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 640ae7b32e7SXiaojian Du if (ret) 641ae7b32e7SXiaojian Du return ret; 642ae7b32e7SXiaojian Du break; 643ae7b32e7SXiaojian Du default: 644ae7b32e7SXiaojian Du break; 645ae7b32e7SXiaojian Du } 646ae7b32e7SXiaojian Du 647ae7b32e7SXiaojian Du switch (clk_type) { 648ae7b32e7SXiaojian Du case SMU_SOCCLK: 649f02c7336SXiaojian Du case SMU_VCLK: 650f02c7336SXiaojian Du case SMU_DCLK: 651ae7b32e7SXiaojian Du case SMU_MCLK: 652ae7b32e7SXiaojian Du case SMU_FCLK: 653ae7b32e7SXiaojian Du for (i = 0; i < count; i++) { 654ae7b32e7SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 655ae7b32e7SXiaojian Du if (ret) 656ae7b32e7SXiaojian Du return ret; 657ae7b32e7SXiaojian Du if (!value) 658ae7b32e7SXiaojian Du continue; 659*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 660ae7b32e7SXiaojian Du cur_value == value ? "*" : ""); 661ae7b32e7SXiaojian Du if (cur_value == value) 662ae7b32e7SXiaojian Du cur_value_match_level = true; 663ae7b32e7SXiaojian Du } 664ae7b32e7SXiaojian Du 665ae7b32e7SXiaojian Du if (!cur_value_match_level) 666*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 667ae7b32e7SXiaojian Du break; 668c98ee897SXiaojian Du default: 669c98ee897SXiaojian Du break; 670c98ee897SXiaojian Du } 671c98ee897SXiaojian Du 672c98ee897SXiaojian Du return size; 673c98ee897SXiaojian Du } 674c98ee897SXiaojian Du 67586c8236eSXiaojian Du static int vangogh_print_clk_levels(struct smu_context *smu, 67686c8236eSXiaojian Du enum smu_clk_type clk_type, char *buf) 67786c8236eSXiaojian Du { 67886c8236eSXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 67986c8236eSXiaojian Du SmuMetrics_t metrics; 68086c8236eSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 68186c8236eSXiaojian Du int i, size = 0, ret = 0; 68286c8236eSXiaojian Du uint32_t cur_value = 0, value = 0, count = 0; 68386c8236eSXiaojian Du bool cur_value_match_level = false; 68486c8236eSXiaojian Du 68586c8236eSXiaojian Du memset(&metrics, 0, sizeof(metrics)); 68686c8236eSXiaojian Du 68786c8236eSXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, false); 68886c8236eSXiaojian Du if (ret) 68986c8236eSXiaojian Du return ret; 69086c8236eSXiaojian Du 69186c8236eSXiaojian Du switch (clk_type) { 69286c8236eSXiaojian Du case SMU_OD_SCLK: 69386c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 694*fe14c285SDarren Powell size = sysfs_emit(buf, "%s:\n", "OD_SCLK"); 695*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 69686c8236eSXiaojian Du (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 697*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 69886c8236eSXiaojian Du (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 69986c8236eSXiaojian Du } 70086c8236eSXiaojian Du break; 70186c8236eSXiaojian Du case SMU_OD_CCLK: 70286c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 703*fe14c285SDarren Powell size = sysfs_emit(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 704*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 70586c8236eSXiaojian Du (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 706*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 70786c8236eSXiaojian Du (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 70886c8236eSXiaojian Du } 70986c8236eSXiaojian Du break; 71086c8236eSXiaojian Du case SMU_OD_RANGE: 71186c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 712*fe14c285SDarren Powell size = sysfs_emit(buf, "%s:\n", "OD_RANGE"); 713*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 71486c8236eSXiaojian Du smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 715*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 71686c8236eSXiaojian Du smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 71786c8236eSXiaojian Du } 71886c8236eSXiaojian Du break; 71986c8236eSXiaojian Du case SMU_SOCCLK: 72086c8236eSXiaojian Du /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 72186c8236eSXiaojian Du count = clk_table->NumSocClkLevelsEnabled; 72286c8236eSXiaojian Du cur_value = metrics.Current.SocclkFrequency; 72386c8236eSXiaojian Du break; 72486c8236eSXiaojian Du case SMU_VCLK: 72586c8236eSXiaojian Du count = clk_table->VcnClkLevelsEnabled; 72686c8236eSXiaojian Du cur_value = metrics.Current.VclkFrequency; 72786c8236eSXiaojian Du break; 72886c8236eSXiaojian Du case SMU_DCLK: 72986c8236eSXiaojian Du count = clk_table->VcnClkLevelsEnabled; 73086c8236eSXiaojian Du cur_value = metrics.Current.DclkFrequency; 73186c8236eSXiaojian Du break; 73286c8236eSXiaojian Du case SMU_MCLK: 73386c8236eSXiaojian Du count = clk_table->NumDfPstatesEnabled; 73486c8236eSXiaojian Du cur_value = metrics.Current.MemclkFrequency; 73586c8236eSXiaojian Du break; 73686c8236eSXiaojian Du case SMU_FCLK: 73786c8236eSXiaojian Du count = clk_table->NumDfPstatesEnabled; 73886c8236eSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 73986c8236eSXiaojian Du if (ret) 74086c8236eSXiaojian Du return ret; 74186c8236eSXiaojian Du break; 74286c8236eSXiaojian Du default: 74386c8236eSXiaojian Du break; 74486c8236eSXiaojian Du } 74586c8236eSXiaojian Du 74686c8236eSXiaojian Du switch (clk_type) { 74786c8236eSXiaojian Du case SMU_SOCCLK: 74886c8236eSXiaojian Du case SMU_VCLK: 74986c8236eSXiaojian Du case SMU_DCLK: 75086c8236eSXiaojian Du case SMU_MCLK: 75186c8236eSXiaojian Du case SMU_FCLK: 75286c8236eSXiaojian Du for (i = 0; i < count; i++) { 75386c8236eSXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 75486c8236eSXiaojian Du if (ret) 75586c8236eSXiaojian Du return ret; 75686c8236eSXiaojian Du if (!value) 75786c8236eSXiaojian Du continue; 758*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 75986c8236eSXiaojian Du cur_value == value ? "*" : ""); 76086c8236eSXiaojian Du if (cur_value == value) 76186c8236eSXiaojian Du cur_value_match_level = true; 76286c8236eSXiaojian Du } 76386c8236eSXiaojian Du 76486c8236eSXiaojian Du if (!cur_value_match_level) 765*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 76686c8236eSXiaojian Du break; 76786c8236eSXiaojian Du default: 76886c8236eSXiaojian Du break; 76986c8236eSXiaojian Du } 77086c8236eSXiaojian Du 77186c8236eSXiaojian Du return size; 77286c8236eSXiaojian Du } 77386c8236eSXiaojian Du 77486c8236eSXiaojian Du static int vangogh_common_print_clk_levels(struct smu_context *smu, 77586c8236eSXiaojian Du enum smu_clk_type clk_type, char *buf) 77686c8236eSXiaojian Du { 77786c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev; 77886c8236eSXiaojian Du uint32_t if_version; 77986c8236eSXiaojian Du int ret = 0; 78086c8236eSXiaojian Du 78186c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 78286c8236eSXiaojian Du if (ret) { 78386c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n"); 78486c8236eSXiaojian Du return ret; 78586c8236eSXiaojian Du } 78686c8236eSXiaojian Du 78786c8236eSXiaojian Du if (if_version < 0x3) 78886c8236eSXiaojian Du ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf); 78986c8236eSXiaojian Du else 79086c8236eSXiaojian Du ret = vangogh_print_clk_levels(smu, clk_type, buf); 79186c8236eSXiaojian Du 79286c8236eSXiaojian Du return ret; 79386c8236eSXiaojian Du } 79486c8236eSXiaojian Du 795d0e4e112SXiaojian Du static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 796d0e4e112SXiaojian Du enum amd_dpm_forced_level level, 797d0e4e112SXiaojian Du uint32_t *vclk_mask, 798d0e4e112SXiaojian Du uint32_t *dclk_mask, 799d0e4e112SXiaojian Du uint32_t *mclk_mask, 800d0e4e112SXiaojian Du uint32_t *fclk_mask, 801d0e4e112SXiaojian Du uint32_t *soc_mask) 802d0e4e112SXiaojian Du { 803d0e4e112SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 804d0e4e112SXiaojian Du 805307f049bSXiaojian Du if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 806d0e4e112SXiaojian Du if (mclk_mask) 807d0e4e112SXiaojian Du *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 808307f049bSXiaojian Du 809d0e4e112SXiaojian Du if (fclk_mask) 810d0e4e112SXiaojian Du *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 811307f049bSXiaojian Du 812307f049bSXiaojian Du if (soc_mask) 813307f049bSXiaojian Du *soc_mask = 0; 814d0e4e112SXiaojian Du } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 815d0e4e112SXiaojian Du if (mclk_mask) 816d0e4e112SXiaojian Du *mclk_mask = 0; 817307f049bSXiaojian Du 818d0e4e112SXiaojian Du if (fclk_mask) 819d0e4e112SXiaojian Du *fclk_mask = 0; 820d0e4e112SXiaojian Du 821d0e4e112SXiaojian Du if (soc_mask) 822307f049bSXiaojian Du *soc_mask = 1; 823307f049bSXiaojian Du 824307f049bSXiaojian Du if (vclk_mask) 825307f049bSXiaojian Du *vclk_mask = 1; 826307f049bSXiaojian Du 827307f049bSXiaojian Du if (dclk_mask) 828307f049bSXiaojian Du *dclk_mask = 1; 829307f049bSXiaojian Du } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 830307f049bSXiaojian Du if (mclk_mask) 831307f049bSXiaojian Du *mclk_mask = 0; 832307f049bSXiaojian Du 833307f049bSXiaojian Du if (fclk_mask) 834307f049bSXiaojian Du *fclk_mask = 0; 835307f049bSXiaojian Du 836307f049bSXiaojian Du if (soc_mask) 837307f049bSXiaojian Du *soc_mask = 1; 838307f049bSXiaojian Du 839307f049bSXiaojian Du if (vclk_mask) 840307f049bSXiaojian Du *vclk_mask = 1; 841307f049bSXiaojian Du 842307f049bSXiaojian Du if (dclk_mask) 843307f049bSXiaojian Du *dclk_mask = 1; 844d0e4e112SXiaojian Du } 845d0e4e112SXiaojian Du 846d0e4e112SXiaojian Du return 0; 847d0e4e112SXiaojian Du } 848d0e4e112SXiaojian Du 8498f8150faSSouptick Joarder static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 850d0e4e112SXiaojian Du enum smu_clk_type clk_type) 851d0e4e112SXiaojian Du { 852d0e4e112SXiaojian Du enum smu_feature_mask feature_id = 0; 853d0e4e112SXiaojian Du 854d0e4e112SXiaojian Du switch (clk_type) { 855d0e4e112SXiaojian Du case SMU_MCLK: 856d0e4e112SXiaojian Du case SMU_UCLK: 857d0e4e112SXiaojian Du case SMU_FCLK: 858d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_FCLK_BIT; 859d0e4e112SXiaojian Du break; 860d0e4e112SXiaojian Du case SMU_GFXCLK: 861d0e4e112SXiaojian Du case SMU_SCLK: 862d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 863d0e4e112SXiaojian Du break; 864d0e4e112SXiaojian Du case SMU_SOCCLK: 865d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 866d0e4e112SXiaojian Du break; 867d0e4e112SXiaojian Du case SMU_VCLK: 868d0e4e112SXiaojian Du case SMU_DCLK: 869d0e4e112SXiaojian Du feature_id = SMU_FEATURE_VCN_DPM_BIT; 870d0e4e112SXiaojian Du break; 871d0e4e112SXiaojian Du default: 872d0e4e112SXiaojian Du return true; 873d0e4e112SXiaojian Du } 874d0e4e112SXiaojian Du 875d0e4e112SXiaojian Du if (!smu_cmn_feature_is_enabled(smu, feature_id)) 876d0e4e112SXiaojian Du return false; 877d0e4e112SXiaojian Du 878d0e4e112SXiaojian Du return true; 879d0e4e112SXiaojian Du } 880d0e4e112SXiaojian Du 881d0e4e112SXiaojian Du static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 882d0e4e112SXiaojian Du enum smu_clk_type clk_type, 883d0e4e112SXiaojian Du uint32_t *min, 884d0e4e112SXiaojian Du uint32_t *max) 885d0e4e112SXiaojian Du { 886d0e4e112SXiaojian Du int ret = 0; 887d0e4e112SXiaojian Du uint32_t soc_mask; 888d0e4e112SXiaojian Du uint32_t vclk_mask; 889d0e4e112SXiaojian Du uint32_t dclk_mask; 890d0e4e112SXiaojian Du uint32_t mclk_mask; 891d0e4e112SXiaojian Du uint32_t fclk_mask; 892d0e4e112SXiaojian Du uint32_t clock_limit; 893d0e4e112SXiaojian Du 894d0e4e112SXiaojian Du if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 895d0e4e112SXiaojian Du switch (clk_type) { 896d0e4e112SXiaojian Du case SMU_MCLK: 897d0e4e112SXiaojian Du case SMU_UCLK: 898d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.uclk; 899d0e4e112SXiaojian Du break; 900d0e4e112SXiaojian Du case SMU_FCLK: 901d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.fclk; 902d0e4e112SXiaojian Du break; 903d0e4e112SXiaojian Du case SMU_GFXCLK: 904d0e4e112SXiaojian Du case SMU_SCLK: 905d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.gfxclk; 906d0e4e112SXiaojian Du break; 907d0e4e112SXiaojian Du case SMU_SOCCLK: 908d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.socclk; 909d0e4e112SXiaojian Du break; 910d0e4e112SXiaojian Du case SMU_VCLK: 911d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.vclk; 912d0e4e112SXiaojian Du break; 913d0e4e112SXiaojian Du case SMU_DCLK: 914d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.dclk; 915d0e4e112SXiaojian Du break; 916d0e4e112SXiaojian Du default: 917d0e4e112SXiaojian Du clock_limit = 0; 918d0e4e112SXiaojian Du break; 919d0e4e112SXiaojian Du } 920d0e4e112SXiaojian Du 921d0e4e112SXiaojian Du /* clock in Mhz unit */ 922d0e4e112SXiaojian Du if (min) 923d0e4e112SXiaojian Du *min = clock_limit / 100; 924d0e4e112SXiaojian Du if (max) 925d0e4e112SXiaojian Du *max = clock_limit / 100; 926d0e4e112SXiaojian Du 927d0e4e112SXiaojian Du return 0; 928d0e4e112SXiaojian Du } 929d0e4e112SXiaojian Du if (max) { 930d0e4e112SXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, 931d0e4e112SXiaojian Du AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 932d0e4e112SXiaojian Du &vclk_mask, 933d0e4e112SXiaojian Du &dclk_mask, 934d0e4e112SXiaojian Du &mclk_mask, 935d0e4e112SXiaojian Du &fclk_mask, 936d0e4e112SXiaojian Du &soc_mask); 937d0e4e112SXiaojian Du if (ret) 938d0e4e112SXiaojian Du goto failed; 939d0e4e112SXiaojian Du 940d0e4e112SXiaojian Du switch (clk_type) { 941d0e4e112SXiaojian Du case SMU_UCLK: 942d0e4e112SXiaojian Du case SMU_MCLK: 943d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 944d0e4e112SXiaojian Du if (ret) 945d0e4e112SXiaojian Du goto failed; 946d0e4e112SXiaojian Du break; 947d0e4e112SXiaojian Du case SMU_SOCCLK: 948d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 949d0e4e112SXiaojian Du if (ret) 950d0e4e112SXiaojian Du goto failed; 951d0e4e112SXiaojian Du break; 952d0e4e112SXiaojian Du case SMU_FCLK: 953d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 954d0e4e112SXiaojian Du if (ret) 955d0e4e112SXiaojian Du goto failed; 956d0e4e112SXiaojian Du break; 957d0e4e112SXiaojian Du case SMU_VCLK: 958d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 959d0e4e112SXiaojian Du if (ret) 960d0e4e112SXiaojian Du goto failed; 961d0e4e112SXiaojian Du break; 962d0e4e112SXiaojian Du case SMU_DCLK: 963d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 964d0e4e112SXiaojian Du if (ret) 965d0e4e112SXiaojian Du goto failed; 966d0e4e112SXiaojian Du break; 967d0e4e112SXiaojian Du default: 968d0e4e112SXiaojian Du ret = -EINVAL; 969d0e4e112SXiaojian Du goto failed; 970d0e4e112SXiaojian Du } 971d0e4e112SXiaojian Du } 972d0e4e112SXiaojian Du if (min) { 973d0e4e112SXiaojian Du switch (clk_type) { 974d0e4e112SXiaojian Du case SMU_UCLK: 975d0e4e112SXiaojian Du case SMU_MCLK: 976d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 977d0e4e112SXiaojian Du if (ret) 978d0e4e112SXiaojian Du goto failed; 979d0e4e112SXiaojian Du break; 980d0e4e112SXiaojian Du case SMU_SOCCLK: 981d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 982d0e4e112SXiaojian Du if (ret) 983d0e4e112SXiaojian Du goto failed; 984d0e4e112SXiaojian Du break; 985d0e4e112SXiaojian Du case SMU_FCLK: 986d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 987d0e4e112SXiaojian Du if (ret) 988d0e4e112SXiaojian Du goto failed; 989d0e4e112SXiaojian Du break; 990d0e4e112SXiaojian Du case SMU_VCLK: 991d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 992d0e4e112SXiaojian Du if (ret) 993d0e4e112SXiaojian Du goto failed; 994d0e4e112SXiaojian Du break; 995d0e4e112SXiaojian Du case SMU_DCLK: 996d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 997d0e4e112SXiaojian Du if (ret) 998d0e4e112SXiaojian Du goto failed; 999d0e4e112SXiaojian Du break; 1000d0e4e112SXiaojian Du default: 1001d0e4e112SXiaojian Du ret = -EINVAL; 1002d0e4e112SXiaojian Du goto failed; 1003d0e4e112SXiaojian Du } 1004d0e4e112SXiaojian Du } 1005d0e4e112SXiaojian Du failed: 1006d0e4e112SXiaojian Du return ret; 1007d0e4e112SXiaojian Du } 1008d0e4e112SXiaojian Du 1009307f049bSXiaojian Du static int vangogh_get_power_profile_mode(struct smu_context *smu, 1010307f049bSXiaojian Du char *buf) 1011307f049bSXiaojian Du { 1012307f049bSXiaojian Du static const char *profile_name[] = { 10132a38ca99SColin Ian King "BOOTUP_DEFAULT", 1014f727ebebSXiaojian Du "3D_FULL_SCREEN", 1015f727ebebSXiaojian Du "POWER_SAVING", 1016307f049bSXiaojian Du "VIDEO", 1017307f049bSXiaojian Du "VR", 1018307f049bSXiaojian Du "COMPUTE", 1019307f049bSXiaojian Du "CUSTOM"}; 1020307f049bSXiaojian Du uint32_t i, size = 0; 1021307f049bSXiaojian Du int16_t workload_type = 0; 1022307f049bSXiaojian Du 1023307f049bSXiaojian Du if (!buf) 1024307f049bSXiaojian Du return -EINVAL; 1025307f049bSXiaojian Du 1026307f049bSXiaojian Du for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1027307f049bSXiaojian Du /* 1028307f049bSXiaojian Du * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1029307f049bSXiaojian Du * Not all profile modes are supported on vangogh. 1030307f049bSXiaojian Du */ 1031307f049bSXiaojian Du workload_type = smu_cmn_to_asic_specific_index(smu, 1032307f049bSXiaojian Du CMN2ASIC_MAPPING_WORKLOAD, 1033307f049bSXiaojian Du i); 1034307f049bSXiaojian Du 1035307f049bSXiaojian Du if (workload_type < 0) 1036307f049bSXiaojian Du continue; 1037307f049bSXiaojian Du 1038*fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 1039307f049bSXiaojian Du i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1040307f049bSXiaojian Du } 1041307f049bSXiaojian Du 1042307f049bSXiaojian Du return size; 1043307f049bSXiaojian Du } 1044307f049bSXiaojian Du 1045d0e4e112SXiaojian Du static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1046d0e4e112SXiaojian Du { 1047d0e4e112SXiaojian Du int workload_type, ret; 1048d0e4e112SXiaojian Du uint32_t profile_mode = input[size]; 1049d0e4e112SXiaojian Du 1050d0e4e112SXiaojian Du if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1051d0e4e112SXiaojian Du dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1052d0e4e112SXiaojian Du return -EINVAL; 1053d0e4e112SXiaojian Du } 1054d0e4e112SXiaojian Du 1055f727ebebSXiaojian Du if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 1056f727ebebSXiaojian Du profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 1057f727ebebSXiaojian Du return 0; 1058f727ebebSXiaojian Du 1059d0e4e112SXiaojian Du /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1060d0e4e112SXiaojian Du workload_type = smu_cmn_to_asic_specific_index(smu, 1061d0e4e112SXiaojian Du CMN2ASIC_MAPPING_WORKLOAD, 1062d0e4e112SXiaojian Du profile_mode); 1063d0e4e112SXiaojian Du if (workload_type < 0) { 10649d489afdSAlex Deucher dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 1065d0e4e112SXiaojian Du profile_mode); 1066d0e4e112SXiaojian Du return -EINVAL; 1067d0e4e112SXiaojian Du } 1068d0e4e112SXiaojian Du 1069d0e4e112SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 1070d0e4e112SXiaojian Du 1 << workload_type, 1071d0e4e112SXiaojian Du NULL); 1072d0e4e112SXiaojian Du if (ret) { 1073d0e4e112SXiaojian Du dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 1074d0e4e112SXiaojian Du workload_type); 1075d0e4e112SXiaojian Du return ret; 1076d0e4e112SXiaojian Du } 1077d0e4e112SXiaojian Du 1078d0e4e112SXiaojian Du smu->power_profile_mode = profile_mode; 1079d0e4e112SXiaojian Du 1080d0e4e112SXiaojian Du return 0; 1081d0e4e112SXiaojian Du } 1082d0e4e112SXiaojian Du 1083dd9e0b21SXiaojian Du static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 1084dd9e0b21SXiaojian Du enum smu_clk_type clk_type, 1085dd9e0b21SXiaojian Du uint32_t min, 1086dd9e0b21SXiaojian Du uint32_t max) 1087dd9e0b21SXiaojian Du { 1088dd9e0b21SXiaojian Du int ret = 0; 1089dd9e0b21SXiaojian Du 1090dd9e0b21SXiaojian Du if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 1091dd9e0b21SXiaojian Du return 0; 1092dd9e0b21SXiaojian Du 1093dd9e0b21SXiaojian Du switch (clk_type) { 1094dd9e0b21SXiaojian Du case SMU_GFXCLK: 1095dd9e0b21SXiaojian Du case SMU_SCLK: 1096dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1097dd9e0b21SXiaojian Du SMU_MSG_SetHardMinGfxClk, 1098dd9e0b21SXiaojian Du min, NULL); 1099dd9e0b21SXiaojian Du if (ret) 1100dd9e0b21SXiaojian Du return ret; 1101dd9e0b21SXiaojian Du 1102dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1103dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxGfxClk, 1104dd9e0b21SXiaojian Du max, NULL); 1105dd9e0b21SXiaojian Du if (ret) 1106dd9e0b21SXiaojian Du return ret; 1107dd9e0b21SXiaojian Du break; 1108dd9e0b21SXiaojian Du case SMU_FCLK: 1109dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1110dd9e0b21SXiaojian Du SMU_MSG_SetHardMinFclkByFreq, 1111dd9e0b21SXiaojian Du min, NULL); 1112dd9e0b21SXiaojian Du if (ret) 1113dd9e0b21SXiaojian Du return ret; 1114dd9e0b21SXiaojian Du 1115dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1116dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxFclkByFreq, 1117dd9e0b21SXiaojian Du max, NULL); 1118dd9e0b21SXiaojian Du if (ret) 1119dd9e0b21SXiaojian Du return ret; 1120dd9e0b21SXiaojian Du break; 1121dd9e0b21SXiaojian Du case SMU_SOCCLK: 1122dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1123dd9e0b21SXiaojian Du SMU_MSG_SetHardMinSocclkByFreq, 1124dd9e0b21SXiaojian Du min, NULL); 1125dd9e0b21SXiaojian Du if (ret) 1126dd9e0b21SXiaojian Du return ret; 1127dd9e0b21SXiaojian Du 1128dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1129dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxSocclkByFreq, 1130dd9e0b21SXiaojian Du max, NULL); 1131dd9e0b21SXiaojian Du if (ret) 1132dd9e0b21SXiaojian Du return ret; 1133dd9e0b21SXiaojian Du break; 1134dd9e0b21SXiaojian Du case SMU_VCLK: 1135dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1136dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn, 1137dd9e0b21SXiaojian Du min << 16, NULL); 1138dd9e0b21SXiaojian Du if (ret) 1139dd9e0b21SXiaojian Du return ret; 1140dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1141dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxVcn, 1142dd9e0b21SXiaojian Du max << 16, NULL); 1143dd9e0b21SXiaojian Du if (ret) 1144dd9e0b21SXiaojian Du return ret; 1145dd9e0b21SXiaojian Du break; 1146dd9e0b21SXiaojian Du case SMU_DCLK: 1147dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1148dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn, 1149dd9e0b21SXiaojian Du min, NULL); 1150dd9e0b21SXiaojian Du if (ret) 1151dd9e0b21SXiaojian Du return ret; 1152dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1153dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxVcn, 1154dd9e0b21SXiaojian Du max, NULL); 1155dd9e0b21SXiaojian Du if (ret) 1156dd9e0b21SXiaojian Du return ret; 1157dd9e0b21SXiaojian Du break; 1158dd9e0b21SXiaojian Du default: 1159dd9e0b21SXiaojian Du return -EINVAL; 1160dd9e0b21SXiaojian Du } 1161dd9e0b21SXiaojian Du 1162dd9e0b21SXiaojian Du return ret; 1163dd9e0b21SXiaojian Du } 1164dd9e0b21SXiaojian Du 1165dd9e0b21SXiaojian Du static int vangogh_force_clk_levels(struct smu_context *smu, 1166dd9e0b21SXiaojian Du enum smu_clk_type clk_type, uint32_t mask) 1167dd9e0b21SXiaojian Du { 1168dd9e0b21SXiaojian Du uint32_t soft_min_level = 0, soft_max_level = 0; 1169dd9e0b21SXiaojian Du uint32_t min_freq = 0, max_freq = 0; 1170dd9e0b21SXiaojian Du int ret = 0 ; 1171dd9e0b21SXiaojian Du 1172dd9e0b21SXiaojian Du soft_min_level = mask ? (ffs(mask) - 1) : 0; 1173dd9e0b21SXiaojian Du soft_max_level = mask ? (fls(mask) - 1) : 0; 1174dd9e0b21SXiaojian Du 1175dd9e0b21SXiaojian Du switch (clk_type) { 1176dd9e0b21SXiaojian Du case SMU_SOCCLK: 1177dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1178dd9e0b21SXiaojian Du soft_min_level, &min_freq); 1179dd9e0b21SXiaojian Du if (ret) 1180dd9e0b21SXiaojian Du return ret; 1181dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1182dd9e0b21SXiaojian Du soft_max_level, &max_freq); 1183dd9e0b21SXiaojian Du if (ret) 1184dd9e0b21SXiaojian Du return ret; 1185dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1186dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxSocclkByFreq, 1187dd9e0b21SXiaojian Du max_freq, NULL); 1188dd9e0b21SXiaojian Du if (ret) 1189dd9e0b21SXiaojian Du return ret; 1190dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1191dd9e0b21SXiaojian Du SMU_MSG_SetHardMinSocclkByFreq, 1192dd9e0b21SXiaojian Du min_freq, NULL); 1193dd9e0b21SXiaojian Du if (ret) 1194dd9e0b21SXiaojian Du return ret; 1195dd9e0b21SXiaojian Du break; 1196dd9e0b21SXiaojian Du case SMU_FCLK: 1197dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1198dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq); 1199dd9e0b21SXiaojian Du if (ret) 1200dd9e0b21SXiaojian Du return ret; 1201dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1202dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq); 1203dd9e0b21SXiaojian Du if (ret) 1204dd9e0b21SXiaojian Du return ret; 1205dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1206dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxFclkByFreq, 1207dd9e0b21SXiaojian Du max_freq, NULL); 1208dd9e0b21SXiaojian Du if (ret) 1209dd9e0b21SXiaojian Du return ret; 1210dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1211dd9e0b21SXiaojian Du SMU_MSG_SetHardMinFclkByFreq, 1212dd9e0b21SXiaojian Du min_freq, NULL); 1213dd9e0b21SXiaojian Du if (ret) 1214dd9e0b21SXiaojian Du return ret; 1215dd9e0b21SXiaojian Du break; 1216dd9e0b21SXiaojian Du case SMU_VCLK: 1217dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1218dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq); 1219dd9e0b21SXiaojian Du if (ret) 1220dd9e0b21SXiaojian Du return ret; 1221307f049bSXiaojian Du 1222dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1223dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq); 1224dd9e0b21SXiaojian Du if (ret) 1225dd9e0b21SXiaojian Du return ret; 1226307f049bSXiaojian Du 1227307f049bSXiaojian Du 1228dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1229dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn, 1230dd9e0b21SXiaojian Du min_freq << 16, NULL); 1231dd9e0b21SXiaojian Du if (ret) 1232dd9e0b21SXiaojian Du return ret; 1233307f049bSXiaojian Du 1234307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1235307f049bSXiaojian Du SMU_MSG_SetSoftMaxVcn, 1236307f049bSXiaojian Du max_freq << 16, NULL); 1237307f049bSXiaojian Du if (ret) 1238307f049bSXiaojian Du return ret; 1239307f049bSXiaojian Du 1240dd9e0b21SXiaojian Du break; 1241dd9e0b21SXiaojian Du case SMU_DCLK: 1242dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1243dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq); 1244dd9e0b21SXiaojian Du if (ret) 1245dd9e0b21SXiaojian Du return ret; 1246307f049bSXiaojian Du 1247dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1248dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq); 1249dd9e0b21SXiaojian Du if (ret) 1250dd9e0b21SXiaojian Du return ret; 1251307f049bSXiaojian Du 1252dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1253dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn, 1254dd9e0b21SXiaojian Du min_freq, NULL); 1255dd9e0b21SXiaojian Du if (ret) 1256dd9e0b21SXiaojian Du return ret; 1257307f049bSXiaojian Du 1258307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1259307f049bSXiaojian Du SMU_MSG_SetSoftMaxVcn, 1260307f049bSXiaojian Du max_freq, NULL); 1261307f049bSXiaojian Du if (ret) 1262307f049bSXiaojian Du return ret; 1263307f049bSXiaojian Du 1264dd9e0b21SXiaojian Du break; 1265dd9e0b21SXiaojian Du default: 1266dd9e0b21SXiaojian Du break; 1267dd9e0b21SXiaojian Du } 1268dd9e0b21SXiaojian Du 1269dd9e0b21SXiaojian Du return ret; 1270dd9e0b21SXiaojian Du } 1271dd9e0b21SXiaojian Du 1272dd9e0b21SXiaojian Du static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1273dd9e0b21SXiaojian Du { 1274dd9e0b21SXiaojian Du int ret = 0, i = 0; 1275dd9e0b21SXiaojian Du uint32_t min_freq, max_freq, force_freq; 1276dd9e0b21SXiaojian Du enum smu_clk_type clk_type; 1277dd9e0b21SXiaojian Du 1278dd9e0b21SXiaojian Du enum smu_clk_type clks[] = { 1279dd9e0b21SXiaojian Du SMU_SOCCLK, 1280dd9e0b21SXiaojian Du SMU_VCLK, 1281dd9e0b21SXiaojian Du SMU_DCLK, 1282dd9e0b21SXiaojian Du SMU_FCLK, 1283dd9e0b21SXiaojian Du }; 1284dd9e0b21SXiaojian Du 1285dd9e0b21SXiaojian Du for (i = 0; i < ARRAY_SIZE(clks); i++) { 1286dd9e0b21SXiaojian Du clk_type = clks[i]; 1287dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1288dd9e0b21SXiaojian Du if (ret) 1289dd9e0b21SXiaojian Du return ret; 1290dd9e0b21SXiaojian Du 1291dd9e0b21SXiaojian Du force_freq = highest ? max_freq : min_freq; 1292dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1293dd9e0b21SXiaojian Du if (ret) 1294dd9e0b21SXiaojian Du return ret; 1295dd9e0b21SXiaojian Du } 1296dd9e0b21SXiaojian Du 1297dd9e0b21SXiaojian Du return ret; 1298dd9e0b21SXiaojian Du } 1299dd9e0b21SXiaojian Du 1300dd9e0b21SXiaojian Du static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1301dd9e0b21SXiaojian Du { 1302dd9e0b21SXiaojian Du int ret = 0, i = 0; 1303dd9e0b21SXiaojian Du uint32_t min_freq, max_freq; 1304dd9e0b21SXiaojian Du enum smu_clk_type clk_type; 1305dd9e0b21SXiaojian Du 1306dd9e0b21SXiaojian Du struct clk_feature_map { 1307dd9e0b21SXiaojian Du enum smu_clk_type clk_type; 1308dd9e0b21SXiaojian Du uint32_t feature; 1309dd9e0b21SXiaojian Du } clk_feature_map[] = { 1310dd9e0b21SXiaojian Du {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1311dd9e0b21SXiaojian Du {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1312b0eec124SXiaojian Du {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1313b0eec124SXiaojian Du {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1314dd9e0b21SXiaojian Du }; 1315dd9e0b21SXiaojian Du 1316dd9e0b21SXiaojian Du for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1317dd9e0b21SXiaojian Du 1318dd9e0b21SXiaojian Du if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1319dd9e0b21SXiaojian Du continue; 1320dd9e0b21SXiaojian Du 1321dd9e0b21SXiaojian Du clk_type = clk_feature_map[i].clk_type; 1322dd9e0b21SXiaojian Du 1323dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1324dd9e0b21SXiaojian Du 1325dd9e0b21SXiaojian Du if (ret) 1326dd9e0b21SXiaojian Du return ret; 1327dd9e0b21SXiaojian Du 1328dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1329dd9e0b21SXiaojian Du 1330dd9e0b21SXiaojian Du if (ret) 1331dd9e0b21SXiaojian Du return ret; 1332dd9e0b21SXiaojian Du } 1333dd9e0b21SXiaojian Du 1334dd9e0b21SXiaojian Du return ret; 1335dd9e0b21SXiaojian Du } 1336dd9e0b21SXiaojian Du 1337dd9e0b21SXiaojian Du static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1338dd9e0b21SXiaojian Du { 1339dd9e0b21SXiaojian Du int ret = 0; 1340dd9e0b21SXiaojian Du uint32_t socclk_freq = 0, fclk_freq = 0; 1341307f049bSXiaojian Du uint32_t vclk_freq = 0, dclk_freq = 0; 1342dd9e0b21SXiaojian Du 1343dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1344dd9e0b21SXiaojian Du if (ret) 1345dd9e0b21SXiaojian Du return ret; 1346dd9e0b21SXiaojian Du 1347dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1348dd9e0b21SXiaojian Du if (ret) 1349dd9e0b21SXiaojian Du return ret; 1350dd9e0b21SXiaojian Du 1351dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1352dd9e0b21SXiaojian Du if (ret) 1353dd9e0b21SXiaojian Du return ret; 1354dd9e0b21SXiaojian Du 1355dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1356dd9e0b21SXiaojian Du if (ret) 1357dd9e0b21SXiaojian Du return ret; 1358dd9e0b21SXiaojian Du 1359307f049bSXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1360307f049bSXiaojian Du if (ret) 1361307f049bSXiaojian Du return ret; 1362307f049bSXiaojian Du 1363307f049bSXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1364307f049bSXiaojian Du if (ret) 1365307f049bSXiaojian Du return ret; 1366307f049bSXiaojian Du 1367307f049bSXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1368307f049bSXiaojian Du if (ret) 1369307f049bSXiaojian Du return ret; 1370307f049bSXiaojian Du 1371307f049bSXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1372307f049bSXiaojian Du if (ret) 1373307f049bSXiaojian Du return ret; 1374307f049bSXiaojian Du 1375dd9e0b21SXiaojian Du return ret; 1376dd9e0b21SXiaojian Du } 1377dd9e0b21SXiaojian Du 1378ea173d15SXiaojian Du static int vangogh_set_performance_level(struct smu_context *smu, 1379ea173d15SXiaojian Du enum amd_dpm_forced_level level) 1380ea173d15SXiaojian Du { 1381ea173d15SXiaojian Du int ret = 0; 1382ea173d15SXiaojian Du uint32_t soc_mask, mclk_mask, fclk_mask; 1383307f049bSXiaojian Du uint32_t vclk_mask = 0, dclk_mask = 0; 1384ea173d15SXiaojian Du 1385ea173d15SXiaojian Du switch (level) { 1386ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_HIGH: 1387d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1388d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1389d7379efaSXiaojian Du 1390d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1391d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1392d7379efaSXiaojian Du 1393ea173d15SXiaojian Du ret = vangogh_force_dpm_limit_value(smu, true); 1394ea173d15SXiaojian Du break; 1395ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_LOW: 1396d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1397d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1398d7379efaSXiaojian Du 1399d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1400d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1401d7379efaSXiaojian Du 1402ea173d15SXiaojian Du ret = vangogh_force_dpm_limit_value(smu, false); 1403ea173d15SXiaojian Du break; 1404ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_AUTO: 1405d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1406d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1407d7379efaSXiaojian Du 1408d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1409d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1410d7379efaSXiaojian Du 1411ea173d15SXiaojian Du ret = vangogh_unforce_dpm_levels(smu); 1412ea173d15SXiaojian Du break; 1413ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1414d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1415d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1416d7379efaSXiaojian Du 1417d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1418d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1419d7379efaSXiaojian Du 1420307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1421307f049bSXiaojian Du SMU_MSG_SetHardMinGfxClk, 1422307f049bSXiaojian Du VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1423307f049bSXiaojian Du if (ret) 1424307f049bSXiaojian Du return ret; 1425307f049bSXiaojian Du 1426307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1427307f049bSXiaojian Du SMU_MSG_SetSoftMaxGfxClk, 1428307f049bSXiaojian Du VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL); 1429307f049bSXiaojian Du if (ret) 1430307f049bSXiaojian Du return ret; 1431307f049bSXiaojian Du 1432307f049bSXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, level, 1433307f049bSXiaojian Du &vclk_mask, 1434307f049bSXiaojian Du &dclk_mask, 1435307f049bSXiaojian Du &mclk_mask, 1436307f049bSXiaojian Du &fclk_mask, 1437307f049bSXiaojian Du &soc_mask); 1438307f049bSXiaojian Du if (ret) 1439307f049bSXiaojian Du return ret; 1440307f049bSXiaojian Du 1441307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1442307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1443307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1444307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1445307f049bSXiaojian Du 1446ea173d15SXiaojian Du break; 1447ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1448d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1449d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1450d7379efaSXiaojian Du 1451d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1452d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1453d7379efaSXiaojian Du 1454307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, 1455307f049bSXiaojian Du VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1456307f049bSXiaojian Du if (ret) 1457307f049bSXiaojian Du return ret; 1458307f049bSXiaojian Du 1459307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, 1460307f049bSXiaojian Du VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL); 1461307f049bSXiaojian Du if (ret) 1462307f049bSXiaojian Du return ret; 1463ea173d15SXiaojian Du break; 1464ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1465d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1466d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1467d7379efaSXiaojian Du 1468d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1469d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1470d7379efaSXiaojian Du 1471ea173d15SXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, level, 1472ea173d15SXiaojian Du NULL, 1473ea173d15SXiaojian Du NULL, 1474ea173d15SXiaojian Du &mclk_mask, 1475ea173d15SXiaojian Du &fclk_mask, 1476307f049bSXiaojian Du NULL); 1477ea173d15SXiaojian Du if (ret) 1478ea173d15SXiaojian Du return ret; 1479307f049bSXiaojian Du 1480ea173d15SXiaojian Du vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1481ea173d15SXiaojian Du break; 1482ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1483d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1484d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1485d7379efaSXiaojian Du 1486d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1487d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1488d7379efaSXiaojian Du 1489307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1490307f049bSXiaojian Du VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1491307f049bSXiaojian Du if (ret) 1492307f049bSXiaojian Du return ret; 1493307f049bSXiaojian Du 1494307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1495307f049bSXiaojian Du VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL); 1496307f049bSXiaojian Du if (ret) 1497307f049bSXiaojian Du return ret; 1498307f049bSXiaojian Du 1499ea173d15SXiaojian Du ret = vangogh_set_peak_clock_by_device(smu); 1500ea173d15SXiaojian Du break; 1501ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_MANUAL: 1502ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1503ea173d15SXiaojian Du default: 1504ea173d15SXiaojian Du break; 1505ea173d15SXiaojian Du } 1506ea173d15SXiaojian Du return ret; 1507ea173d15SXiaojian Du } 1508ea173d15SXiaojian Du 1509271ab489SXiaojian Du static int vangogh_read_sensor(struct smu_context *smu, 1510271ab489SXiaojian Du enum amd_pp_sensors sensor, 1511271ab489SXiaojian Du void *data, uint32_t *size) 1512271ab489SXiaojian Du { 1513271ab489SXiaojian Du int ret = 0; 1514271ab489SXiaojian Du 1515271ab489SXiaojian Du if (!data || !size) 1516271ab489SXiaojian Du return -EINVAL; 1517271ab489SXiaojian Du 1518271ab489SXiaojian Du mutex_lock(&smu->sensor_lock); 1519271ab489SXiaojian Du switch (sensor) { 1520271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GPU_LOAD: 152186c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15226cc24d8dSAlex Deucher METRICS_AVERAGE_GFXACTIVITY, 15236cc24d8dSAlex Deucher (uint32_t *)data); 1524271ab489SXiaojian Du *size = 4; 1525271ab489SXiaojian Du break; 1526271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GPU_POWER: 152786c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15286cc24d8dSAlex Deucher METRICS_AVERAGE_SOCKETPOWER, 15296cc24d8dSAlex Deucher (uint32_t *)data); 1530271ab489SXiaojian Du *size = 4; 1531271ab489SXiaojian Du break; 1532271ab489SXiaojian Du case AMDGPU_PP_SENSOR_EDGE_TEMP: 153386c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15346cc24d8dSAlex Deucher METRICS_TEMPERATURE_EDGE, 15356cc24d8dSAlex Deucher (uint32_t *)data); 15366cc24d8dSAlex Deucher *size = 4; 15376cc24d8dSAlex Deucher break; 1538271ab489SXiaojian Du case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 153986c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15406cc24d8dSAlex Deucher METRICS_TEMPERATURE_HOTSPOT, 15416cc24d8dSAlex Deucher (uint32_t *)data); 1542271ab489SXiaojian Du *size = 4; 1543271ab489SXiaojian Du break; 1544271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GFX_MCLK: 154586c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 1546a99a5116SXiaojian Du METRICS_CURR_UCLK, 15476cc24d8dSAlex Deucher (uint32_t *)data); 1548271ab489SXiaojian Du *(uint32_t *)data *= 100; 1549271ab489SXiaojian Du *size = 4; 1550271ab489SXiaojian Du break; 1551271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GFX_SCLK: 155286c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 1553a99a5116SXiaojian Du METRICS_CURR_GFXCLK, 15546cc24d8dSAlex Deucher (uint32_t *)data); 1555271ab489SXiaojian Du *(uint32_t *)data *= 100; 1556271ab489SXiaojian Du *size = 4; 1557271ab489SXiaojian Du break; 1558271ab489SXiaojian Du case AMDGPU_PP_SENSOR_VDDGFX: 155986c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15602139d12bSAlex Deucher METRICS_VOLTAGE_VDDGFX, 15612139d12bSAlex Deucher (uint32_t *)data); 15622139d12bSAlex Deucher *size = 4; 15632139d12bSAlex Deucher break; 15642139d12bSAlex Deucher case AMDGPU_PP_SENSOR_VDDNB: 156586c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15662139d12bSAlex Deucher METRICS_VOLTAGE_VDDSOC, 15672139d12bSAlex Deucher (uint32_t *)data); 1568271ab489SXiaojian Du *size = 4; 1569271ab489SXiaojian Du break; 1570517cb957SHuang Rui case AMDGPU_PP_SENSOR_CPU_CLK: 157186c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 1572517cb957SHuang Rui METRICS_AVERAGE_CPUCLK, 1573517cb957SHuang Rui (uint32_t *)data); 15744aef0ebcSHuang Rui *size = smu->cpu_core_num * sizeof(uint16_t); 1575517cb957SHuang Rui break; 1576271ab489SXiaojian Du default: 1577271ab489SXiaojian Du ret = -EOPNOTSUPP; 1578271ab489SXiaojian Du break; 1579271ab489SXiaojian Du } 1580271ab489SXiaojian Du mutex_unlock(&smu->sensor_lock); 1581271ab489SXiaojian Du 1582271ab489SXiaojian Du return ret; 1583271ab489SXiaojian Du } 1584271ab489SXiaojian Du 1585271ab489SXiaojian Du static int vangogh_set_watermarks_table(struct smu_context *smu, 1586271ab489SXiaojian Du struct pp_smu_wm_range_sets *clock_ranges) 1587271ab489SXiaojian Du { 1588271ab489SXiaojian Du int i; 1589271ab489SXiaojian Du int ret = 0; 1590271ab489SXiaojian Du Watermarks_t *table = smu->smu_table.watermarks_table; 1591271ab489SXiaojian Du 1592271ab489SXiaojian Du if (!table || !clock_ranges) 1593271ab489SXiaojian Du return -EINVAL; 1594271ab489SXiaojian Du 1595271ab489SXiaojian Du if (clock_ranges) { 1596271ab489SXiaojian Du if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1597271ab489SXiaojian Du clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1598271ab489SXiaojian Du return -EINVAL; 1599271ab489SXiaojian Du 1600271ab489SXiaojian Du for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1601271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MinClock = 1602271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1603271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1604271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1605271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1606271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1607271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1608271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1609271ab489SXiaojian Du 1610271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1611271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].wm_inst; 1612271ab489SXiaojian Du } 1613271ab489SXiaojian Du 1614271ab489SXiaojian Du for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1615271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MinClock = 1616271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1617271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1618271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1619271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1620271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1621271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1622271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1623271ab489SXiaojian Du 1624271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1625271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].wm_inst; 1626271ab489SXiaojian Du } 1627271ab489SXiaojian Du 1628271ab489SXiaojian Du smu->watermarks_bitmap |= WATERMARKS_EXIST; 1629271ab489SXiaojian Du } 1630271ab489SXiaojian Du 1631271ab489SXiaojian Du /* pass data to smu controller */ 1632271ab489SXiaojian Du if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1633271ab489SXiaojian Du !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1634271ab489SXiaojian Du ret = smu_cmn_write_watermarks_table(smu); 1635271ab489SXiaojian Du if (ret) { 1636271ab489SXiaojian Du dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1637271ab489SXiaojian Du return ret; 1638271ab489SXiaojian Du } 1639271ab489SXiaojian Du smu->watermarks_bitmap |= WATERMARKS_LOADED; 1640271ab489SXiaojian Du } 1641271ab489SXiaojian Du 1642271ab489SXiaojian Du return 0; 1643f46a221bSXiaojian Du } 1644f46a221bSXiaojian Du 164586c8236eSXiaojian Du static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, 164686c8236eSXiaojian Du void **table) 164786c8236eSXiaojian Du { 164886c8236eSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 16497cab3cffSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics = 16507cab3cffSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 165186c8236eSXiaojian Du SmuMetrics_legacy_t metrics; 165286c8236eSXiaojian Du int ret = 0; 165386c8236eSXiaojian Du 165486c8236eSXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, true); 165586c8236eSXiaojian Du if (ret) 165686c8236eSXiaojian Du return ret; 165786c8236eSXiaojian Du 16587cab3cffSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 165986c8236eSXiaojian Du 166086c8236eSXiaojian Du gpu_metrics->temperature_gfx = metrics.GfxTemperature; 166186c8236eSXiaojian Du gpu_metrics->temperature_soc = metrics.SocTemperature; 166286c8236eSXiaojian Du memcpy(&gpu_metrics->temperature_core[0], 166386c8236eSXiaojian Du &metrics.CoreTemperature[0], 166486c8236eSXiaojian Du sizeof(uint16_t) * 4); 166586c8236eSXiaojian Du gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 166686c8236eSXiaojian Du 166786c8236eSXiaojian Du gpu_metrics->average_gfx_activity = metrics.GfxActivity; 166886c8236eSXiaojian Du gpu_metrics->average_mm_activity = metrics.UvdActivity; 166986c8236eSXiaojian Du 167086c8236eSXiaojian Du gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 167186c8236eSXiaojian Du gpu_metrics->average_cpu_power = metrics.Power[0]; 167286c8236eSXiaojian Du gpu_metrics->average_soc_power = metrics.Power[1]; 167386c8236eSXiaojian Du gpu_metrics->average_gfx_power = metrics.Power[2]; 167486c8236eSXiaojian Du memcpy(&gpu_metrics->average_core_power[0], 167586c8236eSXiaojian Du &metrics.CorePower[0], 167686c8236eSXiaojian Du sizeof(uint16_t) * 4); 167786c8236eSXiaojian Du 167886c8236eSXiaojian Du gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 167986c8236eSXiaojian Du gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 168086c8236eSXiaojian Du gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 168186c8236eSXiaojian Du gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 168286c8236eSXiaojian Du gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 168386c8236eSXiaojian Du gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 168486c8236eSXiaojian Du 168586c8236eSXiaojian Du memcpy(&gpu_metrics->current_coreclk[0], 168686c8236eSXiaojian Du &metrics.CoreFrequency[0], 168786c8236eSXiaojian Du sizeof(uint16_t) * 4); 168886c8236eSXiaojian Du gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 168986c8236eSXiaojian Du 169086c8236eSXiaojian Du gpu_metrics->throttle_status = metrics.ThrottlerStatus; 16917cab3cffSGraham Sider gpu_metrics->indep_throttle_status = 16927cab3cffSGraham Sider smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 16937cab3cffSGraham Sider vangogh_throttler_map); 169486c8236eSXiaojian Du 169586c8236eSXiaojian Du gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 169686c8236eSXiaojian Du 169786c8236eSXiaojian Du *table = (void *)gpu_metrics; 169886c8236eSXiaojian Du 16997cab3cffSGraham Sider return sizeof(struct gpu_metrics_v2_2); 170086c8236eSXiaojian Du } 170186c8236eSXiaojian Du 1702fd253334SXiaojian Du static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1703fd253334SXiaojian Du void **table) 1704fd253334SXiaojian Du { 1705fd253334SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 17067cab3cffSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics = 17077cab3cffSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1708fd253334SXiaojian Du SmuMetrics_t metrics; 1709fd253334SXiaojian Du int ret = 0; 1710fd253334SXiaojian Du 1711fd253334SXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1712fd253334SXiaojian Du if (ret) 1713fd253334SXiaojian Du return ret; 1714fd253334SXiaojian Du 17157cab3cffSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1716fd253334SXiaojian Du 171786c8236eSXiaojian Du gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 171886c8236eSXiaojian Du gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1719fd253334SXiaojian Du memcpy(&gpu_metrics->temperature_core[0], 172086c8236eSXiaojian Du &metrics.Current.CoreTemperature[0], 172186c8236eSXiaojian Du sizeof(uint16_t) * 4); 172286c8236eSXiaojian Du gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1723fd253334SXiaojian Du 172486c8236eSXiaojian Du gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 172586c8236eSXiaojian Du gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1726fd253334SXiaojian Du 172786c8236eSXiaojian Du gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 172886c8236eSXiaojian Du gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 172986c8236eSXiaojian Du gpu_metrics->average_soc_power = metrics.Current.Power[1]; 173086c8236eSXiaojian Du gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1731fd253334SXiaojian Du memcpy(&gpu_metrics->average_core_power[0], 173286c8236eSXiaojian Du &metrics.Average.CorePower[0], 173386c8236eSXiaojian Du sizeof(uint16_t) * 4); 1734fd253334SXiaojian Du 173586c8236eSXiaojian Du gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 173686c8236eSXiaojian Du gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 173786c8236eSXiaojian Du gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 173886c8236eSXiaojian Du gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 173986c8236eSXiaojian Du gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 174086c8236eSXiaojian Du gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 174186c8236eSXiaojian Du 174286c8236eSXiaojian Du gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 174386c8236eSXiaojian Du gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 174486c8236eSXiaojian Du gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 174586c8236eSXiaojian Du gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 174686c8236eSXiaojian Du gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 174786c8236eSXiaojian Du gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1748fd253334SXiaojian Du 1749fd253334SXiaojian Du memcpy(&gpu_metrics->current_coreclk[0], 175086c8236eSXiaojian Du &metrics.Current.CoreFrequency[0], 175186c8236eSXiaojian Du sizeof(uint16_t) * 4); 175286c8236eSXiaojian Du gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1753fd253334SXiaojian Du 175486c8236eSXiaojian Du gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 17557cab3cffSGraham Sider gpu_metrics->indep_throttle_status = 17567cab3cffSGraham Sider smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 17577cab3cffSGraham Sider vangogh_throttler_map); 1758fd253334SXiaojian Du 1759de4b7cd8SKevin Wang gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1760de4b7cd8SKevin Wang 1761fd253334SXiaojian Du *table = (void *)gpu_metrics; 1762fd253334SXiaojian Du 17637cab3cffSGraham Sider return sizeof(struct gpu_metrics_v2_2); 1764fd253334SXiaojian Du } 1765fd253334SXiaojian Du 176686c8236eSXiaojian Du static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, 176786c8236eSXiaojian Du void **table) 176886c8236eSXiaojian Du { 176986c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev; 177086c8236eSXiaojian Du uint32_t if_version; 177186c8236eSXiaojian Du int ret = 0; 177286c8236eSXiaojian Du 177386c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 177486c8236eSXiaojian Du if (ret) { 177586c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n"); 177686c8236eSXiaojian Du return ret; 177786c8236eSXiaojian Du } 177886c8236eSXiaojian Du 177986c8236eSXiaojian Du if (if_version < 0x3) 178086c8236eSXiaojian Du ret = vangogh_get_legacy_gpu_metrics(smu, table); 178186c8236eSXiaojian Du else 178286c8236eSXiaojian Du ret = vangogh_get_gpu_metrics(smu, table); 178386c8236eSXiaojian Du 178486c8236eSXiaojian Du return ret; 178586c8236eSXiaojian Du } 178686c8236eSXiaojian Du 1787c98ee897SXiaojian Du static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1788c98ee897SXiaojian Du long input[], uint32_t size) 1789c98ee897SXiaojian Du { 1790c98ee897SXiaojian Du int ret = 0; 1791d7379efaSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1792c98ee897SXiaojian Du 1793d7379efaSXiaojian Du if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 1794d7ef887fSXiaojian Du dev_warn(smu->adev->dev, 1795ce7c670dSColin Ian King "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 1796c98ee897SXiaojian Du return -EINVAL; 1797c98ee897SXiaojian Du } 1798c98ee897SXiaojian Du 1799c98ee897SXiaojian Du switch (type) { 18000d90d0ddSHuang Rui case PP_OD_EDIT_CCLK_VDDC_TABLE: 18010d90d0ddSHuang Rui if (size != 3) { 18020d90d0ddSHuang Rui dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 18030d90d0ddSHuang Rui return -EINVAL; 18040d90d0ddSHuang Rui } 18054aef0ebcSHuang Rui if (input[0] >= smu->cpu_core_num) { 18060d90d0ddSHuang Rui dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 18074aef0ebcSHuang Rui smu->cpu_core_num); 18080d90d0ddSHuang Rui } 18090d90d0ddSHuang Rui smu->cpu_core_id_select = input[0]; 18100d90d0ddSHuang Rui if (input[1] == 0) { 18110d90d0ddSHuang Rui if (input[2] < smu->cpu_default_soft_min_freq) { 18120d90d0ddSHuang Rui dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 18130d90d0ddSHuang Rui input[2], smu->cpu_default_soft_min_freq); 18140d90d0ddSHuang Rui return -EINVAL; 18150d90d0ddSHuang Rui } 18160d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = input[2]; 18170d90d0ddSHuang Rui } else if (input[1] == 1) { 18180d90d0ddSHuang Rui if (input[2] > smu->cpu_default_soft_max_freq) { 18190d90d0ddSHuang Rui dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 18200d90d0ddSHuang Rui input[2], smu->cpu_default_soft_max_freq); 18210d90d0ddSHuang Rui return -EINVAL; 18220d90d0ddSHuang Rui } 18230d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = input[2]; 18240d90d0ddSHuang Rui } else { 18250d90d0ddSHuang Rui return -EINVAL; 18260d90d0ddSHuang Rui } 18270d90d0ddSHuang Rui break; 1828c98ee897SXiaojian Du case PP_OD_EDIT_SCLK_VDDC_TABLE: 1829c98ee897SXiaojian Du if (size != 2) { 1830c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1831c98ee897SXiaojian Du return -EINVAL; 1832c98ee897SXiaojian Du } 1833c98ee897SXiaojian Du 1834c98ee897SXiaojian Du if (input[0] == 0) { 1835c98ee897SXiaojian Du if (input[1] < smu->gfx_default_hard_min_freq) { 1836307f049bSXiaojian Du dev_warn(smu->adev->dev, 1837307f049bSXiaojian Du "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1838c98ee897SXiaojian Du input[1], smu->gfx_default_hard_min_freq); 1839c98ee897SXiaojian Du return -EINVAL; 1840c98ee897SXiaojian Du } 1841c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = input[1]; 1842c98ee897SXiaojian Du } else if (input[0] == 1) { 1843c98ee897SXiaojian Du if (input[1] > smu->gfx_default_soft_max_freq) { 1844307f049bSXiaojian Du dev_warn(smu->adev->dev, 1845307f049bSXiaojian Du "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1846c98ee897SXiaojian Du input[1], smu->gfx_default_soft_max_freq); 1847c98ee897SXiaojian Du return -EINVAL; 1848c98ee897SXiaojian Du } 1849c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = input[1]; 1850c98ee897SXiaojian Du } else { 1851c98ee897SXiaojian Du return -EINVAL; 1852c98ee897SXiaojian Du } 1853c98ee897SXiaojian Du break; 1854c98ee897SXiaojian Du case PP_OD_RESTORE_DEFAULT_TABLE: 1855c98ee897SXiaojian Du if (size != 0) { 1856c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1857c98ee897SXiaojian Du return -EINVAL; 1858c98ee897SXiaojian Du } else { 1859c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1860c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 18610d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 18620d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1863c98ee897SXiaojian Du } 1864c98ee897SXiaojian Du break; 1865c98ee897SXiaojian Du case PP_OD_COMMIT_DPM_TABLE: 1866c98ee897SXiaojian Du if (size != 0) { 1867c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1868c98ee897SXiaojian Du return -EINVAL; 1869c98ee897SXiaojian Du } else { 1870c98ee897SXiaojian Du if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1871307f049bSXiaojian Du dev_err(smu->adev->dev, 1872307f049bSXiaojian Du "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1873307f049bSXiaojian Du smu->gfx_actual_hard_min_freq, 1874307f049bSXiaojian Du smu->gfx_actual_soft_max_freq); 1875c98ee897SXiaojian Du return -EINVAL; 1876c98ee897SXiaojian Du } 1877c98ee897SXiaojian Du 1878c98ee897SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1879c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq, NULL); 1880c98ee897SXiaojian Du if (ret) { 1881c98ee897SXiaojian Du dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1882c98ee897SXiaojian Du return ret; 1883c98ee897SXiaojian Du } 1884c98ee897SXiaojian Du 1885c98ee897SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1886c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq, NULL); 1887c98ee897SXiaojian Du if (ret) { 1888c98ee897SXiaojian Du dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1889c98ee897SXiaojian Du return ret; 1890c98ee897SXiaojian Du } 18910d90d0ddSHuang Rui 18920d90d0ddSHuang Rui if (smu->adev->pm.fw_version < 0x43f1b00) { 18930d90d0ddSHuang Rui dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 18940d90d0ddSHuang Rui break; 18950d90d0ddSHuang Rui } 18960d90d0ddSHuang Rui 18970d90d0ddSHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 18980d90d0ddSHuang Rui ((smu->cpu_core_id_select << 20) 18990d90d0ddSHuang Rui | smu->cpu_actual_soft_min_freq), 19000d90d0ddSHuang Rui NULL); 19010d90d0ddSHuang Rui if (ret) { 19020d90d0ddSHuang Rui dev_err(smu->adev->dev, "Set hard min cclk failed!"); 19030d90d0ddSHuang Rui return ret; 19040d90d0ddSHuang Rui } 19050d90d0ddSHuang Rui 19060d90d0ddSHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 19070d90d0ddSHuang Rui ((smu->cpu_core_id_select << 20) 19080d90d0ddSHuang Rui | smu->cpu_actual_soft_max_freq), 19090d90d0ddSHuang Rui NULL); 19100d90d0ddSHuang Rui if (ret) { 19110d90d0ddSHuang Rui dev_err(smu->adev->dev, "Set soft max cclk failed!"); 19120d90d0ddSHuang Rui return ret; 19130d90d0ddSHuang Rui } 1914c98ee897SXiaojian Du } 1915c98ee897SXiaojian Du break; 1916c98ee897SXiaojian Du default: 1917c98ee897SXiaojian Du return -ENOSYS; 1918c98ee897SXiaojian Du } 1919c98ee897SXiaojian Du 1920c98ee897SXiaojian Du return ret; 1921c98ee897SXiaojian Du } 1922c98ee897SXiaojian Du 1923fce8a4acSJinzhou Su static int vangogh_set_default_dpm_tables(struct smu_context *smu) 1924c98ee897SXiaojian Du { 1925c98ee897SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 1926c98ee897SXiaojian Du 1927c98ee897SXiaojian Du return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 1928c98ee897SXiaojian Du } 1929c98ee897SXiaojian Du 1930c98ee897SXiaojian Du static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1931c98ee897SXiaojian Du { 1932c98ee897SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1933c98ee897SXiaojian Du 1934c98ee897SXiaojian Du smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1935c98ee897SXiaojian Du smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1936c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = 0; 1937c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = 0; 1938c98ee897SXiaojian Du 19390d90d0ddSHuang Rui smu->cpu_default_soft_min_freq = 1400; 19400d90d0ddSHuang Rui smu->cpu_default_soft_max_freq = 3500; 19410d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = 0; 19420d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = 0; 19430d90d0ddSHuang Rui 1944c98ee897SXiaojian Du return 0; 1945c98ee897SXiaojian Du } 1946c98ee897SXiaojian Du 1947ae7b32e7SXiaojian Du static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 1948ae7b32e7SXiaojian Du { 1949ae7b32e7SXiaojian Du DpmClocks_t *table = smu->smu_table.clocks_table; 1950ae7b32e7SXiaojian Du int i; 1951ae7b32e7SXiaojian Du 1952ae7b32e7SXiaojian Du if (!clock_table || !table) 1953ae7b32e7SXiaojian Du return -EINVAL; 1954ae7b32e7SXiaojian Du 1955ae7b32e7SXiaojian Du for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 1956ae7b32e7SXiaojian Du clock_table->SocClocks[i].Freq = table->SocClocks[i]; 1957ae7b32e7SXiaojian Du clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 1958ae7b32e7SXiaojian Du } 1959ae7b32e7SXiaojian Du 1960ae7b32e7SXiaojian Du for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1961ae7b32e7SXiaojian Du clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 1962ae7b32e7SXiaojian Du clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 1963ae7b32e7SXiaojian Du } 1964ae7b32e7SXiaojian Du 1965ae7b32e7SXiaojian Du for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1966ae7b32e7SXiaojian Du clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 1967ae7b32e7SXiaojian Du clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 1968ae7b32e7SXiaojian Du } 1969ae7b32e7SXiaojian Du 1970ae7b32e7SXiaojian Du return 0; 1971ae7b32e7SXiaojian Du } 1972ae7b32e7SXiaojian Du 1973ae7b32e7SXiaojian Du 1974a0f55287SXiaomeng Hou static int vangogh_system_features_control(struct smu_context *smu, bool en) 1975a0f55287SXiaomeng Hou { 19769e3a6ab7SXiaomeng Hou struct amdgpu_device *adev = smu->adev; 1977aedebd40SHuang Rui struct smu_feature *feature = &smu->smu_feature; 1978aedebd40SHuang Rui uint32_t feature_mask[2]; 1979aedebd40SHuang Rui int ret = 0; 19809e3a6ab7SXiaomeng Hou 19815b2e2c09SAlex Deucher if (adev->pm.fw_version >= 0x43f1700 && !en) 1982aedebd40SHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 19835b2e2c09SAlex Deucher RLC_STATUS_OFF, NULL); 1984aedebd40SHuang Rui 1985aedebd40SHuang Rui bitmap_zero(feature->enabled, feature->feature_num); 1986aedebd40SHuang Rui bitmap_zero(feature->supported, feature->feature_num); 1987aedebd40SHuang Rui 1988aedebd40SHuang Rui if (!en) 1989aedebd40SHuang Rui return ret; 1990aedebd40SHuang Rui 1991aedebd40SHuang Rui ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2); 1992aedebd40SHuang Rui if (ret) 1993aedebd40SHuang Rui return ret; 1994aedebd40SHuang Rui 1995aedebd40SHuang Rui bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, 1996aedebd40SHuang Rui feature->feature_num); 1997aedebd40SHuang Rui bitmap_copy(feature->supported, (unsigned long *)&feature_mask, 1998aedebd40SHuang Rui feature->feature_num); 1999aedebd40SHuang Rui 20009e3a6ab7SXiaomeng Hou return 0; 2001a0f55287SXiaomeng Hou } 2002a0f55287SXiaomeng Hou 2003eefdf047SJinzhou Su static int vangogh_post_smu_init(struct smu_context *smu) 2004eefdf047SJinzhou Su { 2005eefdf047SJinzhou Su struct amdgpu_device *adev = smu->adev; 2006eefdf047SJinzhou Su uint32_t tmp; 20073313ef18SJinzhou Su int ret = 0; 2008eefdf047SJinzhou Su uint8_t aon_bits = 0; 2009eefdf047SJinzhou Su /* Two CUs in one WGP */ 2010eefdf047SJinzhou Su uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 2011eefdf047SJinzhou Su uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 2012eefdf047SJinzhou Su adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2013eefdf047SJinzhou Su 20143313ef18SJinzhou Su /* allow message will be sent after enable message on Vangogh*/ 2015bb377febSJinzhou Su if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 2016bb377febSJinzhou Su (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 20173313ef18SJinzhou Su ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 20183313ef18SJinzhou Su if (ret) { 20193313ef18SJinzhou Su dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 20203313ef18SJinzhou Su return ret; 20213313ef18SJinzhou Su } 2022bb377febSJinzhou Su } else { 2023bb377febSJinzhou Su adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 2024bb377febSJinzhou Su dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 2025bb377febSJinzhou Su } 20263313ef18SJinzhou Su 2027eefdf047SJinzhou Su /* if all CUs are active, no need to power off any WGPs */ 2028eefdf047SJinzhou Su if (total_cu == adev->gfx.cu_info.number) 2029eefdf047SJinzhou Su return 0; 2030eefdf047SJinzhou Su 2031eefdf047SJinzhou Su /* 2032eefdf047SJinzhou Su * Calculate the total bits number of always on WGPs for all SA/SEs in 2033eefdf047SJinzhou Su * RLC_PG_ALWAYS_ON_WGP_MASK. 2034eefdf047SJinzhou Su */ 2035eefdf047SJinzhou Su tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 2036eefdf047SJinzhou Su tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 2037eefdf047SJinzhou Su 2038eefdf047SJinzhou Su aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2039eefdf047SJinzhou Su 2040eefdf047SJinzhou Su /* Do not request any WGPs less than set in the AON_WGP_MASK */ 2041eefdf047SJinzhou Su if (aon_bits > req_active_wgps) { 2042eefdf047SJinzhou Su dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 2043eefdf047SJinzhou Su return 0; 2044eefdf047SJinzhou Su } else { 2045eefdf047SJinzhou Su return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 2046eefdf047SJinzhou Su } 2047eefdf047SJinzhou Su } 2048eefdf047SJinzhou Su 204974353883SHuang Rui static int vangogh_mode_reset(struct smu_context *smu, int type) 205074353883SHuang Rui { 205174353883SHuang Rui int ret = 0, index = 0; 205274353883SHuang Rui 205374353883SHuang Rui index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 205474353883SHuang Rui SMU_MSG_GfxDeviceDriverReset); 205574353883SHuang Rui if (index < 0) 205674353883SHuang Rui return index == -EACCES ? 0 : index; 205774353883SHuang Rui 205874353883SHuang Rui mutex_lock(&smu->message_lock); 205974353883SHuang Rui 206074353883SHuang Rui ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 206174353883SHuang Rui 206274353883SHuang Rui mutex_unlock(&smu->message_lock); 206374353883SHuang Rui 206474353883SHuang Rui mdelay(10); 206574353883SHuang Rui 206674353883SHuang Rui return ret; 206774353883SHuang Rui } 206874353883SHuang Rui 206920e157c7SAlex Deucher static int vangogh_mode2_reset(struct smu_context *smu) 207020e157c7SAlex Deucher { 207174353883SHuang Rui return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 207220e157c7SAlex Deucher } 207320e157c7SAlex Deucher 2074488f211dSEvan Quan static int vangogh_get_power_limit(struct smu_context *smu, 2075488f211dSEvan Quan uint32_t *current_power_limit, 2076488f211dSEvan Quan uint32_t *default_power_limit, 2077488f211dSEvan Quan uint32_t *max_power_limit) 2078ae07970aSXiaomeng Hou { 2079ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context = 2080ae07970aSXiaomeng Hou smu->smu_power.power_context; 2081ae07970aSXiaomeng Hou uint32_t ppt_limit; 2082ae07970aSXiaomeng Hou int ret = 0; 2083ae07970aSXiaomeng Hou 2084ae07970aSXiaomeng Hou if (smu->adev->pm.fw_version < 0x43f1e00) 2085ae07970aSXiaomeng Hou return ret; 2086ae07970aSXiaomeng Hou 2087ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 2088ae07970aSXiaomeng Hou if (ret) { 2089ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 2090ae07970aSXiaomeng Hou return ret; 2091ae07970aSXiaomeng Hou } 2092ae07970aSXiaomeng Hou /* convert from milliwatt to watt */ 2093488f211dSEvan Quan if (current_power_limit) 2094488f211dSEvan Quan *current_power_limit = ppt_limit / 1000; 2095488f211dSEvan Quan if (default_power_limit) 2096488f211dSEvan Quan *default_power_limit = ppt_limit / 1000; 2097488f211dSEvan Quan if (max_power_limit) 2098488f211dSEvan Quan *max_power_limit = 29; 2099ae07970aSXiaomeng Hou 2100ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 2101ae07970aSXiaomeng Hou if (ret) { 2102ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 2103ae07970aSXiaomeng Hou return ret; 2104ae07970aSXiaomeng Hou } 2105ae07970aSXiaomeng Hou /* convert from milliwatt to watt */ 21066e58941cSEric Huang power_context->current_fast_ppt_limit = 21076e58941cSEric Huang power_context->default_fast_ppt_limit = ppt_limit / 1000; 2108ae07970aSXiaomeng Hou power_context->max_fast_ppt_limit = 30; 2109ae07970aSXiaomeng Hou 2110ae07970aSXiaomeng Hou return ret; 2111ae07970aSXiaomeng Hou } 2112ae07970aSXiaomeng Hou 2113ae07970aSXiaomeng Hou static int vangogh_get_ppt_limit(struct smu_context *smu, 2114ae07970aSXiaomeng Hou uint32_t *ppt_limit, 2115ae07970aSXiaomeng Hou enum smu_ppt_limit_type type, 2116ae07970aSXiaomeng Hou enum smu_ppt_limit_level level) 2117ae07970aSXiaomeng Hou { 2118ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context = 2119ae07970aSXiaomeng Hou smu->smu_power.power_context; 2120ae07970aSXiaomeng Hou 2121ae07970aSXiaomeng Hou if (!power_context) 2122ae07970aSXiaomeng Hou return -EOPNOTSUPP; 2123ae07970aSXiaomeng Hou 2124ae07970aSXiaomeng Hou if (type == SMU_FAST_PPT_LIMIT) { 2125ae07970aSXiaomeng Hou switch (level) { 2126ae07970aSXiaomeng Hou case SMU_PPT_LIMIT_MAX: 2127ae07970aSXiaomeng Hou *ppt_limit = power_context->max_fast_ppt_limit; 2128ae07970aSXiaomeng Hou break; 2129ae07970aSXiaomeng Hou case SMU_PPT_LIMIT_CURRENT: 2130ae07970aSXiaomeng Hou *ppt_limit = power_context->current_fast_ppt_limit; 2131ae07970aSXiaomeng Hou break; 21326e58941cSEric Huang case SMU_PPT_LIMIT_DEFAULT: 21336e58941cSEric Huang *ppt_limit = power_context->default_fast_ppt_limit; 21346e58941cSEric Huang break; 2135ae07970aSXiaomeng Hou default: 2136ae07970aSXiaomeng Hou break; 2137ae07970aSXiaomeng Hou } 2138ae07970aSXiaomeng Hou } 2139ae07970aSXiaomeng Hou 2140ae07970aSXiaomeng Hou return 0; 2141ae07970aSXiaomeng Hou } 2142ae07970aSXiaomeng Hou 2143ae07970aSXiaomeng Hou static int vangogh_set_power_limit(struct smu_context *smu, uint32_t ppt_limit) 2144ae07970aSXiaomeng Hou { 2145ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context = 2146ae07970aSXiaomeng Hou smu->smu_power.power_context; 2147ae07970aSXiaomeng Hou uint32_t limit_type = ppt_limit >> 24; 2148ae07970aSXiaomeng Hou int ret = 0; 2149ae07970aSXiaomeng Hou 2150ae07970aSXiaomeng Hou if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 2151ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 2152ae07970aSXiaomeng Hou return -EOPNOTSUPP; 2153ae07970aSXiaomeng Hou } 2154ae07970aSXiaomeng Hou 2155ae07970aSXiaomeng Hou switch (limit_type) { 2156ae07970aSXiaomeng Hou case SMU_DEFAULT_PPT_LIMIT: 2157ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg_with_param(smu, 2158ae07970aSXiaomeng Hou SMU_MSG_SetSlowPPTLimit, 2159ae07970aSXiaomeng Hou ppt_limit * 1000, /* convert from watt to milliwatt */ 2160ae07970aSXiaomeng Hou NULL); 2161ae07970aSXiaomeng Hou if (ret) 2162ae07970aSXiaomeng Hou return ret; 2163ae07970aSXiaomeng Hou 2164ae07970aSXiaomeng Hou smu->current_power_limit = ppt_limit; 2165ae07970aSXiaomeng Hou break; 2166ae07970aSXiaomeng Hou case SMU_FAST_PPT_LIMIT: 2167ae07970aSXiaomeng Hou ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 2168ae07970aSXiaomeng Hou if (ppt_limit > power_context->max_fast_ppt_limit) { 2169ae07970aSXiaomeng Hou dev_err(smu->adev->dev, 2170ae07970aSXiaomeng Hou "New power limit (%d) is over the max allowed %d\n", 2171ae07970aSXiaomeng Hou ppt_limit, power_context->max_fast_ppt_limit); 2172ae07970aSXiaomeng Hou return ret; 2173ae07970aSXiaomeng Hou } 2174ae07970aSXiaomeng Hou 2175ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg_with_param(smu, 2176ae07970aSXiaomeng Hou SMU_MSG_SetFastPPTLimit, 2177ae07970aSXiaomeng Hou ppt_limit * 1000, /* convert from watt to milliwatt */ 2178ae07970aSXiaomeng Hou NULL); 2179ae07970aSXiaomeng Hou if (ret) 2180ae07970aSXiaomeng Hou return ret; 2181ae07970aSXiaomeng Hou 2182ae07970aSXiaomeng Hou power_context->current_fast_ppt_limit = ppt_limit; 2183ae07970aSXiaomeng Hou break; 2184ae07970aSXiaomeng Hou default: 2185ae07970aSXiaomeng Hou return -EINVAL; 2186ae07970aSXiaomeng Hou } 2187ae07970aSXiaomeng Hou 2188ae07970aSXiaomeng Hou return ret; 2189ae07970aSXiaomeng Hou } 2190ae07970aSXiaomeng Hou 2191f46a221bSXiaojian Du static const struct pptable_funcs vangogh_ppt_funcs = { 2192271ab489SXiaojian Du 2193f46a221bSXiaojian Du .check_fw_status = smu_v11_0_check_fw_status, 2194f46a221bSXiaojian Du .check_fw_version = smu_v11_0_check_fw_version, 2195f46a221bSXiaojian Du .init_smc_tables = vangogh_init_smc_tables, 2196f46a221bSXiaojian Du .fini_smc_tables = smu_v11_0_fini_smc_tables, 2197f46a221bSXiaojian Du .init_power = smu_v11_0_init_power, 2198f46a221bSXiaojian Du .fini_power = smu_v11_0_fini_power, 2199f46a221bSXiaojian Du .register_irq_handler = smu_v11_0_register_irq_handler, 2200f46a221bSXiaojian Du .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2201f46a221bSXiaojian Du .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2202f46a221bSXiaojian Du .send_smc_msg = smu_cmn_send_smc_msg, 2203271ab489SXiaojian Du .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 2204271ab489SXiaojian Du .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 2205f46a221bSXiaojian Du .is_dpm_running = vangogh_is_dpm_running, 2206271ab489SXiaojian Du .read_sensor = vangogh_read_sensor, 2207271ab489SXiaojian Du .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask, 2208f46a221bSXiaojian Du .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2209271ab489SXiaojian Du .set_watermarks_table = vangogh_set_watermarks_table, 2210271ab489SXiaojian Du .set_driver_table_location = smu_v11_0_set_driver_table_location, 2211f46a221bSXiaojian Du .interrupt_work = smu_v11_0_interrupt_work, 221286c8236eSXiaojian Du .get_gpu_metrics = vangogh_common_get_gpu_metrics, 2213c98ee897SXiaojian Du .od_edit_dpm_table = vangogh_od_edit_dpm_table, 221486c8236eSXiaojian Du .print_clk_levels = vangogh_common_print_clk_levels, 2215c98ee897SXiaojian Du .set_default_dpm_table = vangogh_set_default_dpm_tables, 2216c98ee897SXiaojian Du .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 2217a0f55287SXiaomeng Hou .system_features_control = vangogh_system_features_control, 2218d0e4e112SXiaojian Du .feature_is_enabled = smu_cmn_feature_is_enabled, 2219d0e4e112SXiaojian Du .set_power_profile_mode = vangogh_set_power_profile_mode, 2220307f049bSXiaojian Du .get_power_profile_mode = vangogh_get_power_profile_mode, 2221ae7b32e7SXiaojian Du .get_dpm_clock_table = vangogh_get_dpm_clock_table, 2222dd9e0b21SXiaojian Du .force_clk_levels = vangogh_force_clk_levels, 2223ea173d15SXiaojian Du .set_performance_level = vangogh_set_performance_level, 2224eefdf047SJinzhou Su .post_init = vangogh_post_smu_init, 222520e157c7SAlex Deucher .mode2_reset = vangogh_mode2_reset, 2226b58ce1feSJinzhou Su .gfx_off_control = smu_v11_0_gfx_off_control, 2227ae07970aSXiaomeng Hou .get_ppt_limit = vangogh_get_ppt_limit, 2228ae07970aSXiaomeng Hou .get_power_limit = vangogh_get_power_limit, 2229ae07970aSXiaomeng Hou .set_power_limit = vangogh_set_power_limit, 22303495d3c3SXiaojian Du .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2231f46a221bSXiaojian Du }; 2232f46a221bSXiaojian Du 2233f46a221bSXiaojian Du void vangogh_set_ppt_funcs(struct smu_context *smu) 2234f46a221bSXiaojian Du { 2235f46a221bSXiaojian Du smu->ppt_funcs = &vangogh_ppt_funcs; 2236f46a221bSXiaojian Du smu->message_map = vangogh_message_map; 2237f46a221bSXiaojian Du smu->feature_map = vangogh_feature_mask_map; 2238f46a221bSXiaojian Du smu->table_map = vangogh_table_map; 2239ec3b35c8SXiaojian Du smu->workload_map = vangogh_workload_map; 2240f46a221bSXiaojian Du smu->is_apu = true; 2241f46a221bSXiaojian Du } 2242