1f46a221bSXiaojian Du /* 2f46a221bSXiaojian Du * Copyright 2020 Advanced Micro Devices, Inc. 3f46a221bSXiaojian Du * 4f46a221bSXiaojian Du * Permission is hereby granted, free of charge, to any person obtaining a 5f46a221bSXiaojian Du * copy of this software and associated documentation files (the "Software"), 6f46a221bSXiaojian Du * to deal in the Software without restriction, including without limitation 7f46a221bSXiaojian Du * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8f46a221bSXiaojian Du * and/or sell copies of the Software, and to permit persons to whom the 9f46a221bSXiaojian Du * Software is furnished to do so, subject to the following conditions: 10f46a221bSXiaojian Du * 11f46a221bSXiaojian Du * The above copyright notice and this permission notice shall be included in 12f46a221bSXiaojian Du * all copies or substantial portions of the Software. 13f46a221bSXiaojian Du * 14f46a221bSXiaojian Du * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15f46a221bSXiaojian Du * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16f46a221bSXiaojian Du * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17f46a221bSXiaojian Du * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18f46a221bSXiaojian Du * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19f46a221bSXiaojian Du * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20f46a221bSXiaojian Du * OTHER DEALINGS IN THE SOFTWARE. 21f46a221bSXiaojian Du * 22f46a221bSXiaojian Du */ 23f46a221bSXiaojian Du 24f46a221bSXiaojian Du #define SWSMU_CODE_LAYER_L2 25f46a221bSXiaojian Du 26f46a221bSXiaojian Du #include "amdgpu.h" 27f46a221bSXiaojian Du #include "amdgpu_smu.h" 28f46a221bSXiaojian Du #include "smu_v11_0.h" 29f46a221bSXiaojian Du #include "smu11_driver_if_vangogh.h" 30f46a221bSXiaojian Du #include "vangogh_ppt.h" 31f46a221bSXiaojian Du #include "smu_v11_5_ppsmc.h" 32f46a221bSXiaojian Du #include "smu_v11_5_pmfw.h" 33f46a221bSXiaojian Du #include "smu_cmn.h" 34eefdf047SJinzhou Su #include "soc15_common.h" 35eefdf047SJinzhou Su #include "asic_reg/gc/gc_10_3_0_offset.h" 36eefdf047SJinzhou Su #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37517cb957SHuang Rui #include <asm/processor.h> 38f46a221bSXiaojian Du 39f46a221bSXiaojian Du /* 40f46a221bSXiaojian Du * DO NOT use these for err/warn/info/debug messages. 41f46a221bSXiaojian Du * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42f46a221bSXiaojian Du * They are more MGPU friendly. 43f46a221bSXiaojian Du */ 44f46a221bSXiaojian Du #undef pr_err 45f46a221bSXiaojian Du #undef pr_warn 46f46a221bSXiaojian Du #undef pr_info 47f46a221bSXiaojian Du #undef pr_debug 48f46a221bSXiaojian Du 49f46a221bSXiaojian Du #define FEATURE_MASK(feature) (1ULL << feature) 50f46a221bSXiaojian Du #define SMC_DPM_FEATURE ( \ 51f46a221bSXiaojian Du FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 52f46a221bSXiaojian Du FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 53f46a221bSXiaojian Du FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 54f46a221bSXiaojian Du FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 55f46a221bSXiaojian Du FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 56f46a221bSXiaojian Du FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 57f46a221bSXiaojian Du FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 58f46a221bSXiaojian Du FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 59271ab489SXiaojian Du FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 60f46a221bSXiaojian Du 61f46a221bSXiaojian Du static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 62271ab489SXiaojian Du MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 63271ab489SXiaojian Du MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 64271ab489SXiaojian Du MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 65271ab489SXiaojian Du MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 66b58ce1feSJinzhou Su MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 67b58ce1feSJinzhou Su MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 68271ab489SXiaojian Du MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 69271ab489SXiaojian Du MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 70271ab489SXiaojian Du MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 71271ab489SXiaojian Du MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 72a0f55287SXiaomeng Hou MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 73271ab489SXiaojian Du MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 74271ab489SXiaojian Du MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 75271ab489SXiaojian Du MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 76271ab489SXiaojian Du MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 77271ab489SXiaojian Du MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 78271ab489SXiaojian Du MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 79271ab489SXiaojian Du MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 80271ab489SXiaojian Du MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 81271ab489SXiaojian Du MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 82271ab489SXiaojian Du MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 83271ab489SXiaojian Du MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 84271ab489SXiaojian Du MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 85271ab489SXiaojian Du MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 86271ab489SXiaojian Du MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 87271ab489SXiaojian Du MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 88271ab489SXiaojian Du MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 89271ab489SXiaojian Du MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 90271ab489SXiaojian Du MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 91271ab489SXiaojian Du MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 92271ab489SXiaojian Du MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 93271ab489SXiaojian Du MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 94271ab489SXiaojian Du MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 95271ab489SXiaojian Du MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 96271ab489SXiaojian Du MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 97271ab489SXiaojian Du MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 98271ab489SXiaojian Du MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 99271ab489SXiaojian Du MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 100271ab489SXiaojian Du MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 101271ab489SXiaojian Du MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 102271ab489SXiaojian Du MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 103271ab489SXiaojian Du MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 104271ab489SXiaojian Du MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 105271ab489SXiaojian Du MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 106271ab489SXiaojian Du MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 107271ab489SXiaojian Du MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 108271ab489SXiaojian Du MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 109271ab489SXiaojian Du MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 110271ab489SXiaojian Du MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 111271ab489SXiaojian Du MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 112271ab489SXiaojian Du MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 113271ab489SXiaojian Du MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 114271ab489SXiaojian Du MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 115271ab489SXiaojian Du MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 116271ab489SXiaojian Du MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 117271ab489SXiaojian Du MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 118271ab489SXiaojian Du MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 119271ab489SXiaojian Du MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 120271ab489SXiaojian Du MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 121271ab489SXiaojian Du MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 122271ab489SXiaojian Du MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 123271ab489SXiaojian Du MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 124eefdf047SJinzhou Su MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 125ae07970aSXiaomeng Hou MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 126ae07970aSXiaomeng Hou MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 127ae07970aSXiaomeng Hou MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 128ae07970aSXiaomeng Hou MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 129f46a221bSXiaojian Du }; 130f46a221bSXiaojian Du 131f46a221bSXiaojian Du static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 132f46a221bSXiaojian Du FEA_MAP(PPT), 133f46a221bSXiaojian Du FEA_MAP(TDC), 134f46a221bSXiaojian Du FEA_MAP(THERMAL), 135f46a221bSXiaojian Du FEA_MAP(DS_GFXCLK), 136f46a221bSXiaojian Du FEA_MAP(DS_SOCCLK), 137f46a221bSXiaojian Du FEA_MAP(DS_LCLK), 138f46a221bSXiaojian Du FEA_MAP(DS_FCLK), 139f46a221bSXiaojian Du FEA_MAP(DS_MP1CLK), 140f46a221bSXiaojian Du FEA_MAP(DS_MP0CLK), 141f46a221bSXiaojian Du FEA_MAP(ATHUB_PG), 142f46a221bSXiaojian Du FEA_MAP(CCLK_DPM), 143f46a221bSXiaojian Du FEA_MAP(FAN_CONTROLLER), 144f46a221bSXiaojian Du FEA_MAP(ULV), 145f46a221bSXiaojian Du FEA_MAP(VCN_DPM), 146f46a221bSXiaojian Du FEA_MAP(LCLK_DPM), 147f46a221bSXiaojian Du FEA_MAP(SHUBCLK_DPM), 148f46a221bSXiaojian Du FEA_MAP(DCFCLK_DPM), 149f46a221bSXiaojian Du FEA_MAP(DS_DCFCLK), 150f46a221bSXiaojian Du FEA_MAP(S0I2), 151f46a221bSXiaojian Du FEA_MAP(SMU_LOW_POWER), 152f46a221bSXiaojian Du FEA_MAP(GFX_DEM), 153f46a221bSXiaojian Du FEA_MAP(PSI), 154f46a221bSXiaojian Du FEA_MAP(PROCHOT), 155f46a221bSXiaojian Du FEA_MAP(CPUOFF), 156f46a221bSXiaojian Du FEA_MAP(STAPM), 157f46a221bSXiaojian Du FEA_MAP(S0I3), 158f46a221bSXiaojian Du FEA_MAP(DF_CSTATES), 159f46a221bSXiaojian Du FEA_MAP(PERF_LIMIT), 160f46a221bSXiaojian Du FEA_MAP(CORE_DLDO), 161f46a221bSXiaojian Du FEA_MAP(RSMU_LOW_POWER), 162f46a221bSXiaojian Du FEA_MAP(SMN_LOW_POWER), 163f46a221bSXiaojian Du FEA_MAP(THM_LOW_POWER), 164f46a221bSXiaojian Du FEA_MAP(SMUIO_LOW_POWER), 165f46a221bSXiaojian Du FEA_MAP(MP1_LOW_POWER), 166f46a221bSXiaojian Du FEA_MAP(DS_VCN), 167f46a221bSXiaojian Du FEA_MAP(CPPC), 168f46a221bSXiaojian Du FEA_MAP(OS_CSTATES), 169f46a221bSXiaojian Du FEA_MAP(ISP_DPM), 170f46a221bSXiaojian Du FEA_MAP(A55_DPM), 171f46a221bSXiaojian Du FEA_MAP(CVIP_DSP_DPM), 172f46a221bSXiaojian Du FEA_MAP(MSMU_LOW_POWER), 17354800b58SXiaojian Du FEA_MAP_REVERSE(SOCCLK), 17454800b58SXiaojian Du FEA_MAP_REVERSE(FCLK), 17554800b58SXiaojian Du FEA_MAP_HALF_REVERSE(GFX), 176f46a221bSXiaojian Du }; 177f46a221bSXiaojian Du 178f46a221bSXiaojian Du static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 179f46a221bSXiaojian Du TAB_MAP_VALID(WATERMARKS), 180f46a221bSXiaojian Du TAB_MAP_VALID(SMU_METRICS), 181f46a221bSXiaojian Du TAB_MAP_VALID(CUSTOM_DPM), 182f46a221bSXiaojian Du TAB_MAP_VALID(DPMCLOCKS), 183f46a221bSXiaojian Du }; 184f46a221bSXiaojian Du 185f727ebebSXiaojian Du static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 186f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 187f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 188f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 189f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 190f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 191f727ebebSXiaojian Du }; 192f727ebebSXiaojian Du 1937cab3cffSGraham Sider static const uint8_t vangogh_throttler_map[] = { 1947cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), 1957cab3cffSGraham Sider [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), 1967cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), 1977cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), 1987cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), 1997cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), 2007cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), 2017cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), 2027cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), 2037cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT), 2047cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT), 2057cab3cffSGraham Sider }; 2067cab3cffSGraham Sider 207f46a221bSXiaojian Du static int vangogh_tables_init(struct smu_context *smu) 208f46a221bSXiaojian Du { 209f46a221bSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 210f46a221bSXiaojian Du struct smu_table *tables = smu_table->tables; 21186c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev; 21286c8236eSXiaojian Du uint32_t if_version; 21386c8236eSXiaojian Du uint32_t ret = 0; 21486c8236eSXiaojian Du 21586c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 21686c8236eSXiaojian Du if (ret) { 21786c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n"); 21886c8236eSXiaojian Du goto err0_out; 21986c8236eSXiaojian Du } 220f46a221bSXiaojian Du 221f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 222f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 223f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 224f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 225f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 226f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 227f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 228f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 22986c8236eSXiaojian Du 23086c8236eSXiaojian Du if (if_version < 0x3) { 23186c8236eSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t), 23286c8236eSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 23386c8236eSXiaojian Du smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL); 23486c8236eSXiaojian Du } else { 23586c8236eSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 23686c8236eSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 237f46a221bSXiaojian Du smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 23886c8236eSXiaojian Du } 239f46a221bSXiaojian Du if (!smu_table->metrics_table) 240f46a221bSXiaojian Du goto err0_out; 241f46a221bSXiaojian Du smu_table->metrics_time = 0; 242f46a221bSXiaojian Du 2437cab3cffSGraham Sider smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); 244f46a221bSXiaojian Du smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 245f46a221bSXiaojian Du if (!smu_table->gpu_metrics_table) 246f46a221bSXiaojian Du goto err1_out; 247f46a221bSXiaojian Du 248f46a221bSXiaojian Du smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 249f46a221bSXiaojian Du if (!smu_table->watermarks_table) 250f46a221bSXiaojian Du goto err2_out; 251f46a221bSXiaojian Du 252c98ee897SXiaojian Du smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 253c98ee897SXiaojian Du if (!smu_table->clocks_table) 254c98ee897SXiaojian Du goto err3_out; 255c98ee897SXiaojian Du 256f46a221bSXiaojian Du return 0; 257f46a221bSXiaojian Du 258c98ee897SXiaojian Du err3_out: 259a5467ebdSChristophe JAILLET kfree(smu_table->watermarks_table); 260f46a221bSXiaojian Du err2_out: 261f46a221bSXiaojian Du kfree(smu_table->gpu_metrics_table); 262f46a221bSXiaojian Du err1_out: 263f46a221bSXiaojian Du kfree(smu_table->metrics_table); 264f46a221bSXiaojian Du err0_out: 265f46a221bSXiaojian Du return -ENOMEM; 266f46a221bSXiaojian Du } 267f46a221bSXiaojian Du 26886c8236eSXiaojian Du static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu, 269271ab489SXiaojian Du MetricsMember_t member, 270271ab489SXiaojian Du uint32_t *value) 271271ab489SXiaojian Du { 272271ab489SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 27386c8236eSXiaojian Du SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table; 274271ab489SXiaojian Du int ret = 0; 275271ab489SXiaojian Du 276da11407fSEvan Quan ret = smu_cmn_get_metrics_table(smu, 277271ab489SXiaojian Du NULL, 278271ab489SXiaojian Du false); 279da11407fSEvan Quan if (ret) 280271ab489SXiaojian Du return ret; 281271ab489SXiaojian Du 282271ab489SXiaojian Du switch (member) { 283a99a5116SXiaojian Du case METRICS_CURR_GFXCLK: 284271ab489SXiaojian Du *value = metrics->GfxclkFrequency; 285271ab489SXiaojian Du break; 286271ab489SXiaojian Du case METRICS_AVERAGE_SOCCLK: 287271ab489SXiaojian Du *value = metrics->SocclkFrequency; 288271ab489SXiaojian Du break; 289f02c7336SXiaojian Du case METRICS_AVERAGE_VCLK: 290f02c7336SXiaojian Du *value = metrics->VclkFrequency; 291f02c7336SXiaojian Du break; 292f02c7336SXiaojian Du case METRICS_AVERAGE_DCLK: 293f02c7336SXiaojian Du *value = metrics->DclkFrequency; 294f02c7336SXiaojian Du break; 295a99a5116SXiaojian Du case METRICS_CURR_UCLK: 296271ab489SXiaojian Du *value = metrics->MemclkFrequency; 297271ab489SXiaojian Du break; 298271ab489SXiaojian Du case METRICS_AVERAGE_GFXACTIVITY: 299271ab489SXiaojian Du *value = metrics->GfxActivity / 100; 300271ab489SXiaojian Du break; 301271ab489SXiaojian Du case METRICS_AVERAGE_VCNACTIVITY: 302271ab489SXiaojian Du *value = metrics->UvdActivity; 303271ab489SXiaojian Du break; 304271ab489SXiaojian Du case METRICS_AVERAGE_SOCKETPOWER: 30523289a22SXiaojian Du *value = (metrics->CurrentSocketPower << 8) / 30623289a22SXiaojian Du 1000 ; 307271ab489SXiaojian Du break; 308271ab489SXiaojian Du case METRICS_TEMPERATURE_EDGE: 309271ab489SXiaojian Du *value = metrics->GfxTemperature / 100 * 310271ab489SXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 311271ab489SXiaojian Du break; 312271ab489SXiaojian Du case METRICS_TEMPERATURE_HOTSPOT: 313271ab489SXiaojian Du *value = metrics->SocTemperature / 100 * 314271ab489SXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 315271ab489SXiaojian Du break; 316271ab489SXiaojian Du case METRICS_THROTTLER_STATUS: 317271ab489SXiaojian Du *value = metrics->ThrottlerStatus; 318271ab489SXiaojian Du break; 3192139d12bSAlex Deucher case METRICS_VOLTAGE_VDDGFX: 3202139d12bSAlex Deucher *value = metrics->Voltage[2]; 3212139d12bSAlex Deucher break; 3222139d12bSAlex Deucher case METRICS_VOLTAGE_VDDSOC: 3232139d12bSAlex Deucher *value = metrics->Voltage[1]; 3242139d12bSAlex Deucher break; 325517cb957SHuang Rui case METRICS_AVERAGE_CPUCLK: 326517cb957SHuang Rui memcpy(value, &metrics->CoreFrequency[0], 3274aef0ebcSHuang Rui smu->cpu_core_num * sizeof(uint16_t)); 328517cb957SHuang Rui break; 329271ab489SXiaojian Du default: 330271ab489SXiaojian Du *value = UINT_MAX; 331271ab489SXiaojian Du break; 332271ab489SXiaojian Du } 333271ab489SXiaojian Du 334271ab489SXiaojian Du return ret; 335271ab489SXiaojian Du } 336271ab489SXiaojian Du 33786c8236eSXiaojian Du static int vangogh_get_smu_metrics_data(struct smu_context *smu, 33886c8236eSXiaojian Du MetricsMember_t member, 33986c8236eSXiaojian Du uint32_t *value) 34086c8236eSXiaojian Du { 34186c8236eSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 34286c8236eSXiaojian Du SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 34386c8236eSXiaojian Du int ret = 0; 34486c8236eSXiaojian Du 345da11407fSEvan Quan ret = smu_cmn_get_metrics_table(smu, 34686c8236eSXiaojian Du NULL, 34786c8236eSXiaojian Du false); 348da11407fSEvan Quan if (ret) 34986c8236eSXiaojian Du return ret; 35086c8236eSXiaojian Du 35186c8236eSXiaojian Du switch (member) { 352a99a5116SXiaojian Du case METRICS_CURR_GFXCLK: 35386c8236eSXiaojian Du *value = metrics->Current.GfxclkFrequency; 35486c8236eSXiaojian Du break; 35586c8236eSXiaojian Du case METRICS_AVERAGE_SOCCLK: 35686c8236eSXiaojian Du *value = metrics->Current.SocclkFrequency; 35786c8236eSXiaojian Du break; 35886c8236eSXiaojian Du case METRICS_AVERAGE_VCLK: 35986c8236eSXiaojian Du *value = metrics->Current.VclkFrequency; 36086c8236eSXiaojian Du break; 36186c8236eSXiaojian Du case METRICS_AVERAGE_DCLK: 36286c8236eSXiaojian Du *value = metrics->Current.DclkFrequency; 36386c8236eSXiaojian Du break; 364a99a5116SXiaojian Du case METRICS_CURR_UCLK: 36586c8236eSXiaojian Du *value = metrics->Current.MemclkFrequency; 36686c8236eSXiaojian Du break; 36786c8236eSXiaojian Du case METRICS_AVERAGE_GFXACTIVITY: 36886c8236eSXiaojian Du *value = metrics->Current.GfxActivity; 36986c8236eSXiaojian Du break; 37086c8236eSXiaojian Du case METRICS_AVERAGE_VCNACTIVITY: 37186c8236eSXiaojian Du *value = metrics->Current.UvdActivity; 37286c8236eSXiaojian Du break; 37386c8236eSXiaojian Du case METRICS_AVERAGE_SOCKETPOWER: 37486c8236eSXiaojian Du *value = (metrics->Current.CurrentSocketPower << 8) / 37586c8236eSXiaojian Du 1000; 37686c8236eSXiaojian Du break; 37786c8236eSXiaojian Du case METRICS_TEMPERATURE_EDGE: 37886c8236eSXiaojian Du *value = metrics->Current.GfxTemperature / 100 * 37986c8236eSXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 38086c8236eSXiaojian Du break; 38186c8236eSXiaojian Du case METRICS_TEMPERATURE_HOTSPOT: 38286c8236eSXiaojian Du *value = metrics->Current.SocTemperature / 100 * 38386c8236eSXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 38486c8236eSXiaojian Du break; 38586c8236eSXiaojian Du case METRICS_THROTTLER_STATUS: 38686c8236eSXiaojian Du *value = metrics->Current.ThrottlerStatus; 38786c8236eSXiaojian Du break; 38886c8236eSXiaojian Du case METRICS_VOLTAGE_VDDGFX: 38986c8236eSXiaojian Du *value = metrics->Current.Voltage[2]; 39086c8236eSXiaojian Du break; 39186c8236eSXiaojian Du case METRICS_VOLTAGE_VDDSOC: 39286c8236eSXiaojian Du *value = metrics->Current.Voltage[1]; 39386c8236eSXiaojian Du break; 39486c8236eSXiaojian Du case METRICS_AVERAGE_CPUCLK: 39586c8236eSXiaojian Du memcpy(value, &metrics->Current.CoreFrequency[0], 39686c8236eSXiaojian Du smu->cpu_core_num * sizeof(uint16_t)); 39786c8236eSXiaojian Du break; 39886c8236eSXiaojian Du default: 39986c8236eSXiaojian Du *value = UINT_MAX; 40086c8236eSXiaojian Du break; 40186c8236eSXiaojian Du } 40286c8236eSXiaojian Du 40386c8236eSXiaojian Du return ret; 40486c8236eSXiaojian Du } 40586c8236eSXiaojian Du 40686c8236eSXiaojian Du static int vangogh_common_get_smu_metrics_data(struct smu_context *smu, 40786c8236eSXiaojian Du MetricsMember_t member, 40886c8236eSXiaojian Du uint32_t *value) 40986c8236eSXiaojian Du { 41086c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev; 41186c8236eSXiaojian Du uint32_t if_version; 41286c8236eSXiaojian Du int ret = 0; 41386c8236eSXiaojian Du 41486c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 41586c8236eSXiaojian Du if (ret) { 41686c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n"); 41786c8236eSXiaojian Du return ret; 41886c8236eSXiaojian Du } 41986c8236eSXiaojian Du 42086c8236eSXiaojian Du if (if_version < 0x3) 42186c8236eSXiaojian Du ret = vangogh_get_legacy_smu_metrics_data(smu, member, value); 42286c8236eSXiaojian Du else 42386c8236eSXiaojian Du ret = vangogh_get_smu_metrics_data(smu, member, value); 42486c8236eSXiaojian Du 42586c8236eSXiaojian Du return ret; 42686c8236eSXiaojian Du } 42786c8236eSXiaojian Du 428f46a221bSXiaojian Du static int vangogh_allocate_dpm_context(struct smu_context *smu) 429f46a221bSXiaojian Du { 430f46a221bSXiaojian Du struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 431f46a221bSXiaojian Du 432f46a221bSXiaojian Du smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 433f46a221bSXiaojian Du GFP_KERNEL); 434f46a221bSXiaojian Du if (!smu_dpm->dpm_context) 435f46a221bSXiaojian Du return -ENOMEM; 436f46a221bSXiaojian Du 437f46a221bSXiaojian Du smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 438f46a221bSXiaojian Du 439f46a221bSXiaojian Du return 0; 440f46a221bSXiaojian Du } 441f46a221bSXiaojian Du 442f46a221bSXiaojian Du static int vangogh_init_smc_tables(struct smu_context *smu) 443f46a221bSXiaojian Du { 444f46a221bSXiaojian Du int ret = 0; 445f46a221bSXiaojian Du 446f46a221bSXiaojian Du ret = vangogh_tables_init(smu); 447f46a221bSXiaojian Du if (ret) 448f46a221bSXiaojian Du return ret; 449f46a221bSXiaojian Du 450f46a221bSXiaojian Du ret = vangogh_allocate_dpm_context(smu); 451f46a221bSXiaojian Du if (ret) 452f46a221bSXiaojian Du return ret; 453f46a221bSXiaojian Du 4544aef0ebcSHuang Rui #ifdef CONFIG_X86 4554aef0ebcSHuang Rui /* AMD x86 APU only */ 4564aef0ebcSHuang Rui smu->cpu_core_num = boot_cpu_data.x86_max_cores; 4574aef0ebcSHuang Rui #else 4584aef0ebcSHuang Rui smu->cpu_core_num = 4; 4594aef0ebcSHuang Rui #endif 4604aef0ebcSHuang Rui 461f46a221bSXiaojian Du return smu_v11_0_init_smc_tables(smu); 462f46a221bSXiaojian Du } 463f46a221bSXiaojian Du 464f46a221bSXiaojian Du static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 465f46a221bSXiaojian Du { 466f46a221bSXiaojian Du int ret = 0; 467f46a221bSXiaojian Du 468f46a221bSXiaojian Du if (enable) { 469f46a221bSXiaojian Du /* vcn dpm on is a prerequisite for vcn power gate messages */ 470f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 471f46a221bSXiaojian Du if (ret) 472f46a221bSXiaojian Du return ret; 473f46a221bSXiaojian Du } else { 474f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 475f46a221bSXiaojian Du if (ret) 476f46a221bSXiaojian Du return ret; 477f46a221bSXiaojian Du } 478f46a221bSXiaojian Du 479f46a221bSXiaojian Du return ret; 480f46a221bSXiaojian Du } 481f46a221bSXiaojian Du 482f46a221bSXiaojian Du static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 483f46a221bSXiaojian Du { 484f46a221bSXiaojian Du int ret = 0; 485f46a221bSXiaojian Du 486f46a221bSXiaojian Du if (enable) { 487f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 488f46a221bSXiaojian Du if (ret) 489f46a221bSXiaojian Du return ret; 490f46a221bSXiaojian Du } else { 491f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 492f46a221bSXiaojian Du if (ret) 493f46a221bSXiaojian Du return ret; 494f46a221bSXiaojian Du } 495f46a221bSXiaojian Du 496f46a221bSXiaojian Du return ret; 497f46a221bSXiaojian Du } 498f46a221bSXiaojian Du 499f46a221bSXiaojian Du static bool vangogh_is_dpm_running(struct smu_context *smu) 500f46a221bSXiaojian Du { 5011c0f0430SAlex Deucher struct amdgpu_device *adev = smu->adev; 502271ab489SXiaojian Du int ret = 0; 503271ab489SXiaojian Du uint64_t feature_enabled; 504f46a221bSXiaojian Du 5051c0f0430SAlex Deucher /* we need to re-init after suspend so return false */ 5061c0f0430SAlex Deucher if (adev->in_suspend) 5071c0f0430SAlex Deucher return false; 5081c0f0430SAlex Deucher 5092d282665SEvan Quan ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 510271ab489SXiaojian Du 511271ab489SXiaojian Du if (ret) 512f46a221bSXiaojian Du return false; 513f46a221bSXiaojian Du 514271ab489SXiaojian Du return !!(feature_enabled & SMC_DPM_FEATURE); 515271ab489SXiaojian Du } 516271ab489SXiaojian Du 517ae7b32e7SXiaojian Du static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 518ae7b32e7SXiaojian Du uint32_t dpm_level, uint32_t *freq) 519ae7b32e7SXiaojian Du { 520ae7b32e7SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 521ae7b32e7SXiaojian Du 522ae7b32e7SXiaojian Du if (!clk_table || clk_type >= SMU_CLK_COUNT) 523ae7b32e7SXiaojian Du return -EINVAL; 524ae7b32e7SXiaojian Du 525ae7b32e7SXiaojian Du switch (clk_type) { 526ae7b32e7SXiaojian Du case SMU_SOCCLK: 527ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 528ae7b32e7SXiaojian Du return -EINVAL; 529ae7b32e7SXiaojian Du *freq = clk_table->SocClocks[dpm_level]; 530ae7b32e7SXiaojian Du break; 531f02c7336SXiaojian Du case SMU_VCLK: 532f02c7336SXiaojian Du if (dpm_level >= clk_table->VcnClkLevelsEnabled) 533f02c7336SXiaojian Du return -EINVAL; 534f02c7336SXiaojian Du *freq = clk_table->VcnClocks[dpm_level].vclk; 535f02c7336SXiaojian Du break; 536f02c7336SXiaojian Du case SMU_DCLK: 537f02c7336SXiaojian Du if (dpm_level >= clk_table->VcnClkLevelsEnabled) 538f02c7336SXiaojian Du return -EINVAL; 539f02c7336SXiaojian Du *freq = clk_table->VcnClocks[dpm_level].dclk; 540f02c7336SXiaojian Du break; 541ae7b32e7SXiaojian Du case SMU_UCLK: 542ae7b32e7SXiaojian Du case SMU_MCLK: 543ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumDfPstatesEnabled) 544ae7b32e7SXiaojian Du return -EINVAL; 545ae7b32e7SXiaojian Du *freq = clk_table->DfPstateTable[dpm_level].memclk; 546ae7b32e7SXiaojian Du 547ae7b32e7SXiaojian Du break; 548ae7b32e7SXiaojian Du case SMU_FCLK: 549ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumDfPstatesEnabled) 550ae7b32e7SXiaojian Du return -EINVAL; 551ae7b32e7SXiaojian Du *freq = clk_table->DfPstateTable[dpm_level].fclk; 552ae7b32e7SXiaojian Du break; 553ae7b32e7SXiaojian Du default: 554ae7b32e7SXiaojian Du return -EINVAL; 555ae7b32e7SXiaojian Du } 556ae7b32e7SXiaojian Du 557ae7b32e7SXiaojian Du return 0; 558ae7b32e7SXiaojian Du } 559ae7b32e7SXiaojian Du 56086c8236eSXiaojian Du static int vangogh_print_legacy_clk_levels(struct smu_context *smu, 561c98ee897SXiaojian Du enum smu_clk_type clk_type, char *buf) 562c98ee897SXiaojian Du { 563ae7b32e7SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 56486c8236eSXiaojian Du SmuMetrics_legacy_t metrics; 565d7379efaSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 566ae7b32e7SXiaojian Du int i, size = 0, ret = 0; 567ae7b32e7SXiaojian Du uint32_t cur_value = 0, value = 0, count = 0; 568ae7b32e7SXiaojian Du bool cur_value_match_level = false; 569ae7b32e7SXiaojian Du 570ae7b32e7SXiaojian Du memset(&metrics, 0, sizeof(metrics)); 571ae7b32e7SXiaojian Du 572ae7b32e7SXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, false); 573ae7b32e7SXiaojian Du if (ret) 574ae7b32e7SXiaojian Du return ret; 575c98ee897SXiaojian Du 5768f48ba30SLang Yu smu_cmn_get_sysfs_buf(&buf, &size); 5778f48ba30SLang Yu 578c98ee897SXiaojian Du switch (clk_type) { 579c98ee897SXiaojian Du case SMU_OD_SCLK: 580d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 5818f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 582fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 583c98ee897SXiaojian Du (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 584fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 585c98ee897SXiaojian Du (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 586c98ee897SXiaojian Du } 587c98ee897SXiaojian Du break; 5880d90d0ddSHuang Rui case SMU_OD_CCLK: 589d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 5908f48ba30SLang Yu size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 591fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 5920d90d0ddSHuang Rui (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 593fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 5940d90d0ddSHuang Rui (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 5950d90d0ddSHuang Rui } 5960d90d0ddSHuang Rui break; 597c98ee897SXiaojian Du case SMU_OD_RANGE: 598d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 5998f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 600fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 601c98ee897SXiaojian Du smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 602fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 6030d90d0ddSHuang Rui smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 604c98ee897SXiaojian Du } 605c98ee897SXiaojian Du break; 606ae7b32e7SXiaojian Du case SMU_SOCCLK: 607ae7b32e7SXiaojian Du /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 608ae7b32e7SXiaojian Du count = clk_table->NumSocClkLevelsEnabled; 609ae7b32e7SXiaojian Du cur_value = metrics.SocclkFrequency; 610ae7b32e7SXiaojian Du break; 611f02c7336SXiaojian Du case SMU_VCLK: 612f02c7336SXiaojian Du count = clk_table->VcnClkLevelsEnabled; 613f02c7336SXiaojian Du cur_value = metrics.VclkFrequency; 614f02c7336SXiaojian Du break; 615f02c7336SXiaojian Du case SMU_DCLK: 616f02c7336SXiaojian Du count = clk_table->VcnClkLevelsEnabled; 617f02c7336SXiaojian Du cur_value = metrics.DclkFrequency; 618f02c7336SXiaojian Du break; 619ae7b32e7SXiaojian Du case SMU_MCLK: 620ae7b32e7SXiaojian Du count = clk_table->NumDfPstatesEnabled; 621ae7b32e7SXiaojian Du cur_value = metrics.MemclkFrequency; 622ae7b32e7SXiaojian Du break; 623ae7b32e7SXiaojian Du case SMU_FCLK: 624ae7b32e7SXiaojian Du count = clk_table->NumDfPstatesEnabled; 625ae7b32e7SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 626ae7b32e7SXiaojian Du if (ret) 627ae7b32e7SXiaojian Du return ret; 628ae7b32e7SXiaojian Du break; 629ae7b32e7SXiaojian Du default: 630ae7b32e7SXiaojian Du break; 631ae7b32e7SXiaojian Du } 632ae7b32e7SXiaojian Du 633ae7b32e7SXiaojian Du switch (clk_type) { 634ae7b32e7SXiaojian Du case SMU_SOCCLK: 635f02c7336SXiaojian Du case SMU_VCLK: 636f02c7336SXiaojian Du case SMU_DCLK: 637ae7b32e7SXiaojian Du case SMU_MCLK: 638ae7b32e7SXiaojian Du case SMU_FCLK: 639ae7b32e7SXiaojian Du for (i = 0; i < count; i++) { 640ae7b32e7SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 641ae7b32e7SXiaojian Du if (ret) 642ae7b32e7SXiaojian Du return ret; 643ae7b32e7SXiaojian Du if (!value) 644ae7b32e7SXiaojian Du continue; 645fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 646ae7b32e7SXiaojian Du cur_value == value ? "*" : ""); 647ae7b32e7SXiaojian Du if (cur_value == value) 648ae7b32e7SXiaojian Du cur_value_match_level = true; 649ae7b32e7SXiaojian Du } 650ae7b32e7SXiaojian Du 651ae7b32e7SXiaojian Du if (!cur_value_match_level) 652fe14c285SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 653ae7b32e7SXiaojian Du break; 654c98ee897SXiaojian Du default: 655c98ee897SXiaojian Du break; 656c98ee897SXiaojian Du } 657c98ee897SXiaojian Du 658c98ee897SXiaojian Du return size; 659c98ee897SXiaojian Du } 660c98ee897SXiaojian Du 66186c8236eSXiaojian Du static int vangogh_print_clk_levels(struct smu_context *smu, 66286c8236eSXiaojian Du enum smu_clk_type clk_type, char *buf) 66386c8236eSXiaojian Du { 66486c8236eSXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 66586c8236eSXiaojian Du SmuMetrics_t metrics; 66686c8236eSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 66786c8236eSXiaojian Du int i, size = 0, ret = 0; 66886c8236eSXiaojian Du uint32_t cur_value = 0, value = 0, count = 0; 66986c8236eSXiaojian Du bool cur_value_match_level = false; 67048c19a95SPerry Yuan uint32_t min, max; 67186c8236eSXiaojian Du 67286c8236eSXiaojian Du memset(&metrics, 0, sizeof(metrics)); 67386c8236eSXiaojian Du 67486c8236eSXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, false); 67586c8236eSXiaojian Du if (ret) 67686c8236eSXiaojian Du return ret; 67786c8236eSXiaojian Du 6788f48ba30SLang Yu smu_cmn_get_sysfs_buf(&buf, &size); 6798f48ba30SLang Yu 68086c8236eSXiaojian Du switch (clk_type) { 68186c8236eSXiaojian Du case SMU_OD_SCLK: 68286c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 6838f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 684fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 68586c8236eSXiaojian Du (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 686fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 68786c8236eSXiaojian Du (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 68886c8236eSXiaojian Du } 68986c8236eSXiaojian Du break; 69086c8236eSXiaojian Du case SMU_OD_CCLK: 69186c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 6928f48ba30SLang Yu size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 693fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 69486c8236eSXiaojian Du (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 695fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 69686c8236eSXiaojian Du (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 69786c8236eSXiaojian Du } 69886c8236eSXiaojian Du break; 69986c8236eSXiaojian Du case SMU_OD_RANGE: 70086c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 7018f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 702fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 70386c8236eSXiaojian Du smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 704fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 70586c8236eSXiaojian Du smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 70686c8236eSXiaojian Du } 70786c8236eSXiaojian Du break; 70886c8236eSXiaojian Du case SMU_SOCCLK: 70986c8236eSXiaojian Du /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 71086c8236eSXiaojian Du count = clk_table->NumSocClkLevelsEnabled; 71186c8236eSXiaojian Du cur_value = metrics.Current.SocclkFrequency; 71286c8236eSXiaojian Du break; 71386c8236eSXiaojian Du case SMU_VCLK: 71486c8236eSXiaojian Du count = clk_table->VcnClkLevelsEnabled; 71586c8236eSXiaojian Du cur_value = metrics.Current.VclkFrequency; 71686c8236eSXiaojian Du break; 71786c8236eSXiaojian Du case SMU_DCLK: 71886c8236eSXiaojian Du count = clk_table->VcnClkLevelsEnabled; 71986c8236eSXiaojian Du cur_value = metrics.Current.DclkFrequency; 72086c8236eSXiaojian Du break; 72186c8236eSXiaojian Du case SMU_MCLK: 72286c8236eSXiaojian Du count = clk_table->NumDfPstatesEnabled; 72386c8236eSXiaojian Du cur_value = metrics.Current.MemclkFrequency; 72486c8236eSXiaojian Du break; 72586c8236eSXiaojian Du case SMU_FCLK: 72686c8236eSXiaojian Du count = clk_table->NumDfPstatesEnabled; 72786c8236eSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 72886c8236eSXiaojian Du if (ret) 72986c8236eSXiaojian Du return ret; 73086c8236eSXiaojian Du break; 73148c19a95SPerry Yuan case SMU_GFXCLK: 73248c19a95SPerry Yuan case SMU_SCLK: 73348c19a95SPerry Yuan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value); 73448c19a95SPerry Yuan if (ret) { 73548c19a95SPerry Yuan return ret; 73648c19a95SPerry Yuan } 73748c19a95SPerry Yuan break; 73886c8236eSXiaojian Du default: 73986c8236eSXiaojian Du break; 74086c8236eSXiaojian Du } 74186c8236eSXiaojian Du 74286c8236eSXiaojian Du switch (clk_type) { 74386c8236eSXiaojian Du case SMU_SOCCLK: 74486c8236eSXiaojian Du case SMU_VCLK: 74586c8236eSXiaojian Du case SMU_DCLK: 74686c8236eSXiaojian Du case SMU_MCLK: 74786c8236eSXiaojian Du case SMU_FCLK: 74886c8236eSXiaojian Du for (i = 0; i < count; i++) { 74986c8236eSXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); 75086c8236eSXiaojian Du if (ret) 75186c8236eSXiaojian Du return ret; 75286c8236eSXiaojian Du if (!value) 75386c8236eSXiaojian Du continue; 754fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 75586c8236eSXiaojian Du cur_value == value ? "*" : ""); 75686c8236eSXiaojian Du if (cur_value == value) 75786c8236eSXiaojian Du cur_value_match_level = true; 75886c8236eSXiaojian Du } 75986c8236eSXiaojian Du 76086c8236eSXiaojian Du if (!cur_value_match_level) 761fe14c285SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 76286c8236eSXiaojian Du break; 76348c19a95SPerry Yuan case SMU_GFXCLK: 76448c19a95SPerry Yuan case SMU_SCLK: 76548c19a95SPerry Yuan min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 76648c19a95SPerry Yuan max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 76748c19a95SPerry Yuan if (cur_value == max) 76848c19a95SPerry Yuan i = 2; 76948c19a95SPerry Yuan else if (cur_value == min) 77048c19a95SPerry Yuan i = 0; 77148c19a95SPerry Yuan else 77248c19a95SPerry Yuan i = 1; 77348c19a95SPerry Yuan size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 77448c19a95SPerry Yuan i == 0 ? "*" : ""); 77548c19a95SPerry Yuan size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 77648c19a95SPerry Yuan i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, 77748c19a95SPerry Yuan i == 1 ? "*" : ""); 77848c19a95SPerry Yuan size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 77948c19a95SPerry Yuan i == 2 ? "*" : ""); 78048c19a95SPerry Yuan break; 78186c8236eSXiaojian Du default: 78286c8236eSXiaojian Du break; 78386c8236eSXiaojian Du } 78486c8236eSXiaojian Du 78586c8236eSXiaojian Du return size; 78686c8236eSXiaojian Du } 78786c8236eSXiaojian Du 78886c8236eSXiaojian Du static int vangogh_common_print_clk_levels(struct smu_context *smu, 78986c8236eSXiaojian Du enum smu_clk_type clk_type, char *buf) 79086c8236eSXiaojian Du { 79186c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev; 79286c8236eSXiaojian Du uint32_t if_version; 79386c8236eSXiaojian Du int ret = 0; 79486c8236eSXiaojian Du 79586c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 79686c8236eSXiaojian Du if (ret) { 79786c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n"); 79886c8236eSXiaojian Du return ret; 79986c8236eSXiaojian Du } 80086c8236eSXiaojian Du 80186c8236eSXiaojian Du if (if_version < 0x3) 80286c8236eSXiaojian Du ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf); 80386c8236eSXiaojian Du else 80486c8236eSXiaojian Du ret = vangogh_print_clk_levels(smu, clk_type, buf); 80586c8236eSXiaojian Du 80686c8236eSXiaojian Du return ret; 80786c8236eSXiaojian Du } 80886c8236eSXiaojian Du 809d0e4e112SXiaojian Du static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 810d0e4e112SXiaojian Du enum amd_dpm_forced_level level, 811d0e4e112SXiaojian Du uint32_t *vclk_mask, 812d0e4e112SXiaojian Du uint32_t *dclk_mask, 813d0e4e112SXiaojian Du uint32_t *mclk_mask, 814d0e4e112SXiaojian Du uint32_t *fclk_mask, 815d0e4e112SXiaojian Du uint32_t *soc_mask) 816d0e4e112SXiaojian Du { 817d0e4e112SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 818d0e4e112SXiaojian Du 819307f049bSXiaojian Du if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 820d0e4e112SXiaojian Du if (mclk_mask) 821d0e4e112SXiaojian Du *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 822307f049bSXiaojian Du 823d0e4e112SXiaojian Du if (fclk_mask) 824d0e4e112SXiaojian Du *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 825307f049bSXiaojian Du 826307f049bSXiaojian Du if (soc_mask) 827307f049bSXiaojian Du *soc_mask = 0; 828d0e4e112SXiaojian Du } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 829d0e4e112SXiaojian Du if (mclk_mask) 830d0e4e112SXiaojian Du *mclk_mask = 0; 831307f049bSXiaojian Du 832d0e4e112SXiaojian Du if (fclk_mask) 833d0e4e112SXiaojian Du *fclk_mask = 0; 834d0e4e112SXiaojian Du 835d0e4e112SXiaojian Du if (soc_mask) 836307f049bSXiaojian Du *soc_mask = 1; 837307f049bSXiaojian Du 838307f049bSXiaojian Du if (vclk_mask) 839307f049bSXiaojian Du *vclk_mask = 1; 840307f049bSXiaojian Du 841307f049bSXiaojian Du if (dclk_mask) 842307f049bSXiaojian Du *dclk_mask = 1; 843307f049bSXiaojian Du } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 844307f049bSXiaojian Du if (mclk_mask) 845307f049bSXiaojian Du *mclk_mask = 0; 846307f049bSXiaojian Du 847307f049bSXiaojian Du if (fclk_mask) 848307f049bSXiaojian Du *fclk_mask = 0; 849307f049bSXiaojian Du 850307f049bSXiaojian Du if (soc_mask) 851307f049bSXiaojian Du *soc_mask = 1; 852307f049bSXiaojian Du 853307f049bSXiaojian Du if (vclk_mask) 854307f049bSXiaojian Du *vclk_mask = 1; 855307f049bSXiaojian Du 856307f049bSXiaojian Du if (dclk_mask) 857307f049bSXiaojian Du *dclk_mask = 1; 858d0e4e112SXiaojian Du } 859d0e4e112SXiaojian Du 860d0e4e112SXiaojian Du return 0; 861d0e4e112SXiaojian Du } 862d0e4e112SXiaojian Du 8638f8150faSSouptick Joarder static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 864d0e4e112SXiaojian Du enum smu_clk_type clk_type) 865d0e4e112SXiaojian Du { 866d0e4e112SXiaojian Du enum smu_feature_mask feature_id = 0; 867d0e4e112SXiaojian Du 868d0e4e112SXiaojian Du switch (clk_type) { 869d0e4e112SXiaojian Du case SMU_MCLK: 870d0e4e112SXiaojian Du case SMU_UCLK: 871d0e4e112SXiaojian Du case SMU_FCLK: 872d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_FCLK_BIT; 873d0e4e112SXiaojian Du break; 874d0e4e112SXiaojian Du case SMU_GFXCLK: 875d0e4e112SXiaojian Du case SMU_SCLK: 876d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 877d0e4e112SXiaojian Du break; 878d0e4e112SXiaojian Du case SMU_SOCCLK: 879d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 880d0e4e112SXiaojian Du break; 881d0e4e112SXiaojian Du case SMU_VCLK: 882d0e4e112SXiaojian Du case SMU_DCLK: 883d0e4e112SXiaojian Du feature_id = SMU_FEATURE_VCN_DPM_BIT; 884d0e4e112SXiaojian Du break; 885d0e4e112SXiaojian Du default: 886d0e4e112SXiaojian Du return true; 887d0e4e112SXiaojian Du } 888d0e4e112SXiaojian Du 889d0e4e112SXiaojian Du if (!smu_cmn_feature_is_enabled(smu, feature_id)) 890d0e4e112SXiaojian Du return false; 891d0e4e112SXiaojian Du 892d0e4e112SXiaojian Du return true; 893d0e4e112SXiaojian Du } 894d0e4e112SXiaojian Du 895d0e4e112SXiaojian Du static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 896d0e4e112SXiaojian Du enum smu_clk_type clk_type, 897d0e4e112SXiaojian Du uint32_t *min, 898d0e4e112SXiaojian Du uint32_t *max) 899d0e4e112SXiaojian Du { 900d0e4e112SXiaojian Du int ret = 0; 901d0e4e112SXiaojian Du uint32_t soc_mask; 902d0e4e112SXiaojian Du uint32_t vclk_mask; 903d0e4e112SXiaojian Du uint32_t dclk_mask; 904d0e4e112SXiaojian Du uint32_t mclk_mask; 905d0e4e112SXiaojian Du uint32_t fclk_mask; 906d0e4e112SXiaojian Du uint32_t clock_limit; 907d0e4e112SXiaojian Du 908d0e4e112SXiaojian Du if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 909d0e4e112SXiaojian Du switch (clk_type) { 910d0e4e112SXiaojian Du case SMU_MCLK: 911d0e4e112SXiaojian Du case SMU_UCLK: 912d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.uclk; 913d0e4e112SXiaojian Du break; 914d0e4e112SXiaojian Du case SMU_FCLK: 915d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.fclk; 916d0e4e112SXiaojian Du break; 917d0e4e112SXiaojian Du case SMU_GFXCLK: 918d0e4e112SXiaojian Du case SMU_SCLK: 919d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.gfxclk; 920d0e4e112SXiaojian Du break; 921d0e4e112SXiaojian Du case SMU_SOCCLK: 922d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.socclk; 923d0e4e112SXiaojian Du break; 924d0e4e112SXiaojian Du case SMU_VCLK: 925d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.vclk; 926d0e4e112SXiaojian Du break; 927d0e4e112SXiaojian Du case SMU_DCLK: 928d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.dclk; 929d0e4e112SXiaojian Du break; 930d0e4e112SXiaojian Du default: 931d0e4e112SXiaojian Du clock_limit = 0; 932d0e4e112SXiaojian Du break; 933d0e4e112SXiaojian Du } 934d0e4e112SXiaojian Du 935d0e4e112SXiaojian Du /* clock in Mhz unit */ 936d0e4e112SXiaojian Du if (min) 937d0e4e112SXiaojian Du *min = clock_limit / 100; 938d0e4e112SXiaojian Du if (max) 939d0e4e112SXiaojian Du *max = clock_limit / 100; 940d0e4e112SXiaojian Du 941d0e4e112SXiaojian Du return 0; 942d0e4e112SXiaojian Du } 943d0e4e112SXiaojian Du if (max) { 944d0e4e112SXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, 945d0e4e112SXiaojian Du AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 946d0e4e112SXiaojian Du &vclk_mask, 947d0e4e112SXiaojian Du &dclk_mask, 948d0e4e112SXiaojian Du &mclk_mask, 949d0e4e112SXiaojian Du &fclk_mask, 950d0e4e112SXiaojian Du &soc_mask); 951d0e4e112SXiaojian Du if (ret) 952d0e4e112SXiaojian Du goto failed; 953d0e4e112SXiaojian Du 954d0e4e112SXiaojian Du switch (clk_type) { 955d0e4e112SXiaojian Du case SMU_UCLK: 956d0e4e112SXiaojian Du case SMU_MCLK: 957d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 958d0e4e112SXiaojian Du if (ret) 959d0e4e112SXiaojian Du goto failed; 960d0e4e112SXiaojian Du break; 961d0e4e112SXiaojian Du case SMU_SOCCLK: 962d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 963d0e4e112SXiaojian Du if (ret) 964d0e4e112SXiaojian Du goto failed; 965d0e4e112SXiaojian Du break; 966d0e4e112SXiaojian Du case SMU_FCLK: 967d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 968d0e4e112SXiaojian Du if (ret) 969d0e4e112SXiaojian Du goto failed; 970d0e4e112SXiaojian Du break; 971d0e4e112SXiaojian Du case SMU_VCLK: 972d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 973d0e4e112SXiaojian Du if (ret) 974d0e4e112SXiaojian Du goto failed; 975d0e4e112SXiaojian Du break; 976d0e4e112SXiaojian Du case SMU_DCLK: 977d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 978d0e4e112SXiaojian Du if (ret) 979d0e4e112SXiaojian Du goto failed; 980d0e4e112SXiaojian Du break; 981d0e4e112SXiaojian Du default: 982d0e4e112SXiaojian Du ret = -EINVAL; 983d0e4e112SXiaojian Du goto failed; 984d0e4e112SXiaojian Du } 985d0e4e112SXiaojian Du } 986d0e4e112SXiaojian Du if (min) { 987d0e4e112SXiaojian Du switch (clk_type) { 988d0e4e112SXiaojian Du case SMU_UCLK: 989d0e4e112SXiaojian Du case SMU_MCLK: 990d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 991d0e4e112SXiaojian Du if (ret) 992d0e4e112SXiaojian Du goto failed; 993d0e4e112SXiaojian Du break; 994d0e4e112SXiaojian Du case SMU_SOCCLK: 995d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 996d0e4e112SXiaojian Du if (ret) 997d0e4e112SXiaojian Du goto failed; 998d0e4e112SXiaojian Du break; 999d0e4e112SXiaojian Du case SMU_FCLK: 1000d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 1001d0e4e112SXiaojian Du if (ret) 1002d0e4e112SXiaojian Du goto failed; 1003d0e4e112SXiaojian Du break; 1004d0e4e112SXiaojian Du case SMU_VCLK: 1005d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 1006d0e4e112SXiaojian Du if (ret) 1007d0e4e112SXiaojian Du goto failed; 1008d0e4e112SXiaojian Du break; 1009d0e4e112SXiaojian Du case SMU_DCLK: 1010d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 1011d0e4e112SXiaojian Du if (ret) 1012d0e4e112SXiaojian Du goto failed; 1013d0e4e112SXiaojian Du break; 1014d0e4e112SXiaojian Du default: 1015d0e4e112SXiaojian Du ret = -EINVAL; 1016d0e4e112SXiaojian Du goto failed; 1017d0e4e112SXiaojian Du } 1018d0e4e112SXiaojian Du } 1019d0e4e112SXiaojian Du failed: 1020d0e4e112SXiaojian Du return ret; 1021d0e4e112SXiaojian Du } 1022d0e4e112SXiaojian Du 1023307f049bSXiaojian Du static int vangogh_get_power_profile_mode(struct smu_context *smu, 1024307f049bSXiaojian Du char *buf) 1025307f049bSXiaojian Du { 1026307f049bSXiaojian Du uint32_t i, size = 0; 1027307f049bSXiaojian Du int16_t workload_type = 0; 1028307f049bSXiaojian Du 1029307f049bSXiaojian Du if (!buf) 1030307f049bSXiaojian Du return -EINVAL; 1031307f049bSXiaojian Du 1032307f049bSXiaojian Du for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1033307f049bSXiaojian Du /* 1034307f049bSXiaojian Du * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1035307f049bSXiaojian Du * Not all profile modes are supported on vangogh. 1036307f049bSXiaojian Du */ 1037307f049bSXiaojian Du workload_type = smu_cmn_to_asic_specific_index(smu, 1038307f049bSXiaojian Du CMN2ASIC_MAPPING_WORKLOAD, 1039307f049bSXiaojian Du i); 1040307f049bSXiaojian Du 1041307f049bSXiaojian Du if (workload_type < 0) 1042307f049bSXiaojian Du continue; 1043307f049bSXiaojian Du 1044fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 104594a80b5bSDarren Powell i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1046307f049bSXiaojian Du } 1047307f049bSXiaojian Du 1048307f049bSXiaojian Du return size; 1049307f049bSXiaojian Du } 1050307f049bSXiaojian Du 1051d0e4e112SXiaojian Du static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1052d0e4e112SXiaojian Du { 1053d0e4e112SXiaojian Du int workload_type, ret; 1054d0e4e112SXiaojian Du uint32_t profile_mode = input[size]; 1055d0e4e112SXiaojian Du 1056d0e4e112SXiaojian Du if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1057d0e4e112SXiaojian Du dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1058d0e4e112SXiaojian Du return -EINVAL; 1059d0e4e112SXiaojian Du } 1060d0e4e112SXiaojian Du 1061f727ebebSXiaojian Du if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 1062f727ebebSXiaojian Du profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 1063f727ebebSXiaojian Du return 0; 1064f727ebebSXiaojian Du 1065d0e4e112SXiaojian Du /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1066d0e4e112SXiaojian Du workload_type = smu_cmn_to_asic_specific_index(smu, 1067d0e4e112SXiaojian Du CMN2ASIC_MAPPING_WORKLOAD, 1068d0e4e112SXiaojian Du profile_mode); 1069d0e4e112SXiaojian Du if (workload_type < 0) { 10709d489afdSAlex Deucher dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 1071d0e4e112SXiaojian Du profile_mode); 1072d0e4e112SXiaojian Du return -EINVAL; 1073d0e4e112SXiaojian Du } 1074d0e4e112SXiaojian Du 1075d0e4e112SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 1076d0e4e112SXiaojian Du 1 << workload_type, 1077d0e4e112SXiaojian Du NULL); 1078d0e4e112SXiaojian Du if (ret) { 1079d0e4e112SXiaojian Du dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 1080d0e4e112SXiaojian Du workload_type); 1081d0e4e112SXiaojian Du return ret; 1082d0e4e112SXiaojian Du } 1083d0e4e112SXiaojian Du 1084d0e4e112SXiaojian Du smu->power_profile_mode = profile_mode; 1085d0e4e112SXiaojian Du 1086d0e4e112SXiaojian Du return 0; 1087d0e4e112SXiaojian Du } 1088d0e4e112SXiaojian Du 1089dd9e0b21SXiaojian Du static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 1090dd9e0b21SXiaojian Du enum smu_clk_type clk_type, 1091dd9e0b21SXiaojian Du uint32_t min, 1092dd9e0b21SXiaojian Du uint32_t max) 1093dd9e0b21SXiaojian Du { 1094dd9e0b21SXiaojian Du int ret = 0; 1095dd9e0b21SXiaojian Du 1096dd9e0b21SXiaojian Du if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 1097dd9e0b21SXiaojian Du return 0; 1098dd9e0b21SXiaojian Du 1099dd9e0b21SXiaojian Du switch (clk_type) { 1100dd9e0b21SXiaojian Du case SMU_GFXCLK: 1101dd9e0b21SXiaojian Du case SMU_SCLK: 1102dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1103dd9e0b21SXiaojian Du SMU_MSG_SetHardMinGfxClk, 1104dd9e0b21SXiaojian Du min, NULL); 1105dd9e0b21SXiaojian Du if (ret) 1106dd9e0b21SXiaojian Du return ret; 1107dd9e0b21SXiaojian Du 1108dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1109dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxGfxClk, 1110dd9e0b21SXiaojian Du max, NULL); 1111dd9e0b21SXiaojian Du if (ret) 1112dd9e0b21SXiaojian Du return ret; 1113dd9e0b21SXiaojian Du break; 1114dd9e0b21SXiaojian Du case SMU_FCLK: 1115dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1116dd9e0b21SXiaojian Du SMU_MSG_SetHardMinFclkByFreq, 1117dd9e0b21SXiaojian Du min, NULL); 1118dd9e0b21SXiaojian Du if (ret) 1119dd9e0b21SXiaojian Du return ret; 1120dd9e0b21SXiaojian Du 1121dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1122dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxFclkByFreq, 1123dd9e0b21SXiaojian Du max, NULL); 1124dd9e0b21SXiaojian Du if (ret) 1125dd9e0b21SXiaojian Du return ret; 1126dd9e0b21SXiaojian Du break; 1127dd9e0b21SXiaojian Du case SMU_SOCCLK: 1128dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1129dd9e0b21SXiaojian Du SMU_MSG_SetHardMinSocclkByFreq, 1130dd9e0b21SXiaojian Du min, NULL); 1131dd9e0b21SXiaojian Du if (ret) 1132dd9e0b21SXiaojian Du return ret; 1133dd9e0b21SXiaojian Du 1134dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1135dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxSocclkByFreq, 1136dd9e0b21SXiaojian Du max, NULL); 1137dd9e0b21SXiaojian Du if (ret) 1138dd9e0b21SXiaojian Du return ret; 1139dd9e0b21SXiaojian Du break; 1140dd9e0b21SXiaojian Du case SMU_VCLK: 1141dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1142dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn, 1143dd9e0b21SXiaojian Du min << 16, NULL); 1144dd9e0b21SXiaojian Du if (ret) 1145dd9e0b21SXiaojian Du return ret; 1146dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1147dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxVcn, 1148dd9e0b21SXiaojian Du max << 16, NULL); 1149dd9e0b21SXiaojian Du if (ret) 1150dd9e0b21SXiaojian Du return ret; 1151dd9e0b21SXiaojian Du break; 1152dd9e0b21SXiaojian Du case SMU_DCLK: 1153dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1154dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn, 1155dd9e0b21SXiaojian Du min, NULL); 1156dd9e0b21SXiaojian Du if (ret) 1157dd9e0b21SXiaojian Du return ret; 1158dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1159dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxVcn, 1160dd9e0b21SXiaojian Du max, NULL); 1161dd9e0b21SXiaojian Du if (ret) 1162dd9e0b21SXiaojian Du return ret; 1163dd9e0b21SXiaojian Du break; 1164dd9e0b21SXiaojian Du default: 1165dd9e0b21SXiaojian Du return -EINVAL; 1166dd9e0b21SXiaojian Du } 1167dd9e0b21SXiaojian Du 1168dd9e0b21SXiaojian Du return ret; 1169dd9e0b21SXiaojian Du } 1170dd9e0b21SXiaojian Du 1171dd9e0b21SXiaojian Du static int vangogh_force_clk_levels(struct smu_context *smu, 1172dd9e0b21SXiaojian Du enum smu_clk_type clk_type, uint32_t mask) 1173dd9e0b21SXiaojian Du { 1174dd9e0b21SXiaojian Du uint32_t soft_min_level = 0, soft_max_level = 0; 1175dd9e0b21SXiaojian Du uint32_t min_freq = 0, max_freq = 0; 1176dd9e0b21SXiaojian Du int ret = 0 ; 1177dd9e0b21SXiaojian Du 1178dd9e0b21SXiaojian Du soft_min_level = mask ? (ffs(mask) - 1) : 0; 1179dd9e0b21SXiaojian Du soft_max_level = mask ? (fls(mask) - 1) : 0; 1180dd9e0b21SXiaojian Du 1181dd9e0b21SXiaojian Du switch (clk_type) { 1182dd9e0b21SXiaojian Du case SMU_SOCCLK: 1183dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1184dd9e0b21SXiaojian Du soft_min_level, &min_freq); 1185dd9e0b21SXiaojian Du if (ret) 1186dd9e0b21SXiaojian Du return ret; 1187dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1188dd9e0b21SXiaojian Du soft_max_level, &max_freq); 1189dd9e0b21SXiaojian Du if (ret) 1190dd9e0b21SXiaojian Du return ret; 1191dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1192dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxSocclkByFreq, 1193dd9e0b21SXiaojian Du max_freq, NULL); 1194dd9e0b21SXiaojian Du if (ret) 1195dd9e0b21SXiaojian Du return ret; 1196dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1197dd9e0b21SXiaojian Du SMU_MSG_SetHardMinSocclkByFreq, 1198dd9e0b21SXiaojian Du min_freq, NULL); 1199dd9e0b21SXiaojian Du if (ret) 1200dd9e0b21SXiaojian Du return ret; 1201dd9e0b21SXiaojian Du break; 1202dd9e0b21SXiaojian Du case SMU_FCLK: 1203dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1204dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq); 1205dd9e0b21SXiaojian Du if (ret) 1206dd9e0b21SXiaojian Du return ret; 1207dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1208dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq); 1209dd9e0b21SXiaojian Du if (ret) 1210dd9e0b21SXiaojian Du return ret; 1211dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1212dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxFclkByFreq, 1213dd9e0b21SXiaojian Du max_freq, NULL); 1214dd9e0b21SXiaojian Du if (ret) 1215dd9e0b21SXiaojian Du return ret; 1216dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1217dd9e0b21SXiaojian Du SMU_MSG_SetHardMinFclkByFreq, 1218dd9e0b21SXiaojian Du min_freq, NULL); 1219dd9e0b21SXiaojian Du if (ret) 1220dd9e0b21SXiaojian Du return ret; 1221dd9e0b21SXiaojian Du break; 1222dd9e0b21SXiaojian Du case SMU_VCLK: 1223dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1224dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq); 1225dd9e0b21SXiaojian Du if (ret) 1226dd9e0b21SXiaojian Du return ret; 1227307f049bSXiaojian Du 1228dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1229dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq); 1230dd9e0b21SXiaojian Du if (ret) 1231dd9e0b21SXiaojian Du return ret; 1232307f049bSXiaojian Du 1233307f049bSXiaojian Du 1234dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1235dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn, 1236dd9e0b21SXiaojian Du min_freq << 16, NULL); 1237dd9e0b21SXiaojian Du if (ret) 1238dd9e0b21SXiaojian Du return ret; 1239307f049bSXiaojian Du 1240307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1241307f049bSXiaojian Du SMU_MSG_SetSoftMaxVcn, 1242307f049bSXiaojian Du max_freq << 16, NULL); 1243307f049bSXiaojian Du if (ret) 1244307f049bSXiaojian Du return ret; 1245307f049bSXiaojian Du 1246dd9e0b21SXiaojian Du break; 1247dd9e0b21SXiaojian Du case SMU_DCLK: 1248dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1249dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq); 1250dd9e0b21SXiaojian Du if (ret) 1251dd9e0b21SXiaojian Du return ret; 1252307f049bSXiaojian Du 1253dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, 1254dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq); 1255dd9e0b21SXiaojian Du if (ret) 1256dd9e0b21SXiaojian Du return ret; 1257307f049bSXiaojian Du 1258dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1259dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn, 1260dd9e0b21SXiaojian Du min_freq, NULL); 1261dd9e0b21SXiaojian Du if (ret) 1262dd9e0b21SXiaojian Du return ret; 1263307f049bSXiaojian Du 1264307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, 1265307f049bSXiaojian Du SMU_MSG_SetSoftMaxVcn, 1266307f049bSXiaojian Du max_freq, NULL); 1267307f049bSXiaojian Du if (ret) 1268307f049bSXiaojian Du return ret; 1269307f049bSXiaojian Du 1270dd9e0b21SXiaojian Du break; 1271dd9e0b21SXiaojian Du default: 1272dd9e0b21SXiaojian Du break; 1273dd9e0b21SXiaojian Du } 1274dd9e0b21SXiaojian Du 1275dd9e0b21SXiaojian Du return ret; 1276dd9e0b21SXiaojian Du } 1277dd9e0b21SXiaojian Du 1278dd9e0b21SXiaojian Du static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1279dd9e0b21SXiaojian Du { 1280dd9e0b21SXiaojian Du int ret = 0, i = 0; 1281dd9e0b21SXiaojian Du uint32_t min_freq, max_freq, force_freq; 1282dd9e0b21SXiaojian Du enum smu_clk_type clk_type; 1283dd9e0b21SXiaojian Du 1284dd9e0b21SXiaojian Du enum smu_clk_type clks[] = { 1285dd9e0b21SXiaojian Du SMU_SOCCLK, 1286dd9e0b21SXiaojian Du SMU_VCLK, 1287dd9e0b21SXiaojian Du SMU_DCLK, 1288dd9e0b21SXiaojian Du SMU_FCLK, 1289dd9e0b21SXiaojian Du }; 1290dd9e0b21SXiaojian Du 1291dd9e0b21SXiaojian Du for (i = 0; i < ARRAY_SIZE(clks); i++) { 1292dd9e0b21SXiaojian Du clk_type = clks[i]; 1293dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1294dd9e0b21SXiaojian Du if (ret) 1295dd9e0b21SXiaojian Du return ret; 1296dd9e0b21SXiaojian Du 1297dd9e0b21SXiaojian Du force_freq = highest ? max_freq : min_freq; 1298dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1299dd9e0b21SXiaojian Du if (ret) 1300dd9e0b21SXiaojian Du return ret; 1301dd9e0b21SXiaojian Du } 1302dd9e0b21SXiaojian Du 1303dd9e0b21SXiaojian Du return ret; 1304dd9e0b21SXiaojian Du } 1305dd9e0b21SXiaojian Du 1306dd9e0b21SXiaojian Du static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1307dd9e0b21SXiaojian Du { 1308dd9e0b21SXiaojian Du int ret = 0, i = 0; 1309dd9e0b21SXiaojian Du uint32_t min_freq, max_freq; 1310dd9e0b21SXiaojian Du enum smu_clk_type clk_type; 1311dd9e0b21SXiaojian Du 1312dd9e0b21SXiaojian Du struct clk_feature_map { 1313dd9e0b21SXiaojian Du enum smu_clk_type clk_type; 1314dd9e0b21SXiaojian Du uint32_t feature; 1315dd9e0b21SXiaojian Du } clk_feature_map[] = { 1316dd9e0b21SXiaojian Du {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1317dd9e0b21SXiaojian Du {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1318b0eec124SXiaojian Du {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1319b0eec124SXiaojian Du {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1320dd9e0b21SXiaojian Du }; 1321dd9e0b21SXiaojian Du 1322dd9e0b21SXiaojian Du for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1323dd9e0b21SXiaojian Du 1324dd9e0b21SXiaojian Du if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1325dd9e0b21SXiaojian Du continue; 1326dd9e0b21SXiaojian Du 1327dd9e0b21SXiaojian Du clk_type = clk_feature_map[i].clk_type; 1328dd9e0b21SXiaojian Du 1329dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1330dd9e0b21SXiaojian Du 1331dd9e0b21SXiaojian Du if (ret) 1332dd9e0b21SXiaojian Du return ret; 1333dd9e0b21SXiaojian Du 1334dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1335dd9e0b21SXiaojian Du 1336dd9e0b21SXiaojian Du if (ret) 1337dd9e0b21SXiaojian Du return ret; 1338dd9e0b21SXiaojian Du } 1339dd9e0b21SXiaojian Du 1340dd9e0b21SXiaojian Du return ret; 1341dd9e0b21SXiaojian Du } 1342dd9e0b21SXiaojian Du 1343dd9e0b21SXiaojian Du static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1344dd9e0b21SXiaojian Du { 1345dd9e0b21SXiaojian Du int ret = 0; 1346dd9e0b21SXiaojian Du uint32_t socclk_freq = 0, fclk_freq = 0; 1347307f049bSXiaojian Du uint32_t vclk_freq = 0, dclk_freq = 0; 1348dd9e0b21SXiaojian Du 1349dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1350dd9e0b21SXiaojian Du if (ret) 1351dd9e0b21SXiaojian Du return ret; 1352dd9e0b21SXiaojian Du 1353dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1354dd9e0b21SXiaojian Du if (ret) 1355dd9e0b21SXiaojian Du return ret; 1356dd9e0b21SXiaojian Du 1357dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1358dd9e0b21SXiaojian Du if (ret) 1359dd9e0b21SXiaojian Du return ret; 1360dd9e0b21SXiaojian Du 1361dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1362dd9e0b21SXiaojian Du if (ret) 1363dd9e0b21SXiaojian Du return ret; 1364dd9e0b21SXiaojian Du 1365307f049bSXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1366307f049bSXiaojian Du if (ret) 1367307f049bSXiaojian Du return ret; 1368307f049bSXiaojian Du 1369307f049bSXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1370307f049bSXiaojian Du if (ret) 1371307f049bSXiaojian Du return ret; 1372307f049bSXiaojian Du 1373307f049bSXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1374307f049bSXiaojian Du if (ret) 1375307f049bSXiaojian Du return ret; 1376307f049bSXiaojian Du 1377307f049bSXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1378307f049bSXiaojian Du if (ret) 1379307f049bSXiaojian Du return ret; 1380307f049bSXiaojian Du 1381dd9e0b21SXiaojian Du return ret; 1382dd9e0b21SXiaojian Du } 1383dd9e0b21SXiaojian Du 1384ea173d15SXiaojian Du static int vangogh_set_performance_level(struct smu_context *smu, 1385ea173d15SXiaojian Du enum amd_dpm_forced_level level) 1386ea173d15SXiaojian Du { 1387*91aa9c8fSAlex Deucher int ret = 0, i; 1388ea173d15SXiaojian Du uint32_t soc_mask, mclk_mask, fclk_mask; 1389307f049bSXiaojian Du uint32_t vclk_mask = 0, dclk_mask = 0; 1390ea173d15SXiaojian Du 1391d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1392d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1393d7379efaSXiaojian Du 139468e3871dSAlex Deucher switch (level) { 139568e3871dSAlex Deucher case AMD_DPM_FORCED_LEVEL_HIGH: 139668e3871dSAlex Deucher smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq; 139768e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 139868e3871dSAlex Deucher 139968e3871dSAlex Deucher 1400ea173d15SXiaojian Du ret = vangogh_force_dpm_limit_value(smu, true); 140168e3871dSAlex Deucher if (ret) 140268e3871dSAlex Deucher return ret; 1403ea173d15SXiaojian Du break; 1404ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_LOW: 1405d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 140668e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1407d7379efaSXiaojian Du 1408ea173d15SXiaojian Du ret = vangogh_force_dpm_limit_value(smu, false); 140968e3871dSAlex Deucher if (ret) 141068e3871dSAlex Deucher return ret; 1411ea173d15SXiaojian Du break; 1412ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_AUTO: 1413d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1414d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1415d7379efaSXiaojian Du 1416ea173d15SXiaojian Du ret = vangogh_unforce_dpm_levels(smu); 141768e3871dSAlex Deucher if (ret) 141868e3871dSAlex Deucher return ret; 1419ea173d15SXiaojian Du break; 1420ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 142168e3871dSAlex Deucher smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 142268e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1423307f049bSXiaojian Du 1424307f049bSXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, level, 1425307f049bSXiaojian Du &vclk_mask, 1426307f049bSXiaojian Du &dclk_mask, 1427307f049bSXiaojian Du &mclk_mask, 1428307f049bSXiaojian Du &fclk_mask, 1429307f049bSXiaojian Du &soc_mask); 1430307f049bSXiaojian Du if (ret) 1431307f049bSXiaojian Du return ret; 1432307f049bSXiaojian Du 1433307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1434307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1435307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1436307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1437ea173d15SXiaojian Du break; 1438ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1439d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 144068e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1441ea173d15SXiaojian Du break; 1442ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1443d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1444d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1445d7379efaSXiaojian Du 1446ea173d15SXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, level, 1447ea173d15SXiaojian Du NULL, 1448ea173d15SXiaojian Du NULL, 1449ea173d15SXiaojian Du &mclk_mask, 1450ea173d15SXiaojian Du &fclk_mask, 1451307f049bSXiaojian Du NULL); 1452ea173d15SXiaojian Du if (ret) 1453ea173d15SXiaojian Du return ret; 1454307f049bSXiaojian Du 1455ea173d15SXiaojian Du vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1456ea173d15SXiaojian Du break; 1457ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 145868e3871dSAlex Deucher smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 145968e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1460307f049bSXiaojian Du 1461ea173d15SXiaojian Du ret = vangogh_set_peak_clock_by_device(smu); 146268e3871dSAlex Deucher if (ret) 146368e3871dSAlex Deucher return ret; 1464ea173d15SXiaojian Du break; 1465ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_MANUAL: 1466ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1467ea173d15SXiaojian Du default: 146868e3871dSAlex Deucher return 0; 1469ea173d15SXiaojian Du } 147068e3871dSAlex Deucher 147168e3871dSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 147268e3871dSAlex Deucher smu->gfx_actual_hard_min_freq, NULL); 147368e3871dSAlex Deucher if (ret) 147468e3871dSAlex Deucher return ret; 147568e3871dSAlex Deucher 147668e3871dSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 147768e3871dSAlex Deucher smu->gfx_actual_soft_max_freq, NULL); 147868e3871dSAlex Deucher if (ret) 147968e3871dSAlex Deucher return ret; 148068e3871dSAlex Deucher 1481*91aa9c8fSAlex Deucher if (smu->adev->pm.fw_version >= 0x43f1b00) { 1482*91aa9c8fSAlex Deucher for (i = 0; i < smu->cpu_core_num; i++) { 1483*91aa9c8fSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1484*91aa9c8fSAlex Deucher ((i << 20) 1485*91aa9c8fSAlex Deucher | smu->cpu_actual_soft_min_freq), 1486*91aa9c8fSAlex Deucher NULL); 1487*91aa9c8fSAlex Deucher if (ret) 1488*91aa9c8fSAlex Deucher return ret; 1489*91aa9c8fSAlex Deucher 1490*91aa9c8fSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1491*91aa9c8fSAlex Deucher ((i << 20) 1492*91aa9c8fSAlex Deucher | smu->cpu_actual_soft_max_freq), 1493*91aa9c8fSAlex Deucher NULL); 1494*91aa9c8fSAlex Deucher if (ret) 1495*91aa9c8fSAlex Deucher return ret; 1496*91aa9c8fSAlex Deucher } 1497*91aa9c8fSAlex Deucher } 1498*91aa9c8fSAlex Deucher 1499ea173d15SXiaojian Du return ret; 1500ea173d15SXiaojian Du } 1501ea173d15SXiaojian Du 1502271ab489SXiaojian Du static int vangogh_read_sensor(struct smu_context *smu, 1503271ab489SXiaojian Du enum amd_pp_sensors sensor, 1504271ab489SXiaojian Du void *data, uint32_t *size) 1505271ab489SXiaojian Du { 1506271ab489SXiaojian Du int ret = 0; 1507271ab489SXiaojian Du 1508271ab489SXiaojian Du if (!data || !size) 1509271ab489SXiaojian Du return -EINVAL; 1510271ab489SXiaojian Du 1511271ab489SXiaojian Du switch (sensor) { 1512271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GPU_LOAD: 151386c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15146cc24d8dSAlex Deucher METRICS_AVERAGE_GFXACTIVITY, 15156cc24d8dSAlex Deucher (uint32_t *)data); 1516271ab489SXiaojian Du *size = 4; 1517271ab489SXiaojian Du break; 1518271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GPU_POWER: 151986c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15206cc24d8dSAlex Deucher METRICS_AVERAGE_SOCKETPOWER, 15216cc24d8dSAlex Deucher (uint32_t *)data); 1522271ab489SXiaojian Du *size = 4; 1523271ab489SXiaojian Du break; 1524271ab489SXiaojian Du case AMDGPU_PP_SENSOR_EDGE_TEMP: 152586c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15266cc24d8dSAlex Deucher METRICS_TEMPERATURE_EDGE, 15276cc24d8dSAlex Deucher (uint32_t *)data); 15286cc24d8dSAlex Deucher *size = 4; 15296cc24d8dSAlex Deucher break; 1530271ab489SXiaojian Du case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 153186c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15326cc24d8dSAlex Deucher METRICS_TEMPERATURE_HOTSPOT, 15336cc24d8dSAlex Deucher (uint32_t *)data); 1534271ab489SXiaojian Du *size = 4; 1535271ab489SXiaojian Du break; 1536271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GFX_MCLK: 153786c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 1538a99a5116SXiaojian Du METRICS_CURR_UCLK, 15396cc24d8dSAlex Deucher (uint32_t *)data); 1540271ab489SXiaojian Du *(uint32_t *)data *= 100; 1541271ab489SXiaojian Du *size = 4; 1542271ab489SXiaojian Du break; 1543271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GFX_SCLK: 154486c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 1545a99a5116SXiaojian Du METRICS_CURR_GFXCLK, 15466cc24d8dSAlex Deucher (uint32_t *)data); 1547271ab489SXiaojian Du *(uint32_t *)data *= 100; 1548271ab489SXiaojian Du *size = 4; 1549271ab489SXiaojian Du break; 1550271ab489SXiaojian Du case AMDGPU_PP_SENSOR_VDDGFX: 155186c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15522139d12bSAlex Deucher METRICS_VOLTAGE_VDDGFX, 15532139d12bSAlex Deucher (uint32_t *)data); 15542139d12bSAlex Deucher *size = 4; 15552139d12bSAlex Deucher break; 15562139d12bSAlex Deucher case AMDGPU_PP_SENSOR_VDDNB: 155786c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 15582139d12bSAlex Deucher METRICS_VOLTAGE_VDDSOC, 15592139d12bSAlex Deucher (uint32_t *)data); 1560271ab489SXiaojian Du *size = 4; 1561271ab489SXiaojian Du break; 1562517cb957SHuang Rui case AMDGPU_PP_SENSOR_CPU_CLK: 156386c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu, 1564517cb957SHuang Rui METRICS_AVERAGE_CPUCLK, 1565517cb957SHuang Rui (uint32_t *)data); 15664aef0ebcSHuang Rui *size = smu->cpu_core_num * sizeof(uint16_t); 1567517cb957SHuang Rui break; 1568271ab489SXiaojian Du default: 1569271ab489SXiaojian Du ret = -EOPNOTSUPP; 1570271ab489SXiaojian Du break; 1571271ab489SXiaojian Du } 1572271ab489SXiaojian Du 1573271ab489SXiaojian Du return ret; 1574271ab489SXiaojian Du } 1575271ab489SXiaojian Du 1576271ab489SXiaojian Du static int vangogh_set_watermarks_table(struct smu_context *smu, 1577271ab489SXiaojian Du struct pp_smu_wm_range_sets *clock_ranges) 1578271ab489SXiaojian Du { 1579271ab489SXiaojian Du int i; 1580271ab489SXiaojian Du int ret = 0; 1581271ab489SXiaojian Du Watermarks_t *table = smu->smu_table.watermarks_table; 1582271ab489SXiaojian Du 1583271ab489SXiaojian Du if (!table || !clock_ranges) 1584271ab489SXiaojian Du return -EINVAL; 1585271ab489SXiaojian Du 1586271ab489SXiaojian Du if (clock_ranges) { 1587271ab489SXiaojian Du if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1588271ab489SXiaojian Du clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1589271ab489SXiaojian Du return -EINVAL; 1590271ab489SXiaojian Du 1591271ab489SXiaojian Du for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1592271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MinClock = 1593271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1594271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1595271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1596271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1597271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1598271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1599271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1600271ab489SXiaojian Du 1601271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1602271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].wm_inst; 1603271ab489SXiaojian Du } 1604271ab489SXiaojian Du 1605271ab489SXiaojian Du for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1606271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MinClock = 1607271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1608271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1609271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1610271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1611271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1612271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1613271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1614271ab489SXiaojian Du 1615271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1616271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].wm_inst; 1617271ab489SXiaojian Du } 1618271ab489SXiaojian Du 1619271ab489SXiaojian Du smu->watermarks_bitmap |= WATERMARKS_EXIST; 1620271ab489SXiaojian Du } 1621271ab489SXiaojian Du 1622271ab489SXiaojian Du /* pass data to smu controller */ 1623271ab489SXiaojian Du if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1624271ab489SXiaojian Du !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1625271ab489SXiaojian Du ret = smu_cmn_write_watermarks_table(smu); 1626271ab489SXiaojian Du if (ret) { 1627271ab489SXiaojian Du dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1628271ab489SXiaojian Du return ret; 1629271ab489SXiaojian Du } 1630271ab489SXiaojian Du smu->watermarks_bitmap |= WATERMARKS_LOADED; 1631271ab489SXiaojian Du } 1632271ab489SXiaojian Du 1633271ab489SXiaojian Du return 0; 1634f46a221bSXiaojian Du } 1635f46a221bSXiaojian Du 163686c8236eSXiaojian Du static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, 163786c8236eSXiaojian Du void **table) 163886c8236eSXiaojian Du { 163986c8236eSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 16407cab3cffSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics = 16417cab3cffSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 164286c8236eSXiaojian Du SmuMetrics_legacy_t metrics; 164386c8236eSXiaojian Du int ret = 0; 164486c8236eSXiaojian Du 164586c8236eSXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, true); 164686c8236eSXiaojian Du if (ret) 164786c8236eSXiaojian Du return ret; 164886c8236eSXiaojian Du 16497cab3cffSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 165086c8236eSXiaojian Du 165186c8236eSXiaojian Du gpu_metrics->temperature_gfx = metrics.GfxTemperature; 165286c8236eSXiaojian Du gpu_metrics->temperature_soc = metrics.SocTemperature; 165386c8236eSXiaojian Du memcpy(&gpu_metrics->temperature_core[0], 165486c8236eSXiaojian Du &metrics.CoreTemperature[0], 165586c8236eSXiaojian Du sizeof(uint16_t) * 4); 165686c8236eSXiaojian Du gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 165786c8236eSXiaojian Du 165886c8236eSXiaojian Du gpu_metrics->average_gfx_activity = metrics.GfxActivity; 165986c8236eSXiaojian Du gpu_metrics->average_mm_activity = metrics.UvdActivity; 166086c8236eSXiaojian Du 166186c8236eSXiaojian Du gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 166286c8236eSXiaojian Du gpu_metrics->average_cpu_power = metrics.Power[0]; 166386c8236eSXiaojian Du gpu_metrics->average_soc_power = metrics.Power[1]; 166486c8236eSXiaojian Du gpu_metrics->average_gfx_power = metrics.Power[2]; 166586c8236eSXiaojian Du memcpy(&gpu_metrics->average_core_power[0], 166686c8236eSXiaojian Du &metrics.CorePower[0], 166786c8236eSXiaojian Du sizeof(uint16_t) * 4); 166886c8236eSXiaojian Du 166986c8236eSXiaojian Du gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 167086c8236eSXiaojian Du gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 167186c8236eSXiaojian Du gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 167286c8236eSXiaojian Du gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 167386c8236eSXiaojian Du gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 167486c8236eSXiaojian Du gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 167586c8236eSXiaojian Du 167686c8236eSXiaojian Du memcpy(&gpu_metrics->current_coreclk[0], 167786c8236eSXiaojian Du &metrics.CoreFrequency[0], 167886c8236eSXiaojian Du sizeof(uint16_t) * 4); 167986c8236eSXiaojian Du gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 168086c8236eSXiaojian Du 168186c8236eSXiaojian Du gpu_metrics->throttle_status = metrics.ThrottlerStatus; 16827cab3cffSGraham Sider gpu_metrics->indep_throttle_status = 16837cab3cffSGraham Sider smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 16847cab3cffSGraham Sider vangogh_throttler_map); 168586c8236eSXiaojian Du 168686c8236eSXiaojian Du gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 168786c8236eSXiaojian Du 168886c8236eSXiaojian Du *table = (void *)gpu_metrics; 168986c8236eSXiaojian Du 16907cab3cffSGraham Sider return sizeof(struct gpu_metrics_v2_2); 169186c8236eSXiaojian Du } 169286c8236eSXiaojian Du 1693fd253334SXiaojian Du static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1694fd253334SXiaojian Du void **table) 1695fd253334SXiaojian Du { 1696fd253334SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 16977cab3cffSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics = 16987cab3cffSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1699fd253334SXiaojian Du SmuMetrics_t metrics; 1700fd253334SXiaojian Du int ret = 0; 1701fd253334SXiaojian Du 1702fd253334SXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1703fd253334SXiaojian Du if (ret) 1704fd253334SXiaojian Du return ret; 1705fd253334SXiaojian Du 17067cab3cffSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1707fd253334SXiaojian Du 170886c8236eSXiaojian Du gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 170986c8236eSXiaojian Du gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1710fd253334SXiaojian Du memcpy(&gpu_metrics->temperature_core[0], 171186c8236eSXiaojian Du &metrics.Current.CoreTemperature[0], 171286c8236eSXiaojian Du sizeof(uint16_t) * 4); 171386c8236eSXiaojian Du gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1714fd253334SXiaojian Du 171586c8236eSXiaojian Du gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 171686c8236eSXiaojian Du gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1717fd253334SXiaojian Du 171886c8236eSXiaojian Du gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 171986c8236eSXiaojian Du gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 172086c8236eSXiaojian Du gpu_metrics->average_soc_power = metrics.Current.Power[1]; 172186c8236eSXiaojian Du gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1722fd253334SXiaojian Du memcpy(&gpu_metrics->average_core_power[0], 172386c8236eSXiaojian Du &metrics.Average.CorePower[0], 172486c8236eSXiaojian Du sizeof(uint16_t) * 4); 1725fd253334SXiaojian Du 172686c8236eSXiaojian Du gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 172786c8236eSXiaojian Du gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 172886c8236eSXiaojian Du gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 172986c8236eSXiaojian Du gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 173086c8236eSXiaojian Du gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 173186c8236eSXiaojian Du gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 173286c8236eSXiaojian Du 173386c8236eSXiaojian Du gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 173486c8236eSXiaojian Du gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 173586c8236eSXiaojian Du gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 173686c8236eSXiaojian Du gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 173786c8236eSXiaojian Du gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 173886c8236eSXiaojian Du gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1739fd253334SXiaojian Du 1740fd253334SXiaojian Du memcpy(&gpu_metrics->current_coreclk[0], 174186c8236eSXiaojian Du &metrics.Current.CoreFrequency[0], 174286c8236eSXiaojian Du sizeof(uint16_t) * 4); 174386c8236eSXiaojian Du gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1744fd253334SXiaojian Du 174586c8236eSXiaojian Du gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 17467cab3cffSGraham Sider gpu_metrics->indep_throttle_status = 17477cab3cffSGraham Sider smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 17487cab3cffSGraham Sider vangogh_throttler_map); 1749fd253334SXiaojian Du 1750de4b7cd8SKevin Wang gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1751de4b7cd8SKevin Wang 1752fd253334SXiaojian Du *table = (void *)gpu_metrics; 1753fd253334SXiaojian Du 17547cab3cffSGraham Sider return sizeof(struct gpu_metrics_v2_2); 1755fd253334SXiaojian Du } 1756fd253334SXiaojian Du 175786c8236eSXiaojian Du static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, 175886c8236eSXiaojian Du void **table) 175986c8236eSXiaojian Du { 176086c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev; 176186c8236eSXiaojian Du uint32_t if_version; 176286c8236eSXiaojian Du int ret = 0; 176386c8236eSXiaojian Du 176486c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL); 176586c8236eSXiaojian Du if (ret) { 176686c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n"); 176786c8236eSXiaojian Du return ret; 176886c8236eSXiaojian Du } 176986c8236eSXiaojian Du 177086c8236eSXiaojian Du if (if_version < 0x3) 177186c8236eSXiaojian Du ret = vangogh_get_legacy_gpu_metrics(smu, table); 177286c8236eSXiaojian Du else 177386c8236eSXiaojian Du ret = vangogh_get_gpu_metrics(smu, table); 177486c8236eSXiaojian Du 177586c8236eSXiaojian Du return ret; 177686c8236eSXiaojian Du } 177786c8236eSXiaojian Du 1778c98ee897SXiaojian Du static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1779c98ee897SXiaojian Du long input[], uint32_t size) 1780c98ee897SXiaojian Du { 1781c98ee897SXiaojian Du int ret = 0; 1782d7379efaSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1783c98ee897SXiaojian Du 1784d7379efaSXiaojian Du if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 1785d7ef887fSXiaojian Du dev_warn(smu->adev->dev, 1786ce7c670dSColin Ian King "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 1787c98ee897SXiaojian Du return -EINVAL; 1788c98ee897SXiaojian Du } 1789c98ee897SXiaojian Du 1790c98ee897SXiaojian Du switch (type) { 17910d90d0ddSHuang Rui case PP_OD_EDIT_CCLK_VDDC_TABLE: 17920d90d0ddSHuang Rui if (size != 3) { 17930d90d0ddSHuang Rui dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 17940d90d0ddSHuang Rui return -EINVAL; 17950d90d0ddSHuang Rui } 17964aef0ebcSHuang Rui if (input[0] >= smu->cpu_core_num) { 17970d90d0ddSHuang Rui dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 17984aef0ebcSHuang Rui smu->cpu_core_num); 17990d90d0ddSHuang Rui } 18000d90d0ddSHuang Rui smu->cpu_core_id_select = input[0]; 18010d90d0ddSHuang Rui if (input[1] == 0) { 18020d90d0ddSHuang Rui if (input[2] < smu->cpu_default_soft_min_freq) { 18030d90d0ddSHuang Rui dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 18040d90d0ddSHuang Rui input[2], smu->cpu_default_soft_min_freq); 18050d90d0ddSHuang Rui return -EINVAL; 18060d90d0ddSHuang Rui } 18070d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = input[2]; 18080d90d0ddSHuang Rui } else if (input[1] == 1) { 18090d90d0ddSHuang Rui if (input[2] > smu->cpu_default_soft_max_freq) { 18100d90d0ddSHuang Rui dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 18110d90d0ddSHuang Rui input[2], smu->cpu_default_soft_max_freq); 18120d90d0ddSHuang Rui return -EINVAL; 18130d90d0ddSHuang Rui } 18140d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = input[2]; 18150d90d0ddSHuang Rui } else { 18160d90d0ddSHuang Rui return -EINVAL; 18170d90d0ddSHuang Rui } 18180d90d0ddSHuang Rui break; 1819c98ee897SXiaojian Du case PP_OD_EDIT_SCLK_VDDC_TABLE: 1820c98ee897SXiaojian Du if (size != 2) { 1821c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1822c98ee897SXiaojian Du return -EINVAL; 1823c98ee897SXiaojian Du } 1824c98ee897SXiaojian Du 1825c98ee897SXiaojian Du if (input[0] == 0) { 1826c98ee897SXiaojian Du if (input[1] < smu->gfx_default_hard_min_freq) { 1827307f049bSXiaojian Du dev_warn(smu->adev->dev, 1828307f049bSXiaojian Du "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1829c98ee897SXiaojian Du input[1], smu->gfx_default_hard_min_freq); 1830c98ee897SXiaojian Du return -EINVAL; 1831c98ee897SXiaojian Du } 1832c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = input[1]; 1833c98ee897SXiaojian Du } else if (input[0] == 1) { 1834c98ee897SXiaojian Du if (input[1] > smu->gfx_default_soft_max_freq) { 1835307f049bSXiaojian Du dev_warn(smu->adev->dev, 1836307f049bSXiaojian Du "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1837c98ee897SXiaojian Du input[1], smu->gfx_default_soft_max_freq); 1838c98ee897SXiaojian Du return -EINVAL; 1839c98ee897SXiaojian Du } 1840c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = input[1]; 1841c98ee897SXiaojian Du } else { 1842c98ee897SXiaojian Du return -EINVAL; 1843c98ee897SXiaojian Du } 1844c98ee897SXiaojian Du break; 1845c98ee897SXiaojian Du case PP_OD_RESTORE_DEFAULT_TABLE: 1846c98ee897SXiaojian Du if (size != 0) { 1847c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1848c98ee897SXiaojian Du return -EINVAL; 1849c98ee897SXiaojian Du } else { 1850c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1851c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 18520d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 18530d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1854c98ee897SXiaojian Du } 1855c98ee897SXiaojian Du break; 1856c98ee897SXiaojian Du case PP_OD_COMMIT_DPM_TABLE: 1857c98ee897SXiaojian Du if (size != 0) { 1858c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1859c98ee897SXiaojian Du return -EINVAL; 1860c98ee897SXiaojian Du } else { 1861c98ee897SXiaojian Du if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1862307f049bSXiaojian Du dev_err(smu->adev->dev, 1863f5d8e164SColin Ian King "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1864307f049bSXiaojian Du smu->gfx_actual_hard_min_freq, 1865307f049bSXiaojian Du smu->gfx_actual_soft_max_freq); 1866c98ee897SXiaojian Du return -EINVAL; 1867c98ee897SXiaojian Du } 1868c98ee897SXiaojian Du 1869c98ee897SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1870c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq, NULL); 1871c98ee897SXiaojian Du if (ret) { 1872c98ee897SXiaojian Du dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1873c98ee897SXiaojian Du return ret; 1874c98ee897SXiaojian Du } 1875c98ee897SXiaojian Du 1876c98ee897SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1877c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq, NULL); 1878c98ee897SXiaojian Du if (ret) { 1879c98ee897SXiaojian Du dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1880c98ee897SXiaojian Du return ret; 1881c98ee897SXiaojian Du } 18820d90d0ddSHuang Rui 18830d90d0ddSHuang Rui if (smu->adev->pm.fw_version < 0x43f1b00) { 18840d90d0ddSHuang Rui dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 18850d90d0ddSHuang Rui break; 18860d90d0ddSHuang Rui } 18870d90d0ddSHuang Rui 18880d90d0ddSHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 18890d90d0ddSHuang Rui ((smu->cpu_core_id_select << 20) 18900d90d0ddSHuang Rui | smu->cpu_actual_soft_min_freq), 18910d90d0ddSHuang Rui NULL); 18920d90d0ddSHuang Rui if (ret) { 18930d90d0ddSHuang Rui dev_err(smu->adev->dev, "Set hard min cclk failed!"); 18940d90d0ddSHuang Rui return ret; 18950d90d0ddSHuang Rui } 18960d90d0ddSHuang Rui 18970d90d0ddSHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 18980d90d0ddSHuang Rui ((smu->cpu_core_id_select << 20) 18990d90d0ddSHuang Rui | smu->cpu_actual_soft_max_freq), 19000d90d0ddSHuang Rui NULL); 19010d90d0ddSHuang Rui if (ret) { 19020d90d0ddSHuang Rui dev_err(smu->adev->dev, "Set soft max cclk failed!"); 19030d90d0ddSHuang Rui return ret; 19040d90d0ddSHuang Rui } 1905c98ee897SXiaojian Du } 1906c98ee897SXiaojian Du break; 1907c98ee897SXiaojian Du default: 1908c98ee897SXiaojian Du return -ENOSYS; 1909c98ee897SXiaojian Du } 1910c98ee897SXiaojian Du 1911c98ee897SXiaojian Du return ret; 1912c98ee897SXiaojian Du } 1913c98ee897SXiaojian Du 1914fce8a4acSJinzhou Su static int vangogh_set_default_dpm_tables(struct smu_context *smu) 1915c98ee897SXiaojian Du { 1916c98ee897SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table; 1917c98ee897SXiaojian Du 1918c98ee897SXiaojian Du return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 1919c98ee897SXiaojian Du } 1920c98ee897SXiaojian Du 1921c98ee897SXiaojian Du static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1922c98ee897SXiaojian Du { 1923c98ee897SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1924c98ee897SXiaojian Du 1925c98ee897SXiaojian Du smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1926c98ee897SXiaojian Du smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1927c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = 0; 1928c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = 0; 1929c98ee897SXiaojian Du 19300d90d0ddSHuang Rui smu->cpu_default_soft_min_freq = 1400; 19310d90d0ddSHuang Rui smu->cpu_default_soft_max_freq = 3500; 19320d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = 0; 19330d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = 0; 19340d90d0ddSHuang Rui 1935c98ee897SXiaojian Du return 0; 1936c98ee897SXiaojian Du } 1937c98ee897SXiaojian Du 1938ae7b32e7SXiaojian Du static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 1939ae7b32e7SXiaojian Du { 1940ae7b32e7SXiaojian Du DpmClocks_t *table = smu->smu_table.clocks_table; 1941ae7b32e7SXiaojian Du int i; 1942ae7b32e7SXiaojian Du 1943ae7b32e7SXiaojian Du if (!clock_table || !table) 1944ae7b32e7SXiaojian Du return -EINVAL; 1945ae7b32e7SXiaojian Du 1946ae7b32e7SXiaojian Du for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 1947ae7b32e7SXiaojian Du clock_table->SocClocks[i].Freq = table->SocClocks[i]; 1948ae7b32e7SXiaojian Du clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 1949ae7b32e7SXiaojian Du } 1950ae7b32e7SXiaojian Du 1951ae7b32e7SXiaojian Du for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1952ae7b32e7SXiaojian Du clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 1953ae7b32e7SXiaojian Du clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 1954ae7b32e7SXiaojian Du } 1955ae7b32e7SXiaojian Du 1956ae7b32e7SXiaojian Du for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 1957ae7b32e7SXiaojian Du clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 1958ae7b32e7SXiaojian Du clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 1959ae7b32e7SXiaojian Du } 1960ae7b32e7SXiaojian Du 1961ae7b32e7SXiaojian Du return 0; 1962ae7b32e7SXiaojian Du } 1963ae7b32e7SXiaojian Du 1964ae7b32e7SXiaojian Du 1965a0f55287SXiaomeng Hou static int vangogh_system_features_control(struct smu_context *smu, bool en) 1966a0f55287SXiaomeng Hou { 19679e3a6ab7SXiaomeng Hou struct amdgpu_device *adev = smu->adev; 1968aedebd40SHuang Rui int ret = 0; 19699e3a6ab7SXiaomeng Hou 19705b2e2c09SAlex Deucher if (adev->pm.fw_version >= 0x43f1700 && !en) 1971aedebd40SHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 19725b2e2c09SAlex Deucher RLC_STATUS_OFF, NULL); 1973aedebd40SHuang Rui 1974aedebd40SHuang Rui return ret; 1975a0f55287SXiaomeng Hou } 1976a0f55287SXiaomeng Hou 1977eefdf047SJinzhou Su static int vangogh_post_smu_init(struct smu_context *smu) 1978eefdf047SJinzhou Su { 1979eefdf047SJinzhou Su struct amdgpu_device *adev = smu->adev; 1980eefdf047SJinzhou Su uint32_t tmp; 19813313ef18SJinzhou Su int ret = 0; 1982eefdf047SJinzhou Su uint8_t aon_bits = 0; 1983eefdf047SJinzhou Su /* Two CUs in one WGP */ 1984eefdf047SJinzhou Su uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 1985eefdf047SJinzhou Su uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 1986eefdf047SJinzhou Su adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 1987eefdf047SJinzhou Su 19883313ef18SJinzhou Su /* allow message will be sent after enable message on Vangogh*/ 19897ade3ca9SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 1990bb377febSJinzhou Su (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 19913313ef18SJinzhou Su ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 19923313ef18SJinzhou Su if (ret) { 19933313ef18SJinzhou Su dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 19943313ef18SJinzhou Su return ret; 19953313ef18SJinzhou Su } 1996bb377febSJinzhou Su } else { 1997bb377febSJinzhou Su adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1998bb377febSJinzhou Su dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 1999bb377febSJinzhou Su } 20003313ef18SJinzhou Su 2001eefdf047SJinzhou Su /* if all CUs are active, no need to power off any WGPs */ 2002eefdf047SJinzhou Su if (total_cu == adev->gfx.cu_info.number) 2003eefdf047SJinzhou Su return 0; 2004eefdf047SJinzhou Su 2005eefdf047SJinzhou Su /* 2006eefdf047SJinzhou Su * Calculate the total bits number of always on WGPs for all SA/SEs in 2007eefdf047SJinzhou Su * RLC_PG_ALWAYS_ON_WGP_MASK. 2008eefdf047SJinzhou Su */ 2009eefdf047SJinzhou Su tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 2010eefdf047SJinzhou Su tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 2011eefdf047SJinzhou Su 2012eefdf047SJinzhou Su aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2013eefdf047SJinzhou Su 2014eefdf047SJinzhou Su /* Do not request any WGPs less than set in the AON_WGP_MASK */ 2015eefdf047SJinzhou Su if (aon_bits > req_active_wgps) { 2016eefdf047SJinzhou Su dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 2017eefdf047SJinzhou Su return 0; 2018eefdf047SJinzhou Su } else { 2019eefdf047SJinzhou Su return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 2020eefdf047SJinzhou Su } 2021eefdf047SJinzhou Su } 2022eefdf047SJinzhou Su 202374353883SHuang Rui static int vangogh_mode_reset(struct smu_context *smu, int type) 202474353883SHuang Rui { 202574353883SHuang Rui int ret = 0, index = 0; 202674353883SHuang Rui 202774353883SHuang Rui index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 202874353883SHuang Rui SMU_MSG_GfxDeviceDriverReset); 202974353883SHuang Rui if (index < 0) 203074353883SHuang Rui return index == -EACCES ? 0 : index; 203174353883SHuang Rui 203274353883SHuang Rui mutex_lock(&smu->message_lock); 203374353883SHuang Rui 203474353883SHuang Rui ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 203574353883SHuang Rui 203674353883SHuang Rui mutex_unlock(&smu->message_lock); 203774353883SHuang Rui 203874353883SHuang Rui mdelay(10); 203974353883SHuang Rui 204074353883SHuang Rui return ret; 204174353883SHuang Rui } 204274353883SHuang Rui 204320e157c7SAlex Deucher static int vangogh_mode2_reset(struct smu_context *smu) 204420e157c7SAlex Deucher { 204574353883SHuang Rui return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 204620e157c7SAlex Deucher } 204720e157c7SAlex Deucher 2048488f211dSEvan Quan static int vangogh_get_power_limit(struct smu_context *smu, 2049488f211dSEvan Quan uint32_t *current_power_limit, 2050488f211dSEvan Quan uint32_t *default_power_limit, 2051488f211dSEvan Quan uint32_t *max_power_limit) 2052ae07970aSXiaomeng Hou { 2053ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context = 2054ae07970aSXiaomeng Hou smu->smu_power.power_context; 2055ae07970aSXiaomeng Hou uint32_t ppt_limit; 2056ae07970aSXiaomeng Hou int ret = 0; 2057ae07970aSXiaomeng Hou 2058ae07970aSXiaomeng Hou if (smu->adev->pm.fw_version < 0x43f1e00) 2059ae07970aSXiaomeng Hou return ret; 2060ae07970aSXiaomeng Hou 2061ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 2062ae07970aSXiaomeng Hou if (ret) { 2063ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 2064ae07970aSXiaomeng Hou return ret; 2065ae07970aSXiaomeng Hou } 2066ae07970aSXiaomeng Hou /* convert from milliwatt to watt */ 2067488f211dSEvan Quan if (current_power_limit) 2068488f211dSEvan Quan *current_power_limit = ppt_limit / 1000; 2069488f211dSEvan Quan if (default_power_limit) 2070488f211dSEvan Quan *default_power_limit = ppt_limit / 1000; 2071488f211dSEvan Quan if (max_power_limit) 2072488f211dSEvan Quan *max_power_limit = 29; 2073ae07970aSXiaomeng Hou 2074ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 2075ae07970aSXiaomeng Hou if (ret) { 2076ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 2077ae07970aSXiaomeng Hou return ret; 2078ae07970aSXiaomeng Hou } 2079ae07970aSXiaomeng Hou /* convert from milliwatt to watt */ 20806e58941cSEric Huang power_context->current_fast_ppt_limit = 20816e58941cSEric Huang power_context->default_fast_ppt_limit = ppt_limit / 1000; 2082ae07970aSXiaomeng Hou power_context->max_fast_ppt_limit = 30; 2083ae07970aSXiaomeng Hou 2084ae07970aSXiaomeng Hou return ret; 2085ae07970aSXiaomeng Hou } 2086ae07970aSXiaomeng Hou 2087ae07970aSXiaomeng Hou static int vangogh_get_ppt_limit(struct smu_context *smu, 2088ae07970aSXiaomeng Hou uint32_t *ppt_limit, 2089ae07970aSXiaomeng Hou enum smu_ppt_limit_type type, 2090ae07970aSXiaomeng Hou enum smu_ppt_limit_level level) 2091ae07970aSXiaomeng Hou { 2092ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context = 2093ae07970aSXiaomeng Hou smu->smu_power.power_context; 2094ae07970aSXiaomeng Hou 2095ae07970aSXiaomeng Hou if (!power_context) 2096ae07970aSXiaomeng Hou return -EOPNOTSUPP; 2097ae07970aSXiaomeng Hou 2098ae07970aSXiaomeng Hou if (type == SMU_FAST_PPT_LIMIT) { 2099ae07970aSXiaomeng Hou switch (level) { 2100ae07970aSXiaomeng Hou case SMU_PPT_LIMIT_MAX: 2101ae07970aSXiaomeng Hou *ppt_limit = power_context->max_fast_ppt_limit; 2102ae07970aSXiaomeng Hou break; 2103ae07970aSXiaomeng Hou case SMU_PPT_LIMIT_CURRENT: 2104ae07970aSXiaomeng Hou *ppt_limit = power_context->current_fast_ppt_limit; 2105ae07970aSXiaomeng Hou break; 21066e58941cSEric Huang case SMU_PPT_LIMIT_DEFAULT: 21076e58941cSEric Huang *ppt_limit = power_context->default_fast_ppt_limit; 21086e58941cSEric Huang break; 2109ae07970aSXiaomeng Hou default: 2110ae07970aSXiaomeng Hou break; 2111ae07970aSXiaomeng Hou } 2112ae07970aSXiaomeng Hou } 2113ae07970aSXiaomeng Hou 2114ae07970aSXiaomeng Hou return 0; 2115ae07970aSXiaomeng Hou } 2116ae07970aSXiaomeng Hou 21172d1ac1cbSDarren Powell static int vangogh_set_power_limit(struct smu_context *smu, 21182d1ac1cbSDarren Powell enum smu_ppt_limit_type limit_type, 21192d1ac1cbSDarren Powell uint32_t ppt_limit) 2120ae07970aSXiaomeng Hou { 2121ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context = 2122ae07970aSXiaomeng Hou smu->smu_power.power_context; 2123ae07970aSXiaomeng Hou int ret = 0; 2124ae07970aSXiaomeng Hou 2125ae07970aSXiaomeng Hou if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 2126ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 2127ae07970aSXiaomeng Hou return -EOPNOTSUPP; 2128ae07970aSXiaomeng Hou } 2129ae07970aSXiaomeng Hou 2130ae07970aSXiaomeng Hou switch (limit_type) { 2131ae07970aSXiaomeng Hou case SMU_DEFAULT_PPT_LIMIT: 2132ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg_with_param(smu, 2133ae07970aSXiaomeng Hou SMU_MSG_SetSlowPPTLimit, 2134ae07970aSXiaomeng Hou ppt_limit * 1000, /* convert from watt to milliwatt */ 2135ae07970aSXiaomeng Hou NULL); 2136ae07970aSXiaomeng Hou if (ret) 2137ae07970aSXiaomeng Hou return ret; 2138ae07970aSXiaomeng Hou 2139ae07970aSXiaomeng Hou smu->current_power_limit = ppt_limit; 2140ae07970aSXiaomeng Hou break; 2141ae07970aSXiaomeng Hou case SMU_FAST_PPT_LIMIT: 2142ae07970aSXiaomeng Hou ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 2143ae07970aSXiaomeng Hou if (ppt_limit > power_context->max_fast_ppt_limit) { 2144ae07970aSXiaomeng Hou dev_err(smu->adev->dev, 2145ae07970aSXiaomeng Hou "New power limit (%d) is over the max allowed %d\n", 2146ae07970aSXiaomeng Hou ppt_limit, power_context->max_fast_ppt_limit); 2147ae07970aSXiaomeng Hou return ret; 2148ae07970aSXiaomeng Hou } 2149ae07970aSXiaomeng Hou 2150ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg_with_param(smu, 2151ae07970aSXiaomeng Hou SMU_MSG_SetFastPPTLimit, 2152ae07970aSXiaomeng Hou ppt_limit * 1000, /* convert from watt to milliwatt */ 2153ae07970aSXiaomeng Hou NULL); 2154ae07970aSXiaomeng Hou if (ret) 2155ae07970aSXiaomeng Hou return ret; 2156ae07970aSXiaomeng Hou 2157ae07970aSXiaomeng Hou power_context->current_fast_ppt_limit = ppt_limit; 2158ae07970aSXiaomeng Hou break; 2159ae07970aSXiaomeng Hou default: 2160ae07970aSXiaomeng Hou return -EINVAL; 2161ae07970aSXiaomeng Hou } 2162ae07970aSXiaomeng Hou 2163ae07970aSXiaomeng Hou return ret; 2164ae07970aSXiaomeng Hou } 2165ae07970aSXiaomeng Hou 2166f46a221bSXiaojian Du static const struct pptable_funcs vangogh_ppt_funcs = { 2167271ab489SXiaojian Du 2168f46a221bSXiaojian Du .check_fw_status = smu_v11_0_check_fw_status, 2169f46a221bSXiaojian Du .check_fw_version = smu_v11_0_check_fw_version, 2170f46a221bSXiaojian Du .init_smc_tables = vangogh_init_smc_tables, 2171f46a221bSXiaojian Du .fini_smc_tables = smu_v11_0_fini_smc_tables, 2172f46a221bSXiaojian Du .init_power = smu_v11_0_init_power, 2173f46a221bSXiaojian Du .fini_power = smu_v11_0_fini_power, 2174f46a221bSXiaojian Du .register_irq_handler = smu_v11_0_register_irq_handler, 2175f46a221bSXiaojian Du .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2176f46a221bSXiaojian Du .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2177f46a221bSXiaojian Du .send_smc_msg = smu_cmn_send_smc_msg, 2178271ab489SXiaojian Du .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 2179271ab489SXiaojian Du .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 2180f46a221bSXiaojian Du .is_dpm_running = vangogh_is_dpm_running, 2181271ab489SXiaojian Du .read_sensor = vangogh_read_sensor, 21825af779adSEvan Quan .get_enabled_mask = smu_cmn_get_enabled_mask, 2183f46a221bSXiaojian Du .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2184271ab489SXiaojian Du .set_watermarks_table = vangogh_set_watermarks_table, 2185271ab489SXiaojian Du .set_driver_table_location = smu_v11_0_set_driver_table_location, 2186f46a221bSXiaojian Du .interrupt_work = smu_v11_0_interrupt_work, 218786c8236eSXiaojian Du .get_gpu_metrics = vangogh_common_get_gpu_metrics, 2188c98ee897SXiaojian Du .od_edit_dpm_table = vangogh_od_edit_dpm_table, 218986c8236eSXiaojian Du .print_clk_levels = vangogh_common_print_clk_levels, 2190c98ee897SXiaojian Du .set_default_dpm_table = vangogh_set_default_dpm_tables, 2191c98ee897SXiaojian Du .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 2192a0f55287SXiaomeng Hou .system_features_control = vangogh_system_features_control, 2193d0e4e112SXiaojian Du .feature_is_enabled = smu_cmn_feature_is_enabled, 2194d0e4e112SXiaojian Du .set_power_profile_mode = vangogh_set_power_profile_mode, 2195307f049bSXiaojian Du .get_power_profile_mode = vangogh_get_power_profile_mode, 2196ae7b32e7SXiaojian Du .get_dpm_clock_table = vangogh_get_dpm_clock_table, 2197dd9e0b21SXiaojian Du .force_clk_levels = vangogh_force_clk_levels, 2198ea173d15SXiaojian Du .set_performance_level = vangogh_set_performance_level, 2199eefdf047SJinzhou Su .post_init = vangogh_post_smu_init, 220020e157c7SAlex Deucher .mode2_reset = vangogh_mode2_reset, 2201b58ce1feSJinzhou Su .gfx_off_control = smu_v11_0_gfx_off_control, 2202ae07970aSXiaomeng Hou .get_ppt_limit = vangogh_get_ppt_limit, 2203ae07970aSXiaomeng Hou .get_power_limit = vangogh_get_power_limit, 2204ae07970aSXiaomeng Hou .set_power_limit = vangogh_set_power_limit, 22053495d3c3SXiaojian Du .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2206f46a221bSXiaojian Du }; 2207f46a221bSXiaojian Du 2208f46a221bSXiaojian Du void vangogh_set_ppt_funcs(struct smu_context *smu) 2209f46a221bSXiaojian Du { 2210f46a221bSXiaojian Du smu->ppt_funcs = &vangogh_ppt_funcs; 2211f46a221bSXiaojian Du smu->message_map = vangogh_message_map; 2212f46a221bSXiaojian Du smu->feature_map = vangogh_feature_mask_map; 2213f46a221bSXiaojian Du smu->table_map = vangogh_table_map; 2214ec3b35c8SXiaojian Du smu->workload_map = vangogh_workload_map; 2215f46a221bSXiaojian Du smu->is_apu = true; 2216f46a221bSXiaojian Du } 2217